dosimeter/stm32workspace/dosim-v1/Debug/dosim-v1.list

dosim-v1.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   0000013c  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00009784  08000140  08000140  00010140  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       0000116c  080098c8  080098c8  000198c8  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  0800aa34  0800aa34  000201e4  2**0
                  CONTENTS
  4 .ARM          00000008  0800aa34  0800aa34  0001aa34  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  0800aa3c  0800aa3c  000201e4  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  0800aa3c  0800aa3c  0001aa3c  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  0800aa40  0800aa40  0001aa40  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         000001e4  20000000  0800aa44  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000520  200001e4  0800ac28  000201e4  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  20000704  0800ac28  00020704  2**0
                  ALLOC
 11 .ARM.attributes 00000029  00000000  00000000  000201e4  2**0
                  CONTENTS, READONLY
 12 .debug_info   000146de  00000000  00000000  0002020d  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 00002e0a  00000000  00000000  000348eb  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_aranges 00001298  00000000  00000000  000376f8  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_ranges 00001190  00000000  00000000  00038990  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_macro  000173f0  00000000  00000000  00039b20  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_line   000142c5  00000000  00000000  00050f10  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_str    0008cd84  00000000  00000000  000651d5  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .comment      00000053  00000000  00000000  000f1f59  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00006048  00000000  00000000  000f1fac  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

08000140 <__do_global_dtors_aux>:
 8000140:	b510      	push	{r4, lr}
 8000142:	4c05      	ldr	r4, [pc, #20]	; (8000158 <__do_global_dtors_aux+0x18>)
 8000144:	7823      	ldrb	r3, [r4, #0]
 8000146:	b933      	cbnz	r3, 8000156 <__do_global_dtors_aux+0x16>
 8000148:	4b04      	ldr	r3, [pc, #16]	; (800015c <__do_global_dtors_aux+0x1c>)
 800014a:	b113      	cbz	r3, 8000152 <__do_global_dtors_aux+0x12>
 800014c:	4804      	ldr	r0, [pc, #16]	; (8000160 <__do_global_dtors_aux+0x20>)
 800014e:	f3af 8000 	nop.w
 8000152:	2301      	movs	r3, #1
 8000154:	7023      	strb	r3, [r4, #0]
 8000156:	bd10      	pop	{r4, pc}
 8000158:	200001e4 	.word	0x200001e4
 800015c:	00000000 	.word	0x00000000
 8000160:	080098ac 	.word	0x080098ac

08000164 <frame_dummy>:
 8000164:	b508      	push	{r3, lr}
 8000166:	4b03      	ldr	r3, [pc, #12]	; (8000174 <frame_dummy+0x10>)
 8000168:	b11b      	cbz	r3, 8000172 <frame_dummy+0xe>
 800016a:	4903      	ldr	r1, [pc, #12]	; (8000178 <frame_dummy+0x14>)
 800016c:	4803      	ldr	r0, [pc, #12]	; (800017c <frame_dummy+0x18>)
 800016e:	f3af 8000 	nop.w
 8000172:	bd08      	pop	{r3, pc}
 8000174:	00000000 	.word	0x00000000
 8000178:	200001e8 	.word	0x200001e8
 800017c:	080098ac 	.word	0x080098ac

08000180 <strlen>:
 8000180:	4603      	mov	r3, r0
 8000182:	f813 2b01 	ldrb.w	r2, [r3], #1
 8000186:	2a00      	cmp	r2, #0
 8000188:	d1fb      	bne.n	8000182 <strlen+0x2>
 800018a:	1a18      	subs	r0, r3, r0
 800018c:	3801      	subs	r0, #1
 800018e:	4770      	bx	lr

08000190 <__aeabi_drsub>:
 8000190:	f081 4100 	eor.w	r1, r1, #2147483648	; 0x80000000
 8000194:	e002      	b.n	800019c <__adddf3>
 8000196:	bf00      	nop

08000198 <__aeabi_dsub>:
 8000198:	f083 4300 	eor.w	r3, r3, #2147483648	; 0x80000000

0800019c <__adddf3>:
 800019c:	b530      	push	{r4, r5, lr}
 800019e:	ea4f 0441 	mov.w	r4, r1, lsl #1
 80001a2:	ea4f 0543 	mov.w	r5, r3, lsl #1
 80001a6:	ea94 0f05 	teq	r4, r5
 80001aa:	bf08      	it	eq
 80001ac:	ea90 0f02 	teqeq	r0, r2
 80001b0:	bf1f      	itttt	ne
 80001b2:	ea54 0c00 	orrsne.w	ip, r4, r0
 80001b6:	ea55 0c02 	orrsne.w	ip, r5, r2
 80001ba:	ea7f 5c64 	mvnsne.w	ip, r4, asr #21
 80001be:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 80001c2:	f000 80e2 	beq.w	800038a <__adddf3+0x1ee>
 80001c6:	ea4f 5454 	mov.w	r4, r4, lsr #21
 80001ca:	ebd4 5555 	rsbs	r5, r4, r5, lsr #21
 80001ce:	bfb8      	it	lt
 80001d0:	426d      	neglt	r5, r5
 80001d2:	dd0c      	ble.n	80001ee <__adddf3+0x52>
 80001d4:	442c      	add	r4, r5
 80001d6:	ea80 0202 	eor.w	r2, r0, r2
 80001da:	ea81 0303 	eor.w	r3, r1, r3
 80001de:	ea82 0000 	eor.w	r0, r2, r0
 80001e2:	ea83 0101 	eor.w	r1, r3, r1
 80001e6:	ea80 0202 	eor.w	r2, r0, r2
 80001ea:	ea81 0303 	eor.w	r3, r1, r3
 80001ee:	2d36      	cmp	r5, #54	; 0x36
 80001f0:	bf88      	it	hi
 80001f2:	bd30      	pophi	{r4, r5, pc}
 80001f4:	f011 4f00 	tst.w	r1, #2147483648	; 0x80000000
 80001f8:	ea4f 3101 	mov.w	r1, r1, lsl #12
 80001fc:	f44f 1c80 	mov.w	ip, #1048576	; 0x100000
 8000200:	ea4c 3111 	orr.w	r1, ip, r1, lsr #12
 8000204:	d002      	beq.n	800020c <__adddf3+0x70>
 8000206:	4240      	negs	r0, r0
 8000208:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 800020c:	f013 4f00 	tst.w	r3, #2147483648	; 0x80000000
 8000210:	ea4f 3303 	mov.w	r3, r3, lsl #12
 8000214:	ea4c 3313 	orr.w	r3, ip, r3, lsr #12
 8000218:	d002      	beq.n	8000220 <__adddf3+0x84>
 800021a:	4252      	negs	r2, r2
 800021c:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
 8000220:	ea94 0f05 	teq	r4, r5
 8000224:	f000 80a7 	beq.w	8000376 <__adddf3+0x1da>
 8000228:	f1a4 0401 	sub.w	r4, r4, #1
 800022c:	f1d5 0e20 	rsbs	lr, r5, #32
 8000230:	db0d      	blt.n	800024e <__adddf3+0xb2>
 8000232:	fa02 fc0e 	lsl.w	ip, r2, lr
 8000236:	fa22 f205 	lsr.w	r2, r2, r5
 800023a:	1880      	adds	r0, r0, r2
 800023c:	f141 0100 	adc.w	r1, r1, #0
 8000240:	fa03 f20e 	lsl.w	r2, r3, lr
 8000244:	1880      	adds	r0, r0, r2
 8000246:	fa43 f305 	asr.w	r3, r3, r5
 800024a:	4159      	adcs	r1, r3
 800024c:	e00e      	b.n	800026c <__adddf3+0xd0>
 800024e:	f1a5 0520 	sub.w	r5, r5, #32
 8000252:	f10e 0e20 	add.w	lr, lr, #32
 8000256:	2a01      	cmp	r2, #1
 8000258:	fa03 fc0e 	lsl.w	ip, r3, lr
 800025c:	bf28      	it	cs
 800025e:	f04c 0c02 	orrcs.w	ip, ip, #2
 8000262:	fa43 f305 	asr.w	r3, r3, r5
 8000266:	18c0      	adds	r0, r0, r3
 8000268:	eb51 71e3 	adcs.w	r1, r1, r3, asr #31
 800026c:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 8000270:	d507      	bpl.n	8000282 <__adddf3+0xe6>
 8000272:	f04f 0e00 	mov.w	lr, #0
 8000276:	f1dc 0c00 	rsbs	ip, ip, #0
 800027a:	eb7e 0000 	sbcs.w	r0, lr, r0
 800027e:	eb6e 0101 	sbc.w	r1, lr, r1
 8000282:	f5b1 1f80 	cmp.w	r1, #1048576	; 0x100000
 8000286:	d31b      	bcc.n	80002c0 <__adddf3+0x124>
 8000288:	f5b1 1f00 	cmp.w	r1, #2097152	; 0x200000
 800028c:	d30c      	bcc.n	80002a8 <__adddf3+0x10c>
 800028e:	0849      	lsrs	r1, r1, #1
 8000290:	ea5f 0030 	movs.w	r0, r0, rrx
 8000294:	ea4f 0c3c 	mov.w	ip, ip, rrx
 8000298:	f104 0401 	add.w	r4, r4, #1
 800029c:	ea4f 5244 	mov.w	r2, r4, lsl #21
 80002a0:	f512 0f80 	cmn.w	r2, #4194304	; 0x400000
 80002a4:	f080 809a 	bcs.w	80003dc <__adddf3+0x240>
 80002a8:	f1bc 4f00 	cmp.w	ip, #2147483648	; 0x80000000
 80002ac:	bf08      	it	eq
 80002ae:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 80002b2:	f150 0000 	adcs.w	r0, r0, #0
 80002b6:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 80002ba:	ea41 0105 	orr.w	r1, r1, r5
 80002be:	bd30      	pop	{r4, r5, pc}
 80002c0:	ea5f 0c4c 	movs.w	ip, ip, lsl #1
 80002c4:	4140      	adcs	r0, r0
 80002c6:	eb41 0101 	adc.w	r1, r1, r1
 80002ca:	3c01      	subs	r4, #1
 80002cc:	bf28      	it	cs
 80002ce:	f5b1 1f80 	cmpcs.w	r1, #1048576	; 0x100000
 80002d2:	d2e9      	bcs.n	80002a8 <__adddf3+0x10c>
 80002d4:	f091 0f00 	teq	r1, #0
 80002d8:	bf04      	itt	eq
 80002da:	4601      	moveq	r1, r0
 80002dc:	2000      	moveq	r0, #0
 80002de:	fab1 f381 	clz	r3, r1
 80002e2:	bf08      	it	eq
 80002e4:	3320      	addeq	r3, #32
 80002e6:	f1a3 030b 	sub.w	r3, r3, #11
 80002ea:	f1b3 0220 	subs.w	r2, r3, #32
 80002ee:	da0c      	bge.n	800030a <__adddf3+0x16e>
 80002f0:	320c      	adds	r2, #12
 80002f2:	dd08      	ble.n	8000306 <__adddf3+0x16a>
 80002f4:	f102 0c14 	add.w	ip, r2, #20
 80002f8:	f1c2 020c 	rsb	r2, r2, #12
 80002fc:	fa01 f00c 	lsl.w	r0, r1, ip
 8000300:	fa21 f102 	lsr.w	r1, r1, r2
 8000304:	e00c      	b.n	8000320 <__adddf3+0x184>
 8000306:	f102 0214 	add.w	r2, r2, #20
 800030a:	bfd8      	it	le
 800030c:	f1c2 0c20 	rsble	ip, r2, #32
 8000310:	fa01 f102 	lsl.w	r1, r1, r2
 8000314:	fa20 fc0c 	lsr.w	ip, r0, ip
 8000318:	bfdc      	itt	le
 800031a:	ea41 010c 	orrle.w	r1, r1, ip
 800031e:	4090      	lslle	r0, r2
 8000320:	1ae4      	subs	r4, r4, r3
 8000322:	bfa2      	ittt	ge
 8000324:	eb01 5104 	addge.w	r1, r1, r4, lsl #20
 8000328:	4329      	orrge	r1, r5
 800032a:	bd30      	popge	{r4, r5, pc}
 800032c:	ea6f 0404 	mvn.w	r4, r4
 8000330:	3c1f      	subs	r4, #31
 8000332:	da1c      	bge.n	800036e <__adddf3+0x1d2>
 8000334:	340c      	adds	r4, #12
 8000336:	dc0e      	bgt.n	8000356 <__adddf3+0x1ba>
 8000338:	f104 0414 	add.w	r4, r4, #20
 800033c:	f1c4 0220 	rsb	r2, r4, #32
 8000340:	fa20 f004 	lsr.w	r0, r0, r4
 8000344:	fa01 f302 	lsl.w	r3, r1, r2
 8000348:	ea40 0003 	orr.w	r0, r0, r3
 800034c:	fa21 f304 	lsr.w	r3, r1, r4
 8000350:	ea45 0103 	orr.w	r1, r5, r3
 8000354:	bd30      	pop	{r4, r5, pc}
 8000356:	f1c4 040c 	rsb	r4, r4, #12
 800035a:	f1c4 0220 	rsb	r2, r4, #32
 800035e:	fa20 f002 	lsr.w	r0, r0, r2
 8000362:	fa01 f304 	lsl.w	r3, r1, r4
 8000366:	ea40 0003 	orr.w	r0, r0, r3
 800036a:	4629      	mov	r1, r5
 800036c:	bd30      	pop	{r4, r5, pc}
 800036e:	fa21 f004 	lsr.w	r0, r1, r4
 8000372:	4629      	mov	r1, r5
 8000374:	bd30      	pop	{r4, r5, pc}
 8000376:	f094 0f00 	teq	r4, #0
 800037a:	f483 1380 	eor.w	r3, r3, #1048576	; 0x100000
 800037e:	bf06      	itte	eq
 8000380:	f481 1180 	eoreq.w	r1, r1, #1048576	; 0x100000
 8000384:	3401      	addeq	r4, #1
 8000386:	3d01      	subne	r5, #1
 8000388:	e74e      	b.n	8000228 <__adddf3+0x8c>
 800038a:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 800038e:	bf18      	it	ne
 8000390:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 8000394:	d029      	beq.n	80003ea <__adddf3+0x24e>
 8000396:	ea94 0f05 	teq	r4, r5
 800039a:	bf08      	it	eq
 800039c:	ea90 0f02 	teqeq	r0, r2
 80003a0:	d005      	beq.n	80003ae <__adddf3+0x212>
 80003a2:	ea54 0c00 	orrs.w	ip, r4, r0
 80003a6:	bf04      	itt	eq
 80003a8:	4619      	moveq	r1, r3
 80003aa:	4610      	moveq	r0, r2
 80003ac:	bd30      	pop	{r4, r5, pc}
 80003ae:	ea91 0f03 	teq	r1, r3
 80003b2:	bf1e      	ittt	ne
 80003b4:	2100      	movne	r1, #0
 80003b6:	2000      	movne	r0, #0
 80003b8:	bd30      	popne	{r4, r5, pc}
 80003ba:	ea5f 5c54 	movs.w	ip, r4, lsr #21
 80003be:	d105      	bne.n	80003cc <__adddf3+0x230>
 80003c0:	0040      	lsls	r0, r0, #1
 80003c2:	4149      	adcs	r1, r1
 80003c4:	bf28      	it	cs
 80003c6:	f041 4100 	orrcs.w	r1, r1, #2147483648	; 0x80000000
 80003ca:	bd30      	pop	{r4, r5, pc}
 80003cc:	f514 0480 	adds.w	r4, r4, #4194304	; 0x400000
 80003d0:	bf3c      	itt	cc
 80003d2:	f501 1180 	addcc.w	r1, r1, #1048576	; 0x100000
 80003d6:	bd30      	popcc	{r4, r5, pc}
 80003d8:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 80003dc:	f045 41fe 	orr.w	r1, r5, #2130706432	; 0x7f000000
 80003e0:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 80003e4:	f04f 0000 	mov.w	r0, #0
 80003e8:	bd30      	pop	{r4, r5, pc}
 80003ea:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 80003ee:	bf1a      	itte	ne
 80003f0:	4619      	movne	r1, r3
 80003f2:	4610      	movne	r0, r2
 80003f4:	ea7f 5c65 	mvnseq.w	ip, r5, asr #21
 80003f8:	bf1c      	itt	ne
 80003fa:	460b      	movne	r3, r1
 80003fc:	4602      	movne	r2, r0
 80003fe:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 8000402:	bf06      	itte	eq
 8000404:	ea52 3503 	orrseq.w	r5, r2, r3, lsl #12
 8000408:	ea91 0f03 	teqeq	r1, r3
 800040c:	f441 2100 	orrne.w	r1, r1, #524288	; 0x80000
 8000410:	bd30      	pop	{r4, r5, pc}
 8000412:	bf00      	nop

08000414 <__aeabi_ui2d>:
 8000414:	f090 0f00 	teq	r0, #0
 8000418:	bf04      	itt	eq
 800041a:	2100      	moveq	r1, #0
 800041c:	4770      	bxeq	lr
 800041e:	b530      	push	{r4, r5, lr}
 8000420:	f44f 6480 	mov.w	r4, #1024	; 0x400
 8000424:	f104 0432 	add.w	r4, r4, #50	; 0x32
 8000428:	f04f 0500 	mov.w	r5, #0
 800042c:	f04f 0100 	mov.w	r1, #0
 8000430:	e750      	b.n	80002d4 <__adddf3+0x138>
 8000432:	bf00      	nop

08000434 <__aeabi_i2d>:
 8000434:	f090 0f00 	teq	r0, #0
 8000438:	bf04      	itt	eq
 800043a:	2100      	moveq	r1, #0
 800043c:	4770      	bxeq	lr
 800043e:	b530      	push	{r4, r5, lr}
 8000440:	f44f 6480 	mov.w	r4, #1024	; 0x400
 8000444:	f104 0432 	add.w	r4, r4, #50	; 0x32
 8000448:	f010 4500 	ands.w	r5, r0, #2147483648	; 0x80000000
 800044c:	bf48      	it	mi
 800044e:	4240      	negmi	r0, r0
 8000450:	f04f 0100 	mov.w	r1, #0
 8000454:	e73e      	b.n	80002d4 <__adddf3+0x138>
 8000456:	bf00      	nop

08000458 <__aeabi_f2d>:
 8000458:	0042      	lsls	r2, r0, #1
 800045a:	ea4f 01e2 	mov.w	r1, r2, asr #3
 800045e:	ea4f 0131 	mov.w	r1, r1, rrx
 8000462:	ea4f 7002 	mov.w	r0, r2, lsl #28
 8000466:	bf1f      	itttt	ne
 8000468:	f012 437f 	andsne.w	r3, r2, #4278190080	; 0xff000000
 800046c:	f093 4f7f 	teqne	r3, #4278190080	; 0xff000000
 8000470:	f081 5160 	eorne.w	r1, r1, #939524096	; 0x38000000
 8000474:	4770      	bxne	lr
 8000476:	f032 427f 	bics.w	r2, r2, #4278190080	; 0xff000000
 800047a:	bf08      	it	eq
 800047c:	4770      	bxeq	lr
 800047e:	f093 4f7f 	teq	r3, #4278190080	; 0xff000000
 8000482:	bf04      	itt	eq
 8000484:	f441 2100 	orreq.w	r1, r1, #524288	; 0x80000
 8000488:	4770      	bxeq	lr
 800048a:	b530      	push	{r4, r5, lr}
 800048c:	f44f 7460 	mov.w	r4, #896	; 0x380
 8000490:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 8000494:	f021 4100 	bic.w	r1, r1, #2147483648	; 0x80000000
 8000498:	e71c      	b.n	80002d4 <__adddf3+0x138>
 800049a:	bf00      	nop

0800049c <__aeabi_ul2d>:
 800049c:	ea50 0201 	orrs.w	r2, r0, r1
 80004a0:	bf08      	it	eq
 80004a2:	4770      	bxeq	lr
 80004a4:	b530      	push	{r4, r5, lr}
 80004a6:	f04f 0500 	mov.w	r5, #0
 80004aa:	e00a      	b.n	80004c2 <__aeabi_l2d+0x16>

080004ac <__aeabi_l2d>:
 80004ac:	ea50 0201 	orrs.w	r2, r0, r1
 80004b0:	bf08      	it	eq
 80004b2:	4770      	bxeq	lr
 80004b4:	b530      	push	{r4, r5, lr}
 80004b6:	f011 4500 	ands.w	r5, r1, #2147483648	; 0x80000000
 80004ba:	d502      	bpl.n	80004c2 <__aeabi_l2d+0x16>
 80004bc:	4240      	negs	r0, r0
 80004be:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 80004c2:	f44f 6480 	mov.w	r4, #1024	; 0x400
 80004c6:	f104 0432 	add.w	r4, r4, #50	; 0x32
 80004ca:	ea5f 5c91 	movs.w	ip, r1, lsr #22
 80004ce:	f43f aed8 	beq.w	8000282 <__adddf3+0xe6>
 80004d2:	f04f 0203 	mov.w	r2, #3
 80004d6:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 80004da:	bf18      	it	ne
 80004dc:	3203      	addne	r2, #3
 80004de:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 80004e2:	bf18      	it	ne
 80004e4:	3203      	addne	r2, #3
 80004e6:	eb02 02dc 	add.w	r2, r2, ip, lsr #3
 80004ea:	f1c2 0320 	rsb	r3, r2, #32
 80004ee:	fa00 fc03 	lsl.w	ip, r0, r3
 80004f2:	fa20 f002 	lsr.w	r0, r0, r2
 80004f6:	fa01 fe03 	lsl.w	lr, r1, r3
 80004fa:	ea40 000e 	orr.w	r0, r0, lr
 80004fe:	fa21 f102 	lsr.w	r1, r1, r2
 8000502:	4414      	add	r4, r2
 8000504:	e6bd      	b.n	8000282 <__adddf3+0xe6>
 8000506:	bf00      	nop

08000508 <__aeabi_dmul>:
 8000508:	b570      	push	{r4, r5, r6, lr}
 800050a:	f04f 0cff 	mov.w	ip, #255	; 0xff
 800050e:	f44c 6ce0 	orr.w	ip, ip, #1792	; 0x700
 8000512:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 8000516:	bf1d      	ittte	ne
 8000518:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 800051c:	ea94 0f0c 	teqne	r4, ip
 8000520:	ea95 0f0c 	teqne	r5, ip
 8000524:	f000 f8de 	bleq	80006e4 <__aeabi_dmul+0x1dc>
 8000528:	442c      	add	r4, r5
 800052a:	ea81 0603 	eor.w	r6, r1, r3
 800052e:	ea21 514c 	bic.w	r1, r1, ip, lsl #21
 8000532:	ea23 534c 	bic.w	r3, r3, ip, lsl #21
 8000536:	ea50 3501 	orrs.w	r5, r0, r1, lsl #12
 800053a:	bf18      	it	ne
 800053c:	ea52 3503 	orrsne.w	r5, r2, r3, lsl #12
 8000540:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 8000544:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 8000548:	d038      	beq.n	80005bc <__aeabi_dmul+0xb4>
 800054a:	fba0 ce02 	umull	ip, lr, r0, r2
 800054e:	f04f 0500 	mov.w	r5, #0
 8000552:	fbe1 e502 	umlal	lr, r5, r1, r2
 8000556:	f006 4200 	and.w	r2, r6, #2147483648	; 0x80000000
 800055a:	fbe0 e503 	umlal	lr, r5, r0, r3
 800055e:	f04f 0600 	mov.w	r6, #0
 8000562:	fbe1 5603 	umlal	r5, r6, r1, r3
 8000566:	f09c 0f00 	teq	ip, #0
 800056a:	bf18      	it	ne
 800056c:	f04e 0e01 	orrne.w	lr, lr, #1
 8000570:	f1a4 04ff 	sub.w	r4, r4, #255	; 0xff
 8000574:	f5b6 7f00 	cmp.w	r6, #512	; 0x200
 8000578:	f564 7440 	sbc.w	r4, r4, #768	; 0x300
 800057c:	d204      	bcs.n	8000588 <__aeabi_dmul+0x80>
 800057e:	ea5f 0e4e 	movs.w	lr, lr, lsl #1
 8000582:	416d      	adcs	r5, r5
 8000584:	eb46 0606 	adc.w	r6, r6, r6
 8000588:	ea42 21c6 	orr.w	r1, r2, r6, lsl #11
 800058c:	ea41 5155 	orr.w	r1, r1, r5, lsr #21
 8000590:	ea4f 20c5 	mov.w	r0, r5, lsl #11
 8000594:	ea40 505e 	orr.w	r0, r0, lr, lsr #21
 8000598:	ea4f 2ece 	mov.w	lr, lr, lsl #11
 800059c:	f1b4 0cfd 	subs.w	ip, r4, #253	; 0xfd
 80005a0:	bf88      	it	hi
 80005a2:	f5bc 6fe0 	cmphi.w	ip, #1792	; 0x700
 80005a6:	d81e      	bhi.n	80005e6 <__aeabi_dmul+0xde>
 80005a8:	f1be 4f00 	cmp.w	lr, #2147483648	; 0x80000000
 80005ac:	bf08      	it	eq
 80005ae:	ea5f 0e50 	movseq.w	lr, r0, lsr #1
 80005b2:	f150 0000 	adcs.w	r0, r0, #0
 80005b6:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 80005ba:	bd70      	pop	{r4, r5, r6, pc}
 80005bc:	f006 4600 	and.w	r6, r6, #2147483648	; 0x80000000
 80005c0:	ea46 0101 	orr.w	r1, r6, r1
 80005c4:	ea40 0002 	orr.w	r0, r0, r2
 80005c8:	ea81 0103 	eor.w	r1, r1, r3
 80005cc:	ebb4 045c 	subs.w	r4, r4, ip, lsr #1
 80005d0:	bfc2      	ittt	gt
 80005d2:	ebd4 050c 	rsbsgt	r5, r4, ip
 80005d6:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 80005da:	bd70      	popgt	{r4, r5, r6, pc}
 80005dc:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 80005e0:	f04f 0e00 	mov.w	lr, #0
 80005e4:	3c01      	subs	r4, #1
 80005e6:	f300 80ab 	bgt.w	8000740 <__aeabi_dmul+0x238>
 80005ea:	f114 0f36 	cmn.w	r4, #54	; 0x36
 80005ee:	bfde      	ittt	le
 80005f0:	2000      	movle	r0, #0
 80005f2:	f001 4100 	andle.w	r1, r1, #2147483648	; 0x80000000
 80005f6:	bd70      	pople	{r4, r5, r6, pc}
 80005f8:	f1c4 0400 	rsb	r4, r4, #0
 80005fc:	3c20      	subs	r4, #32
 80005fe:	da35      	bge.n	800066c <__aeabi_dmul+0x164>
 8000600:	340c      	adds	r4, #12
 8000602:	dc1b      	bgt.n	800063c <__aeabi_dmul+0x134>
 8000604:	f104 0414 	add.w	r4, r4, #20
 8000608:	f1c4 0520 	rsb	r5, r4, #32
 800060c:	fa00 f305 	lsl.w	r3, r0, r5
 8000610:	fa20 f004 	lsr.w	r0, r0, r4
 8000614:	fa01 f205 	lsl.w	r2, r1, r5
 8000618:	ea40 0002 	orr.w	r0, r0, r2
 800061c:	f001 4200 	and.w	r2, r1, #2147483648	; 0x80000000
 8000620:	f021 4100 	bic.w	r1, r1, #2147483648	; 0x80000000
 8000624:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 8000628:	fa21 f604 	lsr.w	r6, r1, r4
 800062c:	eb42 0106 	adc.w	r1, r2, r6
 8000630:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 8000634:	bf08      	it	eq
 8000636:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 800063a:	bd70      	pop	{r4, r5, r6, pc}
 800063c:	f1c4 040c 	rsb	r4, r4, #12
 8000640:	f1c4 0520 	rsb	r5, r4, #32
 8000644:	fa00 f304 	lsl.w	r3, r0, r4
 8000648:	fa20 f005 	lsr.w	r0, r0, r5
 800064c:	fa01 f204 	lsl.w	r2, r1, r4
 8000650:	ea40 0002 	orr.w	r0, r0, r2
 8000654:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 8000658:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 800065c:	f141 0100 	adc.w	r1, r1, #0
 8000660:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 8000664:	bf08      	it	eq
 8000666:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 800066a:	bd70      	pop	{r4, r5, r6, pc}
 800066c:	f1c4 0520 	rsb	r5, r4, #32
 8000670:	fa00 f205 	lsl.w	r2, r0, r5
 8000674:	ea4e 0e02 	orr.w	lr, lr, r2
 8000678:	fa20 f304 	lsr.w	r3, r0, r4
 800067c:	fa01 f205 	lsl.w	r2, r1, r5
 8000680:	ea43 0302 	orr.w	r3, r3, r2
 8000684:	fa21 f004 	lsr.w	r0, r1, r4
 8000688:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 800068c:	fa21 f204 	lsr.w	r2, r1, r4
 8000690:	ea20 0002 	bic.w	r0, r0, r2
 8000694:	eb00 70d3 	add.w	r0, r0, r3, lsr #31
 8000698:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 800069c:	bf08      	it	eq
 800069e:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 80006a2:	bd70      	pop	{r4, r5, r6, pc}
 80006a4:	f094 0f00 	teq	r4, #0
 80006a8:	d10f      	bne.n	80006ca <__aeabi_dmul+0x1c2>
 80006aa:	f001 4600 	and.w	r6, r1, #2147483648	; 0x80000000
 80006ae:	0040      	lsls	r0, r0, #1
 80006b0:	eb41 0101 	adc.w	r1, r1, r1
 80006b4:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 80006b8:	bf08      	it	eq
 80006ba:	3c01      	subeq	r4, #1
 80006bc:	d0f7      	beq.n	80006ae <__aeabi_dmul+0x1a6>
 80006be:	ea41 0106 	orr.w	r1, r1, r6
 80006c2:	f095 0f00 	teq	r5, #0
 80006c6:	bf18      	it	ne
 80006c8:	4770      	bxne	lr
 80006ca:	f003 4600 	and.w	r6, r3, #2147483648	; 0x80000000
 80006ce:	0052      	lsls	r2, r2, #1
 80006d0:	eb43 0303 	adc.w	r3, r3, r3
 80006d4:	f413 1f80 	tst.w	r3, #1048576	; 0x100000
 80006d8:	bf08      	it	eq
 80006da:	3d01      	subeq	r5, #1
 80006dc:	d0f7      	beq.n	80006ce <__aeabi_dmul+0x1c6>
 80006de:	ea43 0306 	orr.w	r3, r3, r6
 80006e2:	4770      	bx	lr
 80006e4:	ea94 0f0c 	teq	r4, ip
 80006e8:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 80006ec:	bf18      	it	ne
 80006ee:	ea95 0f0c 	teqne	r5, ip
 80006f2:	d00c      	beq.n	800070e <__aeabi_dmul+0x206>
 80006f4:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 80006f8:	bf18      	it	ne
 80006fa:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 80006fe:	d1d1      	bne.n	80006a4 <__aeabi_dmul+0x19c>
 8000700:	ea81 0103 	eor.w	r1, r1, r3
 8000704:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 8000708:	f04f 0000 	mov.w	r0, #0
 800070c:	bd70      	pop	{r4, r5, r6, pc}
 800070e:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 8000712:	bf06      	itte	eq
 8000714:	4610      	moveq	r0, r2
 8000716:	4619      	moveq	r1, r3
 8000718:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 800071c:	d019      	beq.n	8000752 <__aeabi_dmul+0x24a>
 800071e:	ea94 0f0c 	teq	r4, ip
 8000722:	d102      	bne.n	800072a <__aeabi_dmul+0x222>
 8000724:	ea50 3601 	orrs.w	r6, r0, r1, lsl #12
 8000728:	d113      	bne.n	8000752 <__aeabi_dmul+0x24a>
 800072a:	ea95 0f0c 	teq	r5, ip
 800072e:	d105      	bne.n	800073c <__aeabi_dmul+0x234>
 8000730:	ea52 3603 	orrs.w	r6, r2, r3, lsl #12
 8000734:	bf1c      	itt	ne
 8000736:	4610      	movne	r0, r2
 8000738:	4619      	movne	r1, r3
 800073a:	d10a      	bne.n	8000752 <__aeabi_dmul+0x24a>
 800073c:	ea81 0103 	eor.w	r1, r1, r3
 8000740:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 8000744:	f041 41fe 	orr.w	r1, r1, #2130706432	; 0x7f000000
 8000748:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 800074c:	f04f 0000 	mov.w	r0, #0
 8000750:	bd70      	pop	{r4, r5, r6, pc}
 8000752:	f041 41fe 	orr.w	r1, r1, #2130706432	; 0x7f000000
 8000756:	f441 0178 	orr.w	r1, r1, #16252928	; 0xf80000
 800075a:	bd70      	pop	{r4, r5, r6, pc}

0800075c <__aeabi_ddiv>:
 800075c:	b570      	push	{r4, r5, r6, lr}
 800075e:	f04f 0cff 	mov.w	ip, #255	; 0xff
 8000762:	f44c 6ce0 	orr.w	ip, ip, #1792	; 0x700
 8000766:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 800076a:	bf1d      	ittte	ne
 800076c:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 8000770:	ea94 0f0c 	teqne	r4, ip
 8000774:	ea95 0f0c 	teqne	r5, ip
 8000778:	f000 f8a7 	bleq	80008ca <__aeabi_ddiv+0x16e>
 800077c:	eba4 0405 	sub.w	r4, r4, r5
 8000780:	ea81 0e03 	eor.w	lr, r1, r3
 8000784:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 8000788:	ea4f 3101 	mov.w	r1, r1, lsl #12
 800078c:	f000 8088 	beq.w	80008a0 <__aeabi_ddiv+0x144>
 8000790:	ea4f 3303 	mov.w	r3, r3, lsl #12
 8000794:	f04f 5580 	mov.w	r5, #268435456	; 0x10000000
 8000798:	ea45 1313 	orr.w	r3, r5, r3, lsr #4
 800079c:	ea43 6312 	orr.w	r3, r3, r2, lsr #24
 80007a0:	ea4f 2202 	mov.w	r2, r2, lsl #8
 80007a4:	ea45 1511 	orr.w	r5, r5, r1, lsr #4
 80007a8:	ea45 6510 	orr.w	r5, r5, r0, lsr #24
 80007ac:	ea4f 2600 	mov.w	r6, r0, lsl #8
 80007b0:	f00e 4100 	and.w	r1, lr, #2147483648	; 0x80000000
 80007b4:	429d      	cmp	r5, r3
 80007b6:	bf08      	it	eq
 80007b8:	4296      	cmpeq	r6, r2
 80007ba:	f144 04fd 	adc.w	r4, r4, #253	; 0xfd
 80007be:	f504 7440 	add.w	r4, r4, #768	; 0x300
 80007c2:	d202      	bcs.n	80007ca <__aeabi_ddiv+0x6e>
 80007c4:	085b      	lsrs	r3, r3, #1
 80007c6:	ea4f 0232 	mov.w	r2, r2, rrx
 80007ca:	1ab6      	subs	r6, r6, r2
 80007cc:	eb65 0503 	sbc.w	r5, r5, r3
 80007d0:	085b      	lsrs	r3, r3, #1
 80007d2:	ea4f 0232 	mov.w	r2, r2, rrx
 80007d6:	f44f 1080 	mov.w	r0, #1048576	; 0x100000
 80007da:	f44f 2c00 	mov.w	ip, #524288	; 0x80000
 80007de:	ebb6 0e02 	subs.w	lr, r6, r2
 80007e2:	eb75 0e03 	sbcs.w	lr, r5, r3
 80007e6:	bf22      	ittt	cs
 80007e8:	1ab6      	subcs	r6, r6, r2
 80007ea:	4675      	movcs	r5, lr
 80007ec:	ea40 000c 	orrcs.w	r0, r0, ip
 80007f0:	085b      	lsrs	r3, r3, #1
 80007f2:	ea4f 0232 	mov.w	r2, r2, rrx
 80007f6:	ebb6 0e02 	subs.w	lr, r6, r2
 80007fa:	eb75 0e03 	sbcs.w	lr, r5, r3
 80007fe:	bf22      	ittt	cs
 8000800:	1ab6      	subcs	r6, r6, r2
 8000802:	4675      	movcs	r5, lr
 8000804:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
 8000808:	085b      	lsrs	r3, r3, #1
 800080a:	ea4f 0232 	mov.w	r2, r2, rrx
 800080e:	ebb6 0e02 	subs.w	lr, r6, r2
 8000812:	eb75 0e03 	sbcs.w	lr, r5, r3
 8000816:	bf22      	ittt	cs
 8000818:	1ab6      	subcs	r6, r6, r2
 800081a:	4675      	movcs	r5, lr
 800081c:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
 8000820:	085b      	lsrs	r3, r3, #1
 8000822:	ea4f 0232 	mov.w	r2, r2, rrx
 8000826:	ebb6 0e02 	subs.w	lr, r6, r2
 800082a:	eb75 0e03 	sbcs.w	lr, r5, r3
 800082e:	bf22      	ittt	cs
 8000830:	1ab6      	subcs	r6, r6, r2
 8000832:	4675      	movcs	r5, lr
 8000834:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
 8000838:	ea55 0e06 	orrs.w	lr, r5, r6
 800083c:	d018      	beq.n	8000870 <__aeabi_ddiv+0x114>
 800083e:	ea4f 1505 	mov.w	r5, r5, lsl #4
 8000842:	ea45 7516 	orr.w	r5, r5, r6, lsr #28
 8000846:	ea4f 1606 	mov.w	r6, r6, lsl #4
 800084a:	ea4f 03c3 	mov.w	r3, r3, lsl #3
 800084e:	ea43 7352 	orr.w	r3, r3, r2, lsr #29
 8000852:	ea4f 02c2 	mov.w	r2, r2, lsl #3
 8000856:	ea5f 1c1c 	movs.w	ip, ip, lsr #4
 800085a:	d1c0      	bne.n	80007de <__aeabi_ddiv+0x82>
 800085c:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 8000860:	d10b      	bne.n	800087a <__aeabi_ddiv+0x11e>
 8000862:	ea41 0100 	orr.w	r1, r1, r0
 8000866:	f04f 0000 	mov.w	r0, #0
 800086a:	f04f 4c00 	mov.w	ip, #2147483648	; 0x80000000
 800086e:	e7b6      	b.n	80007de <__aeabi_ddiv+0x82>
 8000870:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 8000874:	bf04      	itt	eq
 8000876:	4301      	orreq	r1, r0
 8000878:	2000      	moveq	r0, #0
 800087a:	f1b4 0cfd 	subs.w	ip, r4, #253	; 0xfd
 800087e:	bf88      	it	hi
 8000880:	f5bc 6fe0 	cmphi.w	ip, #1792	; 0x700
 8000884:	f63f aeaf 	bhi.w	80005e6 <__aeabi_dmul+0xde>
 8000888:	ebb5 0c03 	subs.w	ip, r5, r3
 800088c:	bf04      	itt	eq
 800088e:	ebb6 0c02 	subseq.w	ip, r6, r2
 8000892:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 8000896:	f150 0000 	adcs.w	r0, r0, #0
 800089a:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 800089e:	bd70      	pop	{r4, r5, r6, pc}
 80008a0:	f00e 4e00 	and.w	lr, lr, #2147483648	; 0x80000000
 80008a4:	ea4e 3111 	orr.w	r1, lr, r1, lsr #12
 80008a8:	eb14 045c 	adds.w	r4, r4, ip, lsr #1
 80008ac:	bfc2      	ittt	gt
 80008ae:	ebd4 050c 	rsbsgt	r5, r4, ip
 80008b2:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 80008b6:	bd70      	popgt	{r4, r5, r6, pc}
 80008b8:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 80008bc:	f04f 0e00 	mov.w	lr, #0
 80008c0:	3c01      	subs	r4, #1
 80008c2:	e690      	b.n	80005e6 <__aeabi_dmul+0xde>
 80008c4:	ea45 0e06 	orr.w	lr, r5, r6
 80008c8:	e68d      	b.n	80005e6 <__aeabi_dmul+0xde>
 80008ca:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 80008ce:	ea94 0f0c 	teq	r4, ip
 80008d2:	bf08      	it	eq
 80008d4:	ea95 0f0c 	teqeq	r5, ip
 80008d8:	f43f af3b 	beq.w	8000752 <__aeabi_dmul+0x24a>
 80008dc:	ea94 0f0c 	teq	r4, ip
 80008e0:	d10a      	bne.n	80008f8 <__aeabi_ddiv+0x19c>
 80008e2:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 80008e6:	f47f af34 	bne.w	8000752 <__aeabi_dmul+0x24a>
 80008ea:	ea95 0f0c 	teq	r5, ip
 80008ee:	f47f af25 	bne.w	800073c <__aeabi_dmul+0x234>
 80008f2:	4610      	mov	r0, r2
 80008f4:	4619      	mov	r1, r3
 80008f6:	e72c      	b.n	8000752 <__aeabi_dmul+0x24a>
 80008f8:	ea95 0f0c 	teq	r5, ip
 80008fc:	d106      	bne.n	800090c <__aeabi_ddiv+0x1b0>
 80008fe:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 8000902:	f43f aefd 	beq.w	8000700 <__aeabi_dmul+0x1f8>
 8000906:	4610      	mov	r0, r2
 8000908:	4619      	mov	r1, r3
 800090a:	e722      	b.n	8000752 <__aeabi_dmul+0x24a>
 800090c:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 8000910:	bf18      	it	ne
 8000912:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 8000916:	f47f aec5 	bne.w	80006a4 <__aeabi_dmul+0x19c>
 800091a:	ea50 0441 	orrs.w	r4, r0, r1, lsl #1
 800091e:	f47f af0d 	bne.w	800073c <__aeabi_dmul+0x234>
 8000922:	ea52 0543 	orrs.w	r5, r2, r3, lsl #1
 8000926:	f47f aeeb 	bne.w	8000700 <__aeabi_dmul+0x1f8>
 800092a:	e712      	b.n	8000752 <__aeabi_dmul+0x24a>

0800092c <__gedf2>:
 800092c:	f04f 3cff 	mov.w	ip, #4294967295	; 0xffffffff
 8000930:	e006      	b.n	8000940 <__cmpdf2+0x4>
 8000932:	bf00      	nop

08000934 <__ledf2>:
 8000934:	f04f 0c01 	mov.w	ip, #1
 8000938:	e002      	b.n	8000940 <__cmpdf2+0x4>
 800093a:	bf00      	nop

0800093c <__cmpdf2>:
 800093c:	f04f 0c01 	mov.w	ip, #1
 8000940:	f84d cd04 	str.w	ip, [sp, #-4]!
 8000944:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000948:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 800094c:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000950:	bf18      	it	ne
 8000952:	ea7f 5c6c 	mvnsne.w	ip, ip, asr #21
 8000956:	d01b      	beq.n	8000990 <__cmpdf2+0x54>
 8000958:	b001      	add	sp, #4
 800095a:	ea50 0c41 	orrs.w	ip, r0, r1, lsl #1
 800095e:	bf0c      	ite	eq
 8000960:	ea52 0c43 	orrseq.w	ip, r2, r3, lsl #1
 8000964:	ea91 0f03 	teqne	r1, r3
 8000968:	bf02      	ittt	eq
 800096a:	ea90 0f02 	teqeq	r0, r2
 800096e:	2000      	moveq	r0, #0
 8000970:	4770      	bxeq	lr
 8000972:	f110 0f00 	cmn.w	r0, #0
 8000976:	ea91 0f03 	teq	r1, r3
 800097a:	bf58      	it	pl
 800097c:	4299      	cmppl	r1, r3
 800097e:	bf08      	it	eq
 8000980:	4290      	cmpeq	r0, r2
 8000982:	bf2c      	ite	cs
 8000984:	17d8      	asrcs	r0, r3, #31
 8000986:	ea6f 70e3 	mvncc.w	r0, r3, asr #31
 800098a:	f040 0001 	orr.w	r0, r0, #1
 800098e:	4770      	bx	lr
 8000990:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000994:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000998:	d102      	bne.n	80009a0 <__cmpdf2+0x64>
 800099a:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 800099e:	d107      	bne.n	80009b0 <__cmpdf2+0x74>
 80009a0:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 80009a4:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 80009a8:	d1d6      	bne.n	8000958 <__cmpdf2+0x1c>
 80009aa:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 80009ae:	d0d3      	beq.n	8000958 <__cmpdf2+0x1c>
 80009b0:	f85d 0b04 	ldr.w	r0, [sp], #4
 80009b4:	4770      	bx	lr
 80009b6:	bf00      	nop

080009b8 <__aeabi_cdrcmple>:
 80009b8:	4684      	mov	ip, r0
 80009ba:	4610      	mov	r0, r2
 80009bc:	4662      	mov	r2, ip
 80009be:	468c      	mov	ip, r1
 80009c0:	4619      	mov	r1, r3
 80009c2:	4663      	mov	r3, ip
 80009c4:	e000      	b.n	80009c8 <__aeabi_cdcmpeq>
 80009c6:	bf00      	nop

080009c8 <__aeabi_cdcmpeq>:
 80009c8:	b501      	push	{r0, lr}
 80009ca:	f7ff ffb7 	bl	800093c <__cmpdf2>
 80009ce:	2800      	cmp	r0, #0
 80009d0:	bf48      	it	mi
 80009d2:	f110 0f00 	cmnmi.w	r0, #0
 80009d6:	bd01      	pop	{r0, pc}

080009d8 <__aeabi_dcmpeq>:
 80009d8:	f84d ed08 	str.w	lr, [sp, #-8]!
 80009dc:	f7ff fff4 	bl	80009c8 <__aeabi_cdcmpeq>
 80009e0:	bf0c      	ite	eq
 80009e2:	2001      	moveq	r0, #1
 80009e4:	2000      	movne	r0, #0
 80009e6:	f85d fb08 	ldr.w	pc, [sp], #8
 80009ea:	bf00      	nop

080009ec <__aeabi_dcmplt>:
 80009ec:	f84d ed08 	str.w	lr, [sp, #-8]!
 80009f0:	f7ff ffea 	bl	80009c8 <__aeabi_cdcmpeq>
 80009f4:	bf34      	ite	cc
 80009f6:	2001      	movcc	r0, #1
 80009f8:	2000      	movcs	r0, #0
 80009fa:	f85d fb08 	ldr.w	pc, [sp], #8
 80009fe:	bf00      	nop

08000a00 <__aeabi_dcmple>:
 8000a00:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a04:	f7ff ffe0 	bl	80009c8 <__aeabi_cdcmpeq>
 8000a08:	bf94      	ite	ls
 8000a0a:	2001      	movls	r0, #1
 8000a0c:	2000      	movhi	r0, #0
 8000a0e:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a12:	bf00      	nop

08000a14 <__aeabi_dcmpge>:
 8000a14:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a18:	f7ff ffce 	bl	80009b8 <__aeabi_cdrcmple>
 8000a1c:	bf94      	ite	ls
 8000a1e:	2001      	movls	r0, #1
 8000a20:	2000      	movhi	r0, #0
 8000a22:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a26:	bf00      	nop

08000a28 <__aeabi_dcmpgt>:
 8000a28:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a2c:	f7ff ffc4 	bl	80009b8 <__aeabi_cdrcmple>
 8000a30:	bf34      	ite	cc
 8000a32:	2001      	movcc	r0, #1
 8000a34:	2000      	movcs	r0, #0
 8000a36:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a3a:	bf00      	nop

08000a3c <__aeabi_dcmpun>:
 8000a3c:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000a40:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a44:	d102      	bne.n	8000a4c <__aeabi_dcmpun+0x10>
 8000a46:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 8000a4a:	d10a      	bne.n	8000a62 <__aeabi_dcmpun+0x26>
 8000a4c:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000a50:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a54:	d102      	bne.n	8000a5c <__aeabi_dcmpun+0x20>
 8000a56:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 8000a5a:	d102      	bne.n	8000a62 <__aeabi_dcmpun+0x26>
 8000a5c:	f04f 0000 	mov.w	r0, #0
 8000a60:	4770      	bx	lr
 8000a62:	f04f 0001 	mov.w	r0, #1
 8000a66:	4770      	bx	lr

08000a68 <__aeabi_d2iz>:
 8000a68:	ea4f 0241 	mov.w	r2, r1, lsl #1
 8000a6c:	f512 1200 	adds.w	r2, r2, #2097152	; 0x200000
 8000a70:	d215      	bcs.n	8000a9e <__aeabi_d2iz+0x36>
 8000a72:	d511      	bpl.n	8000a98 <__aeabi_d2iz+0x30>
 8000a74:	f46f 7378 	mvn.w	r3, #992	; 0x3e0
 8000a78:	ebb3 5262 	subs.w	r2, r3, r2, asr #21
 8000a7c:	d912      	bls.n	8000aa4 <__aeabi_d2iz+0x3c>
 8000a7e:	ea4f 23c1 	mov.w	r3, r1, lsl #11
 8000a82:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 8000a86:	ea43 5350 	orr.w	r3, r3, r0, lsr #21
 8000a8a:	f011 4f00 	tst.w	r1, #2147483648	; 0x80000000
 8000a8e:	fa23 f002 	lsr.w	r0, r3, r2
 8000a92:	bf18      	it	ne
 8000a94:	4240      	negne	r0, r0
 8000a96:	4770      	bx	lr
 8000a98:	f04f 0000 	mov.w	r0, #0
 8000a9c:	4770      	bx	lr
 8000a9e:	ea50 3001 	orrs.w	r0, r0, r1, lsl #12
 8000aa2:	d105      	bne.n	8000ab0 <__aeabi_d2iz+0x48>
 8000aa4:	f011 4000 	ands.w	r0, r1, #2147483648	; 0x80000000
 8000aa8:	bf08      	it	eq
 8000aaa:	f06f 4000 	mvneq.w	r0, #2147483648	; 0x80000000
 8000aae:	4770      	bx	lr
 8000ab0:	f04f 0000 	mov.w	r0, #0
 8000ab4:	4770      	bx	lr
 8000ab6:	bf00      	nop

08000ab8 <__aeabi_frsub>:
 8000ab8:	f080 4000 	eor.w	r0, r0, #2147483648	; 0x80000000
 8000abc:	e002      	b.n	8000ac4 <__addsf3>
 8000abe:	bf00      	nop

08000ac0 <__aeabi_fsub>:
 8000ac0:	f081 4100 	eor.w	r1, r1, #2147483648	; 0x80000000

08000ac4 <__addsf3>:
 8000ac4:	0042      	lsls	r2, r0, #1
 8000ac6:	bf1f      	itttt	ne
 8000ac8:	ea5f 0341 	movsne.w	r3, r1, lsl #1
 8000acc:	ea92 0f03 	teqne	r2, r3
 8000ad0:	ea7f 6c22 	mvnsne.w	ip, r2, asr #24
 8000ad4:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
 8000ad8:	d06a      	beq.n	8000bb0 <__addsf3+0xec>
 8000ada:	ea4f 6212 	mov.w	r2, r2, lsr #24
 8000ade:	ebd2 6313 	rsbs	r3, r2, r3, lsr #24
 8000ae2:	bfc1      	itttt	gt
 8000ae4:	18d2      	addgt	r2, r2, r3
 8000ae6:	4041      	eorgt	r1, r0
 8000ae8:	4048      	eorgt	r0, r1
 8000aea:	4041      	eorgt	r1, r0
 8000aec:	bfb8      	it	lt
 8000aee:	425b      	neglt	r3, r3
 8000af0:	2b19      	cmp	r3, #25
 8000af2:	bf88      	it	hi
 8000af4:	4770      	bxhi	lr
 8000af6:	f010 4f00 	tst.w	r0, #2147483648	; 0x80000000
 8000afa:	f440 0000 	orr.w	r0, r0, #8388608	; 0x800000
 8000afe:	f020 407f 	bic.w	r0, r0, #4278190080	; 0xff000000
 8000b02:	bf18      	it	ne
 8000b04:	4240      	negne	r0, r0
 8000b06:	f011 4f00 	tst.w	r1, #2147483648	; 0x80000000
 8000b0a:	f441 0100 	orr.w	r1, r1, #8388608	; 0x800000
 8000b0e:	f021 417f 	bic.w	r1, r1, #4278190080	; 0xff000000
 8000b12:	bf18      	it	ne
 8000b14:	4249      	negne	r1, r1
 8000b16:	ea92 0f03 	teq	r2, r3
 8000b1a:	d03f      	beq.n	8000b9c <__addsf3+0xd8>
 8000b1c:	f1a2 0201 	sub.w	r2, r2, #1
 8000b20:	fa41 fc03 	asr.w	ip, r1, r3
 8000b24:	eb10 000c 	adds.w	r0, r0, ip
 8000b28:	f1c3 0320 	rsb	r3, r3, #32
 8000b2c:	fa01 f103 	lsl.w	r1, r1, r3
 8000b30:	f000 4300 	and.w	r3, r0, #2147483648	; 0x80000000
 8000b34:	d502      	bpl.n	8000b3c <__addsf3+0x78>
 8000b36:	4249      	negs	r1, r1
 8000b38:	eb60 0040 	sbc.w	r0, r0, r0, lsl #1
 8000b3c:	f5b0 0f00 	cmp.w	r0, #8388608	; 0x800000
 8000b40:	d313      	bcc.n	8000b6a <__addsf3+0xa6>
 8000b42:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 8000b46:	d306      	bcc.n	8000b56 <__addsf3+0x92>
 8000b48:	0840      	lsrs	r0, r0, #1
 8000b4a:	ea4f 0131 	mov.w	r1, r1, rrx
 8000b4e:	f102 0201 	add.w	r2, r2, #1
 8000b52:	2afe      	cmp	r2, #254	; 0xfe
 8000b54:	d251      	bcs.n	8000bfa <__addsf3+0x136>
 8000b56:	f1b1 4f00 	cmp.w	r1, #2147483648	; 0x80000000
 8000b5a:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
 8000b5e:	bf08      	it	eq
 8000b60:	f020 0001 	biceq.w	r0, r0, #1
 8000b64:	ea40 0003 	orr.w	r0, r0, r3
 8000b68:	4770      	bx	lr
 8000b6a:	0049      	lsls	r1, r1, #1
 8000b6c:	eb40 0000 	adc.w	r0, r0, r0
 8000b70:	3a01      	subs	r2, #1
 8000b72:	bf28      	it	cs
 8000b74:	f5b0 0f00 	cmpcs.w	r0, #8388608	; 0x800000
 8000b78:	d2ed      	bcs.n	8000b56 <__addsf3+0x92>
 8000b7a:	fab0 fc80 	clz	ip, r0
 8000b7e:	f1ac 0c08 	sub.w	ip, ip, #8
 8000b82:	ebb2 020c 	subs.w	r2, r2, ip
 8000b86:	fa00 f00c 	lsl.w	r0, r0, ip
 8000b8a:	bfaa      	itet	ge
 8000b8c:	eb00 50c2 	addge.w	r0, r0, r2, lsl #23
 8000b90:	4252      	neglt	r2, r2
 8000b92:	4318      	orrge	r0, r3
 8000b94:	bfbc      	itt	lt
 8000b96:	40d0      	lsrlt	r0, r2
 8000b98:	4318      	orrlt	r0, r3
 8000b9a:	4770      	bx	lr
 8000b9c:	f092 0f00 	teq	r2, #0
 8000ba0:	f481 0100 	eor.w	r1, r1, #8388608	; 0x800000
 8000ba4:	bf06      	itte	eq
 8000ba6:	f480 0000 	eoreq.w	r0, r0, #8388608	; 0x800000
 8000baa:	3201      	addeq	r2, #1
 8000bac:	3b01      	subne	r3, #1
 8000bae:	e7b5      	b.n	8000b1c <__addsf3+0x58>
 8000bb0:	ea4f 0341 	mov.w	r3, r1, lsl #1
 8000bb4:	ea7f 6c22 	mvns.w	ip, r2, asr #24
 8000bb8:	bf18      	it	ne
 8000bba:	ea7f 6c23 	mvnsne.w	ip, r3, asr #24
 8000bbe:	d021      	beq.n	8000c04 <__addsf3+0x140>
 8000bc0:	ea92 0f03 	teq	r2, r3
 8000bc4:	d004      	beq.n	8000bd0 <__addsf3+0x10c>
 8000bc6:	f092 0f00 	teq	r2, #0
 8000bca:	bf08      	it	eq
 8000bcc:	4608      	moveq	r0, r1
 8000bce:	4770      	bx	lr
 8000bd0:	ea90 0f01 	teq	r0, r1
 8000bd4:	bf1c      	itt	ne
 8000bd6:	2000      	movne	r0, #0
 8000bd8:	4770      	bxne	lr
 8000bda:	f012 4f7f 	tst.w	r2, #4278190080	; 0xff000000
 8000bde:	d104      	bne.n	8000bea <__addsf3+0x126>
 8000be0:	0040      	lsls	r0, r0, #1
 8000be2:	bf28      	it	cs
 8000be4:	f040 4000 	orrcs.w	r0, r0, #2147483648	; 0x80000000
 8000be8:	4770      	bx	lr
 8000bea:	f112 7200 	adds.w	r2, r2, #33554432	; 0x2000000
 8000bee:	bf3c      	itt	cc
 8000bf0:	f500 0000 	addcc.w	r0, r0, #8388608	; 0x800000
 8000bf4:	4770      	bxcc	lr
 8000bf6:	f000 4300 	and.w	r3, r0, #2147483648	; 0x80000000
 8000bfa:	f043 40fe 	orr.w	r0, r3, #2130706432	; 0x7f000000
 8000bfe:	f440 0000 	orr.w	r0, r0, #8388608	; 0x800000
 8000c02:	4770      	bx	lr
 8000c04:	ea7f 6222 	mvns.w	r2, r2, asr #24
 8000c08:	bf16      	itet	ne
 8000c0a:	4608      	movne	r0, r1
 8000c0c:	ea7f 6323 	mvnseq.w	r3, r3, asr #24
 8000c10:	4601      	movne	r1, r0
 8000c12:	0242      	lsls	r2, r0, #9
 8000c14:	bf06      	itte	eq
 8000c16:	ea5f 2341 	movseq.w	r3, r1, lsl #9
 8000c1a:	ea90 0f01 	teqeq	r0, r1
 8000c1e:	f440 0080 	orrne.w	r0, r0, #4194304	; 0x400000
 8000c22:	4770      	bx	lr

08000c24 <__aeabi_ui2f>:
 8000c24:	f04f 0300 	mov.w	r3, #0
 8000c28:	e004      	b.n	8000c34 <__aeabi_i2f+0x8>
 8000c2a:	bf00      	nop

08000c2c <__aeabi_i2f>:
 8000c2c:	f010 4300 	ands.w	r3, r0, #2147483648	; 0x80000000
 8000c30:	bf48      	it	mi
 8000c32:	4240      	negmi	r0, r0
 8000c34:	ea5f 0c00 	movs.w	ip, r0
 8000c38:	bf08      	it	eq
 8000c3a:	4770      	bxeq	lr
 8000c3c:	f043 4396 	orr.w	r3, r3, #1258291200	; 0x4b000000
 8000c40:	4601      	mov	r1, r0
 8000c42:	f04f 0000 	mov.w	r0, #0
 8000c46:	e01c      	b.n	8000c82 <__aeabi_l2f+0x2a>

08000c48 <__aeabi_ul2f>:
 8000c48:	ea50 0201 	orrs.w	r2, r0, r1
 8000c4c:	bf08      	it	eq
 8000c4e:	4770      	bxeq	lr
 8000c50:	f04f 0300 	mov.w	r3, #0
 8000c54:	e00a      	b.n	8000c6c <__aeabi_l2f+0x14>
 8000c56:	bf00      	nop

08000c58 <__aeabi_l2f>:
 8000c58:	ea50 0201 	orrs.w	r2, r0, r1
 8000c5c:	bf08      	it	eq
 8000c5e:	4770      	bxeq	lr
 8000c60:	f011 4300 	ands.w	r3, r1, #2147483648	; 0x80000000
 8000c64:	d502      	bpl.n	8000c6c <__aeabi_l2f+0x14>
 8000c66:	4240      	negs	r0, r0
 8000c68:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 8000c6c:	ea5f 0c01 	movs.w	ip, r1
 8000c70:	bf02      	ittt	eq
 8000c72:	4684      	moveq	ip, r0
 8000c74:	4601      	moveq	r1, r0
 8000c76:	2000      	moveq	r0, #0
 8000c78:	f043 43b6 	orr.w	r3, r3, #1526726656	; 0x5b000000
 8000c7c:	bf08      	it	eq
 8000c7e:	f1a3 5380 	subeq.w	r3, r3, #268435456	; 0x10000000
 8000c82:	f5a3 0300 	sub.w	r3, r3, #8388608	; 0x800000
 8000c86:	fabc f28c 	clz	r2, ip
 8000c8a:	3a08      	subs	r2, #8
 8000c8c:	eba3 53c2 	sub.w	r3, r3, r2, lsl #23
 8000c90:	db10      	blt.n	8000cb4 <__aeabi_l2f+0x5c>
 8000c92:	fa01 fc02 	lsl.w	ip, r1, r2
 8000c96:	4463      	add	r3, ip
 8000c98:	fa00 fc02 	lsl.w	ip, r0, r2
 8000c9c:	f1c2 0220 	rsb	r2, r2, #32
 8000ca0:	f1bc 4f00 	cmp.w	ip, #2147483648	; 0x80000000
 8000ca4:	fa20 f202 	lsr.w	r2, r0, r2
 8000ca8:	eb43 0002 	adc.w	r0, r3, r2
 8000cac:	bf08      	it	eq
 8000cae:	f020 0001 	biceq.w	r0, r0, #1
 8000cb2:	4770      	bx	lr
 8000cb4:	f102 0220 	add.w	r2, r2, #32
 8000cb8:	fa01 fc02 	lsl.w	ip, r1, r2
 8000cbc:	f1c2 0220 	rsb	r2, r2, #32
 8000cc0:	ea50 004c 	orrs.w	r0, r0, ip, lsl #1
 8000cc4:	fa21 f202 	lsr.w	r2, r1, r2
 8000cc8:	eb43 0002 	adc.w	r0, r3, r2
 8000ccc:	bf08      	it	eq
 8000cce:	ea20 70dc 	biceq.w	r0, r0, ip, lsr #31
 8000cd2:	4770      	bx	lr

08000cd4 <__aeabi_uldivmod>:
 8000cd4:	b953      	cbnz	r3, 8000cec <__aeabi_uldivmod+0x18>
 8000cd6:	b94a      	cbnz	r2, 8000cec <__aeabi_uldivmod+0x18>
 8000cd8:	2900      	cmp	r1, #0
 8000cda:	bf08      	it	eq
 8000cdc:	2800      	cmpeq	r0, #0
 8000cde:	bf1c      	itt	ne
 8000ce0:	f04f 31ff 	movne.w	r1, #4294967295	; 0xffffffff
 8000ce4:	f04f 30ff 	movne.w	r0, #4294967295	; 0xffffffff
 8000ce8:	f000 b96e 	b.w	8000fc8 <__aeabi_idiv0>
 8000cec:	f1ad 0c08 	sub.w	ip, sp, #8
 8000cf0:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 8000cf4:	f000 f806 	bl	8000d04 <__udivmoddi4>
 8000cf8:	f8dd e004 	ldr.w	lr, [sp, #4]
 8000cfc:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8000d00:	b004      	add	sp, #16
 8000d02:	4770      	bx	lr

08000d04 <__udivmoddi4>:
 8000d04:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000d08:	9e08      	ldr	r6, [sp, #32]
 8000d0a:	460d      	mov	r5, r1
 8000d0c:	4604      	mov	r4, r0
 8000d0e:	468e      	mov	lr, r1
 8000d10:	2b00      	cmp	r3, #0
 8000d12:	f040 8083 	bne.w	8000e1c <__udivmoddi4+0x118>
 8000d16:	428a      	cmp	r2, r1
 8000d18:	4617      	mov	r7, r2
 8000d1a:	d947      	bls.n	8000dac <__udivmoddi4+0xa8>
 8000d1c:	fab2 f382 	clz	r3, r2
 8000d20:	b14b      	cbz	r3, 8000d36 <__udivmoddi4+0x32>
 8000d22:	f1c3 0120 	rsb	r1, r3, #32
 8000d26:	fa05 fe03 	lsl.w	lr, r5, r3
 8000d2a:	fa20 f101 	lsr.w	r1, r0, r1
 8000d2e:	409f      	lsls	r7, r3
 8000d30:	ea41 0e0e 	orr.w	lr, r1, lr
 8000d34:	409c      	lsls	r4, r3
 8000d36:	ea4f 4817 	mov.w	r8, r7, lsr #16
 8000d3a:	fbbe fcf8 	udiv	ip, lr, r8
 8000d3e:	fa1f f987 	uxth.w	r9, r7
 8000d42:	fb08 e21c 	mls	r2, r8, ip, lr
 8000d46:	fb0c f009 	mul.w	r0, ip, r9
 8000d4a:	0c21      	lsrs	r1, r4, #16
 8000d4c:	ea41 4202 	orr.w	r2, r1, r2, lsl #16
 8000d50:	4290      	cmp	r0, r2
 8000d52:	d90a      	bls.n	8000d6a <__udivmoddi4+0x66>
 8000d54:	18ba      	adds	r2, r7, r2
 8000d56:	f10c 31ff 	add.w	r1, ip, #4294967295	; 0xffffffff
 8000d5a:	f080 8118 	bcs.w	8000f8e <__udivmoddi4+0x28a>
 8000d5e:	4290      	cmp	r0, r2
 8000d60:	f240 8115 	bls.w	8000f8e <__udivmoddi4+0x28a>
 8000d64:	f1ac 0c02 	sub.w	ip, ip, #2
 8000d68:	443a      	add	r2, r7
 8000d6a:	1a12      	subs	r2, r2, r0
 8000d6c:	fbb2 f0f8 	udiv	r0, r2, r8
 8000d70:	fb08 2210 	mls	r2, r8, r0, r2
 8000d74:	fb00 f109 	mul.w	r1, r0, r9
 8000d78:	b2a4      	uxth	r4, r4
 8000d7a:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
 8000d7e:	42a1      	cmp	r1, r4
 8000d80:	d909      	bls.n	8000d96 <__udivmoddi4+0x92>
 8000d82:	193c      	adds	r4, r7, r4
 8000d84:	f100 32ff 	add.w	r2, r0, #4294967295	; 0xffffffff
 8000d88:	f080 8103 	bcs.w	8000f92 <__udivmoddi4+0x28e>
 8000d8c:	42a1      	cmp	r1, r4
 8000d8e:	f240 8100 	bls.w	8000f92 <__udivmoddi4+0x28e>
 8000d92:	3802      	subs	r0, #2
 8000d94:	443c      	add	r4, r7
 8000d96:	1a64      	subs	r4, r4, r1
 8000d98:	2100      	movs	r1, #0
 8000d9a:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
 8000d9e:	b11e      	cbz	r6, 8000da8 <__udivmoddi4+0xa4>
 8000da0:	2200      	movs	r2, #0
 8000da2:	40dc      	lsrs	r4, r3
 8000da4:	e9c6 4200 	strd	r4, r2, [r6]
 8000da8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000dac:	b902      	cbnz	r2, 8000db0 <__udivmoddi4+0xac>
 8000dae:	deff      	udf	#255	; 0xff
 8000db0:	fab2 f382 	clz	r3, r2
 8000db4:	2b00      	cmp	r3, #0
 8000db6:	d14f      	bne.n	8000e58 <__udivmoddi4+0x154>
 8000db8:	1a8d      	subs	r5, r1, r2
 8000dba:	2101      	movs	r1, #1
 8000dbc:	ea4f 4e12 	mov.w	lr, r2, lsr #16
 8000dc0:	fa1f f882 	uxth.w	r8, r2
 8000dc4:	fbb5 fcfe 	udiv	ip, r5, lr
 8000dc8:	fb0e 551c 	mls	r5, lr, ip, r5
 8000dcc:	fb08 f00c 	mul.w	r0, r8, ip
 8000dd0:	0c22      	lsrs	r2, r4, #16
 8000dd2:	ea42 4505 	orr.w	r5, r2, r5, lsl #16
 8000dd6:	42a8      	cmp	r0, r5
 8000dd8:	d907      	bls.n	8000dea <__udivmoddi4+0xe6>
 8000dda:	197d      	adds	r5, r7, r5
 8000ddc:	f10c 32ff 	add.w	r2, ip, #4294967295	; 0xffffffff
 8000de0:	d202      	bcs.n	8000de8 <__udivmoddi4+0xe4>
 8000de2:	42a8      	cmp	r0, r5
 8000de4:	f200 80e9 	bhi.w	8000fba <__udivmoddi4+0x2b6>
 8000de8:	4694      	mov	ip, r2
 8000dea:	1a2d      	subs	r5, r5, r0
 8000dec:	fbb5 f0fe 	udiv	r0, r5, lr
 8000df0:	fb0e 5510 	mls	r5, lr, r0, r5
 8000df4:	fb08 f800 	mul.w	r8, r8, r0
 8000df8:	b2a4      	uxth	r4, r4
 8000dfa:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
 8000dfe:	45a0      	cmp	r8, r4
 8000e00:	d907      	bls.n	8000e12 <__udivmoddi4+0x10e>
 8000e02:	193c      	adds	r4, r7, r4
 8000e04:	f100 32ff 	add.w	r2, r0, #4294967295	; 0xffffffff
 8000e08:	d202      	bcs.n	8000e10 <__udivmoddi4+0x10c>
 8000e0a:	45a0      	cmp	r8, r4
 8000e0c:	f200 80d9 	bhi.w	8000fc2 <__udivmoddi4+0x2be>
 8000e10:	4610      	mov	r0, r2
 8000e12:	eba4 0408 	sub.w	r4, r4, r8
 8000e16:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
 8000e1a:	e7c0      	b.n	8000d9e <__udivmoddi4+0x9a>
 8000e1c:	428b      	cmp	r3, r1
 8000e1e:	d908      	bls.n	8000e32 <__udivmoddi4+0x12e>
 8000e20:	2e00      	cmp	r6, #0
 8000e22:	f000 80b1 	beq.w	8000f88 <__udivmoddi4+0x284>
 8000e26:	2100      	movs	r1, #0
 8000e28:	e9c6 0500 	strd	r0, r5, [r6]
 8000e2c:	4608      	mov	r0, r1
 8000e2e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000e32:	fab3 f183 	clz	r1, r3
 8000e36:	2900      	cmp	r1, #0
 8000e38:	d14b      	bne.n	8000ed2 <__udivmoddi4+0x1ce>
 8000e3a:	42ab      	cmp	r3, r5
 8000e3c:	d302      	bcc.n	8000e44 <__udivmoddi4+0x140>
 8000e3e:	4282      	cmp	r2, r0
 8000e40:	f200 80b9 	bhi.w	8000fb6 <__udivmoddi4+0x2b2>
 8000e44:	1a84      	subs	r4, r0, r2
 8000e46:	eb65 0303 	sbc.w	r3, r5, r3
 8000e4a:	2001      	movs	r0, #1
 8000e4c:	469e      	mov	lr, r3
 8000e4e:	2e00      	cmp	r6, #0
 8000e50:	d0aa      	beq.n	8000da8 <__udivmoddi4+0xa4>
 8000e52:	e9c6 4e00 	strd	r4, lr, [r6]
 8000e56:	e7a7      	b.n	8000da8 <__udivmoddi4+0xa4>
 8000e58:	409f      	lsls	r7, r3
 8000e5a:	f1c3 0220 	rsb	r2, r3, #32
 8000e5e:	40d1      	lsrs	r1, r2
 8000e60:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000e64:	fbb1 f0fe 	udiv	r0, r1, lr
 8000e68:	fa1f f887 	uxth.w	r8, r7
 8000e6c:	fb0e 1110 	mls	r1, lr, r0, r1
 8000e70:	fa24 f202 	lsr.w	r2, r4, r2
 8000e74:	409d      	lsls	r5, r3
 8000e76:	fb00 fc08 	mul.w	ip, r0, r8
 8000e7a:	432a      	orrs	r2, r5
 8000e7c:	0c15      	lsrs	r5, r2, #16
 8000e7e:	ea45 4501 	orr.w	r5, r5, r1, lsl #16
 8000e82:	45ac      	cmp	ip, r5
 8000e84:	fa04 f403 	lsl.w	r4, r4, r3
 8000e88:	d909      	bls.n	8000e9e <__udivmoddi4+0x19a>
 8000e8a:	197d      	adds	r5, r7, r5
 8000e8c:	f100 31ff 	add.w	r1, r0, #4294967295	; 0xffffffff
 8000e90:	f080 808f 	bcs.w	8000fb2 <__udivmoddi4+0x2ae>
 8000e94:	45ac      	cmp	ip, r5
 8000e96:	f240 808c 	bls.w	8000fb2 <__udivmoddi4+0x2ae>
 8000e9a:	3802      	subs	r0, #2
 8000e9c:	443d      	add	r5, r7
 8000e9e:	eba5 050c 	sub.w	r5, r5, ip
 8000ea2:	fbb5 f1fe 	udiv	r1, r5, lr
 8000ea6:	fb0e 5c11 	mls	ip, lr, r1, r5
 8000eaa:	fb01 f908 	mul.w	r9, r1, r8
 8000eae:	b295      	uxth	r5, r2
 8000eb0:	ea45 450c 	orr.w	r5, r5, ip, lsl #16
 8000eb4:	45a9      	cmp	r9, r5
 8000eb6:	d907      	bls.n	8000ec8 <__udivmoddi4+0x1c4>
 8000eb8:	197d      	adds	r5, r7, r5
 8000eba:	f101 32ff 	add.w	r2, r1, #4294967295	; 0xffffffff
 8000ebe:	d274      	bcs.n	8000faa <__udivmoddi4+0x2a6>
 8000ec0:	45a9      	cmp	r9, r5
 8000ec2:	d972      	bls.n	8000faa <__udivmoddi4+0x2a6>
 8000ec4:	3902      	subs	r1, #2
 8000ec6:	443d      	add	r5, r7
 8000ec8:	eba5 0509 	sub.w	r5, r5, r9
 8000ecc:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
 8000ed0:	e778      	b.n	8000dc4 <__udivmoddi4+0xc0>
 8000ed2:	f1c1 0720 	rsb	r7, r1, #32
 8000ed6:	408b      	lsls	r3, r1
 8000ed8:	fa22 fc07 	lsr.w	ip, r2, r7
 8000edc:	ea4c 0c03 	orr.w	ip, ip, r3
 8000ee0:	fa25 f407 	lsr.w	r4, r5, r7
 8000ee4:	ea4f 4e1c 	mov.w	lr, ip, lsr #16
 8000ee8:	fbb4 f9fe 	udiv	r9, r4, lr
 8000eec:	fa1f f88c 	uxth.w	r8, ip
 8000ef0:	fb0e 4419 	mls	r4, lr, r9, r4
 8000ef4:	fa20 f307 	lsr.w	r3, r0, r7
 8000ef8:	fb09 fa08 	mul.w	sl, r9, r8
 8000efc:	408d      	lsls	r5, r1
 8000efe:	431d      	orrs	r5, r3
 8000f00:	0c2b      	lsrs	r3, r5, #16
 8000f02:	ea43 4404 	orr.w	r4, r3, r4, lsl #16
 8000f06:	45a2      	cmp	sl, r4
 8000f08:	fa02 f201 	lsl.w	r2, r2, r1
 8000f0c:	fa00 f301 	lsl.w	r3, r0, r1
 8000f10:	d909      	bls.n	8000f26 <__udivmoddi4+0x222>
 8000f12:	eb1c 0404 	adds.w	r4, ip, r4
 8000f16:	f109 30ff 	add.w	r0, r9, #4294967295	; 0xffffffff
 8000f1a:	d248      	bcs.n	8000fae <__udivmoddi4+0x2aa>
 8000f1c:	45a2      	cmp	sl, r4
 8000f1e:	d946      	bls.n	8000fae <__udivmoddi4+0x2aa>
 8000f20:	f1a9 0902 	sub.w	r9, r9, #2
 8000f24:	4464      	add	r4, ip
 8000f26:	eba4 040a 	sub.w	r4, r4, sl
 8000f2a:	fbb4 f0fe 	udiv	r0, r4, lr
 8000f2e:	fb0e 4410 	mls	r4, lr, r0, r4
 8000f32:	fb00 fa08 	mul.w	sl, r0, r8
 8000f36:	b2ad      	uxth	r5, r5
 8000f38:	ea45 4404 	orr.w	r4, r5, r4, lsl #16
 8000f3c:	45a2      	cmp	sl, r4
 8000f3e:	d908      	bls.n	8000f52 <__udivmoddi4+0x24e>
 8000f40:	eb1c 0404 	adds.w	r4, ip, r4
 8000f44:	f100 35ff 	add.w	r5, r0, #4294967295	; 0xffffffff
 8000f48:	d22d      	bcs.n	8000fa6 <__udivmoddi4+0x2a2>
 8000f4a:	45a2      	cmp	sl, r4
 8000f4c:	d92b      	bls.n	8000fa6 <__udivmoddi4+0x2a2>
 8000f4e:	3802      	subs	r0, #2
 8000f50:	4464      	add	r4, ip
 8000f52:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
 8000f56:	fba0 8902 	umull	r8, r9, r0, r2
 8000f5a:	eba4 040a 	sub.w	r4, r4, sl
 8000f5e:	454c      	cmp	r4, r9
 8000f60:	46c6      	mov	lr, r8
 8000f62:	464d      	mov	r5, r9
 8000f64:	d319      	bcc.n	8000f9a <__udivmoddi4+0x296>
 8000f66:	d016      	beq.n	8000f96 <__udivmoddi4+0x292>
 8000f68:	b15e      	cbz	r6, 8000f82 <__udivmoddi4+0x27e>
 8000f6a:	ebb3 020e 	subs.w	r2, r3, lr
 8000f6e:	eb64 0405 	sbc.w	r4, r4, r5
 8000f72:	fa04 f707 	lsl.w	r7, r4, r7
 8000f76:	fa22 f301 	lsr.w	r3, r2, r1
 8000f7a:	431f      	orrs	r7, r3
 8000f7c:	40cc      	lsrs	r4, r1
 8000f7e:	e9c6 7400 	strd	r7, r4, [r6]
 8000f82:	2100      	movs	r1, #0
 8000f84:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000f88:	4631      	mov	r1, r6
 8000f8a:	4630      	mov	r0, r6
 8000f8c:	e70c      	b.n	8000da8 <__udivmoddi4+0xa4>
 8000f8e:	468c      	mov	ip, r1
 8000f90:	e6eb      	b.n	8000d6a <__udivmoddi4+0x66>
 8000f92:	4610      	mov	r0, r2
 8000f94:	e6ff      	b.n	8000d96 <__udivmoddi4+0x92>
 8000f96:	4543      	cmp	r3, r8
 8000f98:	d2e6      	bcs.n	8000f68 <__udivmoddi4+0x264>
 8000f9a:	ebb8 0e02 	subs.w	lr, r8, r2
 8000f9e:	eb69 050c 	sbc.w	r5, r9, ip
 8000fa2:	3801      	subs	r0, #1
 8000fa4:	e7e0      	b.n	8000f68 <__udivmoddi4+0x264>
 8000fa6:	4628      	mov	r0, r5
 8000fa8:	e7d3      	b.n	8000f52 <__udivmoddi4+0x24e>
 8000faa:	4611      	mov	r1, r2
 8000fac:	e78c      	b.n	8000ec8 <__udivmoddi4+0x1c4>
 8000fae:	4681      	mov	r9, r0
 8000fb0:	e7b9      	b.n	8000f26 <__udivmoddi4+0x222>
 8000fb2:	4608      	mov	r0, r1
 8000fb4:	e773      	b.n	8000e9e <__udivmoddi4+0x19a>
 8000fb6:	4608      	mov	r0, r1
 8000fb8:	e749      	b.n	8000e4e <__udivmoddi4+0x14a>
 8000fba:	f1ac 0c02 	sub.w	ip, ip, #2
 8000fbe:	443d      	add	r5, r7
 8000fc0:	e713      	b.n	8000dea <__udivmoddi4+0xe6>
 8000fc2:	3802      	subs	r0, #2
 8000fc4:	443c      	add	r4, r7
 8000fc6:	e724      	b.n	8000e12 <__udivmoddi4+0x10e>

08000fc8 <__aeabi_idiv0>:
 8000fc8:	4770      	bx	lr
 8000fca:	bf00      	nop

08000fcc <HAL_COMP_TriggerCallback>:
/* USER CODE END PFP */

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
{
 8000fcc:	b480      	push	{r7}
 8000fce:	b083      	sub	sp, #12
 8000fd0:	af00      	add	r7, sp, #0
 8000fd2:	6078      	str	r0, [r7, #4]
  pulses++;
 8000fd4:	4b04      	ldr	r3, [pc, #16]	; (8000fe8 <HAL_COMP_TriggerCallback+0x1c>)
 8000fd6:	681b      	ldr	r3, [r3, #0]
 8000fd8:	3301      	adds	r3, #1
 8000fda:	4a03      	ldr	r2, [pc, #12]	; (8000fe8 <HAL_COMP_TriggerCallback+0x1c>)
 8000fdc:	6013      	str	r3, [r2, #0]
}
 8000fde:	bf00      	nop
 8000fe0:	370c      	adds	r7, #12
 8000fe2:	46bd      	mov	sp, r7
 8000fe4:	bc80      	pop	{r7}
 8000fe6:	4770      	bx	lr
 8000fe8:	20000200 	.word	0x20000200

08000fec <HAL_GPIO_EXTI_Callback>:

void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
 8000fec:	b480      	push	{r7}
 8000fee:	b083      	sub	sp, #12
 8000ff0:	af00      	add	r7, sp, #0
 8000ff2:	4603      	mov	r3, r0
 8000ff4:	80fb      	strh	r3, [r7, #6]
  Flags.Exti |= GPIO_Pin;
 8000ff6:	4b06      	ldr	r3, [pc, #24]	; (8001010 <HAL_GPIO_EXTI_Callback+0x24>)
 8000ff8:	895b      	ldrh	r3, [r3, #10]
 8000ffa:	b29a      	uxth	r2, r3
 8000ffc:	88fb      	ldrh	r3, [r7, #6]
 8000ffe:	4313      	orrs	r3, r2
 8001000:	b29a      	uxth	r2, r3
 8001002:	4b03      	ldr	r3, [pc, #12]	; (8001010 <HAL_GPIO_EXTI_Callback+0x24>)
 8001004:	815a      	strh	r2, [r3, #10]
}
 8001006:	bf00      	nop
 8001008:	370c      	adds	r7, #12
 800100a:	46bd      	mov	sp, r7
 800100c:	bc80      	pop	{r7}
 800100e:	4770      	bx	lr
 8001010:	20000684 	.word	0x20000684

08001014 <HAL_TIM_PeriodElapsedCallback>:

void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8001014:	b480      	push	{r7}
 8001016:	b083      	sub	sp, #12
 8001018:	af00      	add	r7, sp, #0
 800101a:	6078      	str	r0, [r7, #4]
  if(htim == &htim4)
 800101c:	687b      	ldr	r3, [r7, #4]
 800101e:	4a0b      	ldr	r2, [pc, #44]	; (800104c <HAL_TIM_PeriodElapsedCallback+0x38>)
 8001020:	4293      	cmp	r3, r2
 8001022:	d106      	bne.n	8001032 <HAL_TIM_PeriodElapsedCallback+0x1e>
  {
    Flags.Tim4++;
 8001024:	4b0a      	ldr	r3, [pc, #40]	; (8001050 <HAL_TIM_PeriodElapsedCallback+0x3c>)
 8001026:	889b      	ldrh	r3, [r3, #4]
 8001028:	b29b      	uxth	r3, r3
 800102a:	3301      	adds	r3, #1
 800102c:	b29a      	uxth	r2, r3
 800102e:	4b08      	ldr	r3, [pc, #32]	; (8001050 <HAL_TIM_PeriodElapsedCallback+0x3c>)
 8001030:	809a      	strh	r2, [r3, #4]
  }

  if(htim == &htim6)
 8001032:	687b      	ldr	r3, [r7, #4]
 8001034:	4a07      	ldr	r2, [pc, #28]	; (8001054 <HAL_TIM_PeriodElapsedCallback+0x40>)
 8001036:	4293      	cmp	r3, r2
 8001038:	d102      	bne.n	8001040 <HAL_TIM_PeriodElapsedCallback+0x2c>
  {
    Flags.Tim6 = 1;
 800103a:	4b05      	ldr	r3, [pc, #20]	; (8001050 <HAL_TIM_PeriodElapsedCallback+0x3c>)
 800103c:	2201      	movs	r2, #1
 800103e:	80da      	strh	r2, [r3, #6]
  }
}
 8001040:	bf00      	nop
 8001042:	370c      	adds	r7, #12
 8001044:	46bd      	mov	sp, r7
 8001046:	bc80      	pop	{r7}
 8001048:	4770      	bx	lr
 800104a:	bf00      	nop
 800104c:	20000418 	.word	0x20000418
 8001050:	20000684 	.word	0x20000684
 8001054:	20000598 	.word	0x20000598

08001058 <GetVcc>:

uint32_t GetVcc(void)
{
 8001058:	b480      	push	{r7}
 800105a:	af00      	add	r7, sp, #0
  return (VREFINT_CAL_VALUE * VREFINT_CAL_VREF / adc_meas.VREF);
 800105c:	4b07      	ldr	r3, [pc, #28]	; (800107c <GetVcc+0x24>)
 800105e:	881b      	ldrh	r3, [r3, #0]
 8001060:	461a      	mov	r2, r3
 8001062:	f640 33b8 	movw	r3, #3000	; 0xbb8
 8001066:	fb03 f202 	mul.w	r2, r3, r2
 800106a:	4b05      	ldr	r3, [pc, #20]	; (8001080 <GetVcc+0x28>)
 800106c:	689b      	ldr	r3, [r3, #8]
 800106e:	fbb2 f3f3 	udiv	r3, r2, r3
}
 8001072:	4618      	mov	r0, r3
 8001074:	46bd      	mov	sp, r7
 8001076:	bc80      	pop	{r7}
 8001078:	4770      	bx	lr
 800107a:	bf00      	nop
 800107c:	1ff80078 	.word	0x1ff80078
 8001080:	200006e4 	.word	0x200006e4

08001084 <SetDACVoltage>:

void SetDACVoltage(uint32_t channel, uint32_t voltage)
{
 8001084:	b590      	push	{r4, r7, lr}
 8001086:	b083      	sub	sp, #12
 8001088:	af00      	add	r7, sp, #0
 800108a:	6078      	str	r0, [r7, #4]
 800108c:	6039      	str	r1, [r7, #0]
  HAL_DAC_SetValue(&hdac, channel, DAC_ALIGN_12B_R, (voltage * 4095UL) / GetVcc());
 800108e:	683a      	ldr	r2, [r7, #0]
 8001090:	4613      	mov	r3, r2
 8001092:	031b      	lsls	r3, r3, #12
 8001094:	1a9c      	subs	r4, r3, r2
 8001096:	f7ff ffdf 	bl	8001058 <GetVcc>
 800109a:	4603      	mov	r3, r0
 800109c:	fbb4 f3f3 	udiv	r3, r4, r3
 80010a0:	2200      	movs	r2, #0
 80010a2:	6879      	ldr	r1, [r7, #4]
 80010a4:	4803      	ldr	r0, [pc, #12]	; (80010b4 <SetDACVoltage+0x30>)
 80010a6:	f002 f9b3 	bl	8003410 <HAL_DAC_SetValue>
}
 80010aa:	bf00      	nop
 80010ac:	370c      	adds	r7, #12
 80010ae:	46bd      	mov	sp, r7
 80010b0:	bd90      	pop	{r4, r7, pc}
 80010b2:	bf00      	nop
 80010b4:	20000584 	.word	0x20000584

080010b8 <Switch3V3Regulator>:

void Switch3V3Regulator(OnOff_t state)
{
 80010b8:	b580      	push	{r7, lr}
 80010ba:	b082      	sub	sp, #8
 80010bc:	af00      	add	r7, sp, #0
 80010be:	4603      	mov	r3, r0
 80010c0:	71fb      	strb	r3, [r7, #7]
  if(state == ON)
 80010c2:	79fb      	ldrb	r3, [r7, #7]
 80010c4:	2b01      	cmp	r3, #1
 80010c6:	d105      	bne.n	80010d4 <Switch3V3Regulator+0x1c>
    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_SET);
 80010c8:	2201      	movs	r2, #1
 80010ca:	2180      	movs	r1, #128	; 0x80
 80010cc:	4806      	ldr	r0, [pc, #24]	; (80010e8 <Switch3V3Regulator+0x30>)
 80010ce:	f002 fe45 	bl	8003d5c <HAL_GPIO_WritePin>
  else
    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET);
}
 80010d2:	e004      	b.n	80010de <Switch3V3Regulator+0x26>
    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET);
 80010d4:	2200      	movs	r2, #0
 80010d6:	2180      	movs	r1, #128	; 0x80
 80010d8:	4803      	ldr	r0, [pc, #12]	; (80010e8 <Switch3V3Regulator+0x30>)
 80010da:	f002 fe3f 	bl	8003d5c <HAL_GPIO_WritePin>
}
 80010de:	bf00      	nop
 80010e0:	3708      	adds	r7, #8
 80010e2:	46bd      	mov	sp, r7
 80010e4:	bd80      	pop	{r7, pc}
 80010e6:	bf00      	nop
 80010e8:	40020000 	.word	0x40020000

080010ec <SwitchPeriphSupply>:

void SwitchPeriphSupply(OnOff_t state)
{
 80010ec:	b580      	push	{r7, lr}
 80010ee:	b082      	sub	sp, #8
 80010f0:	af00      	add	r7, sp, #0
 80010f2:	4603      	mov	r3, r0
 80010f4:	71fb      	strb	r3, [r7, #7]
  if(state == ON)
 80010f6:	79fb      	ldrb	r3, [r7, #7]
 80010f8:	2b01      	cmp	r3, #1
 80010fa:	d105      	bne.n	8001108 <SwitchPeriphSupply+0x1c>
    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET);
 80010fc:	2200      	movs	r2, #0
 80010fe:	2101      	movs	r1, #1
 8001100:	4806      	ldr	r0, [pc, #24]	; (800111c <SwitchPeriphSupply+0x30>)
 8001102:	f002 fe2b 	bl	8003d5c <HAL_GPIO_WritePin>
  else
    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET);
}
 8001106:	e004      	b.n	8001112 <SwitchPeriphSupply+0x26>
    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET);
 8001108:	2201      	movs	r2, #1
 800110a:	2101      	movs	r1, #1
 800110c:	4803      	ldr	r0, [pc, #12]	; (800111c <SwitchPeriphSupply+0x30>)
 800110e:	f002 fe25 	bl	8003d5c <HAL_GPIO_WritePin>
}
 8001112:	bf00      	nop
 8001114:	3708      	adds	r7, #8
 8001116:	46bd      	mov	sp, r7
 8001118:	bd80      	pop	{r7, pc}
 800111a:	bf00      	nop
 800111c:	40020400 	.word	0x40020400

08001120 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8001120:	b580      	push	{r7, lr}
 8001122:	b08e      	sub	sp, #56	; 0x38
 8001124:	af02      	add	r7, sp, #8
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8001126:	f001 f92a 	bl	800237e <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 800112a:	f000 f93f 	bl	80013ac <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_DMA_Init();
 800112e:	f000 fc4b 	bl	80019c8 <MX_DMA_Init>
  MX_GPIO_Init();
 8001132:	f000 fc67 	bl	8001a04 <MX_GPIO_Init>
  MX_ADC_Init();
 8001136:	f000 f989 	bl	800144c <MX_ADC_Init>
  MX_DAC_Init();
 800113a:	f000 fa25 	bl	8001588 <MX_DAC_Init>
  //MX_I2C2_Init();
  MX_COMP2_Init();
 800113e:	f000 f9fb 	bl	8001538 <MX_COMP2_Init>
  MX_USART1_UART_Init();
 8001142:	f000 fc17 	bl	8001974 <MX_USART1_UART_Init>
  MX_TIM6_Init();
 8001146:	f000 fbdf 	bl	8001908 <MX_TIM6_Init>
  MX_TIM4_Init();
 800114a:	f000 fb8f 	bl	800186c <MX_TIM4_Init>
  MX_TIM3_Init();
 800114e:	f000 fb03 	bl	8001758 <MX_TIM3_Init>
  MX_TIM2_Init();
 8001152:	f000 faab 	bl	80016ac <MX_TIM2_Init>
  MX_I2C1_Init();
 8001156:	f000 fa4d 	bl	80015f4 <MX_I2C1_Init>
  /* USER CODE BEGIN 2 */

  Switch3V3Regulator(ON);
 800115a:	2001      	movs	r0, #1
 800115c:	f7ff ffac 	bl	80010b8 <Switch3V3Regulator>
  SwitchPeriphSupply(ON);
 8001160:	2001      	movs	r0, #1
 8001162:	f7ff ffc3 	bl	80010ec <SwitchPeriphSupply>
  HAL_Delay(100);
 8001166:	2064      	movs	r0, #100	; 0x64
 8001168:	f001 f978 	bl	800245c <HAL_Delay>

  MX_I2C2_Init();
 800116c:	f000 fa70 	bl	8001650 <MX_I2C2_Init>

  ssd1306_Init();
 8001170:	f005 fa22 	bl	80065b8 <ssd1306_Init>
  ssd1306_Fill(Black);
 8001174:	2000      	movs	r0, #0
 8001176:	f005 fa89 	bl	800668c <ssd1306_Fill>
  ssd1306_UpdateScreen();
 800117a:	f005 faa9 	bl	80066d0 <ssd1306_UpdateScreen>

  HAL_DAC_Start(&hdac, DAC_CHANNEL_1);
 800117e:	2100      	movs	r1, #0
 8001180:	4877      	ldr	r0, [pc, #476]	; (8001360 <main+0x240>)
 8001182:	f002 f8f4 	bl	800336e <HAL_DAC_Start>
  HAL_DAC_Start(&hdac, DAC_CHANNEL_2);
 8001186:	2110      	movs	r1, #16
 8001188:	4875      	ldr	r0, [pc, #468]	; (8001360 <main+0x240>)
 800118a:	f002 f8f0 	bl	800336e <HAL_DAC_Start>
  HAL_DAC_SetValue(&hdac, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 0xB50);
 800118e:	f44f 6335 	mov.w	r3, #2896	; 0xb50
 8001192:	2200      	movs	r2, #0
 8001194:	2100      	movs	r1, #0
 8001196:	4872      	ldr	r0, [pc, #456]	; (8001360 <main+0x240>)
 8001198:	f002 f93a 	bl	8003410 <HAL_DAC_SetValue>
  HAL_DAC_SetValue(&hdac, DAC_CHANNEL_2, DAC_ALIGN_12B_R, 0x100);
 800119c:	f44f 7380 	mov.w	r3, #256	; 0x100
 80011a0:	2200      	movs	r2, #0
 80011a2:	2110      	movs	r1, #16
 80011a4:	486e      	ldr	r0, [pc, #440]	; (8001360 <main+0x240>)
 80011a6:	f002 f933 	bl	8003410 <HAL_DAC_SetValue>
  HAL_Delay(10);
 80011aa:	200a      	movs	r0, #10
 80011ac:	f001 f956 	bl	800245c <HAL_Delay>
  HAL_ADC_Start_DMA(&hadc, (uint32_t*)&adc_meas, 3);
 80011b0:	2203      	movs	r2, #3
 80011b2:	496c      	ldr	r1, [pc, #432]	; (8001364 <main+0x244>)
 80011b4:	486c      	ldr	r0, [pc, #432]	; (8001368 <main+0x248>)
 80011b6:	f001 fab9 	bl	800272c <HAL_ADC_Start_DMA>
  HAL_Delay(10);
 80011ba:	200a      	movs	r0, #10
 80011bc:	f001 f94e 	bl	800245c <HAL_Delay>
  HAL_ADC_Stop_DMA(&hadc);
 80011c0:	4869      	ldr	r0, [pc, #420]	; (8001368 <main+0x248>)
 80011c2:	f001 fb41 	bl	8002848 <HAL_ADC_Stop_DMA>

  //uint32_t curr_vcc = GetVcc();
  SetDACVoltage(DAC_CHANNEL_1, 2100);
 80011c6:	f640 0134 	movw	r1, #2100	; 0x834
 80011ca:	2000      	movs	r0, #0
 80011cc:	f7ff ff5a 	bl	8001084 <SetDACVoltage>

  SetDACVoltage(DAC_CHANNEL_2, 135);
 80011d0:	2187      	movs	r1, #135	; 0x87
 80011d2:	2010      	movs	r0, #16
 80011d4:	f7ff ff56 	bl	8001084 <SetDACVoltage>

  HAL_COMP_Start_IT(&hcomp2);
 80011d8:	4864      	ldr	r0, [pc, #400]	; (800136c <main+0x24c>)
 80011da:	f001 ff1f 	bl	800301c <HAL_COMP_Start_IT>
  HAL_TIM_Base_Start_IT(&htim6);
 80011de:	4864      	ldr	r0, [pc, #400]	; (8001370 <main+0x250>)
 80011e0:	f004 f90e 	bl	8005400 <HAL_TIM_Base_Start_IT>
  HAL_TIM_Base_Start_IT(&htim4);
 80011e4:	4863      	ldr	r0, [pc, #396]	; (8001374 <main+0x254>)
 80011e6:	f004 f90b 	bl	8005400 <HAL_TIM_Base_Start_IT>
  HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_4);
 80011ea:	210c      	movs	r1, #12
 80011ec:	4862      	ldr	r0, [pc, #392]	; (8001378 <main+0x258>)
 80011ee:	f004 f959 	bl	80054a4 <HAL_TIM_OC_Start>
  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  char tempstr[32];
  uint32_t pps = 0;
 80011f2:	2300      	movs	r3, #0
 80011f4:	62fb      	str	r3, [r7, #44]	; 0x2c
  uint32_t pps_avg = 0;
 80011f6:	2300      	movs	r3, #0
 80011f8:	62bb      	str	r3, [r7, #40]	; 0x28
  uint32_t test = 0;
 80011fa:	2300      	movs	r3, #0
 80011fc:	627b      	str	r3, [r7, #36]	; 0x24

  Flags.Exti = 0;
 80011fe:	4b5f      	ldr	r3, [pc, #380]	; (800137c <main+0x25c>)
 8001200:	2200      	movs	r2, #0
 8001202:	815a      	strh	r2, [r3, #10]
  while (1)
  {
    if(Flags.Exti)
 8001204:	4b5d      	ldr	r3, [pc, #372]	; (800137c <main+0x25c>)
 8001206:	895b      	ldrh	r3, [r3, #10]
 8001208:	b29b      	uxth	r3, r3
 800120a:	2b00      	cmp	r3, #0
 800120c:	d022      	beq.n	8001254 <main+0x134>
    {
      test = Flags.Exti;
 800120e:	4b5b      	ldr	r3, [pc, #364]	; (800137c <main+0x25c>)
 8001210:	895b      	ldrh	r3, [r3, #10]
 8001212:	b29b      	uxth	r3, r3
 8001214:	627b      	str	r3, [r7, #36]	; 0x24
      Flags.Exti = 0;
 8001216:	4b59      	ldr	r3, [pc, #356]	; (800137c <main+0x25c>)
 8001218:	2200      	movs	r2, #0
 800121a:	815a      	strh	r2, [r3, #10]
      ssd1306_Reset();
 800121c:	f005 f994 	bl	8006548 <ssd1306_Reset>
      SwitchPeriphSupply(OFF);
 8001220:	2000      	movs	r0, #0
 8001222:	f7ff ff63 	bl	80010ec <SwitchPeriphSupply>
      //Switch3V3Regulator(OFF);
      HAL_I2C_DeInit(&hi2c1);
 8001226:	4856      	ldr	r0, [pc, #344]	; (8001380 <main+0x260>)
 8001228:	f002 ff0c 	bl	8004044 <HAL_I2C_DeInit>
      HAL_I2C_DeInit(&hi2c2);
 800122c:	4855      	ldr	r0, [pc, #340]	; (8001384 <main+0x264>)
 800122e:	f002 ff09 	bl	8004044 <HAL_I2C_DeInit>
      HAL_UART_DeInit(&huart1);
 8001232:	4855      	ldr	r0, [pc, #340]	; (8001388 <main+0x268>)
 8001234:	f005 f875 	bl	8006322 <HAL_UART_DeInit>
      HAL_GPIO_DeInit(GPIOB, GPIO_PIN_All);
 8001238:	f64f 71ff 	movw	r1, #65535	; 0xffff
 800123c:	4853      	ldr	r0, [pc, #332]	; (800138c <main+0x26c>)
 800123e:	f002 fcad 	bl	8003b9c <HAL_GPIO_DeInit>
      HAL_GPIO_DeInit(GPIOA, GPIO_PIN_All);
 8001242:	f64f 71ff 	movw	r1, #65535	; 0xffff
 8001246:	4852      	ldr	r0, [pc, #328]	; (8001390 <main+0x270>)
 8001248:	f002 fca8 	bl	8003b9c <HAL_GPIO_DeInit>
      //HAL_Delay(10);
      //HAL_PWR_EnterSTANDBYMode();
      HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI);
 800124c:	2101      	movs	r1, #1
 800124e:	2000      	movs	r0, #0
 8001250:	f003 fa3e 	bl	80046d0 <HAL_PWR_EnterSTOPMode>
    }

    if(Flags.Tim6)
 8001254:	4b49      	ldr	r3, [pc, #292]	; (800137c <main+0x25c>)
 8001256:	88db      	ldrh	r3, [r3, #6]
 8001258:	b29b      	uxth	r3, r3
 800125a:	2b00      	cmp	r3, #0
 800125c:	d049      	beq.n	80012f2 <main+0x1d2>
    {
      Flags.Tim6 = 0;
 800125e:	4b47      	ldr	r3, [pc, #284]	; (800137c <main+0x25c>)
 8001260:	2200      	movs	r2, #0
 8001262:	80da      	strh	r2, [r3, #6]
      HAL_ADC_Stop_DMA(&hadc);
 8001264:	4840      	ldr	r0, [pc, #256]	; (8001368 <main+0x248>)
 8001266:	f001 faef 	bl	8002848 <HAL_ADC_Stop_DMA>
      if((pps / pps_avg > 2) || (pps_avg / pps > 2))
 800126a:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 800126c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800126e:	fbb2 f3f3 	udiv	r3, r2, r3
 8001272:	2b02      	cmp	r3, #2
 8001274:	d805      	bhi.n	8001282 <main+0x162>
 8001276:	6aba      	ldr	r2, [r7, #40]	; 0x28
 8001278:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 800127a:	fbb2 f3f3 	udiv	r3, r2, r3
 800127e:	2b02      	cmp	r3, #2
 8001280:	d902      	bls.n	8001288 <main+0x168>
      {
        pps_avg = pps;
 8001282:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8001284:	62bb      	str	r3, [r7, #40]	; 0x28
 8001286:	e004      	b.n	8001292 <main+0x172>
      }
      else
      {
        pps_avg = (pps + pps_avg) / 2;
 8001288:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 800128a:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800128c:	4413      	add	r3, r2
 800128e:	085b      	lsrs	r3, r3, #1
 8001290:	62bb      	str	r3, [r7, #40]	; 0x28
      }
      sprintf(tempstr, "%5.2f uSv/h", (float)pps_avg / 100.0);
 8001292:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8001294:	f7ff fcc6 	bl	8000c24 <__aeabi_ui2f>
 8001298:	4603      	mov	r3, r0
 800129a:	4618      	mov	r0, r3
 800129c:	f7ff f8dc 	bl	8000458 <__aeabi_f2d>
 80012a0:	f04f 0200 	mov.w	r2, #0
 80012a4:	4b3b      	ldr	r3, [pc, #236]	; (8001394 <main+0x274>)
 80012a6:	f7ff fa59 	bl	800075c <__aeabi_ddiv>
 80012aa:	4602      	mov	r2, r0
 80012ac:	460b      	mov	r3, r1
 80012ae:	4638      	mov	r0, r7
 80012b0:	4939      	ldr	r1, [pc, #228]	; (8001398 <main+0x278>)
 80012b2:	f006 f8e9 	bl	8007488 <siprintf>
      ssd1306_DrawRectangle(0, 0, SSD1306_WIDTH - 1, SSD1306_HEIGHT - 1, White);
 80012b6:	2301      	movs	r3, #1
 80012b8:	9300      	str	r3, [sp, #0]
 80012ba:	231f      	movs	r3, #31
 80012bc:	227f      	movs	r2, #127	; 0x7f
 80012be:	2100      	movs	r1, #0
 80012c0:	2000      	movs	r0, #0
 80012c2:	f005 fbbf 	bl	8006a44 <ssd1306_DrawRectangle>
      ssd1306_SetCursor(1, 7);
 80012c6:	2107      	movs	r1, #7
 80012c8:	2001      	movs	r0, #1
 80012ca:	f005 fb37 	bl	800693c <ssd1306_SetCursor>
      ssd1306_WriteString(tempstr, Font_11x18, White);
 80012ce:	4a33      	ldr	r2, [pc, #204]	; (800139c <main+0x27c>)
 80012d0:	4638      	mov	r0, r7
 80012d2:	2301      	movs	r3, #1
 80012d4:	ca06      	ldmia	r2, {r1, r2}
 80012d6:	f005 fb0b 	bl	80068f0 <ssd1306_WriteString>
      ssd1306_UpdateScreen();
 80012da:	f005 f9f9 	bl	80066d0 <ssd1306_UpdateScreen>
      SetDACVoltage(DAC_CHANNEL_1, 2100);
 80012de:	f640 0134 	movw	r1, #2100	; 0x834
 80012e2:	2000      	movs	r0, #0
 80012e4:	f7ff fece 	bl	8001084 <SetDACVoltage>
      HAL_ADC_Start_DMA(&hadc, (uint32_t*)&adc_meas, 3);
 80012e8:	2203      	movs	r2, #3
 80012ea:	491e      	ldr	r1, [pc, #120]	; (8001364 <main+0x244>)
 80012ec:	481e      	ldr	r0, [pc, #120]	; (8001368 <main+0x248>)
 80012ee:	f001 fa1d 	bl	800272c <HAL_ADC_Start_DMA>
    }

    if(pulses > 50 || Flags.Tim4 > 3)
 80012f2:	4b2b      	ldr	r3, [pc, #172]	; (80013a0 <main+0x280>)
 80012f4:	681b      	ldr	r3, [r3, #0]
 80012f6:	2b32      	cmp	r3, #50	; 0x32
 80012f8:	d805      	bhi.n	8001306 <main+0x1e6>
 80012fa:	4b20      	ldr	r3, [pc, #128]	; (800137c <main+0x25c>)
 80012fc:	889b      	ldrh	r3, [r3, #4]
 80012fe:	b29b      	uxth	r3, r3
 8001300:	2b03      	cmp	r3, #3
 8001302:	f67f af7f 	bls.w	8001204 <main+0xe4>
    {
      uint32_t elapsed = htim4.Instance->CNT + (Flags.Tim4 * 50000);
 8001306:	4b1b      	ldr	r3, [pc, #108]	; (8001374 <main+0x254>)
 8001308:	681b      	ldr	r3, [r3, #0]
 800130a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800130c:	4a1b      	ldr	r2, [pc, #108]	; (800137c <main+0x25c>)
 800130e:	8892      	ldrh	r2, [r2, #4]
 8001310:	b292      	uxth	r2, r2
 8001312:	4611      	mov	r1, r2
 8001314:	f24c 3250 	movw	r2, #50000	; 0xc350
 8001318:	fb02 f201 	mul.w	r2, r2, r1
 800131c:	4413      	add	r3, r2
 800131e:	623b      	str	r3, [r7, #32]
      HAL_TIM_Base_Stop(&htim4);
 8001320:	4814      	ldr	r0, [pc, #80]	; (8001374 <main+0x254>)
 8001322:	f004 f84f 	bl	80053c4 <HAL_TIM_Base_Stop>

      pps = (pulses * 100000) / elapsed;
 8001326:	4b1e      	ldr	r3, [pc, #120]	; (80013a0 <main+0x280>)
 8001328:	681b      	ldr	r3, [r3, #0]
 800132a:	4a1e      	ldr	r2, [pc, #120]	; (80013a4 <main+0x284>)
 800132c:	fb02 f203 	mul.w	r2, r2, r3
 8001330:	6a3b      	ldr	r3, [r7, #32]
 8001332:	fbb2 f3f3 	udiv	r3, r2, r3
 8001336:	62fb      	str	r3, [r7, #44]	; 0x2c

      pulses = 0;
 8001338:	4b19      	ldr	r3, [pc, #100]	; (80013a0 <main+0x280>)
 800133a:	2200      	movs	r2, #0
 800133c:	601a      	str	r2, [r3, #0]
      Flags.Tim4 = 0;
 800133e:	4b0f      	ldr	r3, [pc, #60]	; (800137c <main+0x25c>)
 8001340:	2200      	movs	r2, #0
 8001342:	809a      	strh	r2, [r3, #4]
      htim4.Instance->CNT = 0;
 8001344:	4b0b      	ldr	r3, [pc, #44]	; (8001374 <main+0x254>)
 8001346:	681b      	ldr	r3, [r3, #0]
 8001348:	2200      	movs	r2, #0
 800134a:	625a      	str	r2, [r3, #36]	; 0x24
      HAL_TIM_Base_Start(&htim4);
 800134c:	4809      	ldr	r0, [pc, #36]	; (8001374 <main+0x254>)
 800134e:	f003 ffef 	bl	8005330 <HAL_TIM_Base_Start>

      HAL_TIM_Base_Stop(&htim2);
 8001352:	4815      	ldr	r0, [pc, #84]	; (80013a8 <main+0x288>)
 8001354:	f004 f836 	bl	80053c4 <HAL_TIM_Base_Stop>
      HAL_TIM_Base_Start(&htim2);
 8001358:	4813      	ldr	r0, [pc, #76]	; (80013a8 <main+0x288>)
 800135a:	f003 ffe9 	bl	8005330 <HAL_TIM_Base_Start>
    if(Flags.Exti)
 800135e:	e751      	b.n	8001204 <main+0xe4>
 8001360:	20000584 	.word	0x20000584
 8001364:	200006e4 	.word	0x200006e4
 8001368:	20000690 	.word	0x20000690
 800136c:	200005d8 	.word	0x200005d8
 8001370:	20000598 	.word	0x20000598
 8001374:	20000418 	.word	0x20000418
 8001378:	20000500 	.word	0x20000500
 800137c:	20000684 	.word	0x20000684
 8001380:	20000458 	.word	0x20000458
 8001384:	200004ac 	.word	0x200004ac
 8001388:	20000540 	.word	0x20000540
 800138c:	40020400 	.word	0x40020400
 8001390:	40020000 	.word	0x40020000
 8001394:	40590000 	.word	0x40590000
 8001398:	080098c8 	.word	0x080098c8
 800139c:	2000000c 	.word	0x2000000c
 80013a0:	20000200 	.word	0x20000200
 80013a4:	000186a0 	.word	0x000186a0
 80013a8:	20000600 	.word	0x20000600

080013ac <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 80013ac:	b580      	push	{r7, lr}
 80013ae:	b092      	sub	sp, #72	; 0x48
 80013b0:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80013b2:	f107 0314 	add.w	r3, r7, #20
 80013b6:	2234      	movs	r2, #52	; 0x34
 80013b8:	2100      	movs	r1, #0
 80013ba:	4618      	mov	r0, r3
 80013bc:	f005 fbfc 	bl	8006bb8 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80013c0:	463b      	mov	r3, r7
 80013c2:	2200      	movs	r2, #0
 80013c4:	601a      	str	r2, [r3, #0]
 80013c6:	605a      	str	r2, [r3, #4]
 80013c8:	609a      	str	r2, [r3, #8]
 80013ca:	60da      	str	r2, [r3, #12]
 80013cc:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 80013ce:	4b1e      	ldr	r3, [pc, #120]	; (8001448 <SystemClock_Config+0x9c>)
 80013d0:	681b      	ldr	r3, [r3, #0]
 80013d2:	f423 53c0 	bic.w	r3, r3, #6144	; 0x1800
 80013d6:	4a1c      	ldr	r2, [pc, #112]	; (8001448 <SystemClock_Config+0x9c>)
 80013d8:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
 80013dc:	6013      	str	r3, [r2, #0]
  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
 80013de:	2303      	movs	r3, #3
 80013e0:	617b      	str	r3, [r7, #20]
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 80013e2:	2301      	movs	r3, #1
 80013e4:	61bb      	str	r3, [r7, #24]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 80013e6:	2301      	movs	r3, #1
 80013e8:	623b      	str	r3, [r7, #32]
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 80013ea:	2310      	movs	r3, #16
 80013ec:	627b      	str	r3, [r7, #36]	; 0x24
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 80013ee:	2302      	movs	r3, #2
 80013f0:	63bb      	str	r3, [r7, #56]	; 0x38
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 80013f2:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 80013f6:	63fb      	str	r3, [r7, #60]	; 0x3c
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
 80013f8:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 80013fc:	643b      	str	r3, [r7, #64]	; 0x40
  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV4;
 80013fe:	f44f 0340 	mov.w	r3, #12582912	; 0xc00000
 8001402:	647b      	str	r3, [r7, #68]	; 0x44
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8001404:	f107 0314 	add.w	r3, r7, #20
 8001408:	4618      	mov	r0, r3
 800140a:	f003 f98d 	bl	8004728 <HAL_RCC_OscConfig>
 800140e:	4603      	mov	r3, r0
 8001410:	2b00      	cmp	r3, #0
 8001412:	d001      	beq.n	8001418 <SystemClock_Config+0x6c>
  {
    Error_Handler();
 8001414:	f000 fba0 	bl	8001b58 <Error_Handler>
  }
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8001418:	230f      	movs	r3, #15
 800141a:	603b      	str	r3, [r7, #0]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 800141c:	2303      	movs	r3, #3
 800141e:	607b      	str	r3, [r7, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8001420:	2300      	movs	r3, #0
 8001422:	60bb      	str	r3, [r7, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 8001424:	2300      	movs	r3, #0
 8001426:	60fb      	str	r3, [r7, #12]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8001428:	2300      	movs	r3, #0
 800142a:	613b      	str	r3, [r7, #16]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 800142c:	463b      	mov	r3, r7
 800142e:	2101      	movs	r1, #1
 8001430:	4618      	mov	r0, r3
 8001432:	f003 fca9 	bl	8004d88 <HAL_RCC_ClockConfig>
 8001436:	4603      	mov	r3, r0
 8001438:	2b00      	cmp	r3, #0
 800143a:	d001      	beq.n	8001440 <SystemClock_Config+0x94>
  {
    Error_Handler();
 800143c:	f000 fb8c 	bl	8001b58 <Error_Handler>
  }
}
 8001440:	bf00      	nop
 8001442:	3748      	adds	r7, #72	; 0x48
 8001444:	46bd      	mov	sp, r7
 8001446:	bd80      	pop	{r7, pc}
 8001448:	40007000 	.word	0x40007000

0800144c <MX_ADC_Init>:
  * @brief ADC Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC_Init(void)
{
 800144c:	b580      	push	{r7, lr}
 800144e:	b084      	sub	sp, #16
 8001450:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC_Init 0 */

  /* USER CODE END ADC_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
 8001452:	1d3b      	adds	r3, r7, #4
 8001454:	2200      	movs	r2, #0
 8001456:	601a      	str	r2, [r3, #0]
 8001458:	605a      	str	r2, [r3, #4]
 800145a:	609a      	str	r2, [r3, #8]
  /* USER CODE BEGIN ADC_Init 1 */

  /* USER CODE END ADC_Init 1 */
  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
  */
  hadc.Instance = ADC1;
 800145c:	4b34      	ldr	r3, [pc, #208]	; (8001530 <MX_ADC_Init+0xe4>)
 800145e:	4a35      	ldr	r2, [pc, #212]	; (8001534 <MX_ADC_Init+0xe8>)
 8001460:	601a      	str	r2, [r3, #0]
  hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
 8001462:	4b33      	ldr	r3, [pc, #204]	; (8001530 <MX_ADC_Init+0xe4>)
 8001464:	2200      	movs	r2, #0
 8001466:	605a      	str	r2, [r3, #4]
  hadc.Init.Resolution = ADC_RESOLUTION_12B;
 8001468:	4b31      	ldr	r3, [pc, #196]	; (8001530 <MX_ADC_Init+0xe4>)
 800146a:	2200      	movs	r2, #0
 800146c:	609a      	str	r2, [r3, #8]
  hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 800146e:	4b30      	ldr	r3, [pc, #192]	; (8001530 <MX_ADC_Init+0xe4>)
 8001470:	2200      	movs	r2, #0
 8001472:	60da      	str	r2, [r3, #12]
  hadc.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8001474:	4b2e      	ldr	r3, [pc, #184]	; (8001530 <MX_ADC_Init+0xe4>)
 8001476:	f44f 7280 	mov.w	r2, #256	; 0x100
 800147a:	611a      	str	r2, [r3, #16]
  hadc.Init.EOCSelection = ADC_EOC_SEQ_CONV;
 800147c:	4b2c      	ldr	r3, [pc, #176]	; (8001530 <MX_ADC_Init+0xe4>)
 800147e:	2200      	movs	r2, #0
 8001480:	615a      	str	r2, [r3, #20]
  hadc.Init.LowPowerAutoWait = ADC_AUTOWAIT_DISABLE;
 8001482:	4b2b      	ldr	r3, [pc, #172]	; (8001530 <MX_ADC_Init+0xe4>)
 8001484:	2200      	movs	r2, #0
 8001486:	619a      	str	r2, [r3, #24]
  hadc.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_DISABLE;
 8001488:	4b29      	ldr	r3, [pc, #164]	; (8001530 <MX_ADC_Init+0xe4>)
 800148a:	2200      	movs	r2, #0
 800148c:	61da      	str	r2, [r3, #28]
  hadc.Init.ChannelsBank = ADC_CHANNELS_BANK_A;
 800148e:	4b28      	ldr	r3, [pc, #160]	; (8001530 <MX_ADC_Init+0xe4>)
 8001490:	2200      	movs	r2, #0
 8001492:	621a      	str	r2, [r3, #32]
  hadc.Init.ContinuousConvMode = DISABLE;
 8001494:	4b26      	ldr	r3, [pc, #152]	; (8001530 <MX_ADC_Init+0xe4>)
 8001496:	2200      	movs	r2, #0
 8001498:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
  hadc.Init.NbrOfConversion = 3;
 800149c:	4b24      	ldr	r3, [pc, #144]	; (8001530 <MX_ADC_Init+0xe4>)
 800149e:	2203      	movs	r2, #3
 80014a0:	629a      	str	r2, [r3, #40]	; 0x28
  hadc.Init.DiscontinuousConvMode = DISABLE;
 80014a2:	4b23      	ldr	r3, [pc, #140]	; (8001530 <MX_ADC_Init+0xe4>)
 80014a4:	2200      	movs	r2, #0
 80014a6:	f883 202c 	strb.w	r2, [r3, #44]	; 0x2c
  hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 80014aa:	4b21      	ldr	r3, [pc, #132]	; (8001530 <MX_ADC_Init+0xe4>)
 80014ac:	2210      	movs	r2, #16
 80014ae:	635a      	str	r2, [r3, #52]	; 0x34
  hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
 80014b0:	4b1f      	ldr	r3, [pc, #124]	; (8001530 <MX_ADC_Init+0xe4>)
 80014b2:	2200      	movs	r2, #0
 80014b4:	639a      	str	r2, [r3, #56]	; 0x38
  hadc.Init.DMAContinuousRequests = DISABLE;
 80014b6:	4b1e      	ldr	r3, [pc, #120]	; (8001530 <MX_ADC_Init+0xe4>)
 80014b8:	2200      	movs	r2, #0
 80014ba:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
  if (HAL_ADC_Init(&hadc) != HAL_OK)
 80014be:	481c      	ldr	r0, [pc, #112]	; (8001530 <MX_ADC_Init+0xe4>)
 80014c0:	f000 ffee 	bl	80024a0 <HAL_ADC_Init>
 80014c4:	4603      	mov	r3, r0
 80014c6:	2b00      	cmp	r3, #0
 80014c8:	d001      	beq.n	80014ce <MX_ADC_Init+0x82>
  {
    Error_Handler();
 80014ca:	f000 fb45 	bl	8001b58 <Error_Handler>
  }
  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
  */
  sConfig.Channel = ADC_CHANNEL_0;
 80014ce:	2300      	movs	r3, #0
 80014d0:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 80014d2:	2301      	movs	r3, #1
 80014d4:	60bb      	str	r3, [r7, #8]
  sConfig.SamplingTime = ADC_SAMPLETIME_48CYCLES;
 80014d6:	2304      	movs	r3, #4
 80014d8:	60fb      	str	r3, [r7, #12]
  if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
 80014da:	1d3b      	adds	r3, r7, #4
 80014dc:	4619      	mov	r1, r3
 80014de:	4814      	ldr	r0, [pc, #80]	; (8001530 <MX_ADC_Init+0xe4>)
 80014e0:	f001 fa1e 	bl	8002920 <HAL_ADC_ConfigChannel>
 80014e4:	4603      	mov	r3, r0
 80014e6:	2b00      	cmp	r3, #0
 80014e8:	d001      	beq.n	80014ee <MX_ADC_Init+0xa2>
  {
    Error_Handler();
 80014ea:	f000 fb35 	bl	8001b58 <Error_Handler>
  }
  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
  */
  sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
 80014ee:	2310      	movs	r3, #16
 80014f0:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 80014f2:	2302      	movs	r3, #2
 80014f4:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
 80014f6:	1d3b      	adds	r3, r7, #4
 80014f8:	4619      	mov	r1, r3
 80014fa:	480d      	ldr	r0, [pc, #52]	; (8001530 <MX_ADC_Init+0xe4>)
 80014fc:	f001 fa10 	bl	8002920 <HAL_ADC_ConfigChannel>
 8001500:	4603      	mov	r3, r0
 8001502:	2b00      	cmp	r3, #0
 8001504:	d001      	beq.n	800150a <MX_ADC_Init+0xbe>
  {
    Error_Handler();
 8001506:	f000 fb27 	bl	8001b58 <Error_Handler>
  }
  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
  */
  sConfig.Channel = ADC_CHANNEL_VREFINT;
 800150a:	2311      	movs	r3, #17
 800150c:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 800150e:	2303      	movs	r3, #3
 8001510:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
 8001512:	1d3b      	adds	r3, r7, #4
 8001514:	4619      	mov	r1, r3
 8001516:	4806      	ldr	r0, [pc, #24]	; (8001530 <MX_ADC_Init+0xe4>)
 8001518:	f001 fa02 	bl	8002920 <HAL_ADC_ConfigChannel>
 800151c:	4603      	mov	r3, r0
 800151e:	2b00      	cmp	r3, #0
 8001520:	d001      	beq.n	8001526 <MX_ADC_Init+0xda>
  {
    Error_Handler();
 8001522:	f000 fb19 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN ADC_Init 2 */

  /* USER CODE END ADC_Init 2 */

}
 8001526:	bf00      	nop
 8001528:	3710      	adds	r7, #16
 800152a:	46bd      	mov	sp, r7
 800152c:	bd80      	pop	{r7, pc}
 800152e:	bf00      	nop
 8001530:	20000690 	.word	0x20000690
 8001534:	40012400 	.word	0x40012400

08001538 <MX_COMP2_Init>:
  * @brief COMP2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_COMP2_Init(void)
{
 8001538:	b580      	push	{r7, lr}
 800153a:	af00      	add	r7, sp, #0
  /* USER CODE END COMP2_Init 0 */

  /* USER CODE BEGIN COMP2_Init 1 */

  /* USER CODE END COMP2_Init 1 */
  hcomp2.Instance = COMP2;
 800153c:	4b10      	ldr	r3, [pc, #64]	; (8001580 <MX_COMP2_Init+0x48>)
 800153e:	4a11      	ldr	r2, [pc, #68]	; (8001584 <MX_COMP2_Init+0x4c>)
 8001540:	601a      	str	r2, [r3, #0]
  hcomp2.Init.InvertingInput = COMP_INVERTINGINPUT_DAC2;
 8001542:	4b0f      	ldr	r3, [pc, #60]	; (8001580 <MX_COMP2_Init+0x48>)
 8001544:	f44f 12e0 	mov.w	r2, #1835008	; 0x1c0000
 8001548:	605a      	str	r2, [r3, #4]
  hcomp2.Init.NonInvertingInput = COMP_NONINVERTINGINPUT_PB4;
 800154a:	4b0d      	ldr	r3, [pc, #52]	; (8001580 <MX_COMP2_Init+0x48>)
 800154c:	2210      	movs	r2, #16
 800154e:	609a      	str	r2, [r3, #8]
  hcomp2.Init.Output = COMP_OUTPUT_NONE;
 8001550:	4b0b      	ldr	r3, [pc, #44]	; (8001580 <MX_COMP2_Init+0x48>)
 8001552:	f44f 0260 	mov.w	r2, #14680064	; 0xe00000
 8001556:	60da      	str	r2, [r3, #12]
  hcomp2.Init.Mode = COMP_MODE_HIGHSPEED;
 8001558:	4b09      	ldr	r3, [pc, #36]	; (8001580 <MX_COMP2_Init+0x48>)
 800155a:	f44f 5280 	mov.w	r2, #4096	; 0x1000
 800155e:	611a      	str	r2, [r3, #16]
  hcomp2.Init.WindowMode = COMP_WINDOWMODE_DISABLE;
 8001560:	4b07      	ldr	r3, [pc, #28]	; (8001580 <MX_COMP2_Init+0x48>)
 8001562:	2200      	movs	r2, #0
 8001564:	615a      	str	r2, [r3, #20]
  hcomp2.Init.TriggerMode = COMP_TRIGGERMODE_IT_RISING;
 8001566:	4b06      	ldr	r3, [pc, #24]	; (8001580 <MX_COMP2_Init+0x48>)
 8001568:	2201      	movs	r2, #1
 800156a:	619a      	str	r2, [r3, #24]
  if (HAL_COMP_Init(&hcomp2) != HAL_OK)
 800156c:	4804      	ldr	r0, [pc, #16]	; (8001580 <MX_COMP2_Init+0x48>)
 800156e:	f001 fc41 	bl	8002df4 <HAL_COMP_Init>
 8001572:	4603      	mov	r3, r0
 8001574:	2b00      	cmp	r3, #0
 8001576:	d001      	beq.n	800157c <MX_COMP2_Init+0x44>
  {
    Error_Handler();
 8001578:	f000 faee 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN COMP2_Init 2 */

  /* USER CODE END COMP2_Init 2 */

}
 800157c:	bf00      	nop
 800157e:	bd80      	pop	{r7, pc}
 8001580:	200005d8 	.word	0x200005d8
 8001584:	40007c01 	.word	0x40007c01

08001588 <MX_DAC_Init>:
  * @brief DAC Initialization Function
  * @param None
  * @retval None
  */
static void MX_DAC_Init(void)
{
 8001588:	b580      	push	{r7, lr}
 800158a:	b082      	sub	sp, #8
 800158c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN DAC_Init 0 */

  /* USER CODE END DAC_Init 0 */

  DAC_ChannelConfTypeDef sConfig = {0};
 800158e:	463b      	mov	r3, r7
 8001590:	2200      	movs	r2, #0
 8001592:	601a      	str	r2, [r3, #0]
 8001594:	605a      	str	r2, [r3, #4]
  /* USER CODE BEGIN DAC_Init 1 */

  /* USER CODE END DAC_Init 1 */
  /** DAC Initialization
  */
  hdac.Instance = DAC;
 8001596:	4b15      	ldr	r3, [pc, #84]	; (80015ec <MX_DAC_Init+0x64>)
 8001598:	4a15      	ldr	r2, [pc, #84]	; (80015f0 <MX_DAC_Init+0x68>)
 800159a:	601a      	str	r2, [r3, #0]
  if (HAL_DAC_Init(&hdac) != HAL_OK)
 800159c:	4813      	ldr	r0, [pc, #76]	; (80015ec <MX_DAC_Init+0x64>)
 800159e:	f001 fec4 	bl	800332a <HAL_DAC_Init>
 80015a2:	4603      	mov	r3, r0
 80015a4:	2b00      	cmp	r3, #0
 80015a6:	d001      	beq.n	80015ac <MX_DAC_Init+0x24>
  {
    Error_Handler();
 80015a8:	f000 fad6 	bl	8001b58 <Error_Handler>
  }
  /** DAC channel OUT1 config
  */
  sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
 80015ac:	2300      	movs	r3, #0
 80015ae:	603b      	str	r3, [r7, #0]
  sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
 80015b0:	2300      	movs	r3, #0
 80015b2:	607b      	str	r3, [r7, #4]
  if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK)
 80015b4:	463b      	mov	r3, r7
 80015b6:	2200      	movs	r2, #0
 80015b8:	4619      	mov	r1, r3
 80015ba:	480c      	ldr	r0, [pc, #48]	; (80015ec <MX_DAC_Init+0x64>)
 80015bc:	f001 ff4c 	bl	8003458 <HAL_DAC_ConfigChannel>
 80015c0:	4603      	mov	r3, r0
 80015c2:	2b00      	cmp	r3, #0
 80015c4:	d001      	beq.n	80015ca <MX_DAC_Init+0x42>
  {
    Error_Handler();
 80015c6:	f000 fac7 	bl	8001b58 <Error_Handler>
  }
  /** DAC channel OUT2 config
  */
  sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
 80015ca:	2302      	movs	r3, #2
 80015cc:	607b      	str	r3, [r7, #4]
  if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_2) != HAL_OK)
 80015ce:	463b      	mov	r3, r7
 80015d0:	2210      	movs	r2, #16
 80015d2:	4619      	mov	r1, r3
 80015d4:	4805      	ldr	r0, [pc, #20]	; (80015ec <MX_DAC_Init+0x64>)
 80015d6:	f001 ff3f 	bl	8003458 <HAL_DAC_ConfigChannel>
 80015da:	4603      	mov	r3, r0
 80015dc:	2b00      	cmp	r3, #0
 80015de:	d001      	beq.n	80015e4 <MX_DAC_Init+0x5c>
  {
    Error_Handler();
 80015e0:	f000 faba 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN DAC_Init 2 */

  /* USER CODE END DAC_Init 2 */

}
 80015e4:	bf00      	nop
 80015e6:	3708      	adds	r7, #8
 80015e8:	46bd      	mov	sp, r7
 80015ea:	bd80      	pop	{r7, pc}
 80015ec:	20000584 	.word	0x20000584
 80015f0:	40007400 	.word	0x40007400

080015f4 <MX_I2C1_Init>:
  * @brief I2C1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_I2C1_Init(void)
{
 80015f4:	b580      	push	{r7, lr}
 80015f6:	af00      	add	r7, sp, #0
  /* USER CODE END I2C1_Init 0 */

  /* USER CODE BEGIN I2C1_Init 1 */

  /* USER CODE END I2C1_Init 1 */
  hi2c1.Instance = I2C1;
 80015f8:	4b12      	ldr	r3, [pc, #72]	; (8001644 <MX_I2C1_Init+0x50>)
 80015fa:	4a13      	ldr	r2, [pc, #76]	; (8001648 <MX_I2C1_Init+0x54>)
 80015fc:	601a      	str	r2, [r3, #0]
  hi2c1.Init.ClockSpeed = 400000;
 80015fe:	4b11      	ldr	r3, [pc, #68]	; (8001644 <MX_I2C1_Init+0x50>)
 8001600:	4a12      	ldr	r2, [pc, #72]	; (800164c <MX_I2C1_Init+0x58>)
 8001602:	605a      	str	r2, [r3, #4]
  hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
 8001604:	4b0f      	ldr	r3, [pc, #60]	; (8001644 <MX_I2C1_Init+0x50>)
 8001606:	2200      	movs	r2, #0
 8001608:	609a      	str	r2, [r3, #8]
  hi2c1.Init.OwnAddress1 = 0;
 800160a:	4b0e      	ldr	r3, [pc, #56]	; (8001644 <MX_I2C1_Init+0x50>)
 800160c:	2200      	movs	r2, #0
 800160e:	60da      	str	r2, [r3, #12]
  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 8001610:	4b0c      	ldr	r3, [pc, #48]	; (8001644 <MX_I2C1_Init+0x50>)
 8001612:	f44f 4280 	mov.w	r2, #16384	; 0x4000
 8001616:	611a      	str	r2, [r3, #16]
  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 8001618:	4b0a      	ldr	r3, [pc, #40]	; (8001644 <MX_I2C1_Init+0x50>)
 800161a:	2200      	movs	r2, #0
 800161c:	615a      	str	r2, [r3, #20]
  hi2c1.Init.OwnAddress2 = 0;
 800161e:	4b09      	ldr	r3, [pc, #36]	; (8001644 <MX_I2C1_Init+0x50>)
 8001620:	2200      	movs	r2, #0
 8001622:	619a      	str	r2, [r3, #24]
  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 8001624:	4b07      	ldr	r3, [pc, #28]	; (8001644 <MX_I2C1_Init+0x50>)
 8001626:	2200      	movs	r2, #0
 8001628:	61da      	str	r2, [r3, #28]
  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 800162a:	4b06      	ldr	r3, [pc, #24]	; (8001644 <MX_I2C1_Init+0x50>)
 800162c:	2200      	movs	r2, #0
 800162e:	621a      	str	r2, [r3, #32]
  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
 8001630:	4804      	ldr	r0, [pc, #16]	; (8001644 <MX_I2C1_Init+0x50>)
 8001632:	f002 fbc3 	bl	8003dbc <HAL_I2C_Init>
 8001636:	4603      	mov	r3, r0
 8001638:	2b00      	cmp	r3, #0
 800163a:	d001      	beq.n	8001640 <MX_I2C1_Init+0x4c>
  {
    Error_Handler();
 800163c:	f000 fa8c 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN I2C1_Init 2 */

  /* USER CODE END I2C1_Init 2 */

}
 8001640:	bf00      	nop
 8001642:	bd80      	pop	{r7, pc}
 8001644:	20000458 	.word	0x20000458
 8001648:	40005400 	.word	0x40005400
 800164c:	00061a80 	.word	0x00061a80

08001650 <MX_I2C2_Init>:
  * @brief I2C2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_I2C2_Init(void)
{
 8001650:	b580      	push	{r7, lr}
 8001652:	af00      	add	r7, sp, #0
  /* USER CODE END I2C2_Init 0 */

  /* USER CODE BEGIN I2C2_Init 1 */

  /* USER CODE END I2C2_Init 1 */
  hi2c2.Instance = I2C2;
 8001654:	4b12      	ldr	r3, [pc, #72]	; (80016a0 <MX_I2C2_Init+0x50>)
 8001656:	4a13      	ldr	r2, [pc, #76]	; (80016a4 <MX_I2C2_Init+0x54>)
 8001658:	601a      	str	r2, [r3, #0]
  hi2c2.Init.ClockSpeed = 100000;
 800165a:	4b11      	ldr	r3, [pc, #68]	; (80016a0 <MX_I2C2_Init+0x50>)
 800165c:	4a12      	ldr	r2, [pc, #72]	; (80016a8 <MX_I2C2_Init+0x58>)
 800165e:	605a      	str	r2, [r3, #4]
  hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
 8001660:	4b0f      	ldr	r3, [pc, #60]	; (80016a0 <MX_I2C2_Init+0x50>)
 8001662:	2200      	movs	r2, #0
 8001664:	609a      	str	r2, [r3, #8]
  hi2c2.Init.OwnAddress1 = 0;
 8001666:	4b0e      	ldr	r3, [pc, #56]	; (80016a0 <MX_I2C2_Init+0x50>)
 8001668:	2200      	movs	r2, #0
 800166a:	60da      	str	r2, [r3, #12]
  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 800166c:	4b0c      	ldr	r3, [pc, #48]	; (80016a0 <MX_I2C2_Init+0x50>)
 800166e:	f44f 4280 	mov.w	r2, #16384	; 0x4000
 8001672:	611a      	str	r2, [r3, #16]
  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 8001674:	4b0a      	ldr	r3, [pc, #40]	; (80016a0 <MX_I2C2_Init+0x50>)
 8001676:	2200      	movs	r2, #0
 8001678:	615a      	str	r2, [r3, #20]
  hi2c2.Init.OwnAddress2 = 0;
 800167a:	4b09      	ldr	r3, [pc, #36]	; (80016a0 <MX_I2C2_Init+0x50>)
 800167c:	2200      	movs	r2, #0
 800167e:	619a      	str	r2, [r3, #24]
  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 8001680:	4b07      	ldr	r3, [pc, #28]	; (80016a0 <MX_I2C2_Init+0x50>)
 8001682:	2200      	movs	r2, #0
 8001684:	61da      	str	r2, [r3, #28]
  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 8001686:	4b06      	ldr	r3, [pc, #24]	; (80016a0 <MX_I2C2_Init+0x50>)
 8001688:	2200      	movs	r2, #0
 800168a:	621a      	str	r2, [r3, #32]
  if (HAL_I2C_Init(&hi2c2) != HAL_OK)
 800168c:	4804      	ldr	r0, [pc, #16]	; (80016a0 <MX_I2C2_Init+0x50>)
 800168e:	f002 fb95 	bl	8003dbc <HAL_I2C_Init>
 8001692:	4603      	mov	r3, r0
 8001694:	2b00      	cmp	r3, #0
 8001696:	d001      	beq.n	800169c <MX_I2C2_Init+0x4c>
  {
    Error_Handler();
 8001698:	f000 fa5e 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN I2C2_Init 2 */

  /* USER CODE END I2C2_Init 2 */

}
 800169c:	bf00      	nop
 800169e:	bd80      	pop	{r7, pc}
 80016a0:	200004ac 	.word	0x200004ac
 80016a4:	40005800 	.word	0x40005800
 80016a8:	000186a0 	.word	0x000186a0

080016ac <MX_TIM2_Init>:
  * @brief TIM2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM2_Init(void)
{
 80016ac:	b580      	push	{r7, lr}
 80016ae:	b086      	sub	sp, #24
 80016b0:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM2_Init 0 */

  /* USER CODE END TIM2_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 80016b2:	f107 0308 	add.w	r3, r7, #8
 80016b6:	2200      	movs	r2, #0
 80016b8:	601a      	str	r2, [r3, #0]
 80016ba:	605a      	str	r2, [r3, #4]
 80016bc:	609a      	str	r2, [r3, #8]
 80016be:	60da      	str	r2, [r3, #12]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 80016c0:	463b      	mov	r3, r7
 80016c2:	2200      	movs	r2, #0
 80016c4:	601a      	str	r2, [r3, #0]
 80016c6:	605a      	str	r2, [r3, #4]

  /* USER CODE BEGIN TIM2_Init 1 */

  /* USER CODE END TIM2_Init 1 */
  htim2.Instance = TIM2;
 80016c8:	4b22      	ldr	r3, [pc, #136]	; (8001754 <MX_TIM2_Init+0xa8>)
 80016ca:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
 80016ce:	601a      	str	r2, [r3, #0]
  htim2.Init.Prescaler = 600;
 80016d0:	4b20      	ldr	r3, [pc, #128]	; (8001754 <MX_TIM2_Init+0xa8>)
 80016d2:	f44f 7216 	mov.w	r2, #600	; 0x258
 80016d6:	605a      	str	r2, [r3, #4]
  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
 80016d8:	4b1e      	ldr	r3, [pc, #120]	; (8001754 <MX_TIM2_Init+0xa8>)
 80016da:	2200      	movs	r2, #0
 80016dc:	609a      	str	r2, [r3, #8]
  htim2.Init.Period = 1000;
 80016de:	4b1d      	ldr	r3, [pc, #116]	; (8001754 <MX_TIM2_Init+0xa8>)
 80016e0:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
 80016e4:	60da      	str	r2, [r3, #12]
  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 80016e6:	4b1b      	ldr	r3, [pc, #108]	; (8001754 <MX_TIM2_Init+0xa8>)
 80016e8:	2200      	movs	r2, #0
 80016ea:	611a      	str	r2, [r3, #16]
  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 80016ec:	4b19      	ldr	r3, [pc, #100]	; (8001754 <MX_TIM2_Init+0xa8>)
 80016ee:	2200      	movs	r2, #0
 80016f0:	615a      	str	r2, [r3, #20]
  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
 80016f2:	4818      	ldr	r0, [pc, #96]	; (8001754 <MX_TIM2_Init+0xa8>)
 80016f4:	f003 fddc 	bl	80052b0 <HAL_TIM_Base_Init>
 80016f8:	4603      	mov	r3, r0
 80016fa:	2b00      	cmp	r3, #0
 80016fc:	d001      	beq.n	8001702 <MX_TIM2_Init+0x56>
  {
    Error_Handler();
 80016fe:	f000 fa2b 	bl	8001b58 <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 8001702:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 8001706:	60bb      	str	r3, [r7, #8]
  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
 8001708:	f107 0308 	add.w	r3, r7, #8
 800170c:	4619      	mov	r1, r3
 800170e:	4811      	ldr	r0, [pc, #68]	; (8001754 <MX_TIM2_Init+0xa8>)
 8001710:	f004 f992 	bl	8005a38 <HAL_TIM_ConfigClockSource>
 8001714:	4603      	mov	r3, r0
 8001716:	2b00      	cmp	r3, #0
 8001718:	d001      	beq.n	800171e <MX_TIM2_Init+0x72>
  {
    Error_Handler();
 800171a:	f000 fa1d 	bl	8001b58 <Error_Handler>
  }
  if (HAL_TIM_OnePulse_Init(&htim2, TIM_OPMODE_SINGLE) != HAL_OK)
 800171e:	2108      	movs	r1, #8
 8001720:	480c      	ldr	r0, [pc, #48]	; (8001754 <MX_TIM2_Init+0xa8>)
 8001722:	f003 ff9d 	bl	8005660 <HAL_TIM_OnePulse_Init>
 8001726:	4603      	mov	r3, r0
 8001728:	2b00      	cmp	r3, #0
 800172a:	d001      	beq.n	8001730 <MX_TIM2_Init+0x84>
  {
    Error_Handler();
 800172c:	f000 fa14 	bl	8001b58 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_ENABLE;
 8001730:	2310      	movs	r3, #16
 8001732:	603b      	str	r3, [r7, #0]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8001734:	2300      	movs	r3, #0
 8001736:	607b      	str	r3, [r7, #4]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
 8001738:	463b      	mov	r3, r7
 800173a:	4619      	mov	r1, r3
 800173c:	4805      	ldr	r0, [pc, #20]	; (8001754 <MX_TIM2_Init+0xa8>)
 800173e:	f004 fd45 	bl	80061cc <HAL_TIMEx_MasterConfigSynchronization>
 8001742:	4603      	mov	r3, r0
 8001744:	2b00      	cmp	r3, #0
 8001746:	d001      	beq.n	800174c <MX_TIM2_Init+0xa0>
  {
    Error_Handler();
 8001748:	f000 fa06 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN TIM2_Init 2 */

  /* USER CODE END TIM2_Init 2 */

}
 800174c:	bf00      	nop
 800174e:	3718      	adds	r7, #24
 8001750:	46bd      	mov	sp, r7
 8001752:	bd80      	pop	{r7, pc}
 8001754:	20000600 	.word	0x20000600

08001758 <MX_TIM3_Init>:
  * @brief TIM3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM3_Init(void)
{
 8001758:	b580      	push	{r7, lr}
 800175a:	b090      	sub	sp, #64	; 0x40
 800175c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM3_Init 0 */

  /* USER CODE END TIM3_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 800175e:	f107 0330 	add.w	r3, r7, #48	; 0x30
 8001762:	2200      	movs	r2, #0
 8001764:	601a      	str	r2, [r3, #0]
 8001766:	605a      	str	r2, [r3, #4]
 8001768:	609a      	str	r2, [r3, #8]
 800176a:	60da      	str	r2, [r3, #12]
  TIM_SlaveConfigTypeDef sSlaveConfig = {0};
 800176c:	f107 031c 	add.w	r3, r7, #28
 8001770:	2200      	movs	r2, #0
 8001772:	601a      	str	r2, [r3, #0]
 8001774:	605a      	str	r2, [r3, #4]
 8001776:	609a      	str	r2, [r3, #8]
 8001778:	60da      	str	r2, [r3, #12]
 800177a:	611a      	str	r2, [r3, #16]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 800177c:	f107 0314 	add.w	r3, r7, #20
 8001780:	2200      	movs	r2, #0
 8001782:	601a      	str	r2, [r3, #0]
 8001784:	605a      	str	r2, [r3, #4]
  TIM_OC_InitTypeDef sConfigOC = {0};
 8001786:	1d3b      	adds	r3, r7, #4
 8001788:	2200      	movs	r2, #0
 800178a:	601a      	str	r2, [r3, #0]
 800178c:	605a      	str	r2, [r3, #4]
 800178e:	609a      	str	r2, [r3, #8]
 8001790:	60da      	str	r2, [r3, #12]

  /* USER CODE BEGIN TIM3_Init 1 */

  /* USER CODE END TIM3_Init 1 */
  htim3.Instance = TIM3;
 8001792:	4b34      	ldr	r3, [pc, #208]	; (8001864 <MX_TIM3_Init+0x10c>)
 8001794:	4a34      	ldr	r2, [pc, #208]	; (8001868 <MX_TIM3_Init+0x110>)
 8001796:	601a      	str	r2, [r3, #0]
  htim3.Init.Prescaler = 48;
 8001798:	4b32      	ldr	r3, [pc, #200]	; (8001864 <MX_TIM3_Init+0x10c>)
 800179a:	2230      	movs	r2, #48	; 0x30
 800179c:	605a      	str	r2, [r3, #4]
  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
 800179e:	4b31      	ldr	r3, [pc, #196]	; (8001864 <MX_TIM3_Init+0x10c>)
 80017a0:	2200      	movs	r2, #0
 80017a2:	609a      	str	r2, [r3, #8]
  htim3.Init.Period = 1000;
 80017a4:	4b2f      	ldr	r3, [pc, #188]	; (8001864 <MX_TIM3_Init+0x10c>)
 80017a6:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
 80017aa:	60da      	str	r2, [r3, #12]
  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 80017ac:	4b2d      	ldr	r3, [pc, #180]	; (8001864 <MX_TIM3_Init+0x10c>)
 80017ae:	2200      	movs	r2, #0
 80017b0:	611a      	str	r2, [r3, #16]
  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 80017b2:	4b2c      	ldr	r3, [pc, #176]	; (8001864 <MX_TIM3_Init+0x10c>)
 80017b4:	2200      	movs	r2, #0
 80017b6:	615a      	str	r2, [r3, #20]
  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
 80017b8:	482a      	ldr	r0, [pc, #168]	; (8001864 <MX_TIM3_Init+0x10c>)
 80017ba:	f003 fd79 	bl	80052b0 <HAL_TIM_Base_Init>
 80017be:	4603      	mov	r3, r0
 80017c0:	2b00      	cmp	r3, #0
 80017c2:	d001      	beq.n	80017c8 <MX_TIM3_Init+0x70>
  {
    Error_Handler();
 80017c4:	f000 f9c8 	bl	8001b58 <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 80017c8:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 80017cc:	633b      	str	r3, [r7, #48]	; 0x30
  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
 80017ce:	f107 0330 	add.w	r3, r7, #48	; 0x30
 80017d2:	4619      	mov	r1, r3
 80017d4:	4823      	ldr	r0, [pc, #140]	; (8001864 <MX_TIM3_Init+0x10c>)
 80017d6:	f004 f92f 	bl	8005a38 <HAL_TIM_ConfigClockSource>
 80017da:	4603      	mov	r3, r0
 80017dc:	2b00      	cmp	r3, #0
 80017de:	d001      	beq.n	80017e4 <MX_TIM3_Init+0x8c>
  {
    Error_Handler();
 80017e0:	f000 f9ba 	bl	8001b58 <Error_Handler>
  }
  if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
 80017e4:	481f      	ldr	r0, [pc, #124]	; (8001864 <MX_TIM3_Init+0x10c>)
 80017e6:	f003 fef3 	bl	80055d0 <HAL_TIM_PWM_Init>
 80017ea:	4603      	mov	r3, r0
 80017ec:	2b00      	cmp	r3, #0
 80017ee:	d001      	beq.n	80017f4 <MX_TIM3_Init+0x9c>
  {
    Error_Handler();
 80017f0:	f000 f9b2 	bl	8001b58 <Error_Handler>
  }
  sSlaveConfig.SlaveMode = TIM_SLAVEMODE_GATED;
 80017f4:	2305      	movs	r3, #5
 80017f6:	61fb      	str	r3, [r7, #28]
  sSlaveConfig.InputTrigger = TIM_TS_ITR1;
 80017f8:	2310      	movs	r3, #16
 80017fa:	623b      	str	r3, [r7, #32]
  if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)
 80017fc:	f107 031c 	add.w	r3, r7, #28
 8001800:	4619      	mov	r1, r3
 8001802:	4818      	ldr	r0, [pc, #96]	; (8001864 <MX_TIM3_Init+0x10c>)
 8001804:	f004 f9dc 	bl	8005bc0 <HAL_TIM_SlaveConfigSynchro>
 8001808:	4603      	mov	r3, r0
 800180a:	2b00      	cmp	r3, #0
 800180c:	d001      	beq.n	8001812 <MX_TIM3_Init+0xba>
  {
    Error_Handler();
 800180e:	f000 f9a3 	bl	8001b58 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8001812:	2300      	movs	r3, #0
 8001814:	617b      	str	r3, [r7, #20]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8001816:	2300      	movs	r3, #0
 8001818:	61bb      	str	r3, [r7, #24]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
 800181a:	f107 0314 	add.w	r3, r7, #20
 800181e:	4619      	mov	r1, r3
 8001820:	4810      	ldr	r0, [pc, #64]	; (8001864 <MX_TIM3_Init+0x10c>)
 8001822:	f004 fcd3 	bl	80061cc <HAL_TIMEx_MasterConfigSynchronization>
 8001826:	4603      	mov	r3, r0
 8001828:	2b00      	cmp	r3, #0
 800182a:	d001      	beq.n	8001830 <MX_TIM3_Init+0xd8>
  {
    Error_Handler();
 800182c:	f000 f994 	bl	8001b58 <Error_Handler>
  }
  sConfigOC.OCMode = TIM_OCMODE_PWM1;
 8001830:	2360      	movs	r3, #96	; 0x60
 8001832:	607b      	str	r3, [r7, #4]
  sConfigOC.Pulse = 10;
 8001834:	230a      	movs	r3, #10
 8001836:	60bb      	str	r3, [r7, #8]
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
 8001838:	2300      	movs	r3, #0
 800183a:	60fb      	str	r3, [r7, #12]
  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
 800183c:	2300      	movs	r3, #0
 800183e:	613b      	str	r3, [r7, #16]
  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
 8001840:	1d3b      	adds	r3, r7, #4
 8001842:	220c      	movs	r2, #12
 8001844:	4619      	mov	r1, r3
 8001846:	4807      	ldr	r0, [pc, #28]	; (8001864 <MX_TIM3_Init+0x10c>)
 8001848:	f004 f838 	bl	80058bc <HAL_TIM_PWM_ConfigChannel>
 800184c:	4603      	mov	r3, r0
 800184e:	2b00      	cmp	r3, #0
 8001850:	d001      	beq.n	8001856 <MX_TIM3_Init+0xfe>
  {
    Error_Handler();
 8001852:	f000 f981 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN TIM3_Init 2 */

  /* USER CODE END TIM3_Init 2 */
  HAL_TIM_MspPostInit(&htim3);
 8001856:	4803      	ldr	r0, [pc, #12]	; (8001864 <MX_TIM3_Init+0x10c>)
 8001858:	f000 fbb0 	bl	8001fbc <HAL_TIM_MspPostInit>

}
 800185c:	bf00      	nop
 800185e:	3740      	adds	r7, #64	; 0x40
 8001860:	46bd      	mov	sp, r7
 8001862:	bd80      	pop	{r7, pc}
 8001864:	20000500 	.word	0x20000500
 8001868:	40000400 	.word	0x40000400

0800186c <MX_TIM4_Init>:
  * @brief TIM4 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM4_Init(void)
{
 800186c:	b580      	push	{r7, lr}
 800186e:	b086      	sub	sp, #24
 8001870:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM4_Init 0 */

  /* USER CODE END TIM4_Init 0 */

  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 8001872:	f107 0308 	add.w	r3, r7, #8
 8001876:	2200      	movs	r2, #0
 8001878:	601a      	str	r2, [r3, #0]
 800187a:	605a      	str	r2, [r3, #4]
 800187c:	609a      	str	r2, [r3, #8]
 800187e:	60da      	str	r2, [r3, #12]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8001880:	463b      	mov	r3, r7
 8001882:	2200      	movs	r2, #0
 8001884:	601a      	str	r2, [r3, #0]
 8001886:	605a      	str	r2, [r3, #4]

  /* USER CODE BEGIN TIM4_Init 1 */

  /* USER CODE END TIM4_Init 1 */
  htim4.Instance = TIM4;
 8001888:	4b1d      	ldr	r3, [pc, #116]	; (8001900 <MX_TIM4_Init+0x94>)
 800188a:	4a1e      	ldr	r2, [pc, #120]	; (8001904 <MX_TIM4_Init+0x98>)
 800188c:	601a      	str	r2, [r3, #0]
  htim4.Init.Prescaler = 240;
 800188e:	4b1c      	ldr	r3, [pc, #112]	; (8001900 <MX_TIM4_Init+0x94>)
 8001890:	22f0      	movs	r2, #240	; 0xf0
 8001892:	605a      	str	r2, [r3, #4]
  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
 8001894:	4b1a      	ldr	r3, [pc, #104]	; (8001900 <MX_TIM4_Init+0x94>)
 8001896:	2200      	movs	r2, #0
 8001898:	609a      	str	r2, [r3, #8]
  htim4.Init.Period = 50000-1;
 800189a:	4b19      	ldr	r3, [pc, #100]	; (8001900 <MX_TIM4_Init+0x94>)
 800189c:	f24c 324f 	movw	r2, #49999	; 0xc34f
 80018a0:	60da      	str	r2, [r3, #12]
  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 80018a2:	4b17      	ldr	r3, [pc, #92]	; (8001900 <MX_TIM4_Init+0x94>)
 80018a4:	2200      	movs	r2, #0
 80018a6:	611a      	str	r2, [r3, #16]
  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 80018a8:	4b15      	ldr	r3, [pc, #84]	; (8001900 <MX_TIM4_Init+0x94>)
 80018aa:	2200      	movs	r2, #0
 80018ac:	615a      	str	r2, [r3, #20]
  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
 80018ae:	4814      	ldr	r0, [pc, #80]	; (8001900 <MX_TIM4_Init+0x94>)
 80018b0:	f003 fcfe 	bl	80052b0 <HAL_TIM_Base_Init>
 80018b4:	4603      	mov	r3, r0
 80018b6:	2b00      	cmp	r3, #0
 80018b8:	d001      	beq.n	80018be <MX_TIM4_Init+0x52>
  {
    Error_Handler();
 80018ba:	f000 f94d 	bl	8001b58 <Error_Handler>
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 80018be:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 80018c2:	60bb      	str	r3, [r7, #8]
  if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
 80018c4:	f107 0308 	add.w	r3, r7, #8
 80018c8:	4619      	mov	r1, r3
 80018ca:	480d      	ldr	r0, [pc, #52]	; (8001900 <MX_TIM4_Init+0x94>)
 80018cc:	f004 f8b4 	bl	8005a38 <HAL_TIM_ConfigClockSource>
 80018d0:	4603      	mov	r3, r0
 80018d2:	2b00      	cmp	r3, #0
 80018d4:	d001      	beq.n	80018da <MX_TIM4_Init+0x6e>
  {
    Error_Handler();
 80018d6:	f000 f93f 	bl	8001b58 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
 80018da:	2320      	movs	r3, #32
 80018dc:	603b      	str	r3, [r7, #0]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 80018de:	2300      	movs	r3, #0
 80018e0:	607b      	str	r3, [r7, #4]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
 80018e2:	463b      	mov	r3, r7
 80018e4:	4619      	mov	r1, r3
 80018e6:	4806      	ldr	r0, [pc, #24]	; (8001900 <MX_TIM4_Init+0x94>)
 80018e8:	f004 fc70 	bl	80061cc <HAL_TIMEx_MasterConfigSynchronization>
 80018ec:	4603      	mov	r3, r0
 80018ee:	2b00      	cmp	r3, #0
 80018f0:	d001      	beq.n	80018f6 <MX_TIM4_Init+0x8a>
  {
    Error_Handler();
 80018f2:	f000 f931 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN TIM4_Init 2 */

  /* USER CODE END TIM4_Init 2 */

}
 80018f6:	bf00      	nop
 80018f8:	3718      	adds	r7, #24
 80018fa:	46bd      	mov	sp, r7
 80018fc:	bd80      	pop	{r7, pc}
 80018fe:	bf00      	nop
 8001900:	20000418 	.word	0x20000418
 8001904:	40000800 	.word	0x40000800

08001908 <MX_TIM6_Init>:
  * @brief TIM6 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM6_Init(void)
{
 8001908:	b580      	push	{r7, lr}
 800190a:	b082      	sub	sp, #8
 800190c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM6_Init 0 */

  /* USER CODE END TIM6_Init 0 */

  TIM_MasterConfigTypeDef sMasterConfig = {0};
 800190e:	463b      	mov	r3, r7
 8001910:	2200      	movs	r2, #0
 8001912:	601a      	str	r2, [r3, #0]
 8001914:	605a      	str	r2, [r3, #4]

  /* USER CODE BEGIN TIM6_Init 1 */

  /* USER CODE END TIM6_Init 1 */
  htim6.Instance = TIM6;
 8001916:	4b15      	ldr	r3, [pc, #84]	; (800196c <MX_TIM6_Init+0x64>)
 8001918:	4a15      	ldr	r2, [pc, #84]	; (8001970 <MX_TIM6_Init+0x68>)
 800191a:	601a      	str	r2, [r3, #0]
  htim6.Init.Prescaler = 600;
 800191c:	4b13      	ldr	r3, [pc, #76]	; (800196c <MX_TIM6_Init+0x64>)
 800191e:	f44f 7216 	mov.w	r2, #600	; 0x258
 8001922:	605a      	str	r2, [r3, #4]
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 8001924:	4b11      	ldr	r3, [pc, #68]	; (800196c <MX_TIM6_Init+0x64>)
 8001926:	2200      	movs	r2, #0
 8001928:	609a      	str	r2, [r3, #8]
  htim6.Init.Period = 20000;
 800192a:	4b10      	ldr	r3, [pc, #64]	; (800196c <MX_TIM6_Init+0x64>)
 800192c:	f644 6220 	movw	r2, #20000	; 0x4e20
 8001930:	60da      	str	r2, [r3, #12]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8001932:	4b0e      	ldr	r3, [pc, #56]	; (800196c <MX_TIM6_Init+0x64>)
 8001934:	2200      	movs	r2, #0
 8001936:	615a      	str	r2, [r3, #20]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8001938:	480c      	ldr	r0, [pc, #48]	; (800196c <MX_TIM6_Init+0x64>)
 800193a:	f003 fcb9 	bl	80052b0 <HAL_TIM_Base_Init>
 800193e:	4603      	mov	r3, r0
 8001940:	2b00      	cmp	r3, #0
 8001942:	d001      	beq.n	8001948 <MX_TIM6_Init+0x40>
  {
    Error_Handler();
 8001944:	f000 f908 	bl	8001b58 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
 8001948:	2320      	movs	r3, #32
 800194a:	603b      	str	r3, [r7, #0]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 800194c:	2300      	movs	r3, #0
 800194e:	607b      	str	r3, [r7, #4]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8001950:	463b      	mov	r3, r7
 8001952:	4619      	mov	r1, r3
 8001954:	4805      	ldr	r0, [pc, #20]	; (800196c <MX_TIM6_Init+0x64>)
 8001956:	f004 fc39 	bl	80061cc <HAL_TIMEx_MasterConfigSynchronization>
 800195a:	4603      	mov	r3, r0
 800195c:	2b00      	cmp	r3, #0
 800195e:	d001      	beq.n	8001964 <MX_TIM6_Init+0x5c>
  {
    Error_Handler();
 8001960:	f000 f8fa 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN TIM6_Init 2 */

  /* USER CODE END TIM6_Init 2 */

}
 8001964:	bf00      	nop
 8001966:	3708      	adds	r7, #8
 8001968:	46bd      	mov	sp, r7
 800196a:	bd80      	pop	{r7, pc}
 800196c:	20000598 	.word	0x20000598
 8001970:	40001000 	.word	0x40001000

08001974 <MX_USART1_UART_Init>:
  * @brief USART1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART1_UART_Init(void)
{
 8001974:	b580      	push	{r7, lr}
 8001976:	af00      	add	r7, sp, #0
  /* USER CODE END USART1_Init 0 */

  /* USER CODE BEGIN USART1_Init 1 */

  /* USER CODE END USART1_Init 1 */
  huart1.Instance = USART1;
 8001978:	4b11      	ldr	r3, [pc, #68]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 800197a:	4a12      	ldr	r2, [pc, #72]	; (80019c4 <MX_USART1_UART_Init+0x50>)
 800197c:	601a      	str	r2, [r3, #0]
  huart1.Init.BaudRate = 115200;
 800197e:	4b10      	ldr	r3, [pc, #64]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 8001980:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
 8001984:	605a      	str	r2, [r3, #4]
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8001986:	4b0e      	ldr	r3, [pc, #56]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 8001988:	2200      	movs	r2, #0
 800198a:	609a      	str	r2, [r3, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 800198c:	4b0c      	ldr	r3, [pc, #48]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 800198e:	2200      	movs	r2, #0
 8001990:	60da      	str	r2, [r3, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8001992:	4b0b      	ldr	r3, [pc, #44]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 8001994:	2200      	movs	r2, #0
 8001996:	611a      	str	r2, [r3, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8001998:	4b09      	ldr	r3, [pc, #36]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 800199a:	220c      	movs	r2, #12
 800199c:	615a      	str	r2, [r3, #20]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 800199e:	4b08      	ldr	r3, [pc, #32]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 80019a0:	2200      	movs	r2, #0
 80019a2:	619a      	str	r2, [r3, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 80019a4:	4b06      	ldr	r3, [pc, #24]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 80019a6:	2200      	movs	r2, #0
 80019a8:	61da      	str	r2, [r3, #28]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 80019aa:	4805      	ldr	r0, [pc, #20]	; (80019c0 <MX_USART1_UART_Init+0x4c>)
 80019ac:	f004 fc6c 	bl	8006288 <HAL_UART_Init>
 80019b0:	4603      	mov	r3, r0
 80019b2:	2b00      	cmp	r3, #0
 80019b4:	d001      	beq.n	80019ba <MX_USART1_UART_Init+0x46>
  {
    Error_Handler();
 80019b6:	f000 f8cf 	bl	8001b58 <Error_Handler>
  }
  /* USER CODE BEGIN USART1_Init 2 */

  /* USER CODE END USART1_Init 2 */

}
 80019ba:	bf00      	nop
 80019bc:	bd80      	pop	{r7, pc}
 80019be:	bf00      	nop
 80019c0:	20000540 	.word	0x20000540
 80019c4:	40013800 	.word	0x40013800

080019c8 <MX_DMA_Init>:

/**
  * Enable DMA controller clock
  */
static void MX_DMA_Init(void)
{
 80019c8:	b580      	push	{r7, lr}
 80019ca:	b082      	sub	sp, #8
 80019cc:	af00      	add	r7, sp, #0

  /* DMA controller clock enable */
  __HAL_RCC_DMA1_CLK_ENABLE();
 80019ce:	4b0c      	ldr	r3, [pc, #48]	; (8001a00 <MX_DMA_Init+0x38>)
 80019d0:	69db      	ldr	r3, [r3, #28]
 80019d2:	4a0b      	ldr	r2, [pc, #44]	; (8001a00 <MX_DMA_Init+0x38>)
 80019d4:	f043 7380 	orr.w	r3, r3, #16777216	; 0x1000000
 80019d8:	61d3      	str	r3, [r2, #28]
 80019da:	4b09      	ldr	r3, [pc, #36]	; (8001a00 <MX_DMA_Init+0x38>)
 80019dc:	69db      	ldr	r3, [r3, #28]
 80019de:	f003 7380 	and.w	r3, r3, #16777216	; 0x1000000
 80019e2:	607b      	str	r3, [r7, #4]
 80019e4:	687b      	ldr	r3, [r7, #4]

  /* DMA interrupt init */
  /* DMA1_Channel1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 80019e6:	2200      	movs	r2, #0
 80019e8:	2100      	movs	r1, #0
 80019ea:	200b      	movs	r0, #11
 80019ec:	f001 fc67 	bl	80032be <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 80019f0:	200b      	movs	r0, #11
 80019f2:	f001 fc80 	bl	80032f6 <HAL_NVIC_EnableIRQ>

}
 80019f6:	bf00      	nop
 80019f8:	3708      	adds	r7, #8
 80019fa:	46bd      	mov	sp, r7
 80019fc:	bd80      	pop	{r7, pc}
 80019fe:	bf00      	nop
 8001a00:	40023800 	.word	0x40023800

08001a04 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8001a04:	b580      	push	{r7, lr}
 8001a06:	b08a      	sub	sp, #40	; 0x28
 8001a08:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001a0a:	f107 0314 	add.w	r3, r7, #20
 8001a0e:	2200      	movs	r2, #0
 8001a10:	601a      	str	r2, [r3, #0]
 8001a12:	605a      	str	r2, [r3, #4]
 8001a14:	609a      	str	r2, [r3, #8]
 8001a16:	60da      	str	r2, [r3, #12]
 8001a18:	611a      	str	r2, [r3, #16]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8001a1a:	4b4b      	ldr	r3, [pc, #300]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a1c:	69db      	ldr	r3, [r3, #28]
 8001a1e:	4a4a      	ldr	r2, [pc, #296]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a20:	f043 0304 	orr.w	r3, r3, #4
 8001a24:	61d3      	str	r3, [r2, #28]
 8001a26:	4b48      	ldr	r3, [pc, #288]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a28:	69db      	ldr	r3, [r3, #28]
 8001a2a:	f003 0304 	and.w	r3, r3, #4
 8001a2e:	613b      	str	r3, [r7, #16]
 8001a30:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOH_CLK_ENABLE();
 8001a32:	4b45      	ldr	r3, [pc, #276]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a34:	69db      	ldr	r3, [r3, #28]
 8001a36:	4a44      	ldr	r2, [pc, #272]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a38:	f043 0320 	orr.w	r3, r3, #32
 8001a3c:	61d3      	str	r3, [r2, #28]
 8001a3e:	4b42      	ldr	r3, [pc, #264]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a40:	69db      	ldr	r3, [r3, #28]
 8001a42:	f003 0320 	and.w	r3, r3, #32
 8001a46:	60fb      	str	r3, [r7, #12]
 8001a48:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8001a4a:	4b3f      	ldr	r3, [pc, #252]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a4c:	69db      	ldr	r3, [r3, #28]
 8001a4e:	4a3e      	ldr	r2, [pc, #248]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a50:	f043 0301 	orr.w	r3, r3, #1
 8001a54:	61d3      	str	r3, [r2, #28]
 8001a56:	4b3c      	ldr	r3, [pc, #240]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a58:	69db      	ldr	r3, [r3, #28]
 8001a5a:	f003 0301 	and.w	r3, r3, #1
 8001a5e:	60bb      	str	r3, [r7, #8]
 8001a60:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8001a62:	4b39      	ldr	r3, [pc, #228]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a64:	69db      	ldr	r3, [r3, #28]
 8001a66:	4a38      	ldr	r2, [pc, #224]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a68:	f043 0302 	orr.w	r3, r3, #2
 8001a6c:	61d3      	str	r3, [r2, #28]
 8001a6e:	4b36      	ldr	r3, [pc, #216]	; (8001b48 <MX_GPIO_Init+0x144>)
 8001a70:	69db      	ldr	r3, [r3, #28]
 8001a72:	f003 0302 	and.w	r3, r3, #2
 8001a76:	607b      	str	r3, [r7, #4]
 8001a78:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET);
 8001a7a:	2200      	movs	r2, #0
 8001a7c:	2180      	movs	r1, #128	; 0x80
 8001a7e:	4833      	ldr	r0, [pc, #204]	; (8001b4c <MX_GPIO_Init+0x148>)
 8001a80:	f002 f96c 	bl	8003d5c <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET);
 8001a84:	2201      	movs	r2, #1
 8001a86:	2101      	movs	r1, #1
 8001a88:	4831      	ldr	r0, [pc, #196]	; (8001b50 <MX_GPIO_Init+0x14c>)
 8001a8a:	f002 f967 	bl	8003d5c <HAL_GPIO_WritePin>

  /*Configure GPIO pins : PC13 PC14 PC15 */
  GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
 8001a8e:	f44f 4360 	mov.w	r3, #57344	; 0xe000
 8001a92:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001a94:	2303      	movs	r3, #3
 8001a96:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001a98:	2300      	movs	r3, #0
 8001a9a:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001a9c:	f107 0314 	add.w	r3, r7, #20
 8001aa0:	4619      	mov	r1, r3
 8001aa2:	482c      	ldr	r0, [pc, #176]	; (8001b54 <MX_GPIO_Init+0x150>)
 8001aa4:	f001 fefa 	bl	800389c <HAL_GPIO_Init>

  /*Configure GPIO pins : PA1 PA2 PA3 PA6
                           PA8 PA11 PA12 PA15 */
  GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6
 8001aa8:	f649 134e 	movw	r3, #39246	; 0x994e
 8001aac:	617b      	str	r3, [r7, #20]
                          |GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_15;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001aae:	2303      	movs	r3, #3
 8001ab0:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001ab2:	2300      	movs	r3, #0
 8001ab4:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001ab6:	f107 0314 	add.w	r3, r7, #20
 8001aba:	4619      	mov	r1, r3
 8001abc:	4823      	ldr	r0, [pc, #140]	; (8001b4c <MX_GPIO_Init+0x148>)
 8001abe:	f001 feed 	bl	800389c <HAL_GPIO_Init>

  /*Configure GPIO pin : PA7 */
  GPIO_InitStruct.Pin = GPIO_PIN_7;
 8001ac2:	2380      	movs	r3, #128	; 0x80
 8001ac4:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001ac6:	2301      	movs	r3, #1
 8001ac8:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001aca:	2300      	movs	r3, #0
 8001acc:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001ace:	2300      	movs	r3, #0
 8001ad0:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001ad2:	f107 0314 	add.w	r3, r7, #20
 8001ad6:	4619      	mov	r1, r3
 8001ad8:	481c      	ldr	r0, [pc, #112]	; (8001b4c <MX_GPIO_Init+0x148>)
 8001ada:	f001 fedf 	bl	800389c <HAL_GPIO_Init>

  /*Configure GPIO pin : PB0 */
  GPIO_InitStruct.Pin = GPIO_PIN_0;
 8001ade:	2301      	movs	r3, #1
 8001ae0:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001ae2:	2301      	movs	r3, #1
 8001ae4:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001ae6:	2300      	movs	r3, #0
 8001ae8:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001aea:	2300      	movs	r3, #0
 8001aec:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001aee:	f107 0314 	add.w	r3, r7, #20
 8001af2:	4619      	mov	r1, r3
 8001af4:	4816      	ldr	r0, [pc, #88]	; (8001b50 <MX_GPIO_Init+0x14c>)
 8001af6:	f001 fed1 	bl	800389c <HAL_GPIO_Init>

  /*Configure GPIO pins : PB2 PB12 PB13 PB3
                           PB5 PB8 PB9 */
  GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_3
 8001afa:	f243 332c 	movw	r3, #13100	; 0x332c
 8001afe:	617b      	str	r3, [r7, #20]
                          |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_9;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001b00:	2303      	movs	r3, #3
 8001b02:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001b04:	2300      	movs	r3, #0
 8001b06:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001b08:	f107 0314 	add.w	r3, r7, #20
 8001b0c:	4619      	mov	r1, r3
 8001b0e:	4810      	ldr	r0, [pc, #64]	; (8001b50 <MX_GPIO_Init+0x14c>)
 8001b10:	f001 fec4 	bl	800389c <HAL_GPIO_Init>

  /*Configure GPIO pins : PB14 PB15 */
  GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
 8001b14:	f44f 4340 	mov.w	r3, #49152	; 0xc000
 8001b18:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 8001b1a:	f44f 1304 	mov.w	r3, #2162688	; 0x210000
 8001b1e:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_PULLUP;
 8001b20:	2301      	movs	r3, #1
 8001b22:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001b24:	f107 0314 	add.w	r3, r7, #20
 8001b28:	4619      	mov	r1, r3
 8001b2a:	4809      	ldr	r0, [pc, #36]	; (8001b50 <MX_GPIO_Init+0x14c>)
 8001b2c:	f001 feb6 	bl	800389c <HAL_GPIO_Init>

  /* EXTI interrupt init*/
  HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
 8001b30:	2200      	movs	r2, #0
 8001b32:	2100      	movs	r1, #0
 8001b34:	2028      	movs	r0, #40	; 0x28
 8001b36:	f001 fbc2 	bl	80032be <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
 8001b3a:	2028      	movs	r0, #40	; 0x28
 8001b3c:	f001 fbdb 	bl	80032f6 <HAL_NVIC_EnableIRQ>

}
 8001b40:	bf00      	nop
 8001b42:	3728      	adds	r7, #40	; 0x28
 8001b44:	46bd      	mov	sp, r7
 8001b46:	bd80      	pop	{r7, pc}
 8001b48:	40023800 	.word	0x40023800
 8001b4c:	40020000 	.word	0x40020000
 8001b50:	40020400 	.word	0x40020400
 8001b54:	40020800 	.word	0x40020800

08001b58 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8001b58:	b480      	push	{r7}
 8001b5a:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8001b5c:	b672      	cpsid	i
}
 8001b5e:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8001b60:	e7fe      	b.n	8001b60 <Error_Handler+0x8>
	...

08001b64 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
                    /**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8001b64:	b480      	push	{r7}
 8001b66:	b085      	sub	sp, #20
 8001b68:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_COMP_CLK_ENABLE();
 8001b6a:	4b14      	ldr	r3, [pc, #80]	; (8001bbc <HAL_MspInit+0x58>)
 8001b6c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001b6e:	4a13      	ldr	r2, [pc, #76]	; (8001bbc <HAL_MspInit+0x58>)
 8001b70:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 8001b74:	6253      	str	r3, [r2, #36]	; 0x24
 8001b76:	4b11      	ldr	r3, [pc, #68]	; (8001bbc <HAL_MspInit+0x58>)
 8001b78:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001b7a:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
 8001b7e:	60fb      	str	r3, [r7, #12]
 8001b80:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001b82:	4b0e      	ldr	r3, [pc, #56]	; (8001bbc <HAL_MspInit+0x58>)
 8001b84:	6a1b      	ldr	r3, [r3, #32]
 8001b86:	4a0d      	ldr	r2, [pc, #52]	; (8001bbc <HAL_MspInit+0x58>)
 8001b88:	f043 0301 	orr.w	r3, r3, #1
 8001b8c:	6213      	str	r3, [r2, #32]
 8001b8e:	4b0b      	ldr	r3, [pc, #44]	; (8001bbc <HAL_MspInit+0x58>)
 8001b90:	6a1b      	ldr	r3, [r3, #32]
 8001b92:	f003 0301 	and.w	r3, r3, #1
 8001b96:	60bb      	str	r3, [r7, #8]
 8001b98:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_PWR_CLK_ENABLE();
 8001b9a:	4b08      	ldr	r3, [pc, #32]	; (8001bbc <HAL_MspInit+0x58>)
 8001b9c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001b9e:	4a07      	ldr	r2, [pc, #28]	; (8001bbc <HAL_MspInit+0x58>)
 8001ba0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8001ba4:	6253      	str	r3, [r2, #36]	; 0x24
 8001ba6:	4b05      	ldr	r3, [pc, #20]	; (8001bbc <HAL_MspInit+0x58>)
 8001ba8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001baa:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001bae:	607b      	str	r3, [r7, #4]
 8001bb0:	687b      	ldr	r3, [r7, #4]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8001bb2:	bf00      	nop
 8001bb4:	3714      	adds	r7, #20
 8001bb6:	46bd      	mov	sp, r7
 8001bb8:	bc80      	pop	{r7}
 8001bba:	4770      	bx	lr
 8001bbc:	40023800 	.word	0x40023800

08001bc0 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
 8001bc0:	b580      	push	{r7, lr}
 8001bc2:	b08a      	sub	sp, #40	; 0x28
 8001bc4:	af00      	add	r7, sp, #0
 8001bc6:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001bc8:	f107 0314 	add.w	r3, r7, #20
 8001bcc:	2200      	movs	r2, #0
 8001bce:	601a      	str	r2, [r3, #0]
 8001bd0:	605a      	str	r2, [r3, #4]
 8001bd2:	609a      	str	r2, [r3, #8]
 8001bd4:	60da      	str	r2, [r3, #12]
 8001bd6:	611a      	str	r2, [r3, #16]
  if(hadc->Instance==ADC1)
 8001bd8:	687b      	ldr	r3, [r7, #4]
 8001bda:	681b      	ldr	r3, [r3, #0]
 8001bdc:	4a29      	ldr	r2, [pc, #164]	; (8001c84 <HAL_ADC_MspInit+0xc4>)
 8001bde:	4293      	cmp	r3, r2
 8001be0:	d14b      	bne.n	8001c7a <HAL_ADC_MspInit+0xba>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 8001be2:	4b29      	ldr	r3, [pc, #164]	; (8001c88 <HAL_ADC_MspInit+0xc8>)
 8001be4:	6a1b      	ldr	r3, [r3, #32]
 8001be6:	4a28      	ldr	r2, [pc, #160]	; (8001c88 <HAL_ADC_MspInit+0xc8>)
 8001be8:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 8001bec:	6213      	str	r3, [r2, #32]
 8001bee:	4b26      	ldr	r3, [pc, #152]	; (8001c88 <HAL_ADC_MspInit+0xc8>)
 8001bf0:	6a1b      	ldr	r3, [r3, #32]
 8001bf2:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8001bf6:	613b      	str	r3, [r7, #16]
 8001bf8:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001bfa:	4b23      	ldr	r3, [pc, #140]	; (8001c88 <HAL_ADC_MspInit+0xc8>)
 8001bfc:	69db      	ldr	r3, [r3, #28]
 8001bfe:	4a22      	ldr	r2, [pc, #136]	; (8001c88 <HAL_ADC_MspInit+0xc8>)
 8001c00:	f043 0301 	orr.w	r3, r3, #1
 8001c04:	61d3      	str	r3, [r2, #28]
 8001c06:	4b20      	ldr	r3, [pc, #128]	; (8001c88 <HAL_ADC_MspInit+0xc8>)
 8001c08:	69db      	ldr	r3, [r3, #28]
 8001c0a:	f003 0301 	and.w	r3, r3, #1
 8001c0e:	60fb      	str	r3, [r7, #12]
 8001c10:	68fb      	ldr	r3, [r7, #12]
    /**ADC GPIO Configuration
    PA0-WKUP1     ------> ADC_IN0
    */
    GPIO_InitStruct.Pin = GPIO_PIN_0;
 8001c12:	2301      	movs	r3, #1
 8001c14:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001c16:	2303      	movs	r3, #3
 8001c18:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001c1a:	2300      	movs	r3, #0
 8001c1c:	61fb      	str	r3, [r7, #28]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001c1e:	f107 0314 	add.w	r3, r7, #20
 8001c22:	4619      	mov	r1, r3
 8001c24:	4819      	ldr	r0, [pc, #100]	; (8001c8c <HAL_ADC_MspInit+0xcc>)
 8001c26:	f001 fe39 	bl	800389c <HAL_GPIO_Init>

    /* ADC1 DMA Init */
    /* ADC Init */
    hdma_adc.Instance = DMA1_Channel1;
 8001c2a:	4b19      	ldr	r3, [pc, #100]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c2c:	4a19      	ldr	r2, [pc, #100]	; (8001c94 <HAL_ADC_MspInit+0xd4>)
 8001c2e:	601a      	str	r2, [r3, #0]
    hdma_adc.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8001c30:	4b17      	ldr	r3, [pc, #92]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c32:	2200      	movs	r2, #0
 8001c34:	605a      	str	r2, [r3, #4]
    hdma_adc.Init.PeriphInc = DMA_PINC_DISABLE;
 8001c36:	4b16      	ldr	r3, [pc, #88]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c38:	2200      	movs	r2, #0
 8001c3a:	609a      	str	r2, [r3, #8]
    hdma_adc.Init.MemInc = DMA_MINC_ENABLE;
 8001c3c:	4b14      	ldr	r3, [pc, #80]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c3e:	2280      	movs	r2, #128	; 0x80
 8001c40:	60da      	str	r2, [r3, #12]
    hdma_adc.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 8001c42:	4b13      	ldr	r3, [pc, #76]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c44:	f44f 7200 	mov.w	r2, #512	; 0x200
 8001c48:	611a      	str	r2, [r3, #16]
    hdma_adc.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 8001c4a:	4b11      	ldr	r3, [pc, #68]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c4c:	f44f 6200 	mov.w	r2, #2048	; 0x800
 8001c50:	615a      	str	r2, [r3, #20]
    hdma_adc.Init.Mode = DMA_NORMAL;
 8001c52:	4b0f      	ldr	r3, [pc, #60]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c54:	2200      	movs	r2, #0
 8001c56:	619a      	str	r2, [r3, #24]
    hdma_adc.Init.Priority = DMA_PRIORITY_LOW;
 8001c58:	4b0d      	ldr	r3, [pc, #52]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c5a:	2200      	movs	r2, #0
 8001c5c:	61da      	str	r2, [r3, #28]
    if (HAL_DMA_Init(&hdma_adc) != HAL_OK)
 8001c5e:	480c      	ldr	r0, [pc, #48]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c60:	f001 fc48 	bl	80034f4 <HAL_DMA_Init>
 8001c64:	4603      	mov	r3, r0
 8001c66:	2b00      	cmp	r3, #0
 8001c68:	d001      	beq.n	8001c6e <HAL_ADC_MspInit+0xae>
    {
      Error_Handler();
 8001c6a:	f7ff ff75 	bl	8001b58 <Error_Handler>
    }

    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc);
 8001c6e:	687b      	ldr	r3, [r7, #4]
 8001c70:	4a07      	ldr	r2, [pc, #28]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c72:	645a      	str	r2, [r3, #68]	; 0x44
 8001c74:	4a06      	ldr	r2, [pc, #24]	; (8001c90 <HAL_ADC_MspInit+0xd0>)
 8001c76:	687b      	ldr	r3, [r7, #4]
 8001c78:	6253      	str	r3, [r2, #36]	; 0x24
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }

}
 8001c7a:	bf00      	nop
 8001c7c:	3728      	adds	r7, #40	; 0x28
 8001c7e:	46bd      	mov	sp, r7
 8001c80:	bd80      	pop	{r7, pc}
 8001c82:	bf00      	nop
 8001c84:	40012400 	.word	0x40012400
 8001c88:	40023800 	.word	0x40023800
 8001c8c:	40020000 	.word	0x40020000
 8001c90:	20000640 	.word	0x20000640
 8001c94:	40026008 	.word	0x40026008

08001c98 <HAL_COMP_MspInit>:
* This function configures the hardware resources used in this example
* @param hcomp: COMP handle pointer
* @retval None
*/
void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
{
 8001c98:	b580      	push	{r7, lr}
 8001c9a:	b088      	sub	sp, #32
 8001c9c:	af00      	add	r7, sp, #0
 8001c9e:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001ca0:	f107 030c 	add.w	r3, r7, #12
 8001ca4:	2200      	movs	r2, #0
 8001ca6:	601a      	str	r2, [r3, #0]
 8001ca8:	605a      	str	r2, [r3, #4]
 8001caa:	609a      	str	r2, [r3, #8]
 8001cac:	60da      	str	r2, [r3, #12]
 8001cae:	611a      	str	r2, [r3, #16]
  if(hcomp->Instance==COMP2)
 8001cb0:	687b      	ldr	r3, [r7, #4]
 8001cb2:	681b      	ldr	r3, [r3, #0]
 8001cb4:	4a13      	ldr	r2, [pc, #76]	; (8001d04 <HAL_COMP_MspInit+0x6c>)
 8001cb6:	4293      	cmp	r3, r2
 8001cb8:	d11f      	bne.n	8001cfa <HAL_COMP_MspInit+0x62>
  {
  /* USER CODE BEGIN COMP2_MspInit 0 */

  /* USER CODE END COMP2_MspInit 0 */

    __HAL_RCC_GPIOB_CLK_ENABLE();
 8001cba:	4b13      	ldr	r3, [pc, #76]	; (8001d08 <HAL_COMP_MspInit+0x70>)
 8001cbc:	69db      	ldr	r3, [r3, #28]
 8001cbe:	4a12      	ldr	r2, [pc, #72]	; (8001d08 <HAL_COMP_MspInit+0x70>)
 8001cc0:	f043 0302 	orr.w	r3, r3, #2
 8001cc4:	61d3      	str	r3, [r2, #28]
 8001cc6:	4b10      	ldr	r3, [pc, #64]	; (8001d08 <HAL_COMP_MspInit+0x70>)
 8001cc8:	69db      	ldr	r3, [r3, #28]
 8001cca:	f003 0302 	and.w	r3, r3, #2
 8001cce:	60bb      	str	r3, [r7, #8]
 8001cd0:	68bb      	ldr	r3, [r7, #8]
    /**COMP2 GPIO Configuration
    PB4     ------> COMP2_INP
    */
    GPIO_InitStruct.Pin = GPIO_PIN_4;
 8001cd2:	2310      	movs	r3, #16
 8001cd4:	60fb      	str	r3, [r7, #12]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001cd6:	2303      	movs	r3, #3
 8001cd8:	613b      	str	r3, [r7, #16]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001cda:	2300      	movs	r3, #0
 8001cdc:	617b      	str	r3, [r7, #20]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001cde:	f107 030c 	add.w	r3, r7, #12
 8001ce2:	4619      	mov	r1, r3
 8001ce4:	4809      	ldr	r0, [pc, #36]	; (8001d0c <HAL_COMP_MspInit+0x74>)
 8001ce6:	f001 fdd9 	bl	800389c <HAL_GPIO_Init>

    /* COMP2 interrupt Init */
    HAL_NVIC_SetPriority(COMP_IRQn, 0, 0);
 8001cea:	2200      	movs	r2, #0
 8001cec:	2100      	movs	r1, #0
 8001cee:	2016      	movs	r0, #22
 8001cf0:	f001 fae5 	bl	80032be <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(COMP_IRQn);
 8001cf4:	2016      	movs	r0, #22
 8001cf6:	f001 fafe 	bl	80032f6 <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN COMP2_MspInit 1 */

  /* USER CODE END COMP2_MspInit 1 */
  }

}
 8001cfa:	bf00      	nop
 8001cfc:	3720      	adds	r7, #32
 8001cfe:	46bd      	mov	sp, r7
 8001d00:	bd80      	pop	{r7, pc}
 8001d02:	bf00      	nop
 8001d04:	40007c01 	.word	0x40007c01
 8001d08:	40023800 	.word	0x40023800
 8001d0c:	40020400 	.word	0x40020400

08001d10 <HAL_DAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
 8001d10:	b580      	push	{r7, lr}
 8001d12:	b08a      	sub	sp, #40	; 0x28
 8001d14:	af00      	add	r7, sp, #0
 8001d16:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001d18:	f107 0314 	add.w	r3, r7, #20
 8001d1c:	2200      	movs	r2, #0
 8001d1e:	601a      	str	r2, [r3, #0]
 8001d20:	605a      	str	r2, [r3, #4]
 8001d22:	609a      	str	r2, [r3, #8]
 8001d24:	60da      	str	r2, [r3, #12]
 8001d26:	611a      	str	r2, [r3, #16]
  if(hdac->Instance==DAC)
 8001d28:	687b      	ldr	r3, [r7, #4]
 8001d2a:	681b      	ldr	r3, [r3, #0]
 8001d2c:	4a15      	ldr	r2, [pc, #84]	; (8001d84 <HAL_DAC_MspInit+0x74>)
 8001d2e:	4293      	cmp	r3, r2
 8001d30:	d123      	bne.n	8001d7a <HAL_DAC_MspInit+0x6a>
  {
  /* USER CODE BEGIN DAC_MspInit 0 */

  /* USER CODE END DAC_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_DAC_CLK_ENABLE();
 8001d32:	4b15      	ldr	r3, [pc, #84]	; (8001d88 <HAL_DAC_MspInit+0x78>)
 8001d34:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001d36:	4a14      	ldr	r2, [pc, #80]	; (8001d88 <HAL_DAC_MspInit+0x78>)
 8001d38:	f043 5300 	orr.w	r3, r3, #536870912	; 0x20000000
 8001d3c:	6253      	str	r3, [r2, #36]	; 0x24
 8001d3e:	4b12      	ldr	r3, [pc, #72]	; (8001d88 <HAL_DAC_MspInit+0x78>)
 8001d40:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001d42:	f003 5300 	and.w	r3, r3, #536870912	; 0x20000000
 8001d46:	613b      	str	r3, [r7, #16]
 8001d48:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001d4a:	4b0f      	ldr	r3, [pc, #60]	; (8001d88 <HAL_DAC_MspInit+0x78>)
 8001d4c:	69db      	ldr	r3, [r3, #28]
 8001d4e:	4a0e      	ldr	r2, [pc, #56]	; (8001d88 <HAL_DAC_MspInit+0x78>)
 8001d50:	f043 0301 	orr.w	r3, r3, #1
 8001d54:	61d3      	str	r3, [r2, #28]
 8001d56:	4b0c      	ldr	r3, [pc, #48]	; (8001d88 <HAL_DAC_MspInit+0x78>)
 8001d58:	69db      	ldr	r3, [r3, #28]
 8001d5a:	f003 0301 	and.w	r3, r3, #1
 8001d5e:	60fb      	str	r3, [r7, #12]
 8001d60:	68fb      	ldr	r3, [r7, #12]
    /**DAC GPIO Configuration
    PA4     ------> DAC_OUT1
    PA5     ------> DAC_OUT2
    */
    GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
 8001d62:	2330      	movs	r3, #48	; 0x30
 8001d64:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001d66:	2303      	movs	r3, #3
 8001d68:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001d6a:	2300      	movs	r3, #0
 8001d6c:	61fb      	str	r3, [r7, #28]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001d6e:	f107 0314 	add.w	r3, r7, #20
 8001d72:	4619      	mov	r1, r3
 8001d74:	4805      	ldr	r0, [pc, #20]	; (8001d8c <HAL_DAC_MspInit+0x7c>)
 8001d76:	f001 fd91 	bl	800389c <HAL_GPIO_Init>
  /* USER CODE BEGIN DAC_MspInit 1 */

  /* USER CODE END DAC_MspInit 1 */
  }

}
 8001d7a:	bf00      	nop
 8001d7c:	3728      	adds	r7, #40	; 0x28
 8001d7e:	46bd      	mov	sp, r7
 8001d80:	bd80      	pop	{r7, pc}
 8001d82:	bf00      	nop
 8001d84:	40007400 	.word	0x40007400
 8001d88:	40023800 	.word	0x40023800
 8001d8c:	40020000 	.word	0x40020000

08001d90 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
 8001d90:	b580      	push	{r7, lr}
 8001d92:	b08c      	sub	sp, #48	; 0x30
 8001d94:	af00      	add	r7, sp, #0
 8001d96:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001d98:	f107 031c 	add.w	r3, r7, #28
 8001d9c:	2200      	movs	r2, #0
 8001d9e:	601a      	str	r2, [r3, #0]
 8001da0:	605a      	str	r2, [r3, #4]
 8001da2:	609a      	str	r2, [r3, #8]
 8001da4:	60da      	str	r2, [r3, #12]
 8001da6:	611a      	str	r2, [r3, #16]
  if(hi2c->Instance==I2C1)
 8001da8:	687b      	ldr	r3, [r7, #4]
 8001daa:	681b      	ldr	r3, [r3, #0]
 8001dac:	4a2e      	ldr	r2, [pc, #184]	; (8001e68 <HAL_I2C_MspInit+0xd8>)
 8001dae:	4293      	cmp	r3, r2
 8001db0:	d128      	bne.n	8001e04 <HAL_I2C_MspInit+0x74>
  {
  /* USER CODE BEGIN I2C1_MspInit 0 */

  /* USER CODE END I2C1_MspInit 0 */

    __HAL_RCC_GPIOB_CLK_ENABLE();
 8001db2:	4b2e      	ldr	r3, [pc, #184]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001db4:	69db      	ldr	r3, [r3, #28]
 8001db6:	4a2d      	ldr	r2, [pc, #180]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001db8:	f043 0302 	orr.w	r3, r3, #2
 8001dbc:	61d3      	str	r3, [r2, #28]
 8001dbe:	4b2b      	ldr	r3, [pc, #172]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001dc0:	69db      	ldr	r3, [r3, #28]
 8001dc2:	f003 0302 	and.w	r3, r3, #2
 8001dc6:	61bb      	str	r3, [r7, #24]
 8001dc8:	69bb      	ldr	r3, [r7, #24]
    /**I2C1 GPIO Configuration
    PB6     ------> I2C1_SCL
    PB7     ------> I2C1_SDA
    */
    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
 8001dca:	23c0      	movs	r3, #192	; 0xc0
 8001dcc:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8001dce:	2312      	movs	r3, #18
 8001dd0:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001dd2:	2300      	movs	r3, #0
 8001dd4:	627b      	str	r3, [r7, #36]	; 0x24
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8001dd6:	2303      	movs	r3, #3
 8001dd8:	62bb      	str	r3, [r7, #40]	; 0x28
    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
 8001dda:	2304      	movs	r3, #4
 8001ddc:	62fb      	str	r3, [r7, #44]	; 0x2c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001dde:	f107 031c 	add.w	r3, r7, #28
 8001de2:	4619      	mov	r1, r3
 8001de4:	4822      	ldr	r0, [pc, #136]	; (8001e70 <HAL_I2C_MspInit+0xe0>)
 8001de6:	f001 fd59 	bl	800389c <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_I2C1_CLK_ENABLE();
 8001dea:	4b20      	ldr	r3, [pc, #128]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001dec:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001dee:	4a1f      	ldr	r2, [pc, #124]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001df0:	f443 1300 	orr.w	r3, r3, #2097152	; 0x200000
 8001df4:	6253      	str	r3, [r2, #36]	; 0x24
 8001df6:	4b1d      	ldr	r3, [pc, #116]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001df8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001dfa:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8001dfe:	617b      	str	r3, [r7, #20]
 8001e00:	697b      	ldr	r3, [r7, #20]
  /* USER CODE BEGIN I2C2_MspInit 1 */

  /* USER CODE END I2C2_MspInit 1 */
  }

}
 8001e02:	e02d      	b.n	8001e60 <HAL_I2C_MspInit+0xd0>
  else if(hi2c->Instance==I2C2)
 8001e04:	687b      	ldr	r3, [r7, #4]
 8001e06:	681b      	ldr	r3, [r3, #0]
 8001e08:	4a1a      	ldr	r2, [pc, #104]	; (8001e74 <HAL_I2C_MspInit+0xe4>)
 8001e0a:	4293      	cmp	r3, r2
 8001e0c:	d128      	bne.n	8001e60 <HAL_I2C_MspInit+0xd0>
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8001e0e:	4b17      	ldr	r3, [pc, #92]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001e10:	69db      	ldr	r3, [r3, #28]
 8001e12:	4a16      	ldr	r2, [pc, #88]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001e14:	f043 0302 	orr.w	r3, r3, #2
 8001e18:	61d3      	str	r3, [r2, #28]
 8001e1a:	4b14      	ldr	r3, [pc, #80]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001e1c:	69db      	ldr	r3, [r3, #28]
 8001e1e:	f003 0302 	and.w	r3, r3, #2
 8001e22:	613b      	str	r3, [r7, #16]
 8001e24:	693b      	ldr	r3, [r7, #16]
    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
 8001e26:	f44f 6340 	mov.w	r3, #3072	; 0xc00
 8001e2a:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8001e2c:	2312      	movs	r3, #18
 8001e2e:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001e30:	2300      	movs	r3, #0
 8001e32:	627b      	str	r3, [r7, #36]	; 0x24
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8001e34:	2303      	movs	r3, #3
 8001e36:	62bb      	str	r3, [r7, #40]	; 0x28
    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
 8001e38:	2304      	movs	r3, #4
 8001e3a:	62fb      	str	r3, [r7, #44]	; 0x2c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001e3c:	f107 031c 	add.w	r3, r7, #28
 8001e40:	4619      	mov	r1, r3
 8001e42:	480b      	ldr	r0, [pc, #44]	; (8001e70 <HAL_I2C_MspInit+0xe0>)
 8001e44:	f001 fd2a 	bl	800389c <HAL_GPIO_Init>
    __HAL_RCC_I2C2_CLK_ENABLE();
 8001e48:	4b08      	ldr	r3, [pc, #32]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001e4a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001e4c:	4a07      	ldr	r2, [pc, #28]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001e4e:	f443 0380 	orr.w	r3, r3, #4194304	; 0x400000
 8001e52:	6253      	str	r3, [r2, #36]	; 0x24
 8001e54:	4b05      	ldr	r3, [pc, #20]	; (8001e6c <HAL_I2C_MspInit+0xdc>)
 8001e56:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001e58:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8001e5c:	60fb      	str	r3, [r7, #12]
 8001e5e:	68fb      	ldr	r3, [r7, #12]
}
 8001e60:	bf00      	nop
 8001e62:	3730      	adds	r7, #48	; 0x30
 8001e64:	46bd      	mov	sp, r7
 8001e66:	bd80      	pop	{r7, pc}
 8001e68:	40005400 	.word	0x40005400
 8001e6c:	40023800 	.word	0x40023800
 8001e70:	40020400 	.word	0x40020400
 8001e74:	40005800 	.word	0x40005800

08001e78 <HAL_I2C_MspDeInit>:
* This function freeze the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
{
 8001e78:	b580      	push	{r7, lr}
 8001e7a:	b082      	sub	sp, #8
 8001e7c:	af00      	add	r7, sp, #0
 8001e7e:	6078      	str	r0, [r7, #4]
  if(hi2c->Instance==I2C1)
 8001e80:	687b      	ldr	r3, [r7, #4]
 8001e82:	681b      	ldr	r3, [r3, #0]
 8001e84:	4a15      	ldr	r2, [pc, #84]	; (8001edc <HAL_I2C_MspDeInit+0x64>)
 8001e86:	4293      	cmp	r3, r2
 8001e88:	d10e      	bne.n	8001ea8 <HAL_I2C_MspDeInit+0x30>
  {
  /* USER CODE BEGIN I2C1_MspDeInit 0 */

  /* USER CODE END I2C1_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_I2C1_CLK_DISABLE();
 8001e8a:	4b15      	ldr	r3, [pc, #84]	; (8001ee0 <HAL_I2C_MspDeInit+0x68>)
 8001e8c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001e8e:	4a14      	ldr	r2, [pc, #80]	; (8001ee0 <HAL_I2C_MspDeInit+0x68>)
 8001e90:	f423 1300 	bic.w	r3, r3, #2097152	; 0x200000
 8001e94:	6253      	str	r3, [r2, #36]	; 0x24

    /**I2C1 GPIO Configuration
    PB6     ------> I2C1_SCL
    PB7     ------> I2C1_SDA
    */
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
 8001e96:	2140      	movs	r1, #64	; 0x40
 8001e98:	4812      	ldr	r0, [pc, #72]	; (8001ee4 <HAL_I2C_MspDeInit+0x6c>)
 8001e9a:	f001 fe7f 	bl	8003b9c <HAL_GPIO_DeInit>

    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
 8001e9e:	2180      	movs	r1, #128	; 0x80
 8001ea0:	4810      	ldr	r0, [pc, #64]	; (8001ee4 <HAL_I2C_MspDeInit+0x6c>)
 8001ea2:	f001 fe7b 	bl	8003b9c <HAL_GPIO_DeInit>
  /* USER CODE BEGIN I2C2_MspDeInit 1 */

  /* USER CODE END I2C2_MspDeInit 1 */
  }

}
 8001ea6:	e014      	b.n	8001ed2 <HAL_I2C_MspDeInit+0x5a>
  else if(hi2c->Instance==I2C2)
 8001ea8:	687b      	ldr	r3, [r7, #4]
 8001eaa:	681b      	ldr	r3, [r3, #0]
 8001eac:	4a0e      	ldr	r2, [pc, #56]	; (8001ee8 <HAL_I2C_MspDeInit+0x70>)
 8001eae:	4293      	cmp	r3, r2
 8001eb0:	d10f      	bne.n	8001ed2 <HAL_I2C_MspDeInit+0x5a>
    __HAL_RCC_I2C2_CLK_DISABLE();
 8001eb2:	4b0b      	ldr	r3, [pc, #44]	; (8001ee0 <HAL_I2C_MspDeInit+0x68>)
 8001eb4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001eb6:	4a0a      	ldr	r2, [pc, #40]	; (8001ee0 <HAL_I2C_MspDeInit+0x68>)
 8001eb8:	f423 0380 	bic.w	r3, r3, #4194304	; 0x400000
 8001ebc:	6253      	str	r3, [r2, #36]	; 0x24
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);
 8001ebe:	f44f 6180 	mov.w	r1, #1024	; 0x400
 8001ec2:	4808      	ldr	r0, [pc, #32]	; (8001ee4 <HAL_I2C_MspDeInit+0x6c>)
 8001ec4:	f001 fe6a 	bl	8003b9c <HAL_GPIO_DeInit>
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11);
 8001ec8:	f44f 6100 	mov.w	r1, #2048	; 0x800
 8001ecc:	4805      	ldr	r0, [pc, #20]	; (8001ee4 <HAL_I2C_MspDeInit+0x6c>)
 8001ece:	f001 fe65 	bl	8003b9c <HAL_GPIO_DeInit>
}
 8001ed2:	bf00      	nop
 8001ed4:	3708      	adds	r7, #8
 8001ed6:	46bd      	mov	sp, r7
 8001ed8:	bd80      	pop	{r7, pc}
 8001eda:	bf00      	nop
 8001edc:	40005400 	.word	0x40005400
 8001ee0:	40023800 	.word	0x40023800
 8001ee4:	40020400 	.word	0x40020400
 8001ee8:	40005800 	.word	0x40005800

08001eec <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
 8001eec:	b580      	push	{r7, lr}
 8001eee:	b086      	sub	sp, #24
 8001ef0:	af00      	add	r7, sp, #0
 8001ef2:	6078      	str	r0, [r7, #4]
  if(htim_base->Instance==TIM2)
 8001ef4:	687b      	ldr	r3, [r7, #4]
 8001ef6:	681b      	ldr	r3, [r3, #0]
 8001ef8:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8001efc:	d10c      	bne.n	8001f18 <HAL_TIM_Base_MspInit+0x2c>
  {
  /* USER CODE BEGIN TIM2_MspInit 0 */

  /* USER CODE END TIM2_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM2_CLK_ENABLE();
 8001efe:	4b2b      	ldr	r3, [pc, #172]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f00:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f02:	4a2a      	ldr	r2, [pc, #168]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f04:	f043 0301 	orr.w	r3, r3, #1
 8001f08:	6253      	str	r3, [r2, #36]	; 0x24
 8001f0a:	4b28      	ldr	r3, [pc, #160]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f0c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f0e:	f003 0301 	and.w	r3, r3, #1
 8001f12:	617b      	str	r3, [r7, #20]
 8001f14:	697b      	ldr	r3, [r7, #20]
  /* USER CODE BEGIN TIM6_MspInit 1 */

  /* USER CODE END TIM6_MspInit 1 */
  }

}
 8001f16:	e044      	b.n	8001fa2 <HAL_TIM_Base_MspInit+0xb6>
  else if(htim_base->Instance==TIM3)
 8001f18:	687b      	ldr	r3, [r7, #4]
 8001f1a:	681b      	ldr	r3, [r3, #0]
 8001f1c:	4a24      	ldr	r2, [pc, #144]	; (8001fb0 <HAL_TIM_Base_MspInit+0xc4>)
 8001f1e:	4293      	cmp	r3, r2
 8001f20:	d10c      	bne.n	8001f3c <HAL_TIM_Base_MspInit+0x50>
    __HAL_RCC_TIM3_CLK_ENABLE();
 8001f22:	4b22      	ldr	r3, [pc, #136]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f24:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f26:	4a21      	ldr	r2, [pc, #132]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f28:	f043 0302 	orr.w	r3, r3, #2
 8001f2c:	6253      	str	r3, [r2, #36]	; 0x24
 8001f2e:	4b1f      	ldr	r3, [pc, #124]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f30:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f32:	f003 0302 	and.w	r3, r3, #2
 8001f36:	613b      	str	r3, [r7, #16]
 8001f38:	693b      	ldr	r3, [r7, #16]
}
 8001f3a:	e032      	b.n	8001fa2 <HAL_TIM_Base_MspInit+0xb6>
  else if(htim_base->Instance==TIM4)
 8001f3c:	687b      	ldr	r3, [r7, #4]
 8001f3e:	681b      	ldr	r3, [r3, #0]
 8001f40:	4a1c      	ldr	r2, [pc, #112]	; (8001fb4 <HAL_TIM_Base_MspInit+0xc8>)
 8001f42:	4293      	cmp	r3, r2
 8001f44:	d114      	bne.n	8001f70 <HAL_TIM_Base_MspInit+0x84>
    __HAL_RCC_TIM4_CLK_ENABLE();
 8001f46:	4b19      	ldr	r3, [pc, #100]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f48:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f4a:	4a18      	ldr	r2, [pc, #96]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f4c:	f043 0304 	orr.w	r3, r3, #4
 8001f50:	6253      	str	r3, [r2, #36]	; 0x24
 8001f52:	4b16      	ldr	r3, [pc, #88]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f54:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f56:	f003 0304 	and.w	r3, r3, #4
 8001f5a:	60fb      	str	r3, [r7, #12]
 8001f5c:	68fb      	ldr	r3, [r7, #12]
    HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0);
 8001f5e:	2200      	movs	r2, #0
 8001f60:	2100      	movs	r1, #0
 8001f62:	201e      	movs	r0, #30
 8001f64:	f001 f9ab 	bl	80032be <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM4_IRQn);
 8001f68:	201e      	movs	r0, #30
 8001f6a:	f001 f9c4 	bl	80032f6 <HAL_NVIC_EnableIRQ>
}
 8001f6e:	e018      	b.n	8001fa2 <HAL_TIM_Base_MspInit+0xb6>
  else if(htim_base->Instance==TIM6)
 8001f70:	687b      	ldr	r3, [r7, #4]
 8001f72:	681b      	ldr	r3, [r3, #0]
 8001f74:	4a10      	ldr	r2, [pc, #64]	; (8001fb8 <HAL_TIM_Base_MspInit+0xcc>)
 8001f76:	4293      	cmp	r3, r2
 8001f78:	d113      	bne.n	8001fa2 <HAL_TIM_Base_MspInit+0xb6>
    __HAL_RCC_TIM6_CLK_ENABLE();
 8001f7a:	4b0c      	ldr	r3, [pc, #48]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f7c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f7e:	4a0b      	ldr	r2, [pc, #44]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f80:	f043 0310 	orr.w	r3, r3, #16
 8001f84:	6253      	str	r3, [r2, #36]	; 0x24
 8001f86:	4b09      	ldr	r3, [pc, #36]	; (8001fac <HAL_TIM_Base_MspInit+0xc0>)
 8001f88:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001f8a:	f003 0310 	and.w	r3, r3, #16
 8001f8e:	60bb      	str	r3, [r7, #8]
 8001f90:	68bb      	ldr	r3, [r7, #8]
    HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
 8001f92:	2200      	movs	r2, #0
 8001f94:	2100      	movs	r1, #0
 8001f96:	202b      	movs	r0, #43	; 0x2b
 8001f98:	f001 f991 	bl	80032be <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(TIM6_IRQn);
 8001f9c:	202b      	movs	r0, #43	; 0x2b
 8001f9e:	f001 f9aa 	bl	80032f6 <HAL_NVIC_EnableIRQ>
}
 8001fa2:	bf00      	nop
 8001fa4:	3718      	adds	r7, #24
 8001fa6:	46bd      	mov	sp, r7
 8001fa8:	bd80      	pop	{r7, pc}
 8001faa:	bf00      	nop
 8001fac:	40023800 	.word	0x40023800
 8001fb0:	40000400 	.word	0x40000400
 8001fb4:	40000800 	.word	0x40000800
 8001fb8:	40001000 	.word	0x40001000

08001fbc <HAL_TIM_MspPostInit>:

void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
 8001fbc:	b580      	push	{r7, lr}
 8001fbe:	b088      	sub	sp, #32
 8001fc0:	af00      	add	r7, sp, #0
 8001fc2:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001fc4:	f107 030c 	add.w	r3, r7, #12
 8001fc8:	2200      	movs	r2, #0
 8001fca:	601a      	str	r2, [r3, #0]
 8001fcc:	605a      	str	r2, [r3, #4]
 8001fce:	609a      	str	r2, [r3, #8]
 8001fd0:	60da      	str	r2, [r3, #12]
 8001fd2:	611a      	str	r2, [r3, #16]
  if(htim->Instance==TIM3)
 8001fd4:	687b      	ldr	r3, [r7, #4]
 8001fd6:	681b      	ldr	r3, [r3, #0]
 8001fd8:	4a11      	ldr	r2, [pc, #68]	; (8002020 <HAL_TIM_MspPostInit+0x64>)
 8001fda:	4293      	cmp	r3, r2
 8001fdc:	d11b      	bne.n	8002016 <HAL_TIM_MspPostInit+0x5a>
  {
  /* USER CODE BEGIN TIM3_MspPostInit 0 */

  /* USER CODE END TIM3_MspPostInit 0 */

    __HAL_RCC_GPIOB_CLK_ENABLE();
 8001fde:	4b11      	ldr	r3, [pc, #68]	; (8002024 <HAL_TIM_MspPostInit+0x68>)
 8001fe0:	69db      	ldr	r3, [r3, #28]
 8001fe2:	4a10      	ldr	r2, [pc, #64]	; (8002024 <HAL_TIM_MspPostInit+0x68>)
 8001fe4:	f043 0302 	orr.w	r3, r3, #2
 8001fe8:	61d3      	str	r3, [r2, #28]
 8001fea:	4b0e      	ldr	r3, [pc, #56]	; (8002024 <HAL_TIM_MspPostInit+0x68>)
 8001fec:	69db      	ldr	r3, [r3, #28]
 8001fee:	f003 0302 	and.w	r3, r3, #2
 8001ff2:	60bb      	str	r3, [r7, #8]
 8001ff4:	68bb      	ldr	r3, [r7, #8]
    /**TIM3 GPIO Configuration
    PB1     ------> TIM3_CH4
    */
    GPIO_InitStruct.Pin = GPIO_PIN_1;
 8001ff6:	2302      	movs	r3, #2
 8001ff8:	60fb      	str	r3, [r7, #12]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001ffa:	2302      	movs	r3, #2
 8001ffc:	613b      	str	r3, [r7, #16]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001ffe:	2300      	movs	r3, #0
 8002000:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8002002:	2300      	movs	r3, #0
 8002004:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
 8002006:	2302      	movs	r3, #2
 8002008:	61fb      	str	r3, [r7, #28]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 800200a:	f107 030c 	add.w	r3, r7, #12
 800200e:	4619      	mov	r1, r3
 8002010:	4805      	ldr	r0, [pc, #20]	; (8002028 <HAL_TIM_MspPostInit+0x6c>)
 8002012:	f001 fc43 	bl	800389c <HAL_GPIO_Init>
  /* USER CODE BEGIN TIM3_MspPostInit 1 */

  /* USER CODE END TIM3_MspPostInit 1 */
  }

}
 8002016:	bf00      	nop
 8002018:	3720      	adds	r7, #32
 800201a:	46bd      	mov	sp, r7
 800201c:	bd80      	pop	{r7, pc}
 800201e:	bf00      	nop
 8002020:	40000400 	.word	0x40000400
 8002024:	40023800 	.word	0x40023800
 8002028:	40020400 	.word	0x40020400

0800202c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 800202c:	b580      	push	{r7, lr}
 800202e:	b08a      	sub	sp, #40	; 0x28
 8002030:	af00      	add	r7, sp, #0
 8002032:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8002034:	f107 0314 	add.w	r3, r7, #20
 8002038:	2200      	movs	r2, #0
 800203a:	601a      	str	r2, [r3, #0]
 800203c:	605a      	str	r2, [r3, #4]
 800203e:	609a      	str	r2, [r3, #8]
 8002040:	60da      	str	r2, [r3, #12]
 8002042:	611a      	str	r2, [r3, #16]
  if(huart->Instance==USART1)
 8002044:	687b      	ldr	r3, [r7, #4]
 8002046:	681b      	ldr	r3, [r3, #0]
 8002048:	4a17      	ldr	r2, [pc, #92]	; (80020a8 <HAL_UART_MspInit+0x7c>)
 800204a:	4293      	cmp	r3, r2
 800204c:	d128      	bne.n	80020a0 <HAL_UART_MspInit+0x74>
  {
  /* USER CODE BEGIN USART1_MspInit 0 */

  /* USER CODE END USART1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 800204e:	4b17      	ldr	r3, [pc, #92]	; (80020ac <HAL_UART_MspInit+0x80>)
 8002050:	6a1b      	ldr	r3, [r3, #32]
 8002052:	4a16      	ldr	r2, [pc, #88]	; (80020ac <HAL_UART_MspInit+0x80>)
 8002054:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8002058:	6213      	str	r3, [r2, #32]
 800205a:	4b14      	ldr	r3, [pc, #80]	; (80020ac <HAL_UART_MspInit+0x80>)
 800205c:	6a1b      	ldr	r3, [r3, #32]
 800205e:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8002062:	613b      	str	r3, [r7, #16]
 8002064:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8002066:	4b11      	ldr	r3, [pc, #68]	; (80020ac <HAL_UART_MspInit+0x80>)
 8002068:	69db      	ldr	r3, [r3, #28]
 800206a:	4a10      	ldr	r2, [pc, #64]	; (80020ac <HAL_UART_MspInit+0x80>)
 800206c:	f043 0301 	orr.w	r3, r3, #1
 8002070:	61d3      	str	r3, [r2, #28]
 8002072:	4b0e      	ldr	r3, [pc, #56]	; (80020ac <HAL_UART_MspInit+0x80>)
 8002074:	69db      	ldr	r3, [r3, #28]
 8002076:	f003 0301 	and.w	r3, r3, #1
 800207a:	60fb      	str	r3, [r7, #12]
 800207c:	68fb      	ldr	r3, [r7, #12]
    /**USART1 GPIO Configuration
    PA9     ------> USART1_TX
    PA10     ------> USART1_RX
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
 800207e:	f44f 63c0 	mov.w	r3, #1536	; 0x600
 8002082:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8002084:	2302      	movs	r3, #2
 8002086:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8002088:	2300      	movs	r3, #0
 800208a:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 800208c:	2303      	movs	r3, #3
 800208e:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
 8002090:	2307      	movs	r3, #7
 8002092:	627b      	str	r3, [r7, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8002094:	f107 0314 	add.w	r3, r7, #20
 8002098:	4619      	mov	r1, r3
 800209a:	4805      	ldr	r0, [pc, #20]	; (80020b0 <HAL_UART_MspInit+0x84>)
 800209c:	f001 fbfe 	bl	800389c <HAL_GPIO_Init>
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 80020a0:	bf00      	nop
 80020a2:	3728      	adds	r7, #40	; 0x28
 80020a4:	46bd      	mov	sp, r7
 80020a6:	bd80      	pop	{r7, pc}
 80020a8:	40013800 	.word	0x40013800
 80020ac:	40023800 	.word	0x40023800
 80020b0:	40020000 	.word	0x40020000

080020b4 <HAL_UART_MspDeInit>:
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
 80020b4:	b580      	push	{r7, lr}
 80020b6:	b082      	sub	sp, #8
 80020b8:	af00      	add	r7, sp, #0
 80020ba:	6078      	str	r0, [r7, #4]
  if(huart->Instance==USART1)
 80020bc:	687b      	ldr	r3, [r7, #4]
 80020be:	681b      	ldr	r3, [r3, #0]
 80020c0:	4a08      	ldr	r2, [pc, #32]	; (80020e4 <HAL_UART_MspDeInit+0x30>)
 80020c2:	4293      	cmp	r3, r2
 80020c4:	d10a      	bne.n	80020dc <HAL_UART_MspDeInit+0x28>
  {
  /* USER CODE BEGIN USART1_MspDeInit 0 */

  /* USER CODE END USART1_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_USART1_CLK_DISABLE();
 80020c6:	4b08      	ldr	r3, [pc, #32]	; (80020e8 <HAL_UART_MspDeInit+0x34>)
 80020c8:	6a1b      	ldr	r3, [r3, #32]
 80020ca:	4a07      	ldr	r2, [pc, #28]	; (80020e8 <HAL_UART_MspDeInit+0x34>)
 80020cc:	f423 4380 	bic.w	r3, r3, #16384	; 0x4000
 80020d0:	6213      	str	r3, [r2, #32]

    /**USART1 GPIO Configuration
    PA9     ------> USART1_TX
    PA10     ------> USART1_RX
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
 80020d2:	f44f 61c0 	mov.w	r1, #1536	; 0x600
 80020d6:	4805      	ldr	r0, [pc, #20]	; (80020ec <HAL_UART_MspDeInit+0x38>)
 80020d8:	f001 fd60 	bl	8003b9c <HAL_GPIO_DeInit>
  /* USER CODE BEGIN USART1_MspDeInit 1 */

  /* USER CODE END USART1_MspDeInit 1 */
  }

}
 80020dc:	bf00      	nop
 80020de:	3708      	adds	r7, #8
 80020e0:	46bd      	mov	sp, r7
 80020e2:	bd80      	pop	{r7, pc}
 80020e4:	40013800 	.word	0x40013800
 80020e8:	40023800 	.word	0x40023800
 80020ec:	40020000 	.word	0x40020000

080020f0 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80020f0:	b480      	push	{r7}
 80020f2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 80020f4:	e7fe      	b.n	80020f4 <NMI_Handler+0x4>

080020f6 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80020f6:	b480      	push	{r7}
 80020f8:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 80020fa:	e7fe      	b.n	80020fa <HardFault_Handler+0x4>

080020fc <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80020fc:	b480      	push	{r7}
 80020fe:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8002100:	e7fe      	b.n	8002100 <MemManage_Handler+0x4>

08002102 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8002102:	b480      	push	{r7}
 8002104:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8002106:	e7fe      	b.n	8002106 <BusFault_Handler+0x4>

08002108 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8002108:	b480      	push	{r7}
 800210a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 800210c:	e7fe      	b.n	800210c <UsageFault_Handler+0x4>

0800210e <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 800210e:	b480      	push	{r7}
 8002110:	af00      	add	r7, sp, #0

  /* USER CODE END SVC_IRQn 0 */
  /* USER CODE BEGIN SVC_IRQn 1 */

  /* USER CODE END SVC_IRQn 1 */
}
 8002112:	bf00      	nop
 8002114:	46bd      	mov	sp, r7
 8002116:	bc80      	pop	{r7}
 8002118:	4770      	bx	lr

0800211a <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 800211a:	b480      	push	{r7}
 800211c:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 800211e:	bf00      	nop
 8002120:	46bd      	mov	sp, r7
 8002122:	bc80      	pop	{r7}
 8002124:	4770      	bx	lr

08002126 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8002126:	b480      	push	{r7}
 8002128:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 800212a:	bf00      	nop
 800212c:	46bd      	mov	sp, r7
 800212e:	bc80      	pop	{r7}
 8002130:	4770      	bx	lr

08002132 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8002132:	b580      	push	{r7, lr}
 8002134:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8002136:	f000 f975 	bl	8002424 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 800213a:	bf00      	nop
 800213c:	bd80      	pop	{r7, pc}
	...

08002140 <DMA1_Channel1_IRQHandler>:

/**
  * @brief This function handles DMA1 channel1 global interrupt.
  */
void DMA1_Channel1_IRQHandler(void)
{
 8002140:	b580      	push	{r7, lr}
 8002142:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */

  /* USER CODE END DMA1_Channel1_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc);
 8002144:	4802      	ldr	r0, [pc, #8]	; (8002150 <DMA1_Channel1_IRQHandler+0x10>)
 8002146:	f001 faca 	bl	80036de <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */

  /* USER CODE END DMA1_Channel1_IRQn 1 */
}
 800214a:	bf00      	nop
 800214c:	bd80      	pop	{r7, pc}
 800214e:	bf00      	nop
 8002150:	20000640 	.word	0x20000640

08002154 <COMP_IRQHandler>:

/**
  * @brief This function handles COMP1 and COMP2 wake-up interrupts through EXTI lines 21 and 22.
  */
void COMP_IRQHandler(void)
{
 8002154:	b580      	push	{r7, lr}
 8002156:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN COMP_IRQn 0 */

  /* USER CODE END COMP_IRQn 0 */
  HAL_COMP_IRQHandler(&hcomp2);
 8002158:	4802      	ldr	r0, [pc, #8]	; (8002164 <COMP_IRQHandler+0x10>)
 800215a:	f000 ffb5 	bl	80030c8 <HAL_COMP_IRQHandler>
  /* USER CODE BEGIN COMP_IRQn 1 */

  /* USER CODE END COMP_IRQn 1 */
}
 800215e:	bf00      	nop
 8002160:	bd80      	pop	{r7, pc}
 8002162:	bf00      	nop
 8002164:	200005d8 	.word	0x200005d8

08002168 <TIM4_IRQHandler>:

/**
  * @brief This function handles TIM4 global interrupt.
  */
void TIM4_IRQHandler(void)
{
 8002168:	b580      	push	{r7, lr}
 800216a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM4_IRQn 0 */

  /* USER CODE END TIM4_IRQn 0 */
  HAL_TIM_IRQHandler(&htim4);
 800216c:	4802      	ldr	r0, [pc, #8]	; (8002178 <TIM4_IRQHandler+0x10>)
 800216e:	f003 fac8 	bl	8005702 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM4_IRQn 1 */

  /* USER CODE END TIM4_IRQn 1 */
}
 8002172:	bf00      	nop
 8002174:	bd80      	pop	{r7, pc}
 8002176:	bf00      	nop
 8002178:	20000418 	.word	0x20000418

0800217c <EXTI15_10_IRQHandler>:

/**
  * @brief This function handles EXTI line[15:10] interrupts.
  */
void EXTI15_10_IRQHandler(void)
{
 800217c:	b580      	push	{r7, lr}
 800217e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN EXTI15_10_IRQn 0 */

  /* USER CODE END EXTI15_10_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
 8002180:	f44f 4080 	mov.w	r0, #16384	; 0x4000
 8002184:	f001 fe02 	bl	8003d8c <HAL_GPIO_EXTI_IRQHandler>
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
 8002188:	f44f 4000 	mov.w	r0, #32768	; 0x8000
 800218c:	f001 fdfe 	bl	8003d8c <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI15_10_IRQn 1 */

  /* USER CODE END EXTI15_10_IRQn 1 */
}
 8002190:	bf00      	nop
 8002192:	bd80      	pop	{r7, pc}

08002194 <TIM6_IRQHandler>:

/**
  * @brief This function handles TIM6 global interrupt.
  */
void TIM6_IRQHandler(void)
{
 8002194:	b580      	push	{r7, lr}
 8002196:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM6_IRQn 0 */

  /* USER CODE END TIM6_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 8002198:	4802      	ldr	r0, [pc, #8]	; (80021a4 <TIM6_IRQHandler+0x10>)
 800219a:	f003 fab2 	bl	8005702 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM6_IRQn 1 */

  /* USER CODE END TIM6_IRQn 1 */
}
 800219e:	bf00      	nop
 80021a0:	bd80      	pop	{r7, pc}
 80021a2:	bf00      	nop
 80021a4:	20000598 	.word	0x20000598

080021a8 <_getpid>:
void initialise_monitor_handles()
{
}

int _getpid(void)
{
 80021a8:	b480      	push	{r7}
 80021aa:	af00      	add	r7, sp, #0
	return 1;
 80021ac:	2301      	movs	r3, #1
}
 80021ae:	4618      	mov	r0, r3
 80021b0:	46bd      	mov	sp, r7
 80021b2:	bc80      	pop	{r7}
 80021b4:	4770      	bx	lr

080021b6 <_kill>:

int _kill(int pid, int sig)
{
 80021b6:	b580      	push	{r7, lr}
 80021b8:	b082      	sub	sp, #8
 80021ba:	af00      	add	r7, sp, #0
 80021bc:	6078      	str	r0, [r7, #4]
 80021be:	6039      	str	r1, [r7, #0]
	errno = EINVAL;
 80021c0:	f004 fca8 	bl	8006b14 <__errno>
 80021c4:	4603      	mov	r3, r0
 80021c6:	2216      	movs	r2, #22
 80021c8:	601a      	str	r2, [r3, #0]
	return -1;
 80021ca:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
}
 80021ce:	4618      	mov	r0, r3
 80021d0:	3708      	adds	r7, #8
 80021d2:	46bd      	mov	sp, r7
 80021d4:	bd80      	pop	{r7, pc}

080021d6 <_exit>:

void _exit (int status)
{
 80021d6:	b580      	push	{r7, lr}
 80021d8:	b082      	sub	sp, #8
 80021da:	af00      	add	r7, sp, #0
 80021dc:	6078      	str	r0, [r7, #4]
	_kill(status, -1);
 80021de:	f04f 31ff 	mov.w	r1, #4294967295	; 0xffffffff
 80021e2:	6878      	ldr	r0, [r7, #4]
 80021e4:	f7ff ffe7 	bl	80021b6 <_kill>
	while (1) {}		/* Make sure we hang here */
 80021e8:	e7fe      	b.n	80021e8 <_exit+0x12>

080021ea <_read>:
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 80021ea:	b580      	push	{r7, lr}
 80021ec:	b086      	sub	sp, #24
 80021ee:	af00      	add	r7, sp, #0
 80021f0:	60f8      	str	r0, [r7, #12]
 80021f2:	60b9      	str	r1, [r7, #8]
 80021f4:	607a      	str	r2, [r7, #4]
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 80021f6:	2300      	movs	r3, #0
 80021f8:	617b      	str	r3, [r7, #20]
 80021fa:	e00a      	b.n	8002212 <_read+0x28>
	{
		*ptr++ = __io_getchar();
 80021fc:	f3af 8000 	nop.w
 8002200:	4601      	mov	r1, r0
 8002202:	68bb      	ldr	r3, [r7, #8]
 8002204:	1c5a      	adds	r2, r3, #1
 8002206:	60ba      	str	r2, [r7, #8]
 8002208:	b2ca      	uxtb	r2, r1
 800220a:	701a      	strb	r2, [r3, #0]
	for (DataIdx = 0; DataIdx < len; DataIdx++)
 800220c:	697b      	ldr	r3, [r7, #20]
 800220e:	3301      	adds	r3, #1
 8002210:	617b      	str	r3, [r7, #20]
 8002212:	697a      	ldr	r2, [r7, #20]
 8002214:	687b      	ldr	r3, [r7, #4]
 8002216:	429a      	cmp	r2, r3
 8002218:	dbf0      	blt.n	80021fc <_read+0x12>
	}

return len;
 800221a:	687b      	ldr	r3, [r7, #4]
}
 800221c:	4618      	mov	r0, r3
 800221e:	3718      	adds	r7, #24
 8002220:	46bd      	mov	sp, r7
 8002222:	bd80      	pop	{r7, pc}

08002224 <_write>:

__attribute__((weak)) int _write(int file, char *ptr, int len)
{
 8002224:	b580      	push	{r7, lr}
 8002226:	b086      	sub	sp, #24
 8002228:	af00      	add	r7, sp, #0
 800222a:	60f8      	str	r0, [r7, #12]
 800222c:	60b9      	str	r1, [r7, #8]
 800222e:	607a      	str	r2, [r7, #4]
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 8002230:	2300      	movs	r3, #0
 8002232:	617b      	str	r3, [r7, #20]
 8002234:	e009      	b.n	800224a <_write+0x26>
	{
		__io_putchar(*ptr++);
 8002236:	68bb      	ldr	r3, [r7, #8]
 8002238:	1c5a      	adds	r2, r3, #1
 800223a:	60ba      	str	r2, [r7, #8]
 800223c:	781b      	ldrb	r3, [r3, #0]
 800223e:	4618      	mov	r0, r3
 8002240:	f3af 8000 	nop.w
	for (DataIdx = 0; DataIdx < len; DataIdx++)
 8002244:	697b      	ldr	r3, [r7, #20]
 8002246:	3301      	adds	r3, #1
 8002248:	617b      	str	r3, [r7, #20]
 800224a:	697a      	ldr	r2, [r7, #20]
 800224c:	687b      	ldr	r3, [r7, #4]
 800224e:	429a      	cmp	r2, r3
 8002250:	dbf1      	blt.n	8002236 <_write+0x12>
	}
	return len;
 8002252:	687b      	ldr	r3, [r7, #4]
}
 8002254:	4618      	mov	r0, r3
 8002256:	3718      	adds	r7, #24
 8002258:	46bd      	mov	sp, r7
 800225a:	bd80      	pop	{r7, pc}

0800225c <_close>:

int _close(int file)
{
 800225c:	b480      	push	{r7}
 800225e:	b083      	sub	sp, #12
 8002260:	af00      	add	r7, sp, #0
 8002262:	6078      	str	r0, [r7, #4]
	return -1;
 8002264:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
}
 8002268:	4618      	mov	r0, r3
 800226a:	370c      	adds	r7, #12
 800226c:	46bd      	mov	sp, r7
 800226e:	bc80      	pop	{r7}
 8002270:	4770      	bx	lr

08002272 <_fstat>:


int _fstat(int file, struct stat *st)
{
 8002272:	b480      	push	{r7}
 8002274:	b083      	sub	sp, #12
 8002276:	af00      	add	r7, sp, #0
 8002278:	6078      	str	r0, [r7, #4]
 800227a:	6039      	str	r1, [r7, #0]
	st->st_mode = S_IFCHR;
 800227c:	683b      	ldr	r3, [r7, #0]
 800227e:	f44f 5200 	mov.w	r2, #8192	; 0x2000
 8002282:	605a      	str	r2, [r3, #4]
	return 0;
 8002284:	2300      	movs	r3, #0
}
 8002286:	4618      	mov	r0, r3
 8002288:	370c      	adds	r7, #12
 800228a:	46bd      	mov	sp, r7
 800228c:	bc80      	pop	{r7}
 800228e:	4770      	bx	lr

08002290 <_isatty>:

int _isatty(int file)
{
 8002290:	b480      	push	{r7}
 8002292:	b083      	sub	sp, #12
 8002294:	af00      	add	r7, sp, #0
 8002296:	6078      	str	r0, [r7, #4]
	return 1;
 8002298:	2301      	movs	r3, #1
}
 800229a:	4618      	mov	r0, r3
 800229c:	370c      	adds	r7, #12
 800229e:	46bd      	mov	sp, r7
 80022a0:	bc80      	pop	{r7}
 80022a2:	4770      	bx	lr

080022a4 <_lseek>:

int _lseek(int file, int ptr, int dir)
{
 80022a4:	b480      	push	{r7}
 80022a6:	b085      	sub	sp, #20
 80022a8:	af00      	add	r7, sp, #0
 80022aa:	60f8      	str	r0, [r7, #12]
 80022ac:	60b9      	str	r1, [r7, #8]
 80022ae:	607a      	str	r2, [r7, #4]
	return 0;
 80022b0:	2300      	movs	r3, #0
}
 80022b2:	4618      	mov	r0, r3
 80022b4:	3714      	adds	r7, #20
 80022b6:	46bd      	mov	sp, r7
 80022b8:	bc80      	pop	{r7}
 80022ba:	4770      	bx	lr

080022bc <_sbrk>:
 *
 * @param incr Memory size
 * @return Pointer to allocated memory
 */
void *_sbrk(ptrdiff_t incr)
{
 80022bc:	b580      	push	{r7, lr}
 80022be:	b086      	sub	sp, #24
 80022c0:	af00      	add	r7, sp, #0
 80022c2:	6078      	str	r0, [r7, #4]
  extern uint8_t _end; /* Symbol defined in the linker script */
  extern uint8_t _estack; /* Symbol defined in the linker script */
  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
 80022c4:	4a14      	ldr	r2, [pc, #80]	; (8002318 <_sbrk+0x5c>)
 80022c6:	4b15      	ldr	r3, [pc, #84]	; (800231c <_sbrk+0x60>)
 80022c8:	1ad3      	subs	r3, r2, r3
 80022ca:	617b      	str	r3, [r7, #20]
  const uint8_t *max_heap = (uint8_t *)stack_limit;
 80022cc:	697b      	ldr	r3, [r7, #20]
 80022ce:	613b      	str	r3, [r7, #16]
  uint8_t *prev_heap_end;

  /* Initialize heap end at first call */
  if (NULL == __sbrk_heap_end)
 80022d0:	4b13      	ldr	r3, [pc, #76]	; (8002320 <_sbrk+0x64>)
 80022d2:	681b      	ldr	r3, [r3, #0]
 80022d4:	2b00      	cmp	r3, #0
 80022d6:	d102      	bne.n	80022de <_sbrk+0x22>
  {
    __sbrk_heap_end = &_end;
 80022d8:	4b11      	ldr	r3, [pc, #68]	; (8002320 <_sbrk+0x64>)
 80022da:	4a12      	ldr	r2, [pc, #72]	; (8002324 <_sbrk+0x68>)
 80022dc:	601a      	str	r2, [r3, #0]
  }

  /* Protect heap from growing into the reserved MSP stack */
  if (__sbrk_heap_end + incr > max_heap)
 80022de:	4b10      	ldr	r3, [pc, #64]	; (8002320 <_sbrk+0x64>)
 80022e0:	681a      	ldr	r2, [r3, #0]
 80022e2:	687b      	ldr	r3, [r7, #4]
 80022e4:	4413      	add	r3, r2
 80022e6:	693a      	ldr	r2, [r7, #16]
 80022e8:	429a      	cmp	r2, r3
 80022ea:	d207      	bcs.n	80022fc <_sbrk+0x40>
  {
    errno = ENOMEM;
 80022ec:	f004 fc12 	bl	8006b14 <__errno>
 80022f0:	4603      	mov	r3, r0
 80022f2:	220c      	movs	r2, #12
 80022f4:	601a      	str	r2, [r3, #0]
    return (void *)-1;
 80022f6:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
 80022fa:	e009      	b.n	8002310 <_sbrk+0x54>
  }

  prev_heap_end = __sbrk_heap_end;
 80022fc:	4b08      	ldr	r3, [pc, #32]	; (8002320 <_sbrk+0x64>)
 80022fe:	681b      	ldr	r3, [r3, #0]
 8002300:	60fb      	str	r3, [r7, #12]
  __sbrk_heap_end += incr;
 8002302:	4b07      	ldr	r3, [pc, #28]	; (8002320 <_sbrk+0x64>)
 8002304:	681a      	ldr	r2, [r3, #0]
 8002306:	687b      	ldr	r3, [r7, #4]
 8002308:	4413      	add	r3, r2
 800230a:	4a05      	ldr	r2, [pc, #20]	; (8002320 <_sbrk+0x64>)
 800230c:	6013      	str	r3, [r2, #0]

  return (void *)prev_heap_end;
 800230e:	68fb      	ldr	r3, [r7, #12]
}
 8002310:	4618      	mov	r0, r3
 8002312:	3718      	adds	r7, #24
 8002314:	46bd      	mov	sp, r7
 8002316:	bd80      	pop	{r7, pc}
 8002318:	20008000 	.word	0x20008000
 800231c:	00000400 	.word	0x00000400
 8002320:	20000204 	.word	0x20000204
 8002324:	20000708 	.word	0x20000708

08002328 <SystemInit>:
  *         SystemCoreClock variable.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 8002328:	b480      	push	{r7}
 800232a:	af00      	add	r7, sp, #0
    
  /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
 800232c:	bf00      	nop
 800232e:	46bd      	mov	sp, r7
 8002330:	bc80      	pop	{r7}
 8002332:	4770      	bx	lr

08002334 <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8002334:	480c      	ldr	r0, [pc, #48]	; (8002368 <LoopFillZerobss+0x12>)
  ldr r1, =_edata
 8002336:	490d      	ldr	r1, [pc, #52]	; (800236c <LoopFillZerobss+0x16>)
  ldr r2, =_sidata
 8002338:	4a0d      	ldr	r2, [pc, #52]	; (8002370 <LoopFillZerobss+0x1a>)
  movs r3, #0
 800233a:	2300      	movs	r3, #0
  b LoopCopyDataInit
 800233c:	e002      	b.n	8002344 <LoopCopyDataInit>

0800233e <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 800233e:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8002340:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8002342:	3304      	adds	r3, #4

08002344 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8002344:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8002346:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8002348:	d3f9      	bcc.n	800233e <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 800234a:	4a0a      	ldr	r2, [pc, #40]	; (8002374 <LoopFillZerobss+0x1e>)
  ldr r4, =_ebss
 800234c:	4c0a      	ldr	r4, [pc, #40]	; (8002378 <LoopFillZerobss+0x22>)
  movs r3, #0
 800234e:	2300      	movs	r3, #0
  b LoopFillZerobss
 8002350:	e001      	b.n	8002356 <LoopFillZerobss>

08002352 <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8002352:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8002354:	3204      	adds	r2, #4

08002356 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8002356:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8002358:	d3fb      	bcc.n	8002352 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 800235a:	f7ff ffe5 	bl	8002328 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 800235e:	f004 fbdf 	bl	8006b20 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8002362:	f7fe fedd 	bl	8001120 <main>
  bx lr
 8002366:	4770      	bx	lr
  ldr r0, =_sdata
 8002368:	20000000 	.word	0x20000000
  ldr r1, =_edata
 800236c:	200001e4 	.word	0x200001e4
  ldr r2, =_sidata
 8002370:	0800aa44 	.word	0x0800aa44
  ldr r2, =_sbss
 8002374:	200001e4 	.word	0x200001e4
  ldr r4, =_ebss
 8002378:	20000704 	.word	0x20000704

0800237c <ADC1_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 800237c:	e7fe      	b.n	800237c <ADC1_IRQHandler>

0800237e <HAL_Init>:
  *        In the default implementation,Systick is used as source of time base.
  *        the tick variable is incremented each 1ms in its ISR.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 800237e:	b580      	push	{r7, lr}
 8002380:	b082      	sub	sp, #8
 8002382:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 8002384:	2300      	movs	r3, #0
 8002386:	71fb      	strb	r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8002388:	2003      	movs	r0, #3
 800238a:	f000 ff8d 	bl	80032a8 <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 800238e:	200f      	movs	r0, #15
 8002390:	f000 f80e 	bl	80023b0 <HAL_InitTick>
 8002394:	4603      	mov	r3, r0
 8002396:	2b00      	cmp	r3, #0
 8002398:	d002      	beq.n	80023a0 <HAL_Init+0x22>
  {
    status = HAL_ERROR;
 800239a:	2301      	movs	r3, #1
 800239c:	71fb      	strb	r3, [r7, #7]
 800239e:	e001      	b.n	80023a4 <HAL_Init+0x26>
  }
  else
  {
    /* Init the low level hardware */
    HAL_MspInit();
 80023a0:	f7ff fbe0 	bl	8001b64 <HAL_MspInit>
  }

  /* Return function status */
  return status;
 80023a4:	79fb      	ldrb	r3, [r7, #7]
}
 80023a6:	4618      	mov	r0, r3
 80023a8:	3708      	adds	r7, #8
 80023aa:	46bd      	mov	sp, r7
 80023ac:	bd80      	pop	{r7, pc}
	...

080023b0 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 80023b0:	b580      	push	{r7, lr}
 80023b2:	b084      	sub	sp, #16
 80023b4:	af00      	add	r7, sp, #0
 80023b6:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef  status = HAL_OK;
 80023b8:	2300      	movs	r3, #0
 80023ba:	73fb      	strb	r3, [r7, #15]

  if (uwTickFreq != 0U)
 80023bc:	4b16      	ldr	r3, [pc, #88]	; (8002418 <HAL_InitTick+0x68>)
 80023be:	681b      	ldr	r3, [r3, #0]
 80023c0:	2b00      	cmp	r3, #0
 80023c2:	d022      	beq.n	800240a <HAL_InitTick+0x5a>
  {
    /*Configure the SysTick to have interrupt in 1ms time basis*/
    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
 80023c4:	4b15      	ldr	r3, [pc, #84]	; (800241c <HAL_InitTick+0x6c>)
 80023c6:	681a      	ldr	r2, [r3, #0]
 80023c8:	4b13      	ldr	r3, [pc, #76]	; (8002418 <HAL_InitTick+0x68>)
 80023ca:	681b      	ldr	r3, [r3, #0]
 80023cc:	f44f 717a 	mov.w	r1, #1000	; 0x3e8
 80023d0:	fbb1 f3f3 	udiv	r3, r1, r3
 80023d4:	fbb2 f3f3 	udiv	r3, r2, r3
 80023d8:	4618      	mov	r0, r3
 80023da:	f000 ff9a 	bl	8003312 <HAL_SYSTICK_Config>
 80023de:	4603      	mov	r3, r0
 80023e0:	2b00      	cmp	r3, #0
 80023e2:	d10f      	bne.n	8002404 <HAL_InitTick+0x54>
    {
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 80023e4:	687b      	ldr	r3, [r7, #4]
 80023e6:	2b0f      	cmp	r3, #15
 80023e8:	d809      	bhi.n	80023fe <HAL_InitTick+0x4e>
      {
        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 80023ea:	2200      	movs	r2, #0
 80023ec:	6879      	ldr	r1, [r7, #4]
 80023ee:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 80023f2:	f000 ff64 	bl	80032be <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 80023f6:	4a0a      	ldr	r2, [pc, #40]	; (8002420 <HAL_InitTick+0x70>)
 80023f8:	687b      	ldr	r3, [r7, #4]
 80023fa:	6013      	str	r3, [r2, #0]
 80023fc:	e007      	b.n	800240e <HAL_InitTick+0x5e>
      }
      else
      {
        status = HAL_ERROR;
 80023fe:	2301      	movs	r3, #1
 8002400:	73fb      	strb	r3, [r7, #15]
 8002402:	e004      	b.n	800240e <HAL_InitTick+0x5e>
      }
    }
    else
    {
      status = HAL_ERROR;
 8002404:	2301      	movs	r3, #1
 8002406:	73fb      	strb	r3, [r7, #15]
 8002408:	e001      	b.n	800240e <HAL_InitTick+0x5e>
    }
  }
  else
  {
    status = HAL_ERROR;
 800240a:	2301      	movs	r3, #1
 800240c:	73fb      	strb	r3, [r7, #15]
  }

  /* Return function status */
  return status;
 800240e:	7bfb      	ldrb	r3, [r7, #15]
}
 8002410:	4618      	mov	r0, r3
 8002412:	3710      	adds	r7, #16
 8002414:	46bd      	mov	sp, r7
 8002416:	bd80      	pop	{r7, pc}
 8002418:	20000008 	.word	0x20000008
 800241c:	20000000 	.word	0x20000000
 8002420:	20000004 	.word	0x20000004

08002424 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8002424:	b480      	push	{r7}
 8002426:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 8002428:	4b05      	ldr	r3, [pc, #20]	; (8002440 <HAL_IncTick+0x1c>)
 800242a:	681a      	ldr	r2, [r3, #0]
 800242c:	4b05      	ldr	r3, [pc, #20]	; (8002444 <HAL_IncTick+0x20>)
 800242e:	681b      	ldr	r3, [r3, #0]
 8002430:	4413      	add	r3, r2
 8002432:	4a03      	ldr	r2, [pc, #12]	; (8002440 <HAL_IncTick+0x1c>)
 8002434:	6013      	str	r3, [r2, #0]
}
 8002436:	bf00      	nop
 8002438:	46bd      	mov	sp, r7
 800243a:	bc80      	pop	{r7}
 800243c:	4770      	bx	lr
 800243e:	bf00      	nop
 8002440:	200006f0 	.word	0x200006f0
 8002444:	20000008 	.word	0x20000008

08002448 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8002448:	b480      	push	{r7}
 800244a:	af00      	add	r7, sp, #0
  return uwTick;
 800244c:	4b02      	ldr	r3, [pc, #8]	; (8002458 <HAL_GetTick+0x10>)
 800244e:	681b      	ldr	r3, [r3, #0]
}
 8002450:	4618      	mov	r0, r3
 8002452:	46bd      	mov	sp, r7
 8002454:	bc80      	pop	{r7}
 8002456:	4770      	bx	lr
 8002458:	200006f0 	.word	0x200006f0

0800245c <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 800245c:	b580      	push	{r7, lr}
 800245e:	b084      	sub	sp, #16
 8002460:	af00      	add	r7, sp, #0
 8002462:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8002464:	f7ff fff0 	bl	8002448 <HAL_GetTick>
 8002468:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 800246a:	687b      	ldr	r3, [r7, #4]
 800246c:	60fb      	str	r3, [r7, #12]

  /* Add a period to guaranty minimum wait */
  if (wait < HAL_MAX_DELAY)
 800246e:	68fb      	ldr	r3, [r7, #12]
 8002470:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8002474:	d004      	beq.n	8002480 <HAL_Delay+0x24>
  {
    wait += (uint32_t)(uwTickFreq);
 8002476:	4b09      	ldr	r3, [pc, #36]	; (800249c <HAL_Delay+0x40>)
 8002478:	681b      	ldr	r3, [r3, #0]
 800247a:	68fa      	ldr	r2, [r7, #12]
 800247c:	4413      	add	r3, r2
 800247e:	60fb      	str	r3, [r7, #12]
  }

  while((HAL_GetTick() - tickstart) < wait)
 8002480:	bf00      	nop
 8002482:	f7ff ffe1 	bl	8002448 <HAL_GetTick>
 8002486:	4602      	mov	r2, r0
 8002488:	68bb      	ldr	r3, [r7, #8]
 800248a:	1ad3      	subs	r3, r2, r3
 800248c:	68fa      	ldr	r2, [r7, #12]
 800248e:	429a      	cmp	r2, r3
 8002490:	d8f7      	bhi.n	8002482 <HAL_Delay+0x26>
  {
  }
}
 8002492:	bf00      	nop
 8002494:	bf00      	nop
 8002496:	3710      	adds	r7, #16
 8002498:	46bd      	mov	sp, r7
 800249a:	bd80      	pop	{r7, pc}
 800249c:	20000008 	.word	0x20000008

080024a0 <HAL_ADC_Init>:
  *         of structure "ADC_InitTypeDef".
  * @param  hadc ADC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
 80024a0:	b580      	push	{r7, lr}
 80024a2:	b08e      	sub	sp, #56	; 0x38
 80024a4:	af00      	add	r7, sp, #0
 80024a6:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 80024a8:	2300      	movs	r3, #0
 80024aa:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
  uint32_t tmp_cr1 = 0;
 80024ae:	2300      	movs	r3, #0
 80024b0:	633b      	str	r3, [r7, #48]	; 0x30
  uint32_t tmp_cr2 = 0;
 80024b2:	2300      	movs	r3, #0
 80024b4:	62fb      	str	r3, [r7, #44]	; 0x2c
  
  /* Check ADC handle */
  if(hadc == NULL)
 80024b6:	687b      	ldr	r3, [r7, #4]
 80024b8:	2b00      	cmp	r3, #0
 80024ba:	d101      	bne.n	80024c0 <HAL_ADC_Init+0x20>
  {
    return HAL_ERROR;
 80024bc:	2301      	movs	r3, #1
 80024be:	e127      	b.n	8002710 <HAL_ADC_Init+0x270>
  assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
  
  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
 80024c0:	687b      	ldr	r3, [r7, #4]
 80024c2:	691b      	ldr	r3, [r3, #16]
 80024c4:	2b00      	cmp	r3, #0
  /* Refer to header of this file for more details on clock enabling          */
  /* procedure.                                                               */

  /* Actions performed only if ADC is coming from state reset:                */
  /* - Initialization of ADC MSP                                              */
  if (hadc->State == HAL_ADC_STATE_RESET)
 80024c6:	687b      	ldr	r3, [r7, #4]
 80024c8:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80024ca:	2b00      	cmp	r3, #0
 80024cc:	d115      	bne.n	80024fa <HAL_ADC_Init+0x5a>
  {
    /* Initialize ADC error code */
    ADC_CLEAR_ERRORCODE(hadc);
 80024ce:	687b      	ldr	r3, [r7, #4]
 80024d0:	2200      	movs	r2, #0
 80024d2:	651a      	str	r2, [r3, #80]	; 0x50
    
    /* Allocate lock resource and initialize it */
    hadc->Lock = HAL_UNLOCKED;
 80024d4:	687b      	ldr	r3, [r7, #4]
 80024d6:	2200      	movs	r2, #0
 80024d8:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
    
    /* Enable SYSCFG clock to control the routing Interface (RI) */
    __HAL_RCC_SYSCFG_CLK_ENABLE();
 80024dc:	4b8e      	ldr	r3, [pc, #568]	; (8002718 <HAL_ADC_Init+0x278>)
 80024de:	6a1b      	ldr	r3, [r3, #32]
 80024e0:	4a8d      	ldr	r2, [pc, #564]	; (8002718 <HAL_ADC_Init+0x278>)
 80024e2:	f043 0301 	orr.w	r3, r3, #1
 80024e6:	6213      	str	r3, [r2, #32]
 80024e8:	4b8b      	ldr	r3, [pc, #556]	; (8002718 <HAL_ADC_Init+0x278>)
 80024ea:	6a1b      	ldr	r3, [r3, #32]
 80024ec:	f003 0301 	and.w	r3, r3, #1
 80024f0:	60bb      	str	r3, [r7, #8]
 80024f2:	68bb      	ldr	r3, [r7, #8]
    
    /* Init the low level hardware */
    hadc->MspInitCallback(hadc);
#else
    /* Init the low level hardware */
    HAL_ADC_MspInit(hadc);
 80024f4:	6878      	ldr	r0, [r7, #4]
 80024f6:	f7ff fb63 	bl	8001bc0 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  }
  
  /* Configuration of ADC parameters if previous preliminary actions are      */ 
  /* correctly completed.                                                     */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 80024fa:	687b      	ldr	r3, [r7, #4]
 80024fc:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80024fe:	f003 0310 	and.w	r3, r3, #16
 8002502:	2b00      	cmp	r3, #0
 8002504:	f040 80ff 	bne.w	8002706 <HAL_ADC_Init+0x266>
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8002508:	687b      	ldr	r3, [r7, #4]
 800250a:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800250c:	f423 5388 	bic.w	r3, r3, #4352	; 0x1100
 8002510:	f023 0302 	bic.w	r3, r3, #2
 8002514:	f043 0202 	orr.w	r2, r3, #2
 8002518:	687b      	ldr	r3, [r7, #4]
 800251a:	64da      	str	r2, [r3, #76]	; 0x4c
    
    /* Set ADC parameters */
    
    /* Configuration of common ADC clock: clock source HSI with selectable    */
    /* prescaler                                                              */
    MODIFY_REG(ADC->CCR                 ,
 800251c:	4b7f      	ldr	r3, [pc, #508]	; (800271c <HAL_ADC_Init+0x27c>)
 800251e:	685b      	ldr	r3, [r3, #4]
 8002520:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
 8002524:	687b      	ldr	r3, [r7, #4]
 8002526:	685b      	ldr	r3, [r3, #4]
 8002528:	497c      	ldr	r1, [pc, #496]	; (800271c <HAL_ADC_Init+0x27c>)
 800252a:	4313      	orrs	r3, r2
 800252c:	604b      	str	r3, [r1, #4]
    /*  - external trigger polarity                                           */
    /*  - End of conversion selection                                         */
    /*  - DMA continuous request                                              */
    /*  - Channels bank (Banks availability depends on devices categories)    */
    /*  - continuous conversion mode                                          */
    tmp_cr2 |= (hadc->Init.DataAlign                                           |
 800252e:	687b      	ldr	r3, [r7, #4]
 8002530:	68da      	ldr	r2, [r3, #12]
                hadc->Init.EOCSelection                                        |
 8002532:	687b      	ldr	r3, [r7, #4]
 8002534:	695b      	ldr	r3, [r3, #20]
    tmp_cr2 |= (hadc->Init.DataAlign                                           |
 8002536:	431a      	orrs	r2, r3
                ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
 8002538:	687b      	ldr	r3, [r7, #4]
 800253a:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 800253e:	4619      	mov	r1, r3
 8002540:	f44f 7300 	mov.w	r3, #512	; 0x200
 8002544:	623b      	str	r3, [r7, #32]
  uint32_t result;

#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8002546:	6a3b      	ldr	r3, [r7, #32]
 8002548:	fa93 f3a3 	rbit	r3, r3
 800254c:	61fb      	str	r3, [r7, #28]
    result |= value & 1U;
    s--;
  }
  result <<= s;                        /* shift when v's highest bits are zero */
#endif
  return result;
 800254e:	69fb      	ldr	r3, [r7, #28]
 8002550:	fab3 f383 	clz	r3, r3
 8002554:	b2db      	uxtb	r3, r3
 8002556:	fa01 f303 	lsl.w	r3, r1, r3
                hadc->Init.EOCSelection                                        |
 800255a:	431a      	orrs	r2, r3
                hadc->Init.ChannelsBank                                        |
 800255c:	687b      	ldr	r3, [r7, #4]
 800255e:	6a1b      	ldr	r3, [r3, #32]
                ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
 8002560:	431a      	orrs	r2, r3
                ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)     );
 8002562:	687b      	ldr	r3, [r7, #4]
 8002564:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
 8002568:	4619      	mov	r1, r3
 800256a:	2302      	movs	r3, #2
 800256c:	62bb      	str	r3, [r7, #40]	; 0x28
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800256e:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8002570:	fa93 f3a3 	rbit	r3, r3
 8002574:	627b      	str	r3, [r7, #36]	; 0x24
  return result;
 8002576:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002578:	fab3 f383 	clz	r3, r3
 800257c:	b2db      	uxtb	r3, r3
 800257e:	fa01 f303 	lsl.w	r3, r1, r3
                hadc->Init.ChannelsBank                                        |
 8002582:	4313      	orrs	r3, r2
    tmp_cr2 |= (hadc->Init.DataAlign                                           |
 8002584:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 8002586:	4313      	orrs	r3, r2
 8002588:	62fb      	str	r3, [r7, #44]	; 0x2c
    /* Enable external trigger if trigger selection is different of software  */
    /* start.                                                                 */
    /* Note: This configuration keeps the hardware feature of parameter       */
    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
    /*       software start.                                                  */
    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
 800258a:	687b      	ldr	r3, [r7, #4]
 800258c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800258e:	2b10      	cmp	r3, #16
 8002590:	d007      	beq.n	80025a2 <HAL_ADC_Init+0x102>
    {
      tmp_cr2 |= ( hadc->Init.ExternalTrigConv    |
 8002592:	687b      	ldr	r3, [r7, #4]
 8002594:	6b5a      	ldr	r2, [r3, #52]	; 0x34
                  hadc->Init.ExternalTrigConvEdge );
 8002596:	687b      	ldr	r3, [r7, #4]
 8002598:	6b9b      	ldr	r3, [r3, #56]	; 0x38
      tmp_cr2 |= ( hadc->Init.ExternalTrigConv    |
 800259a:	4313      	orrs	r3, r2
 800259c:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 800259e:	4313      	orrs	r3, r2
 80025a0:	62fb      	str	r3, [r7, #44]	; 0x2c
    /*  - resolution                                                          */
    /*  - auto power off (LowPowerAutoPowerOff mode)                          */
    /*  - scan mode                                                           */
    /*  - discontinuous mode disable/enable                                   */
    /*  - discontinuous mode number of conversions                            */
    if ((ADC_IS_ENABLE(hadc) == RESET))
 80025a2:	687b      	ldr	r3, [r7, #4]
 80025a4:	681b      	ldr	r3, [r3, #0]
 80025a6:	681b      	ldr	r3, [r3, #0]
 80025a8:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80025ac:	2b40      	cmp	r3, #64	; 0x40
 80025ae:	d04f      	beq.n	8002650 <HAL_ADC_Init+0x1b0>
    {
      tmp_cr2 |= hadc->Init.LowPowerAutoWait;
 80025b0:	687b      	ldr	r3, [r7, #4]
 80025b2:	699b      	ldr	r3, [r3, #24]
 80025b4:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 80025b6:	4313      	orrs	r3, r2
 80025b8:	62fb      	str	r3, [r7, #44]	; 0x2c
      
      tmp_cr1 |= (hadc->Init.Resolution                     |
 80025ba:	687b      	ldr	r3, [r7, #4]
 80025bc:	689a      	ldr	r2, [r3, #8]
                  hadc->Init.LowPowerAutoPowerOff           |
 80025be:	687b      	ldr	r3, [r7, #4]
 80025c0:	69db      	ldr	r3, [r3, #28]
      tmp_cr1 |= (hadc->Init.Resolution                     |
 80025c2:	4313      	orrs	r3, r2
                  ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)  );
 80025c4:	687a      	ldr	r2, [r7, #4]
 80025c6:	6912      	ldr	r2, [r2, #16]
 80025c8:	f5b2 7f80 	cmp.w	r2, #256	; 0x100
 80025cc:	d003      	beq.n	80025d6 <HAL_ADC_Init+0x136>
 80025ce:	687a      	ldr	r2, [r7, #4]
 80025d0:	6912      	ldr	r2, [r2, #16]
 80025d2:	2a01      	cmp	r2, #1
 80025d4:	d102      	bne.n	80025dc <HAL_ADC_Init+0x13c>
 80025d6:	f44f 7280 	mov.w	r2, #256	; 0x100
 80025da:	e000      	b.n	80025de <HAL_ADC_Init+0x13e>
 80025dc:	2200      	movs	r2, #0
                  hadc->Init.LowPowerAutoPowerOff           |
 80025de:	4313      	orrs	r3, r2
      tmp_cr1 |= (hadc->Init.Resolution                     |
 80025e0:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 80025e2:	4313      	orrs	r3, r2
 80025e4:	633b      	str	r3, [r7, #48]	; 0x30
      
      /* Enable discontinuous mode only if continuous mode is disabled */
      /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter  */
      /*       discontinuous is set anyway, but has no effect on ADC HW.      */
      if (hadc->Init.DiscontinuousConvMode == ENABLE)
 80025e6:	687b      	ldr	r3, [r7, #4]
 80025e8:	f893 302c 	ldrb.w	r3, [r3, #44]	; 0x2c
 80025ec:	2b01      	cmp	r3, #1
 80025ee:	d125      	bne.n	800263c <HAL_ADC_Init+0x19c>
      {
        if (hadc->Init.ContinuousConvMode == DISABLE)
 80025f0:	687b      	ldr	r3, [r7, #4]
 80025f2:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
 80025f6:	2b00      	cmp	r3, #0
 80025f8:	d114      	bne.n	8002624 <HAL_ADC_Init+0x184>
        {
          /* Enable the selected ADC regular discontinuous mode */
          /* Set the number of channels to be converted in discontinuous mode */
          SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
 80025fa:	687b      	ldr	r3, [r7, #4]
 80025fc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80025fe:	3b01      	subs	r3, #1
 8002600:	f44f 4260 	mov.w	r2, #57344	; 0xe000
 8002604:	61ba      	str	r2, [r7, #24]
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 8002606:	69ba      	ldr	r2, [r7, #24]
 8002608:	fa92 f2a2 	rbit	r2, r2
 800260c:	617a      	str	r2, [r7, #20]
  return result;
 800260e:	697a      	ldr	r2, [r7, #20]
 8002610:	fab2 f282 	clz	r2, r2
 8002614:	b2d2      	uxtb	r2, r2
 8002616:	4093      	lsls	r3, r2
 8002618:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
 800261c:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 800261e:	4313      	orrs	r3, r2
 8002620:	633b      	str	r3, [r7, #48]	; 0x30
 8002622:	e00b      	b.n	800263c <HAL_ADC_Init+0x19c>
        {
          /* ADC regular group settings continuous and sequencer discontinuous*/
          /* cannot be enabled simultaneously.                                */
          
          /* Update ADC state machine to error */
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8002624:	687b      	ldr	r3, [r7, #4]
 8002626:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002628:	f043 0220 	orr.w	r2, r3, #32
 800262c:	687b      	ldr	r3, [r7, #4]
 800262e:	64da      	str	r2, [r3, #76]	; 0x4c
          
          /* Set ADC error code to ADC IP internal error */
          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8002630:	687b      	ldr	r3, [r7, #4]
 8002632:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8002634:	f043 0201 	orr.w	r2, r3, #1
 8002638:	687b      	ldr	r3, [r7, #4]
 800263a:	651a      	str	r2, [r3, #80]	; 0x50
        }
      }
      
      /* Update ADC configuration register CR1 with previous settings */
        MODIFY_REG(hadc->Instance->CR1,
 800263c:	687b      	ldr	r3, [r7, #4]
 800263e:	681b      	ldr	r3, [r3, #0]
 8002640:	685a      	ldr	r2, [r3, #4]
 8002642:	4b37      	ldr	r3, [pc, #220]	; (8002720 <HAL_ADC_Init+0x280>)
 8002644:	4013      	ands	r3, r2
 8002646:	687a      	ldr	r2, [r7, #4]
 8002648:	6812      	ldr	r2, [r2, #0]
 800264a:	6b39      	ldr	r1, [r7, #48]	; 0x30
 800264c:	430b      	orrs	r3, r1
 800264e:	6053      	str	r3, [r2, #4]
                   ADC_CR1_SCAN     ,
                   tmp_cr1           );
    }
    
    /* Update ADC configuration register CR2 with previous settings */
    MODIFY_REG(hadc->Instance->CR2    ,
 8002650:	687b      	ldr	r3, [r7, #4]
 8002652:	681b      	ldr	r3, [r3, #0]
 8002654:	689a      	ldr	r2, [r3, #8]
 8002656:	4b33      	ldr	r3, [pc, #204]	; (8002724 <HAL_ADC_Init+0x284>)
 8002658:	4013      	ands	r3, r2
 800265a:	687a      	ldr	r2, [r7, #4]
 800265c:	6812      	ldr	r2, [r2, #0]
 800265e:	6af9      	ldr	r1, [r7, #44]	; 0x2c
 8002660:	430b      	orrs	r3, r1
 8002662:	6093      	str	r3, [r2, #8]
    /*   Note: Scan mode is present by hardware on this device and, if        */
    /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
    /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
    /* - if scan mode is enabled, regular channels sequence length is set to  */
    /*   parameter "NbrOfConversion"                                          */
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 8002664:	687b      	ldr	r3, [r7, #4]
 8002666:	691b      	ldr	r3, [r3, #16]
 8002668:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 800266c:	d003      	beq.n	8002676 <HAL_ADC_Init+0x1d6>
 800266e:	687b      	ldr	r3, [r7, #4]
 8002670:	691b      	ldr	r3, [r3, #16]
 8002672:	2b01      	cmp	r3, #1
 8002674:	d119      	bne.n	80026aa <HAL_ADC_Init+0x20a>
    {
      MODIFY_REG(hadc->Instance->SQR1                         ,
 8002676:	687b      	ldr	r3, [r7, #4]
 8002678:	681b      	ldr	r3, [r3, #0]
 800267a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800267c:	f023 71f8 	bic.w	r1, r3, #32505856	; 0x1f00000
 8002680:	687b      	ldr	r3, [r7, #4]
 8002682:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8002684:	3b01      	subs	r3, #1
 8002686:	f04f 72f8 	mov.w	r2, #32505856	; 0x1f00000
 800268a:	613a      	str	r2, [r7, #16]
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 800268c:	693a      	ldr	r2, [r7, #16]
 800268e:	fa92 f2a2 	rbit	r2, r2
 8002692:	60fa      	str	r2, [r7, #12]
  return result;
 8002694:	68fa      	ldr	r2, [r7, #12]
 8002696:	fab2 f282 	clz	r2, r2
 800269a:	b2d2      	uxtb	r2, r2
 800269c:	fa03 f202 	lsl.w	r2, r3, r2
 80026a0:	687b      	ldr	r3, [r7, #4]
 80026a2:	681b      	ldr	r3, [r3, #0]
 80026a4:	430a      	orrs	r2, r1
 80026a6:	631a      	str	r2, [r3, #48]	; 0x30
 80026a8:	e007      	b.n	80026ba <HAL_ADC_Init+0x21a>
                 ADC_SQR1_L                                   ,
                 ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion)  );
    }
    else
    {
      MODIFY_REG(hadc->Instance->SQR1,
 80026aa:	687b      	ldr	r3, [r7, #4]
 80026ac:	681b      	ldr	r3, [r3, #0]
 80026ae:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 80026b0:	687b      	ldr	r3, [r7, #4]
 80026b2:	681b      	ldr	r3, [r3, #0]
 80026b4:	f022 72f8 	bic.w	r2, r2, #32505856	; 0x1f00000
 80026b8:	631a      	str	r2, [r3, #48]	; 0x30
    
    /* Check back that ADC registers have effectively been configured to      */
    /* ensure of no potential problem of ADC core IP clocking.                */
    /* Check through register CR2 (excluding execution control bits ADON,     */
    /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL).       */
    if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON |
 80026ba:	687b      	ldr	r3, [r7, #4]
 80026bc:	681b      	ldr	r3, [r3, #0]
 80026be:	689a      	ldr	r2, [r3, #8]
 80026c0:	4b19      	ldr	r3, [pc, #100]	; (8002728 <HAL_ADC_Init+0x288>)
 80026c2:	4013      	ands	r3, r2
 80026c4:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 80026c6:	429a      	cmp	r2, r3
 80026c8:	d10b      	bne.n	80026e2 <HAL_ADC_Init+0x242>
                                           ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
                                           ADC_CR2_JEXTEN  | ADC_CR2_JEXTSEL   ))
         == tmp_cr2)
    {
      /* Set ADC error code to none */
      ADC_CLEAR_ERRORCODE(hadc);
 80026ca:	687b      	ldr	r3, [r7, #4]
 80026cc:	2200      	movs	r2, #0
 80026ce:	651a      	str	r2, [r3, #80]	; 0x50
      
      /* Set the ADC state */
      ADC_STATE_CLR_SET(hadc->State,
 80026d0:	687b      	ldr	r3, [r7, #4]
 80026d2:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80026d4:	f023 0303 	bic.w	r3, r3, #3
 80026d8:	f043 0201 	orr.w	r2, r3, #1
 80026dc:	687b      	ldr	r3, [r7, #4]
 80026de:	64da      	str	r2, [r3, #76]	; 0x4c
 80026e0:	e014      	b.n	800270c <HAL_ADC_Init+0x26c>
                        HAL_ADC_STATE_READY);
    }
    else
    {
      /* Update ADC state machine to error */
      ADC_STATE_CLR_SET(hadc->State,
 80026e2:	687b      	ldr	r3, [r7, #4]
 80026e4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80026e6:	f023 0312 	bic.w	r3, r3, #18
 80026ea:	f043 0210 	orr.w	r2, r3, #16
 80026ee:	687b      	ldr	r3, [r7, #4]
 80026f0:	64da      	str	r2, [r3, #76]	; 0x4c
                        HAL_ADC_STATE_BUSY_INTERNAL,
                        HAL_ADC_STATE_ERROR_INTERNAL);
      
      /* Set ADC error code to ADC IP internal error */
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80026f2:	687b      	ldr	r3, [r7, #4]
 80026f4:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 80026f6:	f043 0201 	orr.w	r2, r3, #1
 80026fa:	687b      	ldr	r3, [r7, #4]
 80026fc:	651a      	str	r2, [r3, #80]	; 0x50
      
      tmp_hal_status = HAL_ERROR;
 80026fe:	2301      	movs	r3, #1
 8002700:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
 8002704:	e002      	b.n	800270c <HAL_ADC_Init+0x26c>
    }
    
  }
  else
  {
    tmp_hal_status = HAL_ERROR;
 8002706:	2301      	movs	r3, #1
 8002708:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
  }
  
  /* Return function status */
  return tmp_hal_status;
 800270c:	f897 3037 	ldrb.w	r3, [r7, #55]	; 0x37
}
 8002710:	4618      	mov	r0, r3
 8002712:	3738      	adds	r7, #56	; 0x38
 8002714:	46bd      	mov	sp, r7
 8002716:	bd80      	pop	{r7, pc}
 8002718:	40023800 	.word	0x40023800
 800271c:	40012700 	.word	0x40012700
 8002720:	fcfc16ff 	.word	0xfcfc16ff
 8002724:	c0fff18d 	.word	0xc0fff18d
 8002728:	bf80fffe 	.word	0xbf80fffe

0800272c <HAL_ADC_Start_DMA>:
  * @param  pData The destination Buffer address.
  * @param  Length The length of data to be transferred from ADC peripheral to memory.
  * @retval None
  */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
 800272c:	b580      	push	{r7, lr}
 800272e:	b086      	sub	sp, #24
 8002730:	af00      	add	r7, sp, #0
 8002732:	60f8      	str	r0, [r7, #12]
 8002734:	60b9      	str	r1, [r7, #8]
 8002736:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8002738:	2300      	movs	r3, #0
 800273a:	75fb      	strb	r3, [r7, #23]
  
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 800273c:	68fb      	ldr	r3, [r7, #12]
 800273e:	f893 3048 	ldrb.w	r3, [r3, #72]	; 0x48
 8002742:	2b01      	cmp	r3, #1
 8002744:	d101      	bne.n	800274a <HAL_ADC_Start_DMA+0x1e>
 8002746:	2302      	movs	r3, #2
 8002748:	e074      	b.n	8002834 <HAL_ADC_Start_DMA+0x108>
 800274a:	68fb      	ldr	r3, [r7, #12]
 800274c:	2201      	movs	r2, #1
 800274e:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
  
  /* Enable the ADC peripheral */
  tmp_hal_status = ADC_Enable(hadc);
 8002752:	68f8      	ldr	r0, [r7, #12]
 8002754:	f000 fa34 	bl	8002bc0 <ADC_Enable>
 8002758:	4603      	mov	r3, r0
 800275a:	75fb      	strb	r3, [r7, #23]
  
  /* Start conversion if ADC is effectively enabled */
  if (tmp_hal_status == HAL_OK)
 800275c:	7dfb      	ldrb	r3, [r7, #23]
 800275e:	2b00      	cmp	r3, #0
 8002760:	d167      	bne.n	8002832 <HAL_ADC_Start_DMA+0x106>
  {
    /* Set ADC state                                                          */
    /* - Clear state bitfield related to regular group conversion results     */
    /* - Set state bitfield related to regular group operation                */
    ADC_STATE_CLR_SET(hadc->State,
 8002762:	68fb      	ldr	r3, [r7, #12]
 8002764:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002766:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 800276a:	f023 0301 	bic.w	r3, r3, #1
 800276e:	f443 7280 	orr.w	r2, r3, #256	; 0x100
 8002772:	68fb      	ldr	r3, [r7, #12]
 8002774:	64da      	str	r2, [r3, #76]	; 0x4c
                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
                      HAL_ADC_STATE_REG_BUSY);
    
    /* If conversions on group regular are also triggering group injected,    */
    /* update ADC state.                                                      */
    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
 8002776:	68fb      	ldr	r3, [r7, #12]
 8002778:	681b      	ldr	r3, [r3, #0]
 800277a:	685b      	ldr	r3, [r3, #4]
 800277c:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8002780:	2b00      	cmp	r3, #0
 8002782:	d007      	beq.n	8002794 <HAL_ADC_Start_DMA+0x68>
    {
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
 8002784:	68fb      	ldr	r3, [r7, #12]
 8002786:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002788:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 800278c:	f443 5280 	orr.w	r2, r3, #4096	; 0x1000
 8002790:	68fb      	ldr	r3, [r7, #12]
 8002792:	64da      	str	r2, [r3, #76]	; 0x4c
    }
    
    /* State machine update: Check if an injected conversion is ongoing */
    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 8002794:	68fb      	ldr	r3, [r7, #12]
 8002796:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002798:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 800279c:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 80027a0:	d106      	bne.n	80027b0 <HAL_ADC_Start_DMA+0x84>
    {
      /* Reset ADC error code fields related to conversions on group regular */
      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
 80027a2:	68fb      	ldr	r3, [r7, #12]
 80027a4:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 80027a6:	f023 0206 	bic.w	r2, r3, #6
 80027aa:	68fb      	ldr	r3, [r7, #12]
 80027ac:	651a      	str	r2, [r3, #80]	; 0x50
 80027ae:	e002      	b.n	80027b6 <HAL_ADC_Start_DMA+0x8a>
    }
    else
    {
      /* Reset ADC all error code fields */
      ADC_CLEAR_ERRORCODE(hadc);
 80027b0:	68fb      	ldr	r3, [r7, #12]
 80027b2:	2200      	movs	r2, #0
 80027b4:	651a      	str	r2, [r3, #80]	; 0x50
    }
    
    /* Process unlocked */
    /* Unlock before starting ADC conversions: in case of potential           */
    /* interruption, to let the process to ADC IRQ Handler.                   */
    __HAL_UNLOCK(hadc);
 80027b6:	68fb      	ldr	r3, [r7, #12]
 80027b8:	2200      	movs	r2, #0
 80027ba:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48

    /* Set the DMA transfer complete callback */
    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 80027be:	68fb      	ldr	r3, [r7, #12]
 80027c0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80027c2:	4a1e      	ldr	r2, [pc, #120]	; (800283c <HAL_ADC_Start_DMA+0x110>)
 80027c4:	629a      	str	r2, [r3, #40]	; 0x28

    /* Set the DMA half transfer complete callback */
    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
 80027c6:	68fb      	ldr	r3, [r7, #12]
 80027c8:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80027ca:	4a1d      	ldr	r2, [pc, #116]	; (8002840 <HAL_ADC_Start_DMA+0x114>)
 80027cc:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Set the DMA error callback */
    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
 80027ce:	68fb      	ldr	r3, [r7, #12]
 80027d0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80027d2:	4a1c      	ldr	r2, [pc, #112]	; (8002844 <HAL_ADC_Start_DMA+0x118>)
 80027d4:	631a      	str	r2, [r3, #48]	; 0x30
    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
    /* start (in case of SW start):                                           */
    
    /* Clear regular group conversion flag and overrun flag */
    /* (To ensure of no unknown state from potential previous ADC operations) */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
 80027d6:	68fb      	ldr	r3, [r7, #12]
 80027d8:	681b      	ldr	r3, [r3, #0]
 80027da:	f06f 0222 	mvn.w	r2, #34	; 0x22
 80027de:	601a      	str	r2, [r3, #0]

    /* Enable ADC overrun interrupt */
    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
 80027e0:	68fb      	ldr	r3, [r7, #12]
 80027e2:	681b      	ldr	r3, [r3, #0]
 80027e4:	685a      	ldr	r2, [r3, #4]
 80027e6:	68fb      	ldr	r3, [r7, #12]
 80027e8:	681b      	ldr	r3, [r3, #0]
 80027ea:	f042 6280 	orr.w	r2, r2, #67108864	; 0x4000000
 80027ee:	605a      	str	r2, [r3, #4]
    
    /* Enable ADC DMA mode */
    hadc->Instance->CR2 |= ADC_CR2_DMA;
 80027f0:	68fb      	ldr	r3, [r7, #12]
 80027f2:	681b      	ldr	r3, [r3, #0]
 80027f4:	689a      	ldr	r2, [r3, #8]
 80027f6:	68fb      	ldr	r3, [r7, #12]
 80027f8:	681b      	ldr	r3, [r3, #0]
 80027fa:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 80027fe:	609a      	str	r2, [r3, #8]
    
    /* Start the DMA channel */
    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
 8002800:	68fb      	ldr	r3, [r7, #12]
 8002802:	6c58      	ldr	r0, [r3, #68]	; 0x44
 8002804:	68fb      	ldr	r3, [r7, #12]
 8002806:	681b      	ldr	r3, [r3, #0]
 8002808:	3358      	adds	r3, #88	; 0x58
 800280a:	4619      	mov	r1, r3
 800280c:	68ba      	ldr	r2, [r7, #8]
 800280e:	687b      	ldr	r3, [r7, #4]
 8002810:	f000 fec8 	bl	80035a4 <HAL_DMA_Start_IT>
    /* If software start has been selected, conversion starts immediately.    */
    /* If external trigger has been selected, conversion will start at next   */
    /* trigger event.                                                         */
    /* Note: Alternate trigger for single conversion could be to force an     */
    /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
    if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
 8002814:	68fb      	ldr	r3, [r7, #12]
 8002816:	681b      	ldr	r3, [r3, #0]
 8002818:	689b      	ldr	r3, [r3, #8]
 800281a:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
 800281e:	2b00      	cmp	r3, #0
 8002820:	d107      	bne.n	8002832 <HAL_ADC_Start_DMA+0x106>
    {
      /* Start ADC conversion on regular group */
      SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
 8002822:	68fb      	ldr	r3, [r7, #12]
 8002824:	681b      	ldr	r3, [r3, #0]
 8002826:	689a      	ldr	r2, [r3, #8]
 8002828:	68fb      	ldr	r3, [r7, #12]
 800282a:	681b      	ldr	r3, [r3, #0]
 800282c:	f042 4280 	orr.w	r2, r2, #1073741824	; 0x40000000
 8002830:	609a      	str	r2, [r3, #8]
    }
  }
  
  /* Return function status */
  return tmp_hal_status;
 8002832:	7dfb      	ldrb	r3, [r7, #23]
}
 8002834:	4618      	mov	r0, r3
 8002836:	3718      	adds	r7, #24
 8002838:	46bd      	mov	sp, r7
 800283a:	bd80      	pop	{r7, pc}
 800283c:	08002cfb 	.word	0x08002cfb
 8002840:	08002da3 	.word	0x08002da3
 8002844:	08002dbf 	.word	0x08002dbf

08002848 <HAL_ADC_Stop_DMA>:
  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
  * @param  hadc ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
 8002848:	b580      	push	{r7, lr}
 800284a:	b084      	sub	sp, #16
 800284c:	af00      	add	r7, sp, #0
 800284e:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8002850:	2300      	movs	r3, #0
 8002852:	73fb      	strb	r3, [r7, #15]
  
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
     
  /* Process locked */
  __HAL_LOCK(hadc);
 8002854:	687b      	ldr	r3, [r7, #4]
 8002856:	f893 3048 	ldrb.w	r3, [r3, #72]	; 0x48
 800285a:	2b01      	cmp	r3, #1
 800285c:	d101      	bne.n	8002862 <HAL_ADC_Stop_DMA+0x1a>
 800285e:	2302      	movs	r3, #2
 8002860:	e03f      	b.n	80028e2 <HAL_ADC_Stop_DMA+0x9a>
 8002862:	687b      	ldr	r3, [r7, #4]
 8002864:	2201      	movs	r2, #1
 8002866:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
  
  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 800286a:	6878      	ldr	r0, [r7, #4]
 800286c:	f000 fa04 	bl	8002c78 <ADC_ConversionStop_Disable>
 8002870:	4603      	mov	r3, r0
 8002872:	73fb      	strb	r3, [r7, #15]
  
  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK)
 8002874:	7bfb      	ldrb	r3, [r7, #15]
 8002876:	2b00      	cmp	r3, #0
 8002878:	d12e      	bne.n	80028d8 <HAL_ADC_Stop_DMA+0x90>
  {
    /* Disable ADC DMA mode */
    hadc->Instance->CR2 &= ~ADC_CR2_DMA;
 800287a:	687b      	ldr	r3, [r7, #4]
 800287c:	681b      	ldr	r3, [r3, #0]
 800287e:	689a      	ldr	r2, [r3, #8]
 8002880:	687b      	ldr	r3, [r7, #4]
 8002882:	681b      	ldr	r3, [r3, #0]
 8002884:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 8002888:	609a      	str	r2, [r3, #8]
    
    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
    /* DMA transfer is on going)                                              */
    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
 800288a:	687b      	ldr	r3, [r7, #4]
 800288c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800288e:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002892:	b2db      	uxtb	r3, r3
 8002894:	2b02      	cmp	r3, #2
 8002896:	d10d      	bne.n	80028b4 <HAL_ADC_Stop_DMA+0x6c>
    {
      HAL_DMA_Abort(hadc->DMA_Handle);
 8002898:	687b      	ldr	r3, [r7, #4]
 800289a:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800289c:	4618      	mov	r0, r3
 800289e:	f000 fee1 	bl	8003664 <HAL_DMA_Abort>
      
      /* Check if DMA channel effectively disabled */
      if (tmp_hal_status != HAL_OK)
 80028a2:	7bfb      	ldrb	r3, [r7, #15]
 80028a4:	2b00      	cmp	r3, #0
 80028a6:	d005      	beq.n	80028b4 <HAL_ADC_Stop_DMA+0x6c>
      {
        /* Update ADC state machine to error */
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
 80028a8:	687b      	ldr	r3, [r7, #4]
 80028aa:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80028ac:	f043 0240 	orr.w	r2, r3, #64	; 0x40
 80028b0:	687b      	ldr	r3, [r7, #4]
 80028b2:	64da      	str	r2, [r3, #76]	; 0x4c
      }
    }
    
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 80028b4:	687b      	ldr	r3, [r7, #4]
 80028b6:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80028b8:	f423 5388 	bic.w	r3, r3, #4352	; 0x1100
 80028bc:	f023 0301 	bic.w	r3, r3, #1
 80028c0:	f043 0201 	orr.w	r2, r3, #1
 80028c4:	687b      	ldr	r3, [r7, #4]
 80028c6:	64da      	str	r2, [r3, #76]	; 0x4c
                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
                      HAL_ADC_STATE_READY);
    
    /* Disable ADC overrun interrupt */
    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
 80028c8:	687b      	ldr	r3, [r7, #4]
 80028ca:	681b      	ldr	r3, [r3, #0]
 80028cc:	685a      	ldr	r2, [r3, #4]
 80028ce:	687b      	ldr	r3, [r7, #4]
 80028d0:	681b      	ldr	r3, [r3, #0]
 80028d2:	f022 6280 	bic.w	r2, r2, #67108864	; 0x4000000
 80028d6:	605a      	str	r2, [r3, #4]
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 80028d8:	687b      	ldr	r3, [r7, #4]
 80028da:	2200      	movs	r2, #0
 80028dc:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
  
  /* Return function status */
  return tmp_hal_status;
 80028e0:	7bfb      	ldrb	r3, [r7, #15]
}
 80028e2:	4618      	mov	r0, r3
 80028e4:	3710      	adds	r7, #16
 80028e6:	46bd      	mov	sp, r7
 80028e8:	bd80      	pop	{r7, pc}

080028ea <HAL_ADC_ConvCpltCallback>:
  * @brief  Conversion complete callback in non blocking mode 
  * @param  hadc ADC handle
  * @retval None
  */
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
 80028ea:	b480      	push	{r7}
 80028ec:	b083      	sub	sp, #12
 80028ee:	af00      	add	r7, sp, #0
 80028f0:	6078      	str	r0, [r7, #4]
  UNUSED(hadc);

  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
   */
}
 80028f2:	bf00      	nop
 80028f4:	370c      	adds	r7, #12
 80028f6:	46bd      	mov	sp, r7
 80028f8:	bc80      	pop	{r7}
 80028fa:	4770      	bx	lr

080028fc <HAL_ADC_ConvHalfCpltCallback>:
  * @brief  Conversion DMA half-transfer callback in non blocking mode 
  * @param  hadc ADC handle
  * @retval None
  */
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
{
 80028fc:	b480      	push	{r7}
 80028fe:	b083      	sub	sp, #12
 8002900:	af00      	add	r7, sp, #0
 8002902:	6078      	str	r0, [r7, #4]
  UNUSED(hadc);

  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
  */
}
 8002904:	bf00      	nop
 8002906:	370c      	adds	r7, #12
 8002908:	46bd      	mov	sp, r7
 800290a:	bc80      	pop	{r7}
 800290c:	4770      	bx	lr

0800290e <HAL_ADC_ErrorCallback>:
  *           (this function is also clearing overrun flag)
  * @param  hadc ADC handle
  * @retval None
  */
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
 800290e:	b480      	push	{r7}
 8002910:	b083      	sub	sp, #12
 8002912:	af00      	add	r7, sp, #0
 8002914:	6078      	str	r0, [r7, #4]
  UNUSED(hadc);

  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ErrorCallback must be implemented in the user file.
  */
}
 8002916:	bf00      	nop
 8002918:	370c      	adds	r7, #12
 800291a:	46bd      	mov	sp, r7
 800291c:	bc80      	pop	{r7}
 800291e:	4770      	bx	lr

08002920 <HAL_ADC_ConfigChannel>:
  * @param  hadc ADC handle
  * @param  sConfig Structure of ADC channel for regular group.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
 8002920:	b480      	push	{r7}
 8002922:	b085      	sub	sp, #20
 8002924:	af00      	add	r7, sp, #0
 8002926:	6078      	str	r0, [r7, #4]
 8002928:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 800292a:	2300      	movs	r3, #0
 800292c:	73fb      	strb	r3, [r7, #15]
  __IO uint32_t wait_loop_index = 0;
 800292e:	2300      	movs	r3, #0
 8002930:	60bb      	str	r3, [r7, #8]
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 8002932:	687b      	ldr	r3, [r7, #4]
 8002934:	f893 3048 	ldrb.w	r3, [r3, #72]	; 0x48
 8002938:	2b01      	cmp	r3, #1
 800293a:	d101      	bne.n	8002940 <HAL_ADC_ConfigChannel+0x20>
 800293c:	2302      	movs	r3, #2
 800293e:	e134      	b.n	8002baa <HAL_ADC_ConfigChannel+0x28a>
 8002940:	687b      	ldr	r3, [r7, #4]
 8002942:	2201      	movs	r2, #1
 8002944:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
  
   
  /* Regular sequence configuration */
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7)
 8002948:	683b      	ldr	r3, [r7, #0]
 800294a:	685b      	ldr	r3, [r3, #4]
 800294c:	2b06      	cmp	r3, #6
 800294e:	d81c      	bhi.n	800298a <HAL_ADC_ConfigChannel+0x6a>
  {
    MODIFY_REG(hadc->Instance->SQR5,
 8002950:	687b      	ldr	r3, [r7, #4]
 8002952:	681b      	ldr	r3, [r3, #0]
 8002954:	6c19      	ldr	r1, [r3, #64]	; 0x40
 8002956:	683b      	ldr	r3, [r7, #0]
 8002958:	685a      	ldr	r2, [r3, #4]
 800295a:	4613      	mov	r3, r2
 800295c:	009b      	lsls	r3, r3, #2
 800295e:	4413      	add	r3, r2
 8002960:	3b05      	subs	r3, #5
 8002962:	221f      	movs	r2, #31
 8002964:	fa02 f303 	lsl.w	r3, r2, r3
 8002968:	43db      	mvns	r3, r3
 800296a:	4019      	ands	r1, r3
 800296c:	683b      	ldr	r3, [r7, #0]
 800296e:	6818      	ldr	r0, [r3, #0]
 8002970:	683b      	ldr	r3, [r7, #0]
 8002972:	685a      	ldr	r2, [r3, #4]
 8002974:	4613      	mov	r3, r2
 8002976:	009b      	lsls	r3, r3, #2
 8002978:	4413      	add	r3, r2
 800297a:	3b05      	subs	r3, #5
 800297c:	fa00 f203 	lsl.w	r2, r0, r3
 8002980:	687b      	ldr	r3, [r7, #4]
 8002982:	681b      	ldr	r3, [r3, #0]
 8002984:	430a      	orrs	r2, r1
 8002986:	641a      	str	r2, [r3, #64]	; 0x40
 8002988:	e07e      	b.n	8002a88 <HAL_ADC_ConfigChannel+0x168>
               ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
               ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
  }
  /* For Rank 7 to 12 */
  else if (sConfig->Rank < 13)
 800298a:	683b      	ldr	r3, [r7, #0]
 800298c:	685b      	ldr	r3, [r3, #4]
 800298e:	2b0c      	cmp	r3, #12
 8002990:	d81c      	bhi.n	80029cc <HAL_ADC_ConfigChannel+0xac>
  {
    MODIFY_REG(hadc->Instance->SQR4,
 8002992:	687b      	ldr	r3, [r7, #4]
 8002994:	681b      	ldr	r3, [r3, #0]
 8002996:	6bd9      	ldr	r1, [r3, #60]	; 0x3c
 8002998:	683b      	ldr	r3, [r7, #0]
 800299a:	685a      	ldr	r2, [r3, #4]
 800299c:	4613      	mov	r3, r2
 800299e:	009b      	lsls	r3, r3, #2
 80029a0:	4413      	add	r3, r2
 80029a2:	3b23      	subs	r3, #35	; 0x23
 80029a4:	221f      	movs	r2, #31
 80029a6:	fa02 f303 	lsl.w	r3, r2, r3
 80029aa:	43db      	mvns	r3, r3
 80029ac:	4019      	ands	r1, r3
 80029ae:	683b      	ldr	r3, [r7, #0]
 80029b0:	6818      	ldr	r0, [r3, #0]
 80029b2:	683b      	ldr	r3, [r7, #0]
 80029b4:	685a      	ldr	r2, [r3, #4]
 80029b6:	4613      	mov	r3, r2
 80029b8:	009b      	lsls	r3, r3, #2
 80029ba:	4413      	add	r3, r2
 80029bc:	3b23      	subs	r3, #35	; 0x23
 80029be:	fa00 f203 	lsl.w	r2, r0, r3
 80029c2:	687b      	ldr	r3, [r7, #4]
 80029c4:	681b      	ldr	r3, [r3, #0]
 80029c6:	430a      	orrs	r2, r1
 80029c8:	63da      	str	r2, [r3, #60]	; 0x3c
 80029ca:	e05d      	b.n	8002a88 <HAL_ADC_ConfigChannel+0x168>
               ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
               ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
  }
  /* For Rank 13 to 18 */
  else if (sConfig->Rank < 19)
 80029cc:	683b      	ldr	r3, [r7, #0]
 80029ce:	685b      	ldr	r3, [r3, #4]
 80029d0:	2b12      	cmp	r3, #18
 80029d2:	d81c      	bhi.n	8002a0e <HAL_ADC_ConfigChannel+0xee>
  {
    MODIFY_REG(hadc->Instance->SQR3,
 80029d4:	687b      	ldr	r3, [r7, #4]
 80029d6:	681b      	ldr	r3, [r3, #0]
 80029d8:	6b99      	ldr	r1, [r3, #56]	; 0x38
 80029da:	683b      	ldr	r3, [r7, #0]
 80029dc:	685a      	ldr	r2, [r3, #4]
 80029de:	4613      	mov	r3, r2
 80029e0:	009b      	lsls	r3, r3, #2
 80029e2:	4413      	add	r3, r2
 80029e4:	3b41      	subs	r3, #65	; 0x41
 80029e6:	221f      	movs	r2, #31
 80029e8:	fa02 f303 	lsl.w	r3, r2, r3
 80029ec:	43db      	mvns	r3, r3
 80029ee:	4019      	ands	r1, r3
 80029f0:	683b      	ldr	r3, [r7, #0]
 80029f2:	6818      	ldr	r0, [r3, #0]
 80029f4:	683b      	ldr	r3, [r7, #0]
 80029f6:	685a      	ldr	r2, [r3, #4]
 80029f8:	4613      	mov	r3, r2
 80029fa:	009b      	lsls	r3, r3, #2
 80029fc:	4413      	add	r3, r2
 80029fe:	3b41      	subs	r3, #65	; 0x41
 8002a00:	fa00 f203 	lsl.w	r2, r0, r3
 8002a04:	687b      	ldr	r3, [r7, #4]
 8002a06:	681b      	ldr	r3, [r3, #0]
 8002a08:	430a      	orrs	r2, r1
 8002a0a:	639a      	str	r2, [r3, #56]	; 0x38
 8002a0c:	e03c      	b.n	8002a88 <HAL_ADC_ConfigChannel+0x168>
               ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
               ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
  }
  /* For Rank 19 to 24 */
  else if (sConfig->Rank < 25)
 8002a0e:	683b      	ldr	r3, [r7, #0]
 8002a10:	685b      	ldr	r3, [r3, #4]
 8002a12:	2b18      	cmp	r3, #24
 8002a14:	d81c      	bhi.n	8002a50 <HAL_ADC_ConfigChannel+0x130>
  {
    MODIFY_REG(hadc->Instance->SQR2,
 8002a16:	687b      	ldr	r3, [r7, #4]
 8002a18:	681b      	ldr	r3, [r3, #0]
 8002a1a:	6b59      	ldr	r1, [r3, #52]	; 0x34
 8002a1c:	683b      	ldr	r3, [r7, #0]
 8002a1e:	685a      	ldr	r2, [r3, #4]
 8002a20:	4613      	mov	r3, r2
 8002a22:	009b      	lsls	r3, r3, #2
 8002a24:	4413      	add	r3, r2
 8002a26:	3b5f      	subs	r3, #95	; 0x5f
 8002a28:	221f      	movs	r2, #31
 8002a2a:	fa02 f303 	lsl.w	r3, r2, r3
 8002a2e:	43db      	mvns	r3, r3
 8002a30:	4019      	ands	r1, r3
 8002a32:	683b      	ldr	r3, [r7, #0]
 8002a34:	6818      	ldr	r0, [r3, #0]
 8002a36:	683b      	ldr	r3, [r7, #0]
 8002a38:	685a      	ldr	r2, [r3, #4]
 8002a3a:	4613      	mov	r3, r2
 8002a3c:	009b      	lsls	r3, r3, #2
 8002a3e:	4413      	add	r3, r2
 8002a40:	3b5f      	subs	r3, #95	; 0x5f
 8002a42:	fa00 f203 	lsl.w	r2, r0, r3
 8002a46:	687b      	ldr	r3, [r7, #4]
 8002a48:	681b      	ldr	r3, [r3, #0]
 8002a4a:	430a      	orrs	r2, r1
 8002a4c:	635a      	str	r2, [r3, #52]	; 0x34
 8002a4e:	e01b      	b.n	8002a88 <HAL_ADC_ConfigChannel+0x168>
               ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
  }
  /* For Rank 25 to 28 */
  else
  {
    MODIFY_REG(hadc->Instance->SQR1,
 8002a50:	687b      	ldr	r3, [r7, #4]
 8002a52:	681b      	ldr	r3, [r3, #0]
 8002a54:	6b19      	ldr	r1, [r3, #48]	; 0x30
 8002a56:	683b      	ldr	r3, [r7, #0]
 8002a58:	685a      	ldr	r2, [r3, #4]
 8002a5a:	4613      	mov	r3, r2
 8002a5c:	009b      	lsls	r3, r3, #2
 8002a5e:	4413      	add	r3, r2
 8002a60:	3b7d      	subs	r3, #125	; 0x7d
 8002a62:	221f      	movs	r2, #31
 8002a64:	fa02 f303 	lsl.w	r3, r2, r3
 8002a68:	43db      	mvns	r3, r3
 8002a6a:	4019      	ands	r1, r3
 8002a6c:	683b      	ldr	r3, [r7, #0]
 8002a6e:	6818      	ldr	r0, [r3, #0]
 8002a70:	683b      	ldr	r3, [r7, #0]
 8002a72:	685a      	ldr	r2, [r3, #4]
 8002a74:	4613      	mov	r3, r2
 8002a76:	009b      	lsls	r3, r3, #2
 8002a78:	4413      	add	r3, r2
 8002a7a:	3b7d      	subs	r3, #125	; 0x7d
 8002a7c:	fa00 f203 	lsl.w	r2, r0, r3
 8002a80:	687b      	ldr	r3, [r7, #4]
 8002a82:	681b      	ldr	r3, [r3, #0]
 8002a84:	430a      	orrs	r2, r1
 8002a86:	631a      	str	r2, [r3, #48]	; 0x30
  }
  
  
  /* Channel sampling time configuration */
  /* For channels 0 to 9 */
  if (sConfig->Channel < ADC_CHANNEL_10)
 8002a88:	683b      	ldr	r3, [r7, #0]
 8002a8a:	681b      	ldr	r3, [r3, #0]
 8002a8c:	2b09      	cmp	r3, #9
 8002a8e:	d81a      	bhi.n	8002ac6 <HAL_ADC_ConfigChannel+0x1a6>
  {
    MODIFY_REG(hadc->Instance->SMPR3,
 8002a90:	687b      	ldr	r3, [r7, #4]
 8002a92:	681b      	ldr	r3, [r3, #0]
 8002a94:	6959      	ldr	r1, [r3, #20]
 8002a96:	683b      	ldr	r3, [r7, #0]
 8002a98:	681a      	ldr	r2, [r3, #0]
 8002a9a:	4613      	mov	r3, r2
 8002a9c:	005b      	lsls	r3, r3, #1
 8002a9e:	4413      	add	r3, r2
 8002aa0:	2207      	movs	r2, #7
 8002aa2:	fa02 f303 	lsl.w	r3, r2, r3
 8002aa6:	43db      	mvns	r3, r3
 8002aa8:	4019      	ands	r1, r3
 8002aaa:	683b      	ldr	r3, [r7, #0]
 8002aac:	6898      	ldr	r0, [r3, #8]
 8002aae:	683b      	ldr	r3, [r7, #0]
 8002ab0:	681a      	ldr	r2, [r3, #0]
 8002ab2:	4613      	mov	r3, r2
 8002ab4:	005b      	lsls	r3, r3, #1
 8002ab6:	4413      	add	r3, r2
 8002ab8:	fa00 f203 	lsl.w	r2, r0, r3
 8002abc:	687b      	ldr	r3, [r7, #4]
 8002abe:	681b      	ldr	r3, [r3, #0]
 8002ac0:	430a      	orrs	r2, r1
 8002ac2:	615a      	str	r2, [r3, #20]
 8002ac4:	e042      	b.n	8002b4c <HAL_ADC_ConfigChannel+0x22c>
               ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
               ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
  }
  /* For channels 10 to 19 */
  else if (sConfig->Channel < ADC_CHANNEL_20)
 8002ac6:	683b      	ldr	r3, [r7, #0]
 8002ac8:	681b      	ldr	r3, [r3, #0]
 8002aca:	2b13      	cmp	r3, #19
 8002acc:	d81c      	bhi.n	8002b08 <HAL_ADC_ConfigChannel+0x1e8>
  {
    MODIFY_REG(hadc->Instance->SMPR2,
 8002ace:	687b      	ldr	r3, [r7, #4]
 8002ad0:	681b      	ldr	r3, [r3, #0]
 8002ad2:	6919      	ldr	r1, [r3, #16]
 8002ad4:	683b      	ldr	r3, [r7, #0]
 8002ad6:	681a      	ldr	r2, [r3, #0]
 8002ad8:	4613      	mov	r3, r2
 8002ada:	005b      	lsls	r3, r3, #1
 8002adc:	4413      	add	r3, r2
 8002ade:	3b1e      	subs	r3, #30
 8002ae0:	2207      	movs	r2, #7
 8002ae2:	fa02 f303 	lsl.w	r3, r2, r3
 8002ae6:	43db      	mvns	r3, r3
 8002ae8:	4019      	ands	r1, r3
 8002aea:	683b      	ldr	r3, [r7, #0]
 8002aec:	6898      	ldr	r0, [r3, #8]
 8002aee:	683b      	ldr	r3, [r7, #0]
 8002af0:	681a      	ldr	r2, [r3, #0]
 8002af2:	4613      	mov	r3, r2
 8002af4:	005b      	lsls	r3, r3, #1
 8002af6:	4413      	add	r3, r2
 8002af8:	3b1e      	subs	r3, #30
 8002afa:	fa00 f203 	lsl.w	r2, r0, r3
 8002afe:	687b      	ldr	r3, [r7, #4]
 8002b00:	681b      	ldr	r3, [r3, #0]
 8002b02:	430a      	orrs	r2, r1
 8002b04:	611a      	str	r2, [r3, #16]
 8002b06:	e021      	b.n	8002b4c <HAL_ADC_ConfigChannel+0x22c>
               ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
  }
  /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
  /* For channels 20 to 29 for devices Cat4, Cat.5 */
  else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
 8002b08:	683b      	ldr	r3, [r7, #0]
 8002b0a:	681b      	ldr	r3, [r3, #0]
 8002b0c:	2b1a      	cmp	r3, #26
 8002b0e:	d81c      	bhi.n	8002b4a <HAL_ADC_ConfigChannel+0x22a>
  {
    MODIFY_REG(hadc->Instance->SMPR1,
 8002b10:	687b      	ldr	r3, [r7, #4]
 8002b12:	681b      	ldr	r3, [r3, #0]
 8002b14:	68d9      	ldr	r1, [r3, #12]
 8002b16:	683b      	ldr	r3, [r7, #0]
 8002b18:	681a      	ldr	r2, [r3, #0]
 8002b1a:	4613      	mov	r3, r2
 8002b1c:	005b      	lsls	r3, r3, #1
 8002b1e:	4413      	add	r3, r2
 8002b20:	3b3c      	subs	r3, #60	; 0x3c
 8002b22:	2207      	movs	r2, #7
 8002b24:	fa02 f303 	lsl.w	r3, r2, r3
 8002b28:	43db      	mvns	r3, r3
 8002b2a:	4019      	ands	r1, r3
 8002b2c:	683b      	ldr	r3, [r7, #0]
 8002b2e:	6898      	ldr	r0, [r3, #8]
 8002b30:	683b      	ldr	r3, [r7, #0]
 8002b32:	681a      	ldr	r2, [r3, #0]
 8002b34:	4613      	mov	r3, r2
 8002b36:	005b      	lsls	r3, r3, #1
 8002b38:	4413      	add	r3, r2
 8002b3a:	3b3c      	subs	r3, #60	; 0x3c
 8002b3c:	fa00 f203 	lsl.w	r2, r0, r3
 8002b40:	687b      	ldr	r3, [r7, #4]
 8002b42:	681b      	ldr	r3, [r3, #0]
 8002b44:	430a      	orrs	r2, r1
 8002b46:	60da      	str	r2, [r3, #12]
 8002b48:	e000      	b.n	8002b4c <HAL_ADC_ConfigChannel+0x22c>
               ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
  }
  /* For channels 30 to 31 for devices Cat4, Cat.5 */
  else
  {
    ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
 8002b4a:	bf00      	nop
  }

  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  /* and VREFINT measurement path.                                            */
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8002b4c:	683b      	ldr	r3, [r7, #0]
 8002b4e:	681b      	ldr	r3, [r3, #0]
 8002b50:	2b10      	cmp	r3, #16
 8002b52:	d003      	beq.n	8002b5c <HAL_ADC_ConfigChannel+0x23c>
      (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
 8002b54:	683b      	ldr	r3, [r7, #0]
 8002b56:	681b      	ldr	r3, [r3, #0]
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8002b58:	2b11      	cmp	r3, #17
 8002b5a:	d121      	bne.n	8002ba0 <HAL_ADC_ConfigChannel+0x280>
  {
      if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET)
 8002b5c:	4b15      	ldr	r3, [pc, #84]	; (8002bb4 <HAL_ADC_ConfigChannel+0x294>)
 8002b5e:	685b      	ldr	r3, [r3, #4]
 8002b60:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
 8002b64:	2b00      	cmp	r3, #0
 8002b66:	d11b      	bne.n	8002ba0 <HAL_ADC_ConfigChannel+0x280>
      {
        SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
 8002b68:	4b12      	ldr	r3, [pc, #72]	; (8002bb4 <HAL_ADC_ConfigChannel+0x294>)
 8002b6a:	685b      	ldr	r3, [r3, #4]
 8002b6c:	4a11      	ldr	r2, [pc, #68]	; (8002bb4 <HAL_ADC_ConfigChannel+0x294>)
 8002b6e:	f443 0300 	orr.w	r3, r3, #8388608	; 0x800000
 8002b72:	6053      	str	r3, [r2, #4]
        
        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
 8002b74:	683b      	ldr	r3, [r7, #0]
 8002b76:	681b      	ldr	r3, [r3, #0]
 8002b78:	2b10      	cmp	r3, #16
 8002b7a:	d111      	bne.n	8002ba0 <HAL_ADC_ConfigChannel+0x280>
        {
          /* Delay for temperature sensor stabilization time */
          /* Compute number of CPU cycles to wait for */
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
 8002b7c:	4b0e      	ldr	r3, [pc, #56]	; (8002bb8 <HAL_ADC_ConfigChannel+0x298>)
 8002b7e:	681b      	ldr	r3, [r3, #0]
 8002b80:	4a0e      	ldr	r2, [pc, #56]	; (8002bbc <HAL_ADC_ConfigChannel+0x29c>)
 8002b82:	fba2 2303 	umull	r2, r3, r2, r3
 8002b86:	0c9a      	lsrs	r2, r3, #18
 8002b88:	4613      	mov	r3, r2
 8002b8a:	009b      	lsls	r3, r3, #2
 8002b8c:	4413      	add	r3, r2
 8002b8e:	005b      	lsls	r3, r3, #1
 8002b90:	60bb      	str	r3, [r7, #8]
          while(wait_loop_index != 0)
 8002b92:	e002      	b.n	8002b9a <HAL_ADC_ConfigChannel+0x27a>
          {
            wait_loop_index--;
 8002b94:	68bb      	ldr	r3, [r7, #8]
 8002b96:	3b01      	subs	r3, #1
 8002b98:	60bb      	str	r3, [r7, #8]
          while(wait_loop_index != 0)
 8002b9a:	68bb      	ldr	r3, [r7, #8]
 8002b9c:	2b00      	cmp	r3, #0
 8002b9e:	d1f9      	bne.n	8002b94 <HAL_ADC_ConfigChannel+0x274>
        }
    }
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8002ba0:	687b      	ldr	r3, [r7, #4]
 8002ba2:	2200      	movs	r2, #0
 8002ba4:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
  
  /* Return function status */
  return tmp_hal_status;
 8002ba8:	7bfb      	ldrb	r3, [r7, #15]
}
 8002baa:	4618      	mov	r0, r3
 8002bac:	3714      	adds	r7, #20
 8002bae:	46bd      	mov	sp, r7
 8002bb0:	bc80      	pop	{r7}
 8002bb2:	4770      	bx	lr
 8002bb4:	40012700 	.word	0x40012700
 8002bb8:	20000000 	.word	0x20000000
 8002bbc:	431bde83 	.word	0x431bde83

08002bc0 <ADC_Enable>:
  *         "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
  * @param  hadc ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
 8002bc0:	b580      	push	{r7, lr}
 8002bc2:	b084      	sub	sp, #16
 8002bc4:	af00      	add	r7, sp, #0
 8002bc6:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0;
 8002bc8:	2300      	movs	r3, #0
 8002bca:	60fb      	str	r3, [r7, #12]
  __IO uint32_t wait_loop_index = 0;
 8002bcc:	2300      	movs	r3, #0
 8002bce:	60bb      	str	r3, [r7, #8]
  
  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
  /* enabling phase not yet completed: flag ADC ready not yet set).           */
  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
  /* causes: ADC clock not running, ...).                                     */
  if (ADC_IS_ENABLE(hadc) == RESET)
 8002bd0:	687b      	ldr	r3, [r7, #4]
 8002bd2:	681b      	ldr	r3, [r3, #0]
 8002bd4:	681b      	ldr	r3, [r3, #0]
 8002bd6:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002bda:	2b40      	cmp	r3, #64	; 0x40
 8002bdc:	d043      	beq.n	8002c66 <ADC_Enable+0xa6>
  {
    /* Enable the Peripheral */
    __HAL_ADC_ENABLE(hadc);
 8002bde:	687b      	ldr	r3, [r7, #4]
 8002be0:	681b      	ldr	r3, [r3, #0]
 8002be2:	689a      	ldr	r2, [r3, #8]
 8002be4:	687b      	ldr	r3, [r7, #4]
 8002be6:	681b      	ldr	r3, [r3, #0]
 8002be8:	f042 0201 	orr.w	r2, r2, #1
 8002bec:	609a      	str	r2, [r3, #8]
    
    /* Delay for ADC stabilization time */
    /* Compute number of CPU cycles to wait for */
    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
 8002bee:	4b20      	ldr	r3, [pc, #128]	; (8002c70 <ADC_Enable+0xb0>)
 8002bf0:	681b      	ldr	r3, [r3, #0]
 8002bf2:	4a20      	ldr	r2, [pc, #128]	; (8002c74 <ADC_Enable+0xb4>)
 8002bf4:	fba2 2303 	umull	r2, r3, r2, r3
 8002bf8:	0c9a      	lsrs	r2, r3, #18
 8002bfa:	4613      	mov	r3, r2
 8002bfc:	005b      	lsls	r3, r3, #1
 8002bfe:	4413      	add	r3, r2
 8002c00:	60bb      	str	r3, [r7, #8]
    while(wait_loop_index != 0)
 8002c02:	e002      	b.n	8002c0a <ADC_Enable+0x4a>
    {
      wait_loop_index--;
 8002c04:	68bb      	ldr	r3, [r7, #8]
 8002c06:	3b01      	subs	r3, #1
 8002c08:	60bb      	str	r3, [r7, #8]
    while(wait_loop_index != 0)
 8002c0a:	68bb      	ldr	r3, [r7, #8]
 8002c0c:	2b00      	cmp	r3, #0
 8002c0e:	d1f9      	bne.n	8002c04 <ADC_Enable+0x44>
    }
    
    /* Get tick count */
    tickstart = HAL_GetTick();    
 8002c10:	f7ff fc1a 	bl	8002448 <HAL_GetTick>
 8002c14:	60f8      	str	r0, [r7, #12]

    /* Wait for ADC effectively enabled */
    while(ADC_IS_ENABLE(hadc) == RESET)
 8002c16:	e01f      	b.n	8002c58 <ADC_Enable+0x98>
    {
      if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
 8002c18:	f7ff fc16 	bl	8002448 <HAL_GetTick>
 8002c1c:	4602      	mov	r2, r0
 8002c1e:	68fb      	ldr	r3, [r7, #12]
 8002c20:	1ad3      	subs	r3, r2, r3
 8002c22:	2b02      	cmp	r3, #2
 8002c24:	d918      	bls.n	8002c58 <ADC_Enable+0x98>
      {
        /* New check to avoid false timeout detection in case of preemption */
        if(ADC_IS_ENABLE(hadc) == RESET)
 8002c26:	687b      	ldr	r3, [r7, #4]
 8002c28:	681b      	ldr	r3, [r3, #0]
 8002c2a:	681b      	ldr	r3, [r3, #0]
 8002c2c:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002c30:	2b40      	cmp	r3, #64	; 0x40
 8002c32:	d011      	beq.n	8002c58 <ADC_Enable+0x98>
        {
          /* Update ADC state machine to error */
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8002c34:	687b      	ldr	r3, [r7, #4]
 8002c36:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002c38:	f043 0210 	orr.w	r2, r3, #16
 8002c3c:	687b      	ldr	r3, [r7, #4]
 8002c3e:	64da      	str	r2, [r3, #76]	; 0x4c

          /* Set ADC error code to ADC IP internal error */
          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8002c40:	687b      	ldr	r3, [r7, #4]
 8002c42:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8002c44:	f043 0201 	orr.w	r2, r3, #1
 8002c48:	687b      	ldr	r3, [r7, #4]
 8002c4a:	651a      	str	r2, [r3, #80]	; 0x50

          /* Process unlocked */
          __HAL_UNLOCK(hadc);
 8002c4c:	687b      	ldr	r3, [r7, #4]
 8002c4e:	2200      	movs	r2, #0
 8002c50:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48

          return HAL_ERROR;
 8002c54:	2301      	movs	r3, #1
 8002c56:	e007      	b.n	8002c68 <ADC_Enable+0xa8>
    while(ADC_IS_ENABLE(hadc) == RESET)
 8002c58:	687b      	ldr	r3, [r7, #4]
 8002c5a:	681b      	ldr	r3, [r3, #0]
 8002c5c:	681b      	ldr	r3, [r3, #0]
 8002c5e:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002c62:	2b40      	cmp	r3, #64	; 0x40
 8002c64:	d1d8      	bne.n	8002c18 <ADC_Enable+0x58>
      }
    }
  }
   
  /* Return HAL status */
  return HAL_OK;
 8002c66:	2300      	movs	r3, #0
}
 8002c68:	4618      	mov	r0, r3
 8002c6a:	3710      	adds	r7, #16
 8002c6c:	46bd      	mov	sp, r7
 8002c6e:	bd80      	pop	{r7, pc}
 8002c70:	20000000 	.word	0x20000000
 8002c74:	431bde83 	.word	0x431bde83

08002c78 <ADC_ConversionStop_Disable>:
  *         stopped to disable the ADC.
  * @param  hadc ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
 8002c78:	b580      	push	{r7, lr}
 8002c7a:	b084      	sub	sp, #16
 8002c7c:	af00      	add	r7, sp, #0
 8002c7e:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0;
 8002c80:	2300      	movs	r3, #0
 8002c82:	60fb      	str	r3, [r7, #12]
  
  /* Verification if ADC is not already disabled */
  if (ADC_IS_ENABLE(hadc) != RESET)
 8002c84:	687b      	ldr	r3, [r7, #4]
 8002c86:	681b      	ldr	r3, [r3, #0]
 8002c88:	681b      	ldr	r3, [r3, #0]
 8002c8a:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002c8e:	2b40      	cmp	r3, #64	; 0x40
 8002c90:	d12e      	bne.n	8002cf0 <ADC_ConversionStop_Disable+0x78>
  {
    /* Disable the ADC peripheral */
    __HAL_ADC_DISABLE(hadc);
 8002c92:	687b      	ldr	r3, [r7, #4]
 8002c94:	681b      	ldr	r3, [r3, #0]
 8002c96:	689a      	ldr	r2, [r3, #8]
 8002c98:	687b      	ldr	r3, [r7, #4]
 8002c9a:	681b      	ldr	r3, [r3, #0]
 8002c9c:	f022 0201 	bic.w	r2, r2, #1
 8002ca0:	609a      	str	r2, [r3, #8]
     
    /* Get tick count */
    tickstart = HAL_GetTick();
 8002ca2:	f7ff fbd1 	bl	8002448 <HAL_GetTick>
 8002ca6:	60f8      	str	r0, [r7, #12]
    
    /* Wait for ADC effectively disabled */    
    while(ADC_IS_ENABLE(hadc) != RESET)
 8002ca8:	e01b      	b.n	8002ce2 <ADC_ConversionStop_Disable+0x6a>
    {
      if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
 8002caa:	f7ff fbcd 	bl	8002448 <HAL_GetTick>
 8002cae:	4602      	mov	r2, r0
 8002cb0:	68fb      	ldr	r3, [r7, #12]
 8002cb2:	1ad3      	subs	r3, r2, r3
 8002cb4:	2b02      	cmp	r3, #2
 8002cb6:	d914      	bls.n	8002ce2 <ADC_ConversionStop_Disable+0x6a>
      {
        /* New check to avoid false timeout detection in case of preemption */
        if(ADC_IS_ENABLE(hadc) != RESET)
 8002cb8:	687b      	ldr	r3, [r7, #4]
 8002cba:	681b      	ldr	r3, [r3, #0]
 8002cbc:	681b      	ldr	r3, [r3, #0]
 8002cbe:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002cc2:	2b40      	cmp	r3, #64	; 0x40
 8002cc4:	d10d      	bne.n	8002ce2 <ADC_ConversionStop_Disable+0x6a>
        {
          /* Update ADC state machine to error */
          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8002cc6:	687b      	ldr	r3, [r7, #4]
 8002cc8:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002cca:	f043 0210 	orr.w	r2, r3, #16
 8002cce:	687b      	ldr	r3, [r7, #4]
 8002cd0:	64da      	str	r2, [r3, #76]	; 0x4c

          /* Set ADC error code to ADC IP internal error */
          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8002cd2:	687b      	ldr	r3, [r7, #4]
 8002cd4:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8002cd6:	f043 0201 	orr.w	r2, r3, #1
 8002cda:	687b      	ldr	r3, [r7, #4]
 8002cdc:	651a      	str	r2, [r3, #80]	; 0x50

          return HAL_ERROR;
 8002cde:	2301      	movs	r3, #1
 8002ce0:	e007      	b.n	8002cf2 <ADC_ConversionStop_Disable+0x7a>
    while(ADC_IS_ENABLE(hadc) != RESET)
 8002ce2:	687b      	ldr	r3, [r7, #4]
 8002ce4:	681b      	ldr	r3, [r3, #0]
 8002ce6:	681b      	ldr	r3, [r3, #0]
 8002ce8:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002cec:	2b40      	cmp	r3, #64	; 0x40
 8002cee:	d0dc      	beq.n	8002caa <ADC_ConversionStop_Disable+0x32>
      }
    }
  }
  
  /* Return HAL status */
  return HAL_OK;
 8002cf0:	2300      	movs	r3, #0
}
 8002cf2:	4618      	mov	r0, r3
 8002cf4:	3710      	adds	r7, #16
 8002cf6:	46bd      	mov	sp, r7
 8002cf8:	bd80      	pop	{r7, pc}

08002cfa <ADC_DMAConvCplt>:
  * @brief  DMA transfer complete callback. 
  * @param  hdma pointer to DMA handle.
  * @retval None
  */
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
 8002cfa:	b580      	push	{r7, lr}
 8002cfc:	b084      	sub	sp, #16
 8002cfe:	af00      	add	r7, sp, #0
 8002d00:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8002d02:	687b      	ldr	r3, [r7, #4]
 8002d04:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8002d06:	60fb      	str	r3, [r7, #12]
  
  /* Update state machine on conversion status if not in error state */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
 8002d08:	68fb      	ldr	r3, [r7, #12]
 8002d0a:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002d0c:	f003 0350 	and.w	r3, r3, #80	; 0x50
 8002d10:	2b00      	cmp	r3, #0
 8002d12:	d13d      	bne.n	8002d90 <ADC_DMAConvCplt+0x96>
  {
    /* Update ADC state machine */
    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
 8002d14:	68fb      	ldr	r3, [r7, #12]
 8002d16:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002d18:	f443 7200 	orr.w	r2, r3, #512	; 0x200
 8002d1c:	68fb      	ldr	r3, [r7, #12]
 8002d1e:	64da      	str	r2, [r3, #76]	; 0x4c
    /* by external trigger, continuous mode or scan sequence on going.      */
    /* Note: On STM32L1, there is no independent flag of end of sequence.   */
    /*       The test of scan sequence on going is done either with scan    */
    /*       sequence disabled or with end of conversion flag set to        */
    /*       of end of sequence.                                            */
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
 8002d20:	68fb      	ldr	r3, [r7, #12]
 8002d22:	681b      	ldr	r3, [r3, #0]
 8002d24:	689b      	ldr	r3, [r3, #8]
 8002d26:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
 8002d2a:	2b00      	cmp	r3, #0
 8002d2c:	d12c      	bne.n	8002d88 <ADC_DMAConvCplt+0x8e>
       (hadc->Init.ContinuousConvMode == DISABLE)            &&
 8002d2e:	68fb      	ldr	r3, [r7, #12]
 8002d30:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
 8002d34:	2b00      	cmp	r3, #0
 8002d36:	d127      	bne.n	8002d88 <ADC_DMAConvCplt+0x8e>
       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
 8002d38:	68fb      	ldr	r3, [r7, #12]
 8002d3a:	681b      	ldr	r3, [r3, #0]
 8002d3c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8002d3e:	f003 73f8 	and.w	r3, r3, #32505856	; 0x1f00000
       (hadc->Init.ContinuousConvMode == DISABLE)            &&
 8002d42:	2b00      	cmp	r3, #0
 8002d44:	d006      	beq.n	8002d54 <ADC_DMAConvCplt+0x5a>
        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
 8002d46:	68fb      	ldr	r3, [r7, #12]
 8002d48:	681b      	ldr	r3, [r3, #0]
 8002d4a:	689b      	ldr	r3, [r3, #8]
 8002d4c:	f403 6380 	and.w	r3, r3, #1024	; 0x400
       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
 8002d50:	2b00      	cmp	r3, #0
 8002d52:	d119      	bne.n	8002d88 <ADC_DMAConvCplt+0x8e>
    {
      /* Disable ADC end of single conversion interrupt on group regular */
      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
      /* by overrun IRQ process below.                                      */
      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
 8002d54:	68fb      	ldr	r3, [r7, #12]
 8002d56:	681b      	ldr	r3, [r3, #0]
 8002d58:	685a      	ldr	r2, [r3, #4]
 8002d5a:	68fb      	ldr	r3, [r7, #12]
 8002d5c:	681b      	ldr	r3, [r3, #0]
 8002d5e:	f022 0220 	bic.w	r2, r2, #32
 8002d62:	605a      	str	r2, [r3, #4]
      
      /* Set ADC state */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
 8002d64:	68fb      	ldr	r3, [r7, #12]
 8002d66:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002d68:	f423 7280 	bic.w	r2, r3, #256	; 0x100
 8002d6c:	68fb      	ldr	r3, [r7, #12]
 8002d6e:	64da      	str	r2, [r3, #76]	; 0x4c
      
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 8002d70:	68fb      	ldr	r3, [r7, #12]
 8002d72:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002d74:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 8002d78:	2b00      	cmp	r3, #0
 8002d7a:	d105      	bne.n	8002d88 <ADC_DMAConvCplt+0x8e>
      {
        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8002d7c:	68fb      	ldr	r3, [r7, #12]
 8002d7e:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002d80:	f043 0201 	orr.w	r2, r3, #1
 8002d84:	68fb      	ldr	r3, [r7, #12]
 8002d86:	64da      	str	r2, [r3, #76]	; 0x4c
    
    /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
    hadc->ConvCpltCallback(hadc);
#else
    HAL_ADC_ConvCpltCallback(hadc);
 8002d88:	68f8      	ldr	r0, [r7, #12]
 8002d8a:	f7ff fdae 	bl	80028ea <HAL_ADC_ConvCpltCallback>
  else
  {
    /* Call DMA error callback */
    hadc->DMA_Handle->XferErrorCallback(hdma);
  }
}
 8002d8e:	e004      	b.n	8002d9a <ADC_DMAConvCplt+0xa0>
    hadc->DMA_Handle->XferErrorCallback(hdma);
 8002d90:	68fb      	ldr	r3, [r7, #12]
 8002d92:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8002d94:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8002d96:	6878      	ldr	r0, [r7, #4]
 8002d98:	4798      	blx	r3
}
 8002d9a:	bf00      	nop
 8002d9c:	3710      	adds	r7, #16
 8002d9e:	46bd      	mov	sp, r7
 8002da0:	bd80      	pop	{r7, pc}

08002da2 <ADC_DMAHalfConvCplt>:
  * @brief  DMA half transfer complete callback. 
  * @param  hdma pointer to DMA handle.
  * @retval None
  */
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
{
 8002da2:	b580      	push	{r7, lr}
 8002da4:	b084      	sub	sp, #16
 8002da6:	af00      	add	r7, sp, #0
 8002da8:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8002daa:	687b      	ldr	r3, [r7, #4]
 8002dac:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8002dae:	60fb      	str	r3, [r7, #12]
  
  /* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
    hadc->ConvHalfCpltCallback(hadc);
#else
  HAL_ADC_ConvHalfCpltCallback(hadc);
 8002db0:	68f8      	ldr	r0, [r7, #12]
 8002db2:	f7ff fda3 	bl	80028fc <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 8002db6:	bf00      	nop
 8002db8:	3710      	adds	r7, #16
 8002dba:	46bd      	mov	sp, r7
 8002dbc:	bd80      	pop	{r7, pc}

08002dbe <ADC_DMAError>:
  * @brief  DMA error callback 
  * @param  hdma pointer to DMA handle.
  * @retval None
  */
static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
{
 8002dbe:	b580      	push	{r7, lr}
 8002dc0:	b084      	sub	sp, #16
 8002dc2:	af00      	add	r7, sp, #0
 8002dc4:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8002dc6:	687b      	ldr	r3, [r7, #4]
 8002dc8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8002dca:	60fb      	str	r3, [r7, #12]
  
  /* Set ADC state */
  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
 8002dcc:	68fb      	ldr	r3, [r7, #12]
 8002dce:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8002dd0:	f043 0240 	orr.w	r2, r3, #64	; 0x40
 8002dd4:	68fb      	ldr	r3, [r7, #12]
 8002dd6:	64da      	str	r2, [r3, #76]	; 0x4c
  
  /* Set ADC error code to DMA error */
  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
 8002dd8:	68fb      	ldr	r3, [r7, #12]
 8002dda:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8002ddc:	f043 0204 	orr.w	r2, r3, #4
 8002de0:	68fb      	ldr	r3, [r7, #12]
 8002de2:	651a      	str	r2, [r3, #80]	; 0x50
  
  /* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  hadc->ErrorCallback(hadc);
#else
  HAL_ADC_ErrorCallback(hadc);
 8002de4:	68f8      	ldr	r0, [r7, #12]
 8002de6:	f7ff fd92 	bl	800290e <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 8002dea:	bf00      	nop
 8002dec:	3710      	adds	r7, #16
 8002dee:	46bd      	mov	sp, r7
 8002df0:	bd80      	pop	{r7, pc}
	...

08002df4 <HAL_COMP_Init>:
  *         To unlock the configuration, perform a system reset.
  * @param  hcomp COMP handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{ 
 8002df4:	b580      	push	{r7, lr}
 8002df6:	b084      	sub	sp, #16
 8002df8:	af00      	add	r7, sp, #0
 8002dfa:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8002dfc:	2300      	movs	r3, #0
 8002dfe:	73fb      	strb	r3, [r7, #15]
  
  /* Check the COMP handle allocation and lock status */
  if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
 8002e00:	687b      	ldr	r3, [r7, #4]
 8002e02:	2b00      	cmp	r3, #0
 8002e04:	d007      	beq.n	8002e16 <HAL_COMP_Init+0x22>
 8002e06:	687b      	ldr	r3, [r7, #4]
 8002e08:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002e0c:	b2db      	uxtb	r3, r3
 8002e0e:	f003 0310 	and.w	r3, r3, #16
 8002e12:	2b00      	cmp	r3, #0
 8002e14:	d002      	beq.n	8002e1c <HAL_COMP_Init+0x28>
  {
    status = HAL_ERROR;
 8002e16:	2301      	movs	r3, #1
 8002e18:	73fb      	strb	r3, [r7, #15]
 8002e1a:	e09e      	b.n	8002f5a <HAL_COMP_Init+0x166>
    }
  
    /* In window mode, non-inverting inputs of the 2 comparators are          */
    /* connected together and are using inputs of COMP2 only. If COMP1 is     */
    /* selected, this parameter is discarded.                                 */
    if ((hcomp->Init.WindowMode == COMP_WINDOWMODE_DISABLE) ||
 8002e1c:	687b      	ldr	r3, [r7, #4]
 8002e1e:	695b      	ldr	r3, [r3, #20]
 8002e20:	2b00      	cmp	r3, #0
      assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
    }
    
      
    /* Enable SYSCFG clock and the low level hardware to access comparators */
    if(hcomp->State == HAL_COMP_STATE_RESET)
 8002e22:	687b      	ldr	r3, [r7, #4]
 8002e24:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002e28:	b2db      	uxtb	r3, r3
 8002e2a:	2b00      	cmp	r3, #0
 8002e2c:	d112      	bne.n	8002e54 <HAL_COMP_Init+0x60>
    {
      /* Allocate lock resource and initialize it */
      hcomp->Lock = HAL_UNLOCKED;
 8002e2e:	687b      	ldr	r3, [r7, #4]
 8002e30:	2200      	movs	r2, #0
 8002e32:	f883 2020 	strb.w	r2, [r3, #32]

      /* Enable SYSCFG clock to control the routing Interface (RI) */
      __HAL_RCC_SYSCFG_CLK_ENABLE();
 8002e36:	4b4b      	ldr	r3, [pc, #300]	; (8002f64 <HAL_COMP_Init+0x170>)
 8002e38:	6a1b      	ldr	r3, [r3, #32]
 8002e3a:	4a4a      	ldr	r2, [pc, #296]	; (8002f64 <HAL_COMP_Init+0x170>)
 8002e3c:	f043 0301 	orr.w	r3, r3, #1
 8002e40:	6213      	str	r3, [r2, #32]
 8002e42:	4b48      	ldr	r3, [pc, #288]	; (8002f64 <HAL_COMP_Init+0x170>)
 8002e44:	6a1b      	ldr	r3, [r3, #32]
 8002e46:	f003 0301 	and.w	r3, r3, #1
 8002e4a:	60bb      	str	r3, [r7, #8]
 8002e4c:	68bb      	ldr	r3, [r7, #8]
      
      /* Init the low level hardware */
      hcomp->MspInitCallback(hcomp);
#else
      /* Init the low level hardware */
      HAL_COMP_MspInit(hcomp);
 8002e4e:	6878      	ldr	r0, [r7, #4]
 8002e50:	f7fe ff22 	bl	8001c98 <HAL_COMP_MspInit>
    /*  - Window mode                                                         */
    /*  - Mode fast/slow speed                                                */
    /*  - Inverting input pull-up/down resistors                              */
    
    /* Configuration depending on comparator instance */
    if (hcomp->Instance == COMP1)
 8002e54:	687b      	ldr	r3, [r7, #4]
 8002e56:	681b      	ldr	r3, [r3, #0]
 8002e58:	4a43      	ldr	r2, [pc, #268]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002e5a:	4293      	cmp	r3, r2
 8002e5c:	d109      	bne.n	8002e72 <HAL_COMP_Init+0x7e>
    {
      MODIFY_REG(COMP->CSR, COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU,
 8002e5e:	4b42      	ldr	r3, [pc, #264]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002e60:	681b      	ldr	r3, [r3, #0]
 8002e62:	f023 020f 	bic.w	r2, r3, #15
 8002e66:	687b      	ldr	r3, [r7, #4]
 8002e68:	69db      	ldr	r3, [r3, #28]
 8002e6a:	493f      	ldr	r1, [pc, #252]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002e6c:	4313      	orrs	r3, r2
 8002e6e:	600b      	str	r3, [r1, #0]
 8002e70:	e03f      	b.n	8002ef2 <HAL_COMP_Init+0xfe>
      /*       "hcomp->Init.InvertingInput") is configured into function      */
      /*       "HAL_COMP_Start()" since inverting  input selection also       */
      /*       enables the comparator 2.                                      */
      /*       If comparator 2 is already enabled, inverting input is         */
      /*       reconfigured on the fly.                                       */
      if (__COMP_IS_ENABLED(hcomp) == RESET)
 8002e72:	687b      	ldr	r3, [r7, #4]
 8002e74:	681b      	ldr	r3, [r3, #0]
 8002e76:	4a3c      	ldr	r2, [pc, #240]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002e78:	4293      	cmp	r3, r2
 8002e7a:	d109      	bne.n	8002e90 <HAL_COMP_Init+0x9c>
 8002e7c:	4b3a      	ldr	r3, [pc, #232]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002e7e:	681b      	ldr	r3, [r3, #0]
 8002e80:	f003 0310 	and.w	r3, r3, #16
 8002e84:	2b10      	cmp	r3, #16
 8002e86:	bf14      	ite	ne
 8002e88:	2301      	movne	r3, #1
 8002e8a:	2300      	moveq	r3, #0
 8002e8c:	b2db      	uxtb	r3, r3
 8002e8e:	e008      	b.n	8002ea2 <HAL_COMP_Init+0xae>
 8002e90:	4b35      	ldr	r3, [pc, #212]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002e92:	681b      	ldr	r3, [r3, #0]
 8002e94:	f403 13e0 	and.w	r3, r3, #1835008	; 0x1c0000
 8002e98:	2b00      	cmp	r3, #0
 8002e9a:	bf0c      	ite	eq
 8002e9c:	2301      	moveq	r3, #1
 8002e9e:	2300      	movne	r3, #0
 8002ea0:	b2db      	uxtb	r3, r3
 8002ea2:	2b00      	cmp	r3, #0
 8002ea4:	d011      	beq.n	8002eca <HAL_COMP_Init+0xd6>
      {
        MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL  |
 8002ea6:	4b30      	ldr	r3, [pc, #192]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002ea8:	681b      	ldr	r3, [r3, #0]
 8002eaa:	f423 0362 	bic.w	r3, r3, #14811136	; 0xe20000
 8002eae:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 8002eb2:	687a      	ldr	r2, [r7, #4]
 8002eb4:	68d1      	ldr	r1, [r2, #12]
 8002eb6:	687a      	ldr	r2, [r7, #4]
 8002eb8:	6952      	ldr	r2, [r2, #20]
 8002eba:	4311      	orrs	r1, r2
 8002ebc:	687a      	ldr	r2, [r7, #4]
 8002ebe:	6912      	ldr	r2, [r2, #16]
 8002ec0:	430a      	orrs	r2, r1
 8002ec2:	4929      	ldr	r1, [pc, #164]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002ec4:	4313      	orrs	r3, r2
 8002ec6:	600b      	str	r3, [r1, #0]
 8002ec8:	e013      	b.n	8002ef2 <HAL_COMP_Init+0xfe>
                              hcomp->Init.WindowMode |
                              hcomp->Init.Mode        );
      }
      else
      {
        MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL  |
 8002eca:	4b27      	ldr	r3, [pc, #156]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002ecc:	681b      	ldr	r3, [r3, #0]
 8002ece:	f423 037e 	bic.w	r3, r3, #16646144	; 0xfe0000
 8002ed2:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 8002ed6:	687a      	ldr	r2, [r7, #4]
 8002ed8:	68d1      	ldr	r1, [r2, #12]
 8002eda:	687a      	ldr	r2, [r7, #4]
 8002edc:	6852      	ldr	r2, [r2, #4]
 8002ede:	4311      	orrs	r1, r2
 8002ee0:	687a      	ldr	r2, [r7, #4]
 8002ee2:	6952      	ldr	r2, [r2, #20]
 8002ee4:	4311      	orrs	r1, r2
 8002ee6:	687a      	ldr	r2, [r7, #4]
 8002ee8:	6912      	ldr	r2, [r2, #16]
 8002eea:	430a      	orrs	r2, r1
 8002eec:	491e      	ldr	r1, [pc, #120]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002eee:	4313      	orrs	r3, r2
 8002ef0:	600b      	str	r3, [r1, #0]
      }
    }
    else
#endif
    {
      if (__COMP_ROUTING_INTERFACE_TOBECONFIGURED(hcomp))
 8002ef2:	687b      	ldr	r3, [r7, #4]
 8002ef4:	689b      	ldr	r3, [r3, #8]
 8002ef6:	2b00      	cmp	r3, #0
 8002ef8:	d025      	beq.n	8002f46 <HAL_COMP_Init+0x152>
      {
        if (hcomp->Instance == COMP1)
 8002efa:	687b      	ldr	r3, [r7, #4]
 8002efc:	681b      	ldr	r3, [r3, #0]
 8002efe:	4a1a      	ldr	r2, [pc, #104]	; (8002f68 <HAL_COMP_Init+0x174>)
 8002f00:	4293      	cmp	r3, r2
 8002f02:	d10b      	bne.n	8002f1c <HAL_COMP_Init+0x128>
        {
          /* Enable the switch control mode */
          __HAL_RI_SWITCHCONTROLMODE_ENABLE();
 8002f04:	4b19      	ldr	r3, [pc, #100]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f06:	685b      	ldr	r3, [r3, #4]
 8002f08:	4a18      	ldr	r2, [pc, #96]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f0a:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 8002f0e:	6053      	str	r3, [r2, #4]

          /* Close the analog switch of ADC switch matrix to COMP1 (ADC         */
          /* channel 26: Vcomp)                                                 */
          __HAL_RI_IOSWITCH_CLOSE(RI_IOSWITCH_VCOMP);
 8002f10:	4b16      	ldr	r3, [pc, #88]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f12:	685b      	ldr	r3, [r3, #4]
 8002f14:	4a15      	ldr	r2, [pc, #84]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f16:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
 8002f1a:	6053      	str	r3, [r2, #4]
        }

        /* Close the I/O analog switch corresponding to comparator              */
        /* non-inverting input selected.                                        */
        __HAL_RI_IOSWITCH_CLOSE(hcomp->Init.NonInvertingInput);
 8002f1c:	687b      	ldr	r3, [r7, #4]
 8002f1e:	689b      	ldr	r3, [r3, #8]
 8002f20:	2b00      	cmp	r3, #0
 8002f22:	da09      	bge.n	8002f38 <HAL_COMP_Init+0x144>
 8002f24:	4b11      	ldr	r3, [pc, #68]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f26:	685a      	ldr	r2, [r3, #4]
 8002f28:	687b      	ldr	r3, [r7, #4]
 8002f2a:	689b      	ldr	r3, [r3, #8]
 8002f2c:	f023 4300 	bic.w	r3, r3, #2147483648	; 0x80000000
 8002f30:	490e      	ldr	r1, [pc, #56]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f32:	4313      	orrs	r3, r2
 8002f34:	604b      	str	r3, [r1, #4]
 8002f36:	e006      	b.n	8002f46 <HAL_COMP_Init+0x152>
 8002f38:	4b0c      	ldr	r3, [pc, #48]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f3a:	689a      	ldr	r2, [r3, #8]
 8002f3c:	687b      	ldr	r3, [r7, #4]
 8002f3e:	689b      	ldr	r3, [r3, #8]
 8002f40:	490a      	ldr	r1, [pc, #40]	; (8002f6c <HAL_COMP_Init+0x178>)
 8002f42:	4313      	orrs	r3, r2
 8002f44:	608b      	str	r3, [r1, #8]
      }
    }

    
    /* Initialize the COMP state*/
    if(hcomp->State == HAL_COMP_STATE_RESET)
 8002f46:	687b      	ldr	r3, [r7, #4]
 8002f48:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002f4c:	b2db      	uxtb	r3, r3
 8002f4e:	2b00      	cmp	r3, #0
 8002f50:	d103      	bne.n	8002f5a <HAL_COMP_Init+0x166>
    {
      hcomp->State = HAL_COMP_STATE_READY;
 8002f52:	687b      	ldr	r3, [r7, #4]
 8002f54:	2201      	movs	r2, #1
 8002f56:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
    }
  }
  
  return status;
 8002f5a:	7bfb      	ldrb	r3, [r7, #15]
}
 8002f5c:	4618      	mov	r0, r3
 8002f5e:	3710      	adds	r7, #16
 8002f60:	46bd      	mov	sp, r7
 8002f62:	bd80      	pop	{r7, pc}
 8002f64:	40023800 	.word	0x40023800
 8002f68:	40007c00 	.word	0x40007c00
 8002f6c:	40007c04 	.word	0x40007c04

08002f70 <HAL_COMP_Start>:
  * @brief  Start the comparator 
  * @param  hcomp COMP handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{ 
 8002f70:	b480      	push	{r7}
 8002f72:	b087      	sub	sp, #28
 8002f74:	af00      	add	r7, sp, #0
 8002f76:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 8002f78:	2300      	movs	r3, #0
 8002f7a:	75fb      	strb	r3, [r7, #23]
  uint32_t wait_loop_cycles = 0;
 8002f7c:	2300      	movs	r3, #0
 8002f7e:	613b      	str	r3, [r7, #16]
  __IO uint32_t wait_loop_index = 0;
 8002f80:	2300      	movs	r3, #0
 8002f82:	60fb      	str	r3, [r7, #12]
  
  /* Check the COMP handle allocation and lock status */
  if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
 8002f84:	687b      	ldr	r3, [r7, #4]
 8002f86:	2b00      	cmp	r3, #0
 8002f88:	d007      	beq.n	8002f9a <HAL_COMP_Start+0x2a>
 8002f8a:	687b      	ldr	r3, [r7, #4]
 8002f8c:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002f90:	b2db      	uxtb	r3, r3
 8002f92:	f003 0310 	and.w	r3, r3, #16
 8002f96:	2b00      	cmp	r3, #0
 8002f98:	d002      	beq.n	8002fa0 <HAL_COMP_Start+0x30>
  {
    status = HAL_ERROR;
 8002f9a:	2301      	movs	r3, #1
 8002f9c:	75fb      	strb	r3, [r7, #23]
 8002f9e:	e034      	b.n	800300a <HAL_COMP_Start+0x9a>
  else
  {
    /* Check the parameter */
    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));

    if(hcomp->State == HAL_COMP_STATE_READY)
 8002fa0:	687b      	ldr	r3, [r7, #4]
 8002fa2:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002fa6:	b2db      	uxtb	r3, r3
 8002fa8:	2b01      	cmp	r3, #1
 8002faa:	d12c      	bne.n	8003006 <HAL_COMP_Start+0x96>
      
      /* Note: For comparator 2, inverting input (parameter                   */
      /*       "hcomp->Init.InvertingInput") is configured into this          */
      /*       function instead of function "HAL_COMP_Init()" since           */
      /*       inverting input selection also enables the comparator 2.       */
      __HAL_COMP_ENABLE(hcomp);
 8002fac:	687b      	ldr	r3, [r7, #4]
 8002fae:	681b      	ldr	r3, [r3, #0]
 8002fb0:	4a19      	ldr	r2, [pc, #100]	; (8003018 <HAL_COMP_Start+0xa8>)
 8002fb2:	4293      	cmp	r3, r2
 8002fb4:	d106      	bne.n	8002fc4 <HAL_COMP_Start+0x54>
 8002fb6:	4b18      	ldr	r3, [pc, #96]	; (8003018 <HAL_COMP_Start+0xa8>)
 8002fb8:	681b      	ldr	r3, [r3, #0]
 8002fba:	4a17      	ldr	r2, [pc, #92]	; (8003018 <HAL_COMP_Start+0xa8>)
 8002fbc:	f043 0310 	orr.w	r3, r3, #16
 8002fc0:	6013      	str	r3, [r2, #0]
 8002fc2:	e008      	b.n	8002fd6 <HAL_COMP_Start+0x66>
 8002fc4:	4b14      	ldr	r3, [pc, #80]	; (8003018 <HAL_COMP_Start+0xa8>)
 8002fc6:	681b      	ldr	r3, [r3, #0]
 8002fc8:	f423 12e0 	bic.w	r2, r3, #1835008	; 0x1c0000
 8002fcc:	687b      	ldr	r3, [r7, #4]
 8002fce:	685b      	ldr	r3, [r3, #4]
 8002fd0:	4911      	ldr	r1, [pc, #68]	; (8003018 <HAL_COMP_Start+0xa8>)
 8002fd2:	4313      	orrs	r3, r2
 8002fd4:	600b      	str	r3, [r1, #0]

      /* Set delay for COMP start-up time */
      if (hcomp->Instance == COMP1)
 8002fd6:	687b      	ldr	r3, [r7, #4]
 8002fd8:	681b      	ldr	r3, [r3, #0]
 8002fda:	4a0f      	ldr	r2, [pc, #60]	; (8003018 <HAL_COMP_Start+0xa8>)
 8002fdc:	4293      	cmp	r3, r2
 8002fde:	d102      	bne.n	8002fe6 <HAL_COMP_Start+0x76>
      {
        wait_loop_cycles = COMP1_START_DELAY_CPU_CYCLES;
 8002fe0:	236a      	movs	r3, #106	; 0x6a
 8002fe2:	613b      	str	r3, [r7, #16]
 8002fe4:	e006      	b.n	8002ff4 <HAL_COMP_Start+0x84>
      }
      else /* if (hcomp->Instance == COMP2) */
      {
        wait_loop_cycles = COMP2_START_DELAY_CPU_CYCLES;
 8002fe6:	f44f 7385 	mov.w	r3, #266	; 0x10a
 8002fea:	613b      	str	r3, [r7, #16]
      }

      /* Delay for COMP start-up time.                                         */
      /* Delay fixed to worst case: maximum CPU frequency                     */
      while(wait_loop_index < wait_loop_cycles)
 8002fec:	e002      	b.n	8002ff4 <HAL_COMP_Start+0x84>
      {
        wait_loop_index++;
 8002fee:	68fb      	ldr	r3, [r7, #12]
 8002ff0:	3301      	adds	r3, #1
 8002ff2:	60fb      	str	r3, [r7, #12]
      while(wait_loop_index < wait_loop_cycles)
 8002ff4:	68fb      	ldr	r3, [r7, #12]
 8002ff6:	693a      	ldr	r2, [r7, #16]
 8002ff8:	429a      	cmp	r2, r3
 8002ffa:	d8f8      	bhi.n	8002fee <HAL_COMP_Start+0x7e>
      }

      /* Update COMP state */
      hcomp->State = HAL_COMP_STATE_BUSY;
 8002ffc:	687b      	ldr	r3, [r7, #4]
 8002ffe:	2202      	movs	r2, #2
 8003000:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
 8003004:	e001      	b.n	800300a <HAL_COMP_Start+0x9a>
      
    }
    else
    {
      status = HAL_ERROR;
 8003006:	2301      	movs	r3, #1
 8003008:	75fb      	strb	r3, [r7, #23]
    }
  }

  return status;
 800300a:	7dfb      	ldrb	r3, [r7, #23]
}
 800300c:	4618      	mov	r0, r3
 800300e:	371c      	adds	r7, #28
 8003010:	46bd      	mov	sp, r7
 8003012:	bc80      	pop	{r7}
 8003014:	4770      	bx	lr
 8003016:	bf00      	nop
 8003018:	40007c00 	.word	0x40007c00

0800301c <HAL_COMP_Start_IT>:
  * @brief  Enables the interrupt and starts the comparator
  * @param  hcomp COMP handle
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
{ 
 800301c:	b580      	push	{r7, lr}
 800301e:	b084      	sub	sp, #16
 8003020:	af00      	add	r7, sp, #0
 8003022:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK; 
 8003024:	2300      	movs	r3, #0
 8003026:	73fb      	strb	r3, [r7, #15]
  uint32_t extiline = 0;
 8003028:	2300      	movs	r3, #0
 800302a:	60bb      	str	r3, [r7, #8]
  
  status = HAL_COMP_Start(hcomp);
 800302c:	6878      	ldr	r0, [r7, #4]
 800302e:	f7ff ff9f 	bl	8002f70 <HAL_COMP_Start>
 8003032:	4603      	mov	r3, r0
 8003034:	73fb      	strb	r3, [r7, #15]
  if(status == HAL_OK)
 8003036:	7bfb      	ldrb	r3, [r7, #15]
 8003038:	2b00      	cmp	r3, #0
 800303a:	d13b      	bne.n	80030b4 <HAL_COMP_Start_IT+0x98>
  {
    /* Check the parameter */
    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
    
    /* Get the Exti Line output configuration */
    extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
 800303c:	687b      	ldr	r3, [r7, #4]
 800303e:	681b      	ldr	r3, [r3, #0]
 8003040:	4a1f      	ldr	r2, [pc, #124]	; (80030c0 <HAL_COMP_Start_IT+0xa4>)
 8003042:	4293      	cmp	r3, r2
 8003044:	d102      	bne.n	800304c <HAL_COMP_Start_IT+0x30>
 8003046:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 800304a:	e001      	b.n	8003050 <HAL_COMP_Start_IT+0x34>
 800304c:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 8003050:	60bb      	str	r3, [r7, #8]
    
    /* Configure the trigger rising edge */
    if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
 8003052:	687b      	ldr	r3, [r7, #4]
 8003054:	699b      	ldr	r3, [r3, #24]
 8003056:	f003 0301 	and.w	r3, r3, #1
 800305a:	2b00      	cmp	r3, #0
 800305c:	d006      	beq.n	800306c <HAL_COMP_Start_IT+0x50>
    {
      SET_BIT(EXTI->RTSR, extiline);
 800305e:	4b19      	ldr	r3, [pc, #100]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 8003060:	689a      	ldr	r2, [r3, #8]
 8003062:	4918      	ldr	r1, [pc, #96]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 8003064:	68bb      	ldr	r3, [r7, #8]
 8003066:	4313      	orrs	r3, r2
 8003068:	608b      	str	r3, [r1, #8]
 800306a:	e006      	b.n	800307a <HAL_COMP_Start_IT+0x5e>
    }
    else
    {
      CLEAR_BIT(EXTI->RTSR, extiline);
 800306c:	4b15      	ldr	r3, [pc, #84]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 800306e:	689a      	ldr	r2, [r3, #8]
 8003070:	68bb      	ldr	r3, [r7, #8]
 8003072:	43db      	mvns	r3, r3
 8003074:	4913      	ldr	r1, [pc, #76]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 8003076:	4013      	ands	r3, r2
 8003078:	608b      	str	r3, [r1, #8]
    }
  
    /* Configure the trigger falling edge */
    if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
 800307a:	687b      	ldr	r3, [r7, #4]
 800307c:	699b      	ldr	r3, [r3, #24]
 800307e:	f003 0302 	and.w	r3, r3, #2
 8003082:	2b00      	cmp	r3, #0
 8003084:	d006      	beq.n	8003094 <HAL_COMP_Start_IT+0x78>
    {
      SET_BIT(EXTI->FTSR, extiline);
 8003086:	4b0f      	ldr	r3, [pc, #60]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 8003088:	68da      	ldr	r2, [r3, #12]
 800308a:	490e      	ldr	r1, [pc, #56]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 800308c:	68bb      	ldr	r3, [r7, #8]
 800308e:	4313      	orrs	r3, r2
 8003090:	60cb      	str	r3, [r1, #12]
 8003092:	e006      	b.n	80030a2 <HAL_COMP_Start_IT+0x86>
    }
    else
    {
      CLEAR_BIT(EXTI->FTSR, extiline);
 8003094:	4b0b      	ldr	r3, [pc, #44]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 8003096:	68da      	ldr	r2, [r3, #12]
 8003098:	68bb      	ldr	r3, [r7, #8]
 800309a:	43db      	mvns	r3, r3
 800309c:	4909      	ldr	r1, [pc, #36]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 800309e:	4013      	ands	r3, r2
 80030a0:	60cb      	str	r3, [r1, #12]
    }
    
    /* Clear COMP EXTI pending bit */
    WRITE_REG(EXTI->PR, extiline);
 80030a2:	4a08      	ldr	r2, [pc, #32]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 80030a4:	68bb      	ldr	r3, [r7, #8]
 80030a6:	6153      	str	r3, [r2, #20]
    
    /* Enable EXTI interrupt mode */
    SET_BIT(EXTI->IMR, extiline);
 80030a8:	4b06      	ldr	r3, [pc, #24]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 80030aa:	681a      	ldr	r2, [r3, #0]
 80030ac:	4905      	ldr	r1, [pc, #20]	; (80030c4 <HAL_COMP_Start_IT+0xa8>)
 80030ae:	68bb      	ldr	r3, [r7, #8]
 80030b0:	4313      	orrs	r3, r2
 80030b2:	600b      	str	r3, [r1, #0]
    
  }

  return status;
 80030b4:	7bfb      	ldrb	r3, [r7, #15]
}
 80030b6:	4618      	mov	r0, r3
 80030b8:	3710      	adds	r7, #16
 80030ba:	46bd      	mov	sp, r7
 80030bc:	bd80      	pop	{r7, pc}
 80030be:	bf00      	nop
 80030c0:	40007c00 	.word	0x40007c00
 80030c4:	40010400 	.word	0x40010400

080030c8 <HAL_COMP_IRQHandler>:
  * @brief  Comparator IRQ Handler 
  * @param  hcomp COMP handle
  * @retval HAL status
  */
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
 80030c8:	b580      	push	{r7, lr}
 80030ca:	b084      	sub	sp, #16
 80030cc:	af00      	add	r7, sp, #0
 80030ce:	6078      	str	r0, [r7, #4]
  uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
 80030d0:	687b      	ldr	r3, [r7, #4]
 80030d2:	681b      	ldr	r3, [r3, #0]
 80030d4:	4a0c      	ldr	r2, [pc, #48]	; (8003108 <HAL_COMP_IRQHandler+0x40>)
 80030d6:	4293      	cmp	r3, r2
 80030d8:	d102      	bne.n	80030e0 <HAL_COMP_IRQHandler+0x18>
 80030da:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 80030de:	e001      	b.n	80030e4 <HAL_COMP_IRQHandler+0x1c>
 80030e0:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 80030e4:	60fb      	str	r3, [r7, #12]
  
  /* Check COMP Exti flag */
  if(READ_BIT(EXTI->PR, extiline) != RESET)
 80030e6:	4b09      	ldr	r3, [pc, #36]	; (800310c <HAL_COMP_IRQHandler+0x44>)
 80030e8:	695a      	ldr	r2, [r3, #20]
 80030ea:	68fb      	ldr	r3, [r7, #12]
 80030ec:	4013      	ands	r3, r2
 80030ee:	2b00      	cmp	r3, #0
 80030f0:	d005      	beq.n	80030fe <HAL_COMP_IRQHandler+0x36>
  {
    /* Clear COMP EXTI pending bit */
    WRITE_REG(EXTI->PR, extiline);
 80030f2:	4a06      	ldr	r2, [pc, #24]	; (800310c <HAL_COMP_IRQHandler+0x44>)
 80030f4:	68fb      	ldr	r3, [r7, #12]
 80030f6:	6153      	str	r3, [r2, #20]

    /* COMP trigger callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
    hcomp->TriggerCallback(hcomp);
#else
    HAL_COMP_TriggerCallback(hcomp);    
 80030f8:	6878      	ldr	r0, [r7, #4]
 80030fa:	f7fd ff67 	bl	8000fcc <HAL_COMP_TriggerCallback>
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
  }
}
 80030fe:	bf00      	nop
 8003100:	3710      	adds	r7, #16
 8003102:	46bd      	mov	sp, r7
 8003104:	bd80      	pop	{r7, pc}
 8003106:	bf00      	nop
 8003108:	40007c00 	.word	0x40007c00
 800310c:	40010400 	.word	0x40010400

08003110 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8003110:	b480      	push	{r7}
 8003112:	b085      	sub	sp, #20
 8003114:	af00      	add	r7, sp, #0
 8003116:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8003118:	687b      	ldr	r3, [r7, #4]
 800311a:	f003 0307 	and.w	r3, r3, #7
 800311e:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8003120:	4b0c      	ldr	r3, [pc, #48]	; (8003154 <__NVIC_SetPriorityGrouping+0x44>)
 8003122:	68db      	ldr	r3, [r3, #12]
 8003124:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8003126:	68ba      	ldr	r2, [r7, #8]
 8003128:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 800312c:	4013      	ands	r3, r2
 800312e:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 8003130:	68fb      	ldr	r3, [r7, #12]
 8003132:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8003134:	68bb      	ldr	r3, [r7, #8]
 8003136:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 8003138:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 800313c:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8003140:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8003142:	4a04      	ldr	r2, [pc, #16]	; (8003154 <__NVIC_SetPriorityGrouping+0x44>)
 8003144:	68bb      	ldr	r3, [r7, #8]
 8003146:	60d3      	str	r3, [r2, #12]
}
 8003148:	bf00      	nop
 800314a:	3714      	adds	r7, #20
 800314c:	46bd      	mov	sp, r7
 800314e:	bc80      	pop	{r7}
 8003150:	4770      	bx	lr
 8003152:	bf00      	nop
 8003154:	e000ed00 	.word	0xe000ed00

08003158 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 8003158:	b480      	push	{r7}
 800315a:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 800315c:	4b04      	ldr	r3, [pc, #16]	; (8003170 <__NVIC_GetPriorityGrouping+0x18>)
 800315e:	68db      	ldr	r3, [r3, #12]
 8003160:	0a1b      	lsrs	r3, r3, #8
 8003162:	f003 0307 	and.w	r3, r3, #7
}
 8003166:	4618      	mov	r0, r3
 8003168:	46bd      	mov	sp, r7
 800316a:	bc80      	pop	{r7}
 800316c:	4770      	bx	lr
 800316e:	bf00      	nop
 8003170:	e000ed00 	.word	0xe000ed00

08003174 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8003174:	b480      	push	{r7}
 8003176:	b083      	sub	sp, #12
 8003178:	af00      	add	r7, sp, #0
 800317a:	4603      	mov	r3, r0
 800317c:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 800317e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8003182:	2b00      	cmp	r3, #0
 8003184:	db0b      	blt.n	800319e <__NVIC_EnableIRQ+0x2a>
  {
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8003186:	79fb      	ldrb	r3, [r7, #7]
 8003188:	f003 021f 	and.w	r2, r3, #31
 800318c:	4906      	ldr	r1, [pc, #24]	; (80031a8 <__NVIC_EnableIRQ+0x34>)
 800318e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8003192:	095b      	lsrs	r3, r3, #5
 8003194:	2001      	movs	r0, #1
 8003196:	fa00 f202 	lsl.w	r2, r0, r2
 800319a:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  }
}
 800319e:	bf00      	nop
 80031a0:	370c      	adds	r7, #12
 80031a2:	46bd      	mov	sp, r7
 80031a4:	bc80      	pop	{r7}
 80031a6:	4770      	bx	lr
 80031a8:	e000e100 	.word	0xe000e100

080031ac <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 80031ac:	b480      	push	{r7}
 80031ae:	b083      	sub	sp, #12
 80031b0:	af00      	add	r7, sp, #0
 80031b2:	4603      	mov	r3, r0
 80031b4:	6039      	str	r1, [r7, #0]
 80031b6:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80031b8:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80031bc:	2b00      	cmp	r3, #0
 80031be:	db0a      	blt.n	80031d6 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80031c0:	683b      	ldr	r3, [r7, #0]
 80031c2:	b2da      	uxtb	r2, r3
 80031c4:	490c      	ldr	r1, [pc, #48]	; (80031f8 <__NVIC_SetPriority+0x4c>)
 80031c6:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80031ca:	0112      	lsls	r2, r2, #4
 80031cc:	b2d2      	uxtb	r2, r2
 80031ce:	440b      	add	r3, r1
 80031d0:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 80031d4:	e00a      	b.n	80031ec <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80031d6:	683b      	ldr	r3, [r7, #0]
 80031d8:	b2da      	uxtb	r2, r3
 80031da:	4908      	ldr	r1, [pc, #32]	; (80031fc <__NVIC_SetPriority+0x50>)
 80031dc:	79fb      	ldrb	r3, [r7, #7]
 80031de:	f003 030f 	and.w	r3, r3, #15
 80031e2:	3b04      	subs	r3, #4
 80031e4:	0112      	lsls	r2, r2, #4
 80031e6:	b2d2      	uxtb	r2, r2
 80031e8:	440b      	add	r3, r1
 80031ea:	761a      	strb	r2, [r3, #24]
}
 80031ec:	bf00      	nop
 80031ee:	370c      	adds	r7, #12
 80031f0:	46bd      	mov	sp, r7
 80031f2:	bc80      	pop	{r7}
 80031f4:	4770      	bx	lr
 80031f6:	bf00      	nop
 80031f8:	e000e100 	.word	0xe000e100
 80031fc:	e000ed00 	.word	0xe000ed00

08003200 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8003200:	b480      	push	{r7}
 8003202:	b089      	sub	sp, #36	; 0x24
 8003204:	af00      	add	r7, sp, #0
 8003206:	60f8      	str	r0, [r7, #12]
 8003208:	60b9      	str	r1, [r7, #8]
 800320a:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 800320c:	68fb      	ldr	r3, [r7, #12]
 800320e:	f003 0307 	and.w	r3, r3, #7
 8003212:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8003214:	69fb      	ldr	r3, [r7, #28]
 8003216:	f1c3 0307 	rsb	r3, r3, #7
 800321a:	2b04      	cmp	r3, #4
 800321c:	bf28      	it	cs
 800321e:	2304      	movcs	r3, #4
 8003220:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8003222:	69fb      	ldr	r3, [r7, #28]
 8003224:	3304      	adds	r3, #4
 8003226:	2b06      	cmp	r3, #6
 8003228:	d902      	bls.n	8003230 <NVIC_EncodePriority+0x30>
 800322a:	69fb      	ldr	r3, [r7, #28]
 800322c:	3b03      	subs	r3, #3
 800322e:	e000      	b.n	8003232 <NVIC_EncodePriority+0x32>
 8003230:	2300      	movs	r3, #0
 8003232:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8003234:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8003238:	69bb      	ldr	r3, [r7, #24]
 800323a:	fa02 f303 	lsl.w	r3, r2, r3
 800323e:	43da      	mvns	r2, r3
 8003240:	68bb      	ldr	r3, [r7, #8]
 8003242:	401a      	ands	r2, r3
 8003244:	697b      	ldr	r3, [r7, #20]
 8003246:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8003248:	f04f 31ff 	mov.w	r1, #4294967295	; 0xffffffff
 800324c:	697b      	ldr	r3, [r7, #20]
 800324e:	fa01 f303 	lsl.w	r3, r1, r3
 8003252:	43d9      	mvns	r1, r3
 8003254:	687b      	ldr	r3, [r7, #4]
 8003256:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8003258:	4313      	orrs	r3, r2
         );
}
 800325a:	4618      	mov	r0, r3
 800325c:	3724      	adds	r7, #36	; 0x24
 800325e:	46bd      	mov	sp, r7
 8003260:	bc80      	pop	{r7}
 8003262:	4770      	bx	lr

08003264 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8003264:	b580      	push	{r7, lr}
 8003266:	b082      	sub	sp, #8
 8003268:	af00      	add	r7, sp, #0
 800326a:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 800326c:	687b      	ldr	r3, [r7, #4]
 800326e:	3b01      	subs	r3, #1
 8003270:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 8003274:	d301      	bcc.n	800327a <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 8003276:	2301      	movs	r3, #1
 8003278:	e00f      	b.n	800329a <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 800327a:	4a0a      	ldr	r2, [pc, #40]	; (80032a4 <SysTick_Config+0x40>)
 800327c:	687b      	ldr	r3, [r7, #4]
 800327e:	3b01      	subs	r3, #1
 8003280:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 8003282:	210f      	movs	r1, #15
 8003284:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8003288:	f7ff ff90 	bl	80031ac <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 800328c:	4b05      	ldr	r3, [pc, #20]	; (80032a4 <SysTick_Config+0x40>)
 800328e:	2200      	movs	r2, #0
 8003290:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8003292:	4b04      	ldr	r3, [pc, #16]	; (80032a4 <SysTick_Config+0x40>)
 8003294:	2207      	movs	r2, #7
 8003296:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8003298:	2300      	movs	r3, #0
}
 800329a:	4618      	mov	r0, r3
 800329c:	3708      	adds	r7, #8
 800329e:	46bd      	mov	sp, r7
 80032a0:	bd80      	pop	{r7, pc}
 80032a2:	bf00      	nop
 80032a4:	e000e010 	.word	0xe000e010

080032a8 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80032a8:	b580      	push	{r7, lr}
 80032aa:	b082      	sub	sp, #8
 80032ac:	af00      	add	r7, sp, #0
 80032ae:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 80032b0:	6878      	ldr	r0, [r7, #4]
 80032b2:	f7ff ff2d 	bl	8003110 <__NVIC_SetPriorityGrouping>
}
 80032b6:	bf00      	nop
 80032b8:	3708      	adds	r7, #8
 80032ba:	46bd      	mov	sp, r7
 80032bc:	bd80      	pop	{r7, pc}

080032be <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 80032be:	b580      	push	{r7, lr}
 80032c0:	b086      	sub	sp, #24
 80032c2:	af00      	add	r7, sp, #0
 80032c4:	4603      	mov	r3, r0
 80032c6:	60b9      	str	r1, [r7, #8]
 80032c8:	607a      	str	r2, [r7, #4]
 80032ca:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00;
 80032cc:	2300      	movs	r3, #0
 80032ce:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 80032d0:	f7ff ff42 	bl	8003158 <__NVIC_GetPriorityGrouping>
 80032d4:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 80032d6:	687a      	ldr	r2, [r7, #4]
 80032d8:	68b9      	ldr	r1, [r7, #8]
 80032da:	6978      	ldr	r0, [r7, #20]
 80032dc:	f7ff ff90 	bl	8003200 <NVIC_EncodePriority>
 80032e0:	4602      	mov	r2, r0
 80032e2:	f997 300f 	ldrsb.w	r3, [r7, #15]
 80032e6:	4611      	mov	r1, r2
 80032e8:	4618      	mov	r0, r3
 80032ea:	f7ff ff5f 	bl	80031ac <__NVIC_SetPriority>
}
 80032ee:	bf00      	nop
 80032f0:	3718      	adds	r7, #24
 80032f2:	46bd      	mov	sp, r7
 80032f4:	bd80      	pop	{r7, pc}

080032f6 <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80032f6:	b580      	push	{r7, lr}
 80032f8:	b082      	sub	sp, #8
 80032fa:	af00      	add	r7, sp, #0
 80032fc:	4603      	mov	r3, r0
 80032fe:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8003300:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8003304:	4618      	mov	r0, r3
 8003306:	f7ff ff35 	bl	8003174 <__NVIC_EnableIRQ>
}
 800330a:	bf00      	nop
 800330c:	3708      	adds	r7, #8
 800330e:	46bd      	mov	sp, r7
 8003310:	bd80      	pop	{r7, pc}

08003312 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8003312:	b580      	push	{r7, lr}
 8003314:	b082      	sub	sp, #8
 8003316:	af00      	add	r7, sp, #0
 8003318:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 800331a:	6878      	ldr	r0, [r7, #4]
 800331c:	f7ff ffa2 	bl	8003264 <SysTick_Config>
 8003320:	4603      	mov	r3, r0
}
 8003322:	4618      	mov	r0, r3
 8003324:	3708      	adds	r7, #8
 8003326:	46bd      	mov	sp, r7
 8003328:	bd80      	pop	{r7, pc}

0800332a <HAL_DAC_Init>:
  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
  *         the configuration information for the specified DAC.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
 800332a:	b580      	push	{r7, lr}
 800332c:	b082      	sub	sp, #8
 800332e:	af00      	add	r7, sp, #0
 8003330:	6078      	str	r0, [r7, #4]
  /* Check DAC handle */
  if (hdac == NULL)
 8003332:	687b      	ldr	r3, [r7, #4]
 8003334:	2b00      	cmp	r3, #0
 8003336:	d101      	bne.n	800333c <HAL_DAC_Init+0x12>
  {
    return HAL_ERROR;
 8003338:	2301      	movs	r3, #1
 800333a:	e014      	b.n	8003366 <HAL_DAC_Init+0x3c>
  }
  /* Check the parameters */
  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));

  if (hdac->State == HAL_DAC_STATE_RESET)
 800333c:	687b      	ldr	r3, [r7, #4]
 800333e:	791b      	ldrb	r3, [r3, #4]
 8003340:	b2db      	uxtb	r3, r3
 8003342:	2b00      	cmp	r3, #0
 8003344:	d105      	bne.n	8003352 <HAL_DAC_Init+0x28>
      hdac->MspInitCallback             = HAL_DAC_MspInit;
    }
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

    /* Allocate lock resource and initialize it */
    hdac->Lock = HAL_UNLOCKED;
 8003346:	687b      	ldr	r3, [r7, #4]
 8003348:	2200      	movs	r2, #0
 800334a:	715a      	strb	r2, [r3, #5]
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
    /* Init the low level hardware */
    hdac->MspInitCallback(hdac);
#else
    /* Init the low level hardware */
    HAL_DAC_MspInit(hdac);
 800334c:	6878      	ldr	r0, [r7, #4]
 800334e:	f7fe fcdf 	bl	8001d10 <HAL_DAC_MspInit>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
  }

  /* Initialize the DAC state*/
  hdac->State = HAL_DAC_STATE_BUSY;
 8003352:	687b      	ldr	r3, [r7, #4]
 8003354:	2202      	movs	r2, #2
 8003356:	711a      	strb	r2, [r3, #4]

  /* Set DAC error code to none */
  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
 8003358:	687b      	ldr	r3, [r7, #4]
 800335a:	2200      	movs	r2, #0
 800335c:	611a      	str	r2, [r3, #16]

  /* Initialize the DAC state*/
  hdac->State = HAL_DAC_STATE_READY;
 800335e:	687b      	ldr	r3, [r7, #4]
 8003360:	2201      	movs	r2, #1
 8003362:	711a      	strb	r2, [r3, #4]

  /* Return function status */
  return HAL_OK;
 8003364:	2300      	movs	r3, #0
}
 8003366:	4618      	mov	r0, r3
 8003368:	3708      	adds	r7, #8
 800336a:	46bd      	mov	sp, r7
 800336c:	bd80      	pop	{r7, pc}

0800336e <HAL_DAC_Start>:
  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
 800336e:	b480      	push	{r7}
 8003370:	b083      	sub	sp, #12
 8003372:	af00      	add	r7, sp, #0
 8003374:	6078      	str	r0, [r7, #4]
 8003376:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_DAC_CHANNEL(Channel));

  /* Process locked */
  __HAL_LOCK(hdac);
 8003378:	687b      	ldr	r3, [r7, #4]
 800337a:	795b      	ldrb	r3, [r3, #5]
 800337c:	2b01      	cmp	r3, #1
 800337e:	d101      	bne.n	8003384 <HAL_DAC_Start+0x16>
 8003380:	2302      	movs	r3, #2
 8003382:	e040      	b.n	8003406 <HAL_DAC_Start+0x98>
 8003384:	687b      	ldr	r3, [r7, #4]
 8003386:	2201      	movs	r2, #1
 8003388:	715a      	strb	r2, [r3, #5]

  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_BUSY;
 800338a:	687b      	ldr	r3, [r7, #4]
 800338c:	2202      	movs	r2, #2
 800338e:	711a      	strb	r2, [r3, #4]

  /* Enable the Peripheral */
  __HAL_DAC_ENABLE(hdac, Channel);
 8003390:	687b      	ldr	r3, [r7, #4]
 8003392:	681b      	ldr	r3, [r3, #0]
 8003394:	6819      	ldr	r1, [r3, #0]
 8003396:	683b      	ldr	r3, [r7, #0]
 8003398:	f003 0310 	and.w	r3, r3, #16
 800339c:	2201      	movs	r2, #1
 800339e:	409a      	lsls	r2, r3
 80033a0:	687b      	ldr	r3, [r7, #4]
 80033a2:	681b      	ldr	r3, [r3, #0]
 80033a4:	430a      	orrs	r2, r1
 80033a6:	601a      	str	r2, [r3, #0]

  if (Channel == DAC_CHANNEL_1)
 80033a8:	683b      	ldr	r3, [r7, #0]
 80033aa:	2b00      	cmp	r3, #0
 80033ac:	d10f      	bne.n	80033ce <HAL_DAC_Start+0x60>
  {
    /* Check if software trigger enabled */
    if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
 80033ae:	687b      	ldr	r3, [r7, #4]
 80033b0:	681b      	ldr	r3, [r3, #0]
 80033b2:	681b      	ldr	r3, [r3, #0]
 80033b4:	f003 033c 	and.w	r3, r3, #60	; 0x3c
 80033b8:	2b3c      	cmp	r3, #60	; 0x3c
 80033ba:	d11d      	bne.n	80033f8 <HAL_DAC_Start+0x8a>
    {
      /* Enable the selected DAC software conversion */
      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
 80033bc:	687b      	ldr	r3, [r7, #4]
 80033be:	681b      	ldr	r3, [r3, #0]
 80033c0:	685a      	ldr	r2, [r3, #4]
 80033c2:	687b      	ldr	r3, [r7, #4]
 80033c4:	681b      	ldr	r3, [r3, #0]
 80033c6:	f042 0201 	orr.w	r2, r2, #1
 80033ca:	605a      	str	r2, [r3, #4]
 80033cc:	e014      	b.n	80033f8 <HAL_DAC_Start+0x8a>
  }

  else
  {
    /* Check if software trigger enabled */
    if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
 80033ce:	687b      	ldr	r3, [r7, #4]
 80033d0:	681b      	ldr	r3, [r3, #0]
 80033d2:	681b      	ldr	r3, [r3, #0]
 80033d4:	f403 1270 	and.w	r2, r3, #3932160	; 0x3c0000
 80033d8:	683b      	ldr	r3, [r7, #0]
 80033da:	f003 0310 	and.w	r3, r3, #16
 80033de:	213c      	movs	r1, #60	; 0x3c
 80033e0:	fa01 f303 	lsl.w	r3, r1, r3
 80033e4:	429a      	cmp	r2, r3
 80033e6:	d107      	bne.n	80033f8 <HAL_DAC_Start+0x8a>
    {
      /* Enable the selected DAC software conversion*/
      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
 80033e8:	687b      	ldr	r3, [r7, #4]
 80033ea:	681b      	ldr	r3, [r3, #0]
 80033ec:	685a      	ldr	r2, [r3, #4]
 80033ee:	687b      	ldr	r3, [r7, #4]
 80033f0:	681b      	ldr	r3, [r3, #0]
 80033f2:	f042 0202 	orr.w	r2, r2, #2
 80033f6:	605a      	str	r2, [r3, #4]
    }
  }


  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_READY;
 80033f8:	687b      	ldr	r3, [r7, #4]
 80033fa:	2201      	movs	r2, #1
 80033fc:	711a      	strb	r2, [r3, #4]

  /* Process unlocked */
  __HAL_UNLOCK(hdac);
 80033fe:	687b      	ldr	r3, [r7, #4]
 8003400:	2200      	movs	r2, #0
 8003402:	715a      	strb	r2, [r3, #5]

  /* Return function status */
  return HAL_OK;
 8003404:	2300      	movs	r3, #0
}
 8003406:	4618      	mov	r0, r3
 8003408:	370c      	adds	r7, #12
 800340a:	46bd      	mov	sp, r7
 800340c:	bc80      	pop	{r7}
 800340e:	4770      	bx	lr

08003410 <HAL_DAC_SetValue>:
  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
  * @param  Data Data to be loaded in the selected data holding register.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
 8003410:	b480      	push	{r7}
 8003412:	b087      	sub	sp, #28
 8003414:	af00      	add	r7, sp, #0
 8003416:	60f8      	str	r0, [r7, #12]
 8003418:	60b9      	str	r1, [r7, #8]
 800341a:	607a      	str	r2, [r7, #4]
 800341c:	603b      	str	r3, [r7, #0]
  __IO uint32_t tmp = 0UL;
 800341e:	2300      	movs	r3, #0
 8003420:	617b      	str	r3, [r7, #20]
  /* Check the parameters */
  assert_param(IS_DAC_CHANNEL(Channel));
  assert_param(IS_DAC_ALIGN(Alignment));
  assert_param(IS_DAC_DATA(Data));

  tmp = (uint32_t)hdac->Instance;
 8003422:	68fb      	ldr	r3, [r7, #12]
 8003424:	681b      	ldr	r3, [r3, #0]
 8003426:	617b      	str	r3, [r7, #20]
  if (Channel == DAC_CHANNEL_1)
 8003428:	68bb      	ldr	r3, [r7, #8]
 800342a:	2b00      	cmp	r3, #0
 800342c:	d105      	bne.n	800343a <HAL_DAC_SetValue+0x2a>
  {
    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
 800342e:	697a      	ldr	r2, [r7, #20]
 8003430:	687b      	ldr	r3, [r7, #4]
 8003432:	4413      	add	r3, r2
 8003434:	3308      	adds	r3, #8
 8003436:	617b      	str	r3, [r7, #20]
 8003438:	e004      	b.n	8003444 <HAL_DAC_SetValue+0x34>
  }

  else
  {
    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
 800343a:	697a      	ldr	r2, [r7, #20]
 800343c:	687b      	ldr	r3, [r7, #4]
 800343e:	4413      	add	r3, r2
 8003440:	3314      	adds	r3, #20
 8003442:	617b      	str	r3, [r7, #20]
  }


  /* Set the DAC channel selected data holding register */
  *(__IO uint32_t *) tmp = Data;
 8003444:	697b      	ldr	r3, [r7, #20]
 8003446:	461a      	mov	r2, r3
 8003448:	683b      	ldr	r3, [r7, #0]
 800344a:	6013      	str	r3, [r2, #0]

  /* Return function status */
  return HAL_OK;
 800344c:	2300      	movs	r3, #0
}
 800344e:	4618      	mov	r0, r3
 8003450:	371c      	adds	r7, #28
 8003452:	46bd      	mov	sp, r7
 8003454:	bc80      	pop	{r7}
 8003456:	4770      	bx	lr

08003458 <HAL_DAC_ConfigChannel>:
  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
 8003458:	b480      	push	{r7}
 800345a:	b087      	sub	sp, #28
 800345c:	af00      	add	r7, sp, #0
 800345e:	60f8      	str	r0, [r7, #12]
 8003460:	60b9      	str	r1, [r7, #8]
 8003462:	607a      	str	r2, [r7, #4]
  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
  assert_param(IS_DAC_CHANNEL(Channel));

  /* Process locked */
  __HAL_LOCK(hdac);
 8003464:	68fb      	ldr	r3, [r7, #12]
 8003466:	795b      	ldrb	r3, [r3, #5]
 8003468:	2b01      	cmp	r3, #1
 800346a:	d101      	bne.n	8003470 <HAL_DAC_ConfigChannel+0x18>
 800346c:	2302      	movs	r3, #2
 800346e:	e03c      	b.n	80034ea <HAL_DAC_ConfigChannel+0x92>
 8003470:	68fb      	ldr	r3, [r7, #12]
 8003472:	2201      	movs	r2, #1
 8003474:	715a      	strb	r2, [r3, #5]

  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_BUSY;
 8003476:	68fb      	ldr	r3, [r7, #12]
 8003478:	2202      	movs	r2, #2
 800347a:	711a      	strb	r2, [r3, #4]

  /* Get the DAC CR value */
  tmpreg1 = hdac->Instance->CR;
 800347c:	68fb      	ldr	r3, [r7, #12]
 800347e:	681b      	ldr	r3, [r3, #0]
 8003480:	681b      	ldr	r3, [r3, #0]
 8003482:	617b      	str	r3, [r7, #20]
  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL));
 8003484:	687b      	ldr	r3, [r7, #4]
 8003486:	f003 0310 	and.w	r3, r3, #16
 800348a:	f640 72fe 	movw	r2, #4094	; 0xffe
 800348e:	fa02 f303 	lsl.w	r3, r2, r3
 8003492:	43db      	mvns	r3, r3
 8003494:	697a      	ldr	r2, [r7, #20]
 8003496:	4013      	ands	r3, r2
 8003498:	617b      	str	r3, [r7, #20]
  /* Configure for the selected DAC channel: buffer output, trigger */
  /* Set TSELx and TENx bits according to DAC_Trigger value */
  /* Set BOFFx bit according to DAC_OutputBuffer value */
  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
 800349a:	68bb      	ldr	r3, [r7, #8]
 800349c:	681a      	ldr	r2, [r3, #0]
 800349e:	68bb      	ldr	r3, [r7, #8]
 80034a0:	685b      	ldr	r3, [r3, #4]
 80034a2:	4313      	orrs	r3, r2
 80034a4:	613b      	str	r3, [r7, #16]
  /* Calculate CR register value depending on DAC_Channel */
  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
 80034a6:	687b      	ldr	r3, [r7, #4]
 80034a8:	f003 0310 	and.w	r3, r3, #16
 80034ac:	693a      	ldr	r2, [r7, #16]
 80034ae:	fa02 f303 	lsl.w	r3, r2, r3
 80034b2:	697a      	ldr	r2, [r7, #20]
 80034b4:	4313      	orrs	r3, r2
 80034b6:	617b      	str	r3, [r7, #20]
  /* Write to DAC CR */
  hdac->Instance->CR = tmpreg1;
 80034b8:	68fb      	ldr	r3, [r7, #12]
 80034ba:	681b      	ldr	r3, [r3, #0]
 80034bc:	697a      	ldr	r2, [r7, #20]
 80034be:	601a      	str	r2, [r3, #0]
  /* Disable wave generation */
  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
 80034c0:	68fb      	ldr	r3, [r7, #12]
 80034c2:	681b      	ldr	r3, [r3, #0]
 80034c4:	6819      	ldr	r1, [r3, #0]
 80034c6:	687b      	ldr	r3, [r7, #4]
 80034c8:	f003 0310 	and.w	r3, r3, #16
 80034cc:	22c0      	movs	r2, #192	; 0xc0
 80034ce:	fa02 f303 	lsl.w	r3, r2, r3
 80034d2:	43da      	mvns	r2, r3
 80034d4:	68fb      	ldr	r3, [r7, #12]
 80034d6:	681b      	ldr	r3, [r3, #0]
 80034d8:	400a      	ands	r2, r1
 80034da:	601a      	str	r2, [r3, #0]

  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_READY;
 80034dc:	68fb      	ldr	r3, [r7, #12]
 80034de:	2201      	movs	r2, #1
 80034e0:	711a      	strb	r2, [r3, #4]

  /* Process unlocked */
  __HAL_UNLOCK(hdac);
 80034e2:	68fb      	ldr	r3, [r7, #12]
 80034e4:	2200      	movs	r2, #0
 80034e6:	715a      	strb	r2, [r3, #5]

  /* Return function status */
  return HAL_OK;
 80034e8:	2300      	movs	r3, #0
}
 80034ea:	4618      	mov	r0, r3
 80034ec:	371c      	adds	r7, #28
 80034ee:	46bd      	mov	sp, r7
 80034f0:	bc80      	pop	{r7}
 80034f2:	4770      	bx	lr

080034f4 <HAL_DMA_Init>:
  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 80034f4:	b480      	push	{r7}
 80034f6:	b085      	sub	sp, #20
 80034f8:	af00      	add	r7, sp, #0
 80034fa:	6078      	str	r0, [r7, #4]
  uint32_t tmp;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 80034fc:	687b      	ldr	r3, [r7, #4]
 80034fe:	2b00      	cmp	r3, #0
 8003500:	d101      	bne.n	8003506 <HAL_DMA_Init+0x12>
  {
    return HAL_ERROR;
 8003502:	2301      	movs	r3, #1
 8003504:	e043      	b.n	800358e <HAL_DMA_Init+0x9a>
    hdma->DmaBaseAddress = DMA2;
  }
#else
  /* calculation of the channel index */
  /* DMA1 */
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
 8003506:	687b      	ldr	r3, [r7, #4]
 8003508:	681b      	ldr	r3, [r3, #0]
 800350a:	461a      	mov	r2, r3
 800350c:	4b22      	ldr	r3, [pc, #136]	; (8003598 <HAL_DMA_Init+0xa4>)
 800350e:	4413      	add	r3, r2
 8003510:	4a22      	ldr	r2, [pc, #136]	; (800359c <HAL_DMA_Init+0xa8>)
 8003512:	fba2 2303 	umull	r2, r3, r2, r3
 8003516:	091b      	lsrs	r3, r3, #4
 8003518:	009a      	lsls	r2, r3, #2
 800351a:	687b      	ldr	r3, [r7, #4]
 800351c:	641a      	str	r2, [r3, #64]	; 0x40
  hdma->DmaBaseAddress = DMA1;
 800351e:	687b      	ldr	r3, [r7, #4]
 8003520:	4a1f      	ldr	r2, [pc, #124]	; (80035a0 <HAL_DMA_Init+0xac>)
 8003522:	63da      	str	r2, [r3, #60]	; 0x3c
#endif

  /* Change DMA peripheral state */
  hdma->State = HAL_DMA_STATE_BUSY;
 8003524:	687b      	ldr	r3, [r7, #4]
 8003526:	2202      	movs	r2, #2
 8003528:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

  /* Get the CR register value */
  tmp = hdma->Instance->CCR;
 800352c:	687b      	ldr	r3, [r7, #4]
 800352e:	681b      	ldr	r3, [r3, #0]
 8003530:	681b      	ldr	r3, [r3, #0]
 8003532:	60fb      	str	r3, [r7, #12]

  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE   | DMA_CCR_PSIZE  |
 8003534:	68fb      	ldr	r3, [r7, #12]
 8003536:	f423 43ff 	bic.w	r3, r3, #32640	; 0x7f80
 800353a:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 800353e:	60fb      	str	r3, [r7, #12]
                      DMA_CCR_MINC  | DMA_CCR_PINC    | DMA_CCR_CIRC   |
                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 8003540:	687b      	ldr	r3, [r7, #4]
 8003542:	685a      	ldr	r2, [r3, #4]
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8003544:	687b      	ldr	r3, [r7, #4]
 8003546:	689b      	ldr	r3, [r3, #8]
  tmp |=  hdma->Init.Direction        |
 8003548:	431a      	orrs	r2, r3
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800354a:	687b      	ldr	r3, [r7, #4]
 800354c:	68db      	ldr	r3, [r3, #12]
 800354e:	431a      	orrs	r2, r3
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8003550:	687b      	ldr	r3, [r7, #4]
 8003552:	691b      	ldr	r3, [r3, #16]
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8003554:	431a      	orrs	r2, r3
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8003556:	687b      	ldr	r3, [r7, #4]
 8003558:	695b      	ldr	r3, [r3, #20]
 800355a:	431a      	orrs	r2, r3
          hdma->Init.Mode                | hdma->Init.Priority;
 800355c:	687b      	ldr	r3, [r7, #4]
 800355e:	699b      	ldr	r3, [r3, #24]
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8003560:	431a      	orrs	r2, r3
          hdma->Init.Mode                | hdma->Init.Priority;
 8003562:	687b      	ldr	r3, [r7, #4]
 8003564:	69db      	ldr	r3, [r3, #28]
 8003566:	4313      	orrs	r3, r2
  tmp |=  hdma->Init.Direction        |
 8003568:	68fa      	ldr	r2, [r7, #12]
 800356a:	4313      	orrs	r3, r2
 800356c:	60fb      	str	r3, [r7, #12]

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 800356e:	687b      	ldr	r3, [r7, #4]
 8003570:	681b      	ldr	r3, [r3, #0]
 8003572:	68fa      	ldr	r2, [r7, #12]
 8003574:	601a      	str	r2, [r3, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8003576:	687b      	ldr	r3, [r7, #4]
 8003578:	2200      	movs	r2, #0
 800357a:	639a      	str	r2, [r3, #56]	; 0x38

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 800357c:	687b      	ldr	r3, [r7, #4]
 800357e:	2201      	movs	r2, #1
 8003580:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 8003584:	687b      	ldr	r3, [r7, #4]
 8003586:	2200      	movs	r2, #0
 8003588:	f883 2020 	strb.w	r2, [r3, #32]

  return HAL_OK;
 800358c:	2300      	movs	r3, #0
}
 800358e:	4618      	mov	r0, r3
 8003590:	3714      	adds	r7, #20
 8003592:	46bd      	mov	sp, r7
 8003594:	bc80      	pop	{r7}
 8003596:	4770      	bx	lr
 8003598:	bffd9ff8 	.word	0xbffd9ff8
 800359c:	cccccccd 	.word	0xcccccccd
 80035a0:	40026000 	.word	0x40026000

080035a4 <HAL_DMA_Start_IT>:
  * @param  DstAddress The destination memory Buffer address
  * @param  DataLength The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 80035a4:	b580      	push	{r7, lr}
 80035a6:	b086      	sub	sp, #24
 80035a8:	af00      	add	r7, sp, #0
 80035aa:	60f8      	str	r0, [r7, #12]
 80035ac:	60b9      	str	r1, [r7, #8]
 80035ae:	607a      	str	r2, [r7, #4]
 80035b0:	603b      	str	r3, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80035b2:	2300      	movs	r3, #0
 80035b4:	75fb      	strb	r3, [r7, #23]

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 80035b6:	68fb      	ldr	r3, [r7, #12]
 80035b8:	f893 3020 	ldrb.w	r3, [r3, #32]
 80035bc:	2b01      	cmp	r3, #1
 80035be:	d101      	bne.n	80035c4 <HAL_DMA_Start_IT+0x20>
 80035c0:	2302      	movs	r3, #2
 80035c2:	e04b      	b.n	800365c <HAL_DMA_Start_IT+0xb8>
 80035c4:	68fb      	ldr	r3, [r7, #12]
 80035c6:	2201      	movs	r2, #1
 80035c8:	f883 2020 	strb.w	r2, [r3, #32]

  if(HAL_DMA_STATE_READY == hdma->State)
 80035cc:	68fb      	ldr	r3, [r7, #12]
 80035ce:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 80035d2:	b2db      	uxtb	r3, r3
 80035d4:	2b01      	cmp	r3, #1
 80035d6:	d13a      	bne.n	800364e <HAL_DMA_Start_IT+0xaa>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 80035d8:	68fb      	ldr	r3, [r7, #12]
 80035da:	2202      	movs	r2, #2
 80035dc:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80035e0:	68fb      	ldr	r3, [r7, #12]
 80035e2:	2200      	movs	r2, #0
 80035e4:	639a      	str	r2, [r3, #56]	; 0x38

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 80035e6:	68fb      	ldr	r3, [r7, #12]
 80035e8:	681b      	ldr	r3, [r3, #0]
 80035ea:	681a      	ldr	r2, [r3, #0]
 80035ec:	68fb      	ldr	r3, [r7, #12]
 80035ee:	681b      	ldr	r3, [r3, #0]
 80035f0:	f022 0201 	bic.w	r2, r2, #1
 80035f4:	601a      	str	r2, [r3, #0]

    /* Configure the source, destination address and the data length & clear flags*/
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 80035f6:	683b      	ldr	r3, [r7, #0]
 80035f8:	687a      	ldr	r2, [r7, #4]
 80035fa:	68b9      	ldr	r1, [r7, #8]
 80035fc:	68f8      	ldr	r0, [r7, #12]
 80035fe:	f000 f91d 	bl	800383c <DMA_SetConfig>

    /* Enable the transfer complete interrupt */
    /* Enable the transfer Error interrupt */
    if(NULL != hdma->XferHalfCpltCallback )
 8003602:	68fb      	ldr	r3, [r7, #12]
 8003604:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8003606:	2b00      	cmp	r3, #0
 8003608:	d008      	beq.n	800361c <HAL_DMA_Start_IT+0x78>
    {
      /* Enable the Half transfer complete interrupt as well */
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800360a:	68fb      	ldr	r3, [r7, #12]
 800360c:	681b      	ldr	r3, [r3, #0]
 800360e:	681a      	ldr	r2, [r3, #0]
 8003610:	68fb      	ldr	r3, [r7, #12]
 8003612:	681b      	ldr	r3, [r3, #0]
 8003614:	f042 020e 	orr.w	r2, r2, #14
 8003618:	601a      	str	r2, [r3, #0]
 800361a:	e00f      	b.n	800363c <HAL_DMA_Start_IT+0x98>
    }
    else
    {
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 800361c:	68fb      	ldr	r3, [r7, #12]
 800361e:	681b      	ldr	r3, [r3, #0]
 8003620:	681a      	ldr	r2, [r3, #0]
 8003622:	68fb      	ldr	r3, [r7, #12]
 8003624:	681b      	ldr	r3, [r3, #0]
 8003626:	f022 0204 	bic.w	r2, r2, #4
 800362a:	601a      	str	r2, [r3, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 800362c:	68fb      	ldr	r3, [r7, #12]
 800362e:	681b      	ldr	r3, [r3, #0]
 8003630:	681a      	ldr	r2, [r3, #0]
 8003632:	68fb      	ldr	r3, [r7, #12]
 8003634:	681b      	ldr	r3, [r3, #0]
 8003636:	f042 020a 	orr.w	r2, r2, #10
 800363a:	601a      	str	r2, [r3, #0]
    }

    /* Enable the Peripheral */
    __HAL_DMA_ENABLE(hdma);
 800363c:	68fb      	ldr	r3, [r7, #12]
 800363e:	681b      	ldr	r3, [r3, #0]
 8003640:	681a      	ldr	r2, [r3, #0]
 8003642:	68fb      	ldr	r3, [r7, #12]
 8003644:	681b      	ldr	r3, [r3, #0]
 8003646:	f042 0201 	orr.w	r2, r2, #1
 800364a:	601a      	str	r2, [r3, #0]
 800364c:	e005      	b.n	800365a <HAL_DMA_Start_IT+0xb6>
  }
  else
  {
    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 800364e:	68fb      	ldr	r3, [r7, #12]
 8003650:	2200      	movs	r2, #0
 8003652:	f883 2020 	strb.w	r2, [r3, #32]

    /* Remain BUSY */
    status = HAL_BUSY;
 8003656:	2302      	movs	r3, #2
 8003658:	75fb      	strb	r3, [r7, #23]
  }
  return status;
 800365a:	7dfb      	ldrb	r3, [r7, #23]
}
 800365c:	4618      	mov	r0, r3
 800365e:	3718      	adds	r7, #24
 8003660:	46bd      	mov	sp, r7
 8003662:	bd80      	pop	{r7, pc}

08003664 <HAL_DMA_Abort>:
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
 8003664:	b480      	push	{r7}
 8003666:	b085      	sub	sp, #20
 8003668:	af00      	add	r7, sp, #0
 800366a:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 800366c:	2300      	movs	r3, #0
 800366e:	73fb      	strb	r3, [r7, #15]

  /* Check the DMA peripheral state */
  if(hdma->State != HAL_DMA_STATE_BUSY)
 8003670:	687b      	ldr	r3, [r7, #4]
 8003672:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8003676:	b2db      	uxtb	r3, r3
 8003678:	2b02      	cmp	r3, #2
 800367a:	d008      	beq.n	800368e <HAL_DMA_Abort+0x2a>
  {
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 800367c:	687b      	ldr	r3, [r7, #4]
 800367e:	2204      	movs	r2, #4
 8003680:	639a      	str	r2, [r3, #56]	; 0x38

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8003682:	687b      	ldr	r3, [r7, #4]
 8003684:	2200      	movs	r2, #0
 8003686:	f883 2020 	strb.w	r2, [r3, #32]

    return HAL_ERROR;
 800368a:	2301      	movs	r3, #1
 800368c:	e022      	b.n	80036d4 <HAL_DMA_Abort+0x70>
  }
  else
  {
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800368e:	687b      	ldr	r3, [r7, #4]
 8003690:	681b      	ldr	r3, [r3, #0]
 8003692:	681a      	ldr	r2, [r3, #0]
 8003694:	687b      	ldr	r3, [r7, #4]
 8003696:	681b      	ldr	r3, [r3, #0]
 8003698:	f022 020e 	bic.w	r2, r2, #14
 800369c:	601a      	str	r2, [r3, #0]

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);
 800369e:	687b      	ldr	r3, [r7, #4]
 80036a0:	681b      	ldr	r3, [r3, #0]
 80036a2:	681a      	ldr	r2, [r3, #0]
 80036a4:	687b      	ldr	r3, [r7, #4]
 80036a6:	681b      	ldr	r3, [r3, #0]
 80036a8:	f022 0201 	bic.w	r2, r2, #1
 80036ac:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 80036ae:	687b      	ldr	r3, [r7, #4]
 80036b0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80036b2:	f003 021c 	and.w	r2, r3, #28
 80036b6:	687b      	ldr	r3, [r7, #4]
 80036b8:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80036ba:	2101      	movs	r1, #1
 80036bc:	fa01 f202 	lsl.w	r2, r1, r2
 80036c0:	605a      	str	r2, [r3, #4]

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 80036c2:	687b      	ldr	r3, [r7, #4]
 80036c4:	2201      	movs	r2, #1
 80036c6:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 80036ca:	687b      	ldr	r3, [r7, #4]
 80036cc:	2200      	movs	r2, #0
 80036ce:	f883 2020 	strb.w	r2, [r3, #32]

    return status;
 80036d2:	7bfb      	ldrb	r3, [r7, #15]
  }
}
 80036d4:	4618      	mov	r0, r3
 80036d6:	3714      	adds	r7, #20
 80036d8:	46bd      	mov	sp, r7
 80036da:	bc80      	pop	{r7}
 80036dc:	4770      	bx	lr

080036de <HAL_DMA_IRQHandler>:
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval None
  */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
 80036de:	b580      	push	{r7, lr}
 80036e0:	b084      	sub	sp, #16
 80036e2:	af00      	add	r7, sp, #0
 80036e4:	6078      	str	r0, [r7, #4]
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80036e6:	687b      	ldr	r3, [r7, #4]
 80036e8:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80036ea:	681b      	ldr	r3, [r3, #0]
 80036ec:	60fb      	str	r3, [r7, #12]
  uint32_t source_it = hdma->Instance->CCR;
 80036ee:	687b      	ldr	r3, [r7, #4]
 80036f0:	681b      	ldr	r3, [r3, #0]
 80036f2:	681b      	ldr	r3, [r3, #0]
 80036f4:	60bb      	str	r3, [r7, #8]

  /* Half Transfer Complete Interrupt management ******************************/
  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
 80036f6:	687b      	ldr	r3, [r7, #4]
 80036f8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80036fa:	f003 031c 	and.w	r3, r3, #28
 80036fe:	2204      	movs	r2, #4
 8003700:	409a      	lsls	r2, r3
 8003702:	68fb      	ldr	r3, [r7, #12]
 8003704:	4013      	ands	r3, r2
 8003706:	2b00      	cmp	r3, #0
 8003708:	d026      	beq.n	8003758 <HAL_DMA_IRQHandler+0x7a>
 800370a:	68bb      	ldr	r3, [r7, #8]
 800370c:	f003 0304 	and.w	r3, r3, #4
 8003710:	2b00      	cmp	r3, #0
 8003712:	d021      	beq.n	8003758 <HAL_DMA_IRQHandler+0x7a>
  {
    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8003714:	687b      	ldr	r3, [r7, #4]
 8003716:	681b      	ldr	r3, [r3, #0]
 8003718:	681b      	ldr	r3, [r3, #0]
 800371a:	f003 0320 	and.w	r3, r3, #32
 800371e:	2b00      	cmp	r3, #0
 8003720:	d107      	bne.n	8003732 <HAL_DMA_IRQHandler+0x54>
    {
      /* Disable the half transfer interrupt */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 8003722:	687b      	ldr	r3, [r7, #4]
 8003724:	681b      	ldr	r3, [r3, #0]
 8003726:	681a      	ldr	r2, [r3, #0]
 8003728:	687b      	ldr	r3, [r7, #4]
 800372a:	681b      	ldr	r3, [r3, #0]
 800372c:	f022 0204 	bic.w	r2, r2, #4
 8003730:	601a      	str	r2, [r3, #0]
    }
    /* Clear the half transfer complete flag */
    hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
 8003732:	687b      	ldr	r3, [r7, #4]
 8003734:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8003736:	f003 021c 	and.w	r2, r3, #28
 800373a:	687b      	ldr	r3, [r7, #4]
 800373c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 800373e:	2104      	movs	r1, #4
 8003740:	fa01 f202 	lsl.w	r2, r1, r2
 8003744:	605a      	str	r2, [r3, #4]

    /* DMA peripheral state is not updated in Half Transfer */
    /* but in Transfer Complete case */

    if(hdma->XferHalfCpltCallback != NULL)
 8003746:	687b      	ldr	r3, [r7, #4]
 8003748:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800374a:	2b00      	cmp	r3, #0
 800374c:	d071      	beq.n	8003832 <HAL_DMA_IRQHandler+0x154>
    {
      /* Half transfer callback */
      hdma->XferHalfCpltCallback(hdma);
 800374e:	687b      	ldr	r3, [r7, #4]
 8003750:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8003752:	6878      	ldr	r0, [r7, #4]
 8003754:	4798      	blx	r3
    if(hdma->XferHalfCpltCallback != NULL)
 8003756:	e06c      	b.n	8003832 <HAL_DMA_IRQHandler+0x154>
    }
  }

  /* Transfer Complete Interrupt management ***********************************/
  else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
 8003758:	687b      	ldr	r3, [r7, #4]
 800375a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800375c:	f003 031c 	and.w	r3, r3, #28
 8003760:	2202      	movs	r2, #2
 8003762:	409a      	lsls	r2, r3
 8003764:	68fb      	ldr	r3, [r7, #12]
 8003766:	4013      	ands	r3, r2
 8003768:	2b00      	cmp	r3, #0
 800376a:	d02e      	beq.n	80037ca <HAL_DMA_IRQHandler+0xec>
 800376c:	68bb      	ldr	r3, [r7, #8]
 800376e:	f003 0302 	and.w	r3, r3, #2
 8003772:	2b00      	cmp	r3, #0
 8003774:	d029      	beq.n	80037ca <HAL_DMA_IRQHandler+0xec>
  {
    
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8003776:	687b      	ldr	r3, [r7, #4]
 8003778:	681b      	ldr	r3, [r3, #0]
 800377a:	681b      	ldr	r3, [r3, #0]
 800377c:	f003 0320 	and.w	r3, r3, #32
 8003780:	2b00      	cmp	r3, #0
 8003782:	d10b      	bne.n	800379c <HAL_DMA_IRQHandler+0xbe>
    {
      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
      /* Disable the transfer complete and error interrupt */
      /* if the DMA mode is not CIRCULAR  */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 8003784:	687b      	ldr	r3, [r7, #4]
 8003786:	681b      	ldr	r3, [r3, #0]
 8003788:	681a      	ldr	r2, [r3, #0]
 800378a:	687b      	ldr	r3, [r7, #4]
 800378c:	681b      	ldr	r3, [r3, #0]
 800378e:	f022 020a 	bic.w	r2, r2, #10
 8003792:	601a      	str	r2, [r3, #0]

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
 8003794:	687b      	ldr	r3, [r7, #4]
 8003796:	2201      	movs	r2, #1
 8003798:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
    }
    /* Clear the transfer complete flag */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
 800379c:	687b      	ldr	r3, [r7, #4]
 800379e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80037a0:	f003 021c 	and.w	r2, r3, #28
 80037a4:	687b      	ldr	r3, [r7, #4]
 80037a6:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80037a8:	2102      	movs	r1, #2
 80037aa:	fa01 f202 	lsl.w	r2, r1, r2
 80037ae:	605a      	str	r2, [r3, #4]

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 80037b0:	687b      	ldr	r3, [r7, #4]
 80037b2:	2200      	movs	r2, #0
 80037b4:	f883 2020 	strb.w	r2, [r3, #32]

    if(hdma->XferCpltCallback != NULL)
 80037b8:	687b      	ldr	r3, [r7, #4]
 80037ba:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80037bc:	2b00      	cmp	r3, #0
 80037be:	d038      	beq.n	8003832 <HAL_DMA_IRQHandler+0x154>
    {
      /* Transfer complete callback */
      hdma->XferCpltCallback(hdma);
 80037c0:	687b      	ldr	r3, [r7, #4]
 80037c2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80037c4:	6878      	ldr	r0, [r7, #4]
 80037c6:	4798      	blx	r3
    if(hdma->XferCpltCallback != NULL)
 80037c8:	e033      	b.n	8003832 <HAL_DMA_IRQHandler+0x154>
    }
  }

  /* Transfer Error Interrupt management **************************************/
  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) !=  0U))
 80037ca:	687b      	ldr	r3, [r7, #4]
 80037cc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80037ce:	f003 031c 	and.w	r3, r3, #28
 80037d2:	2208      	movs	r2, #8
 80037d4:	409a      	lsls	r2, r3
 80037d6:	68fb      	ldr	r3, [r7, #12]
 80037d8:	4013      	ands	r3, r2
 80037da:	2b00      	cmp	r3, #0
 80037dc:	d02a      	beq.n	8003834 <HAL_DMA_IRQHandler+0x156>
 80037de:	68bb      	ldr	r3, [r7, #8]
 80037e0:	f003 0308 	and.w	r3, r3, #8
 80037e4:	2b00      	cmp	r3, #0
 80037e6:	d025      	beq.n	8003834 <HAL_DMA_IRQHandler+0x156>
  {
    /* When a DMA transfer error occurs */
    /* A hardware clear of its EN bits is performed */
    /* Disable ALL DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80037e8:	687b      	ldr	r3, [r7, #4]
 80037ea:	681b      	ldr	r3, [r3, #0]
 80037ec:	681a      	ldr	r2, [r3, #0]
 80037ee:	687b      	ldr	r3, [r7, #4]
 80037f0:	681b      	ldr	r3, [r3, #0]
 80037f2:	f022 020e 	bic.w	r2, r2, #14
 80037f6:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 80037f8:	687b      	ldr	r3, [r7, #4]
 80037fa:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80037fc:	f003 021c 	and.w	r2, r3, #28
 8003800:	687b      	ldr	r3, [r7, #4]
 8003802:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8003804:	2101      	movs	r1, #1
 8003806:	fa01 f202 	lsl.w	r2, r1, r2
 800380a:	605a      	str	r2, [r3, #4]

    /* Update error code */
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 800380c:	687b      	ldr	r3, [r7, #4]
 800380e:	2201      	movs	r2, #1
 8003810:	639a      	str	r2, [r3, #56]	; 0x38

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 8003812:	687b      	ldr	r3, [r7, #4]
 8003814:	2201      	movs	r2, #1
 8003816:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 800381a:	687b      	ldr	r3, [r7, #4]
 800381c:	2200      	movs	r2, #0
 800381e:	f883 2020 	strb.w	r2, [r3, #32]

    if (hdma->XferErrorCallback != NULL)
 8003822:	687b      	ldr	r3, [r7, #4]
 8003824:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8003826:	2b00      	cmp	r3, #0
 8003828:	d004      	beq.n	8003834 <HAL_DMA_IRQHandler+0x156>
    {
      /* Transfer error callback */
      hdma->XferErrorCallback(hdma);
 800382a:	687b      	ldr	r3, [r7, #4]
 800382c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800382e:	6878      	ldr	r0, [r7, #4]
 8003830:	4798      	blx	r3
  }
  else
  {
    /* Nothing To Do */
  }
  return;
 8003832:	bf00      	nop
 8003834:	bf00      	nop
}
 8003836:	3710      	adds	r7, #16
 8003838:	46bd      	mov	sp, r7
 800383a:	bd80      	pop	{r7, pc}

0800383c <DMA_SetConfig>:
  * @param  DstAddress The destination memory Buffer address
  * @param  DataLength The length of data to be transferred from source to destination
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 800383c:	b480      	push	{r7}
 800383e:	b085      	sub	sp, #20
 8003840:	af00      	add	r7, sp, #0
 8003842:	60f8      	str	r0, [r7, #12]
 8003844:	60b9      	str	r1, [r7, #8]
 8003846:	607a      	str	r2, [r7, #4]
 8003848:	603b      	str	r3, [r7, #0]
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 800384a:	68fb      	ldr	r3, [r7, #12]
 800384c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800384e:	f003 021c 	and.w	r2, r3, #28
 8003852:	68fb      	ldr	r3, [r7, #12]
 8003854:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8003856:	2101      	movs	r1, #1
 8003858:	fa01 f202 	lsl.w	r2, r1, r2
 800385c:	605a      	str	r2, [r3, #4]

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 800385e:	68fb      	ldr	r3, [r7, #12]
 8003860:	681b      	ldr	r3, [r3, #0]
 8003862:	683a      	ldr	r2, [r7, #0]
 8003864:	605a      	str	r2, [r3, #4]

  /* Memory to Peripheral */
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 8003866:	68fb      	ldr	r3, [r7, #12]
 8003868:	685b      	ldr	r3, [r3, #4]
 800386a:	2b10      	cmp	r3, #16
 800386c:	d108      	bne.n	8003880 <DMA_SetConfig+0x44>
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 800386e:	68fb      	ldr	r3, [r7, #12]
 8003870:	681b      	ldr	r3, [r3, #0]
 8003872:	687a      	ldr	r2, [r7, #4]
 8003874:	609a      	str	r2, [r3, #8]

    /* Configure DMA Channel source address */
    hdma->Instance->CMAR = SrcAddress;
 8003876:	68fb      	ldr	r3, [r7, #12]
 8003878:	681b      	ldr	r3, [r3, #0]
 800387a:	68ba      	ldr	r2, [r7, #8]
 800387c:	60da      	str	r2, [r3, #12]
    hdma->Instance->CPAR = SrcAddress;

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
  }
}
 800387e:	e007      	b.n	8003890 <DMA_SetConfig+0x54>
    hdma->Instance->CPAR = SrcAddress;
 8003880:	68fb      	ldr	r3, [r7, #12]
 8003882:	681b      	ldr	r3, [r3, #0]
 8003884:	68ba      	ldr	r2, [r7, #8]
 8003886:	609a      	str	r2, [r3, #8]
    hdma->Instance->CMAR = DstAddress;
 8003888:	68fb      	ldr	r3, [r7, #12]
 800388a:	681b      	ldr	r3, [r3, #0]
 800388c:	687a      	ldr	r2, [r7, #4]
 800388e:	60da      	str	r2, [r3, #12]
}
 8003890:	bf00      	nop
 8003892:	3714      	adds	r7, #20
 8003894:	46bd      	mov	sp, r7
 8003896:	bc80      	pop	{r7}
 8003898:	4770      	bx	lr
	...

0800389c <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 800389c:	b480      	push	{r7}
 800389e:	b087      	sub	sp, #28
 80038a0:	af00      	add	r7, sp, #0
 80038a2:	6078      	str	r0, [r7, #4]
 80038a4:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00;
 80038a6:	2300      	movs	r3, #0
 80038a8:	617b      	str	r3, [r7, #20]
  uint32_t iocurrent = 0x00;
 80038aa:	2300      	movs	r3, #0
 80038ac:	60fb      	str	r3, [r7, #12]
  uint32_t temp = 0x00;
 80038ae:	2300      	movs	r3, #0
 80038b0:	613b      	str	r3, [r7, #16]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0)
 80038b2:	e154      	b.n	8003b5e <HAL_GPIO_Init+0x2c2>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1U << position);
 80038b4:	683b      	ldr	r3, [r7, #0]
 80038b6:	681a      	ldr	r2, [r3, #0]
 80038b8:	2101      	movs	r1, #1
 80038ba:	697b      	ldr	r3, [r7, #20]
 80038bc:	fa01 f303 	lsl.w	r3, r1, r3
 80038c0:	4013      	ands	r3, r2
 80038c2:	60fb      	str	r3, [r7, #12]

    if (iocurrent)
 80038c4:	68fb      	ldr	r3, [r7, #12]
 80038c6:	2b00      	cmp	r3, #0
 80038c8:	f000 8146 	beq.w	8003b58 <HAL_GPIO_Init+0x2bc>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
 80038cc:	683b      	ldr	r3, [r7, #0]
 80038ce:	685b      	ldr	r3, [r3, #4]
 80038d0:	f003 0303 	and.w	r3, r3, #3
 80038d4:	2b01      	cmp	r3, #1
 80038d6:	d005      	beq.n	80038e4 <HAL_GPIO_Init+0x48>
          ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 80038d8:	683b      	ldr	r3, [r7, #0]
 80038da:	685b      	ldr	r3, [r3, #4]
 80038dc:	f003 0303 	and.w	r3, r3, #3
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
 80038e0:	2b02      	cmp	r3, #2
 80038e2:	d130      	bne.n	8003946 <HAL_GPIO_Init+0xaa>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 80038e4:	687b      	ldr	r3, [r7, #4]
 80038e6:	689b      	ldr	r3, [r3, #8]
 80038e8:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
 80038ea:	697b      	ldr	r3, [r7, #20]
 80038ec:	005b      	lsls	r3, r3, #1
 80038ee:	2203      	movs	r2, #3
 80038f0:	fa02 f303 	lsl.w	r3, r2, r3
 80038f4:	43db      	mvns	r3, r3
 80038f6:	693a      	ldr	r2, [r7, #16]
 80038f8:	4013      	ands	r3, r2
 80038fa:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, GPIO_Init->Speed << (position * 2));
 80038fc:	683b      	ldr	r3, [r7, #0]
 80038fe:	68da      	ldr	r2, [r3, #12]
 8003900:	697b      	ldr	r3, [r7, #20]
 8003902:	005b      	lsls	r3, r3, #1
 8003904:	fa02 f303 	lsl.w	r3, r2, r3
 8003908:	693a      	ldr	r2, [r7, #16]
 800390a:	4313      	orrs	r3, r2
 800390c:	613b      	str	r3, [r7, #16]
        GPIOx->OSPEEDR = temp;
 800390e:	687b      	ldr	r3, [r7, #4]
 8003910:	693a      	ldr	r2, [r7, #16]
 8003912:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8003914:	687b      	ldr	r3, [r7, #4]
 8003916:	685b      	ldr	r3, [r3, #4]
 8003918:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
 800391a:	2201      	movs	r2, #1
 800391c:	697b      	ldr	r3, [r7, #20]
 800391e:	fa02 f303 	lsl.w	r3, r2, r3
 8003922:	43db      	mvns	r3, r3
 8003924:	693a      	ldr	r2, [r7, #16]
 8003926:	4013      	ands	r3, r2
 8003928:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 800392a:	683b      	ldr	r3, [r7, #0]
 800392c:	685b      	ldr	r3, [r3, #4]
 800392e:	091b      	lsrs	r3, r3, #4
 8003930:	f003 0201 	and.w	r2, r3, #1
 8003934:	697b      	ldr	r3, [r7, #20]
 8003936:	fa02 f303 	lsl.w	r3, r2, r3
 800393a:	693a      	ldr	r2, [r7, #16]
 800393c:	4313      	orrs	r3, r2
 800393e:	613b      	str	r3, [r7, #16]
        GPIOx->OTYPER = temp;
 8003940:	687b      	ldr	r3, [r7, #4]
 8003942:	693a      	ldr	r2, [r7, #16]
 8003944:	605a      	str	r2, [r3, #4]
      }

      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8003946:	683b      	ldr	r3, [r7, #0]
 8003948:	685b      	ldr	r3, [r3, #4]
 800394a:	f003 0303 	and.w	r3, r3, #3
 800394e:	2b03      	cmp	r3, #3
 8003950:	d017      	beq.n	8003982 <HAL_GPIO_Init+0xe6>
      {
        /* Check the Pull parameter */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

        /* Activate the Pull-up or Pull down resistor for the current IO */
        temp = GPIOx->PUPDR;
 8003952:	687b      	ldr	r3, [r7, #4]
 8003954:	68db      	ldr	r3, [r3, #12]
 8003956:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
 8003958:	697b      	ldr	r3, [r7, #20]
 800395a:	005b      	lsls	r3, r3, #1
 800395c:	2203      	movs	r2, #3
 800395e:	fa02 f303 	lsl.w	r3, r2, r3
 8003962:	43db      	mvns	r3, r3
 8003964:	693a      	ldr	r2, [r7, #16]
 8003966:	4013      	ands	r3, r2
 8003968:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
 800396a:	683b      	ldr	r3, [r7, #0]
 800396c:	689a      	ldr	r2, [r3, #8]
 800396e:	697b      	ldr	r3, [r7, #20]
 8003970:	005b      	lsls	r3, r3, #1
 8003972:	fa02 f303 	lsl.w	r3, r2, r3
 8003976:	693a      	ldr	r2, [r7, #16]
 8003978:	4313      	orrs	r3, r2
 800397a:	613b      	str	r3, [r7, #16]
        GPIOx->PUPDR = temp;
 800397c:	687b      	ldr	r3, [r7, #4]
 800397e:	693a      	ldr	r2, [r7, #16]
 8003980:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8003982:	683b      	ldr	r3, [r7, #0]
 8003984:	685b      	ldr	r3, [r3, #4]
 8003986:	f003 0303 	and.w	r3, r3, #3
 800398a:	2b02      	cmp	r3, #2
 800398c:	d123      	bne.n	80039d6 <HAL_GPIO_Init+0x13a>
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        /* Identify AFRL or AFRH register based on IO position*/
        temp = GPIOx->AFR[position >> 3];
 800398e:	697b      	ldr	r3, [r7, #20]
 8003990:	08da      	lsrs	r2, r3, #3
 8003992:	687b      	ldr	r3, [r7, #4]
 8003994:	3208      	adds	r2, #8
 8003996:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 800399a:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
 800399c:	697b      	ldr	r3, [r7, #20]
 800399e:	f003 0307 	and.w	r3, r3, #7
 80039a2:	009b      	lsls	r3, r3, #2
 80039a4:	220f      	movs	r2, #15
 80039a6:	fa02 f303 	lsl.w	r3, r2, r3
 80039aa:	43db      	mvns	r3, r3
 80039ac:	693a      	ldr	r2, [r7, #16]
 80039ae:	4013      	ands	r3, r2
 80039b0:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
 80039b2:	683b      	ldr	r3, [r7, #0]
 80039b4:	691a      	ldr	r2, [r3, #16]
 80039b6:	697b      	ldr	r3, [r7, #20]
 80039b8:	f003 0307 	and.w	r3, r3, #7
 80039bc:	009b      	lsls	r3, r3, #2
 80039be:	fa02 f303 	lsl.w	r3, r2, r3
 80039c2:	693a      	ldr	r2, [r7, #16]
 80039c4:	4313      	orrs	r3, r2
 80039c6:	613b      	str	r3, [r7, #16]
        GPIOx->AFR[position >> 3] = temp;
 80039c8:	697b      	ldr	r3, [r7, #20]
 80039ca:	08da      	lsrs	r2, r3, #3
 80039cc:	687b      	ldr	r3, [r7, #4]
 80039ce:	3208      	adds	r2, #8
 80039d0:	6939      	ldr	r1, [r7, #16]
 80039d2:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 80039d6:	687b      	ldr	r3, [r7, #4]
 80039d8:	681b      	ldr	r3, [r3, #0]
 80039da:	613b      	str	r3, [r7, #16]
      CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
 80039dc:	697b      	ldr	r3, [r7, #20]
 80039de:	005b      	lsls	r3, r3, #1
 80039e0:	2203      	movs	r2, #3
 80039e2:	fa02 f303 	lsl.w	r3, r2, r3
 80039e6:	43db      	mvns	r3, r3
 80039e8:	693a      	ldr	r2, [r7, #16]
 80039ea:	4013      	ands	r3, r2
 80039ec:	613b      	str	r3, [r7, #16]
      SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
 80039ee:	683b      	ldr	r3, [r7, #0]
 80039f0:	685b      	ldr	r3, [r3, #4]
 80039f2:	f003 0203 	and.w	r2, r3, #3
 80039f6:	697b      	ldr	r3, [r7, #20]
 80039f8:	005b      	lsls	r3, r3, #1
 80039fa:	fa02 f303 	lsl.w	r3, r2, r3
 80039fe:	693a      	ldr	r2, [r7, #16]
 8003a00:	4313      	orrs	r3, r2
 8003a02:	613b      	str	r3, [r7, #16]
      GPIOx->MODER = temp;
 8003a04:	687b      	ldr	r3, [r7, #4]
 8003a06:	693a      	ldr	r2, [r7, #16]
 8003a08:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
 8003a0a:	683b      	ldr	r3, [r7, #0]
 8003a0c:	685b      	ldr	r3, [r3, #4]
 8003a0e:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8003a12:	2b00      	cmp	r3, #0
 8003a14:	f000 80a0 	beq.w	8003b58 <HAL_GPIO_Init+0x2bc>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8003a18:	4b58      	ldr	r3, [pc, #352]	; (8003b7c <HAL_GPIO_Init+0x2e0>)
 8003a1a:	6a1b      	ldr	r3, [r3, #32]
 8003a1c:	4a57      	ldr	r2, [pc, #348]	; (8003b7c <HAL_GPIO_Init+0x2e0>)
 8003a1e:	f043 0301 	orr.w	r3, r3, #1
 8003a22:	6213      	str	r3, [r2, #32]
 8003a24:	4b55      	ldr	r3, [pc, #340]	; (8003b7c <HAL_GPIO_Init+0x2e0>)
 8003a26:	6a1b      	ldr	r3, [r3, #32]
 8003a28:	f003 0301 	and.w	r3, r3, #1
 8003a2c:	60bb      	str	r3, [r7, #8]
 8003a2e:	68bb      	ldr	r3, [r7, #8]

        temp = SYSCFG->EXTICR[position >> 2];
 8003a30:	4a53      	ldr	r2, [pc, #332]	; (8003b80 <HAL_GPIO_Init+0x2e4>)
 8003a32:	697b      	ldr	r3, [r7, #20]
 8003a34:	089b      	lsrs	r3, r3, #2
 8003a36:	3302      	adds	r3, #2
 8003a38:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8003a3c:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
 8003a3e:	697b      	ldr	r3, [r7, #20]
 8003a40:	f003 0303 	and.w	r3, r3, #3
 8003a44:	009b      	lsls	r3, r3, #2
 8003a46:	220f      	movs	r2, #15
 8003a48:	fa02 f303 	lsl.w	r3, r2, r3
 8003a4c:	43db      	mvns	r3, r3
 8003a4e:	693a      	ldr	r2, [r7, #16]
 8003a50:	4013      	ands	r3, r2
 8003a52:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
 8003a54:	687b      	ldr	r3, [r7, #4]
 8003a56:	4a4b      	ldr	r2, [pc, #300]	; (8003b84 <HAL_GPIO_Init+0x2e8>)
 8003a58:	4293      	cmp	r3, r2
 8003a5a:	d019      	beq.n	8003a90 <HAL_GPIO_Init+0x1f4>
 8003a5c:	687b      	ldr	r3, [r7, #4]
 8003a5e:	4a4a      	ldr	r2, [pc, #296]	; (8003b88 <HAL_GPIO_Init+0x2ec>)
 8003a60:	4293      	cmp	r3, r2
 8003a62:	d013      	beq.n	8003a8c <HAL_GPIO_Init+0x1f0>
 8003a64:	687b      	ldr	r3, [r7, #4]
 8003a66:	4a49      	ldr	r2, [pc, #292]	; (8003b8c <HAL_GPIO_Init+0x2f0>)
 8003a68:	4293      	cmp	r3, r2
 8003a6a:	d00d      	beq.n	8003a88 <HAL_GPIO_Init+0x1ec>
 8003a6c:	687b      	ldr	r3, [r7, #4]
 8003a6e:	4a48      	ldr	r2, [pc, #288]	; (8003b90 <HAL_GPIO_Init+0x2f4>)
 8003a70:	4293      	cmp	r3, r2
 8003a72:	d007      	beq.n	8003a84 <HAL_GPIO_Init+0x1e8>
 8003a74:	687b      	ldr	r3, [r7, #4]
 8003a76:	4a47      	ldr	r2, [pc, #284]	; (8003b94 <HAL_GPIO_Init+0x2f8>)
 8003a78:	4293      	cmp	r3, r2
 8003a7a:	d101      	bne.n	8003a80 <HAL_GPIO_Init+0x1e4>
 8003a7c:	2304      	movs	r3, #4
 8003a7e:	e008      	b.n	8003a92 <HAL_GPIO_Init+0x1f6>
 8003a80:	2305      	movs	r3, #5
 8003a82:	e006      	b.n	8003a92 <HAL_GPIO_Init+0x1f6>
 8003a84:	2303      	movs	r3, #3
 8003a86:	e004      	b.n	8003a92 <HAL_GPIO_Init+0x1f6>
 8003a88:	2302      	movs	r3, #2
 8003a8a:	e002      	b.n	8003a92 <HAL_GPIO_Init+0x1f6>
 8003a8c:	2301      	movs	r3, #1
 8003a8e:	e000      	b.n	8003a92 <HAL_GPIO_Init+0x1f6>
 8003a90:	2300      	movs	r3, #0
 8003a92:	697a      	ldr	r2, [r7, #20]
 8003a94:	f002 0203 	and.w	r2, r2, #3
 8003a98:	0092      	lsls	r2, r2, #2
 8003a9a:	4093      	lsls	r3, r2
 8003a9c:	693a      	ldr	r2, [r7, #16]
 8003a9e:	4313      	orrs	r3, r2
 8003aa0:	613b      	str	r3, [r7, #16]
        SYSCFG->EXTICR[position >> 2] = temp;
 8003aa2:	4937      	ldr	r1, [pc, #220]	; (8003b80 <HAL_GPIO_Init+0x2e4>)
 8003aa4:	697b      	ldr	r3, [r7, #20]
 8003aa6:	089b      	lsrs	r3, r3, #2
 8003aa8:	3302      	adds	r3, #2
 8003aaa:	693a      	ldr	r2, [r7, #16]
 8003aac:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR;
 8003ab0:	4b39      	ldr	r3, [pc, #228]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003ab2:	681b      	ldr	r3, [r3, #0]
 8003ab4:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8003ab6:	68fb      	ldr	r3, [r7, #12]
 8003ab8:	43db      	mvns	r3, r3
 8003aba:	693a      	ldr	r2, [r7, #16]
 8003abc:	4013      	ands	r3, r2
 8003abe:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 8003ac0:	683b      	ldr	r3, [r7, #0]
 8003ac2:	685b      	ldr	r3, [r3, #4]
 8003ac4:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8003ac8:	2b00      	cmp	r3, #0
 8003aca:	d003      	beq.n	8003ad4 <HAL_GPIO_Init+0x238>
        {
          SET_BIT(temp, iocurrent);
 8003acc:	693a      	ldr	r2, [r7, #16]
 8003ace:	68fb      	ldr	r3, [r7, #12]
 8003ad0:	4313      	orrs	r3, r2
 8003ad2:	613b      	str	r3, [r7, #16]
        }
        EXTI->IMR = temp;
 8003ad4:	4a30      	ldr	r2, [pc, #192]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003ad6:	693b      	ldr	r3, [r7, #16]
 8003ad8:	6013      	str	r3, [r2, #0]

        temp = EXTI->EMR;
 8003ada:	4b2f      	ldr	r3, [pc, #188]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003adc:	685b      	ldr	r3, [r3, #4]
 8003ade:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8003ae0:	68fb      	ldr	r3, [r7, #12]
 8003ae2:	43db      	mvns	r3, r3
 8003ae4:	693a      	ldr	r2, [r7, #16]
 8003ae6:	4013      	ands	r3, r2
 8003ae8:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 8003aea:	683b      	ldr	r3, [r7, #0]
 8003aec:	685b      	ldr	r3, [r3, #4]
 8003aee:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8003af2:	2b00      	cmp	r3, #0
 8003af4:	d003      	beq.n	8003afe <HAL_GPIO_Init+0x262>
        {
          SET_BIT(temp, iocurrent);
 8003af6:	693a      	ldr	r2, [r7, #16]
 8003af8:	68fb      	ldr	r3, [r7, #12]
 8003afa:	4313      	orrs	r3, r2
 8003afc:	613b      	str	r3, [r7, #16]
        }
        EXTI->EMR = temp;
 8003afe:	4a26      	ldr	r2, [pc, #152]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003b00:	693b      	ldr	r3, [r7, #16]
 8003b02:	6053      	str	r3, [r2, #4]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 8003b04:	4b24      	ldr	r3, [pc, #144]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003b06:	689b      	ldr	r3, [r3, #8]
 8003b08:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8003b0a:	68fb      	ldr	r3, [r7, #12]
 8003b0c:	43db      	mvns	r3, r3
 8003b0e:	693a      	ldr	r2, [r7, #16]
 8003b10:	4013      	ands	r3, r2
 8003b12:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 8003b14:	683b      	ldr	r3, [r7, #0]
 8003b16:	685b      	ldr	r3, [r3, #4]
 8003b18:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 8003b1c:	2b00      	cmp	r3, #0
 8003b1e:	d003      	beq.n	8003b28 <HAL_GPIO_Init+0x28c>
        {
          SET_BIT(temp, iocurrent);
 8003b20:	693a      	ldr	r2, [r7, #16]
 8003b22:	68fb      	ldr	r3, [r7, #12]
 8003b24:	4313      	orrs	r3, r2
 8003b26:	613b      	str	r3, [r7, #16]
        }
        EXTI->RTSR = temp;
 8003b28:	4a1b      	ldr	r2, [pc, #108]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003b2a:	693b      	ldr	r3, [r7, #16]
 8003b2c:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR;
 8003b2e:	4b1a      	ldr	r3, [pc, #104]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003b30:	68db      	ldr	r3, [r3, #12]
 8003b32:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8003b34:	68fb      	ldr	r3, [r7, #12]
 8003b36:	43db      	mvns	r3, r3
 8003b38:	693a      	ldr	r2, [r7, #16]
 8003b3a:	4013      	ands	r3, r2
 8003b3c:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 8003b3e:	683b      	ldr	r3, [r7, #0]
 8003b40:	685b      	ldr	r3, [r3, #4]
 8003b42:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8003b46:	2b00      	cmp	r3, #0
 8003b48:	d003      	beq.n	8003b52 <HAL_GPIO_Init+0x2b6>
        {
          SET_BIT(temp, iocurrent);
 8003b4a:	693a      	ldr	r2, [r7, #16]
 8003b4c:	68fb      	ldr	r3, [r7, #12]
 8003b4e:	4313      	orrs	r3, r2
 8003b50:	613b      	str	r3, [r7, #16]
        }
        EXTI->FTSR = temp;
 8003b52:	4a11      	ldr	r2, [pc, #68]	; (8003b98 <HAL_GPIO_Init+0x2fc>)
 8003b54:	693b      	ldr	r3, [r7, #16]
 8003b56:	60d3      	str	r3, [r2, #12]
      }
    }

    position++;
 8003b58:	697b      	ldr	r3, [r7, #20]
 8003b5a:	3301      	adds	r3, #1
 8003b5c:	617b      	str	r3, [r7, #20]
  while (((GPIO_Init->Pin) >> position) != 0)
 8003b5e:	683b      	ldr	r3, [r7, #0]
 8003b60:	681a      	ldr	r2, [r3, #0]
 8003b62:	697b      	ldr	r3, [r7, #20]
 8003b64:	fa22 f303 	lsr.w	r3, r2, r3
 8003b68:	2b00      	cmp	r3, #0
 8003b6a:	f47f aea3 	bne.w	80038b4 <HAL_GPIO_Init+0x18>
  }
}
 8003b6e:	bf00      	nop
 8003b70:	bf00      	nop
 8003b72:	371c      	adds	r7, #28
 8003b74:	46bd      	mov	sp, r7
 8003b76:	bc80      	pop	{r7}
 8003b78:	4770      	bx	lr
 8003b7a:	bf00      	nop
 8003b7c:	40023800 	.word	0x40023800
 8003b80:	40010000 	.word	0x40010000
 8003b84:	40020000 	.word	0x40020000
 8003b88:	40020400 	.word	0x40020400
 8003b8c:	40020800 	.word	0x40020800
 8003b90:	40020c00 	.word	0x40020c00
 8003b94:	40021000 	.word	0x40021000
 8003b98:	40010400 	.word	0x40010400

08003b9c <HAL_GPIO_DeInit>:
  * @param  GPIO_Pin specifies the port bit to be written.
  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
  * @retval None
  */
void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
{
 8003b9c:	b480      	push	{r7}
 8003b9e:	b087      	sub	sp, #28
 8003ba0:	af00      	add	r7, sp, #0
 8003ba2:	6078      	str	r0, [r7, #4]
 8003ba4:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00;
 8003ba6:	2300      	movs	r3, #0
 8003ba8:	617b      	str	r3, [r7, #20]
  uint32_t iocurrent = 0x00;
 8003baa:	2300      	movs	r3, #0
 8003bac:	613b      	str	r3, [r7, #16]
  uint32_t tmp = 0x00;
 8003bae:	2300      	movs	r3, #0
 8003bb0:	60fb      	str	r3, [r7, #12]
  /* Check the parameters */
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* Configure the port pins */
  while ((GPIO_Pin >> position) != 0)
 8003bb2:	e0b8      	b.n	8003d26 <HAL_GPIO_DeInit+0x18a>
  {
    /* Get current io position */
    iocurrent = (GPIO_Pin) & (1U << position);
 8003bb4:	2201      	movs	r2, #1
 8003bb6:	697b      	ldr	r3, [r7, #20]
 8003bb8:	fa02 f303 	lsl.w	r3, r2, r3
 8003bbc:	683a      	ldr	r2, [r7, #0]
 8003bbe:	4013      	ands	r3, r2
 8003bc0:	613b      	str	r3, [r7, #16]

    if (iocurrent)
 8003bc2:	693b      	ldr	r3, [r7, #16]
 8003bc4:	2b00      	cmp	r3, #0
 8003bc6:	f000 80ab 	beq.w	8003d20 <HAL_GPIO_DeInit+0x184>
    {
      /*------------------------- EXTI Mode Configuration --------------------*/
      /* Clear the External Interrupt or Event for the current IO */

      tmp = SYSCFG->EXTICR[position >> 2];
 8003bca:	4a5d      	ldr	r2, [pc, #372]	; (8003d40 <HAL_GPIO_DeInit+0x1a4>)
 8003bcc:	697b      	ldr	r3, [r7, #20]
 8003bce:	089b      	lsrs	r3, r3, #2
 8003bd0:	3302      	adds	r3, #2
 8003bd2:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8003bd6:	60fb      	str	r3, [r7, #12]
      tmp &= ((0x0FU) << (4 * (position & 0x03)));
 8003bd8:	697b      	ldr	r3, [r7, #20]
 8003bda:	f003 0303 	and.w	r3, r3, #3
 8003bde:	009b      	lsls	r3, r3, #2
 8003be0:	220f      	movs	r2, #15
 8003be2:	fa02 f303 	lsl.w	r3, r2, r3
 8003be6:	68fa      	ldr	r2, [r7, #12]
 8003be8:	4013      	ands	r3, r2
 8003bea:	60fb      	str	r3, [r7, #12]
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
 8003bec:	687b      	ldr	r3, [r7, #4]
 8003bee:	4a55      	ldr	r2, [pc, #340]	; (8003d44 <HAL_GPIO_DeInit+0x1a8>)
 8003bf0:	4293      	cmp	r3, r2
 8003bf2:	d019      	beq.n	8003c28 <HAL_GPIO_DeInit+0x8c>
 8003bf4:	687b      	ldr	r3, [r7, #4]
 8003bf6:	4a54      	ldr	r2, [pc, #336]	; (8003d48 <HAL_GPIO_DeInit+0x1ac>)
 8003bf8:	4293      	cmp	r3, r2
 8003bfa:	d013      	beq.n	8003c24 <HAL_GPIO_DeInit+0x88>
 8003bfc:	687b      	ldr	r3, [r7, #4]
 8003bfe:	4a53      	ldr	r2, [pc, #332]	; (8003d4c <HAL_GPIO_DeInit+0x1b0>)
 8003c00:	4293      	cmp	r3, r2
 8003c02:	d00d      	beq.n	8003c20 <HAL_GPIO_DeInit+0x84>
 8003c04:	687b      	ldr	r3, [r7, #4]
 8003c06:	4a52      	ldr	r2, [pc, #328]	; (8003d50 <HAL_GPIO_DeInit+0x1b4>)
 8003c08:	4293      	cmp	r3, r2
 8003c0a:	d007      	beq.n	8003c1c <HAL_GPIO_DeInit+0x80>
 8003c0c:	687b      	ldr	r3, [r7, #4]
 8003c0e:	4a51      	ldr	r2, [pc, #324]	; (8003d54 <HAL_GPIO_DeInit+0x1b8>)
 8003c10:	4293      	cmp	r3, r2
 8003c12:	d101      	bne.n	8003c18 <HAL_GPIO_DeInit+0x7c>
 8003c14:	2304      	movs	r3, #4
 8003c16:	e008      	b.n	8003c2a <HAL_GPIO_DeInit+0x8e>
 8003c18:	2305      	movs	r3, #5
 8003c1a:	e006      	b.n	8003c2a <HAL_GPIO_DeInit+0x8e>
 8003c1c:	2303      	movs	r3, #3
 8003c1e:	e004      	b.n	8003c2a <HAL_GPIO_DeInit+0x8e>
 8003c20:	2302      	movs	r3, #2
 8003c22:	e002      	b.n	8003c2a <HAL_GPIO_DeInit+0x8e>
 8003c24:	2301      	movs	r3, #1
 8003c26:	e000      	b.n	8003c2a <HAL_GPIO_DeInit+0x8e>
 8003c28:	2300      	movs	r3, #0
 8003c2a:	697a      	ldr	r2, [r7, #20]
 8003c2c:	f002 0203 	and.w	r2, r2, #3
 8003c30:	0092      	lsls	r2, r2, #2
 8003c32:	4093      	lsls	r3, r2
 8003c34:	68fa      	ldr	r2, [r7, #12]
 8003c36:	429a      	cmp	r2, r3
 8003c38:	d132      	bne.n	8003ca0 <HAL_GPIO_DeInit+0x104>
      {
        /* Clear EXTI line configuration */
        CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
 8003c3a:	4b47      	ldr	r3, [pc, #284]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c3c:	681a      	ldr	r2, [r3, #0]
 8003c3e:	693b      	ldr	r3, [r7, #16]
 8003c40:	43db      	mvns	r3, r3
 8003c42:	4945      	ldr	r1, [pc, #276]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c44:	4013      	ands	r3, r2
 8003c46:	600b      	str	r3, [r1, #0]
        CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
 8003c48:	4b43      	ldr	r3, [pc, #268]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c4a:	685a      	ldr	r2, [r3, #4]
 8003c4c:	693b      	ldr	r3, [r7, #16]
 8003c4e:	43db      	mvns	r3, r3
 8003c50:	4941      	ldr	r1, [pc, #260]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c52:	4013      	ands	r3, r2
 8003c54:	604b      	str	r3, [r1, #4]

        /* Clear Rising Falling edge configuration */
        CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
 8003c56:	4b40      	ldr	r3, [pc, #256]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c58:	689a      	ldr	r2, [r3, #8]
 8003c5a:	693b      	ldr	r3, [r7, #16]
 8003c5c:	43db      	mvns	r3, r3
 8003c5e:	493e      	ldr	r1, [pc, #248]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c60:	4013      	ands	r3, r2
 8003c62:	608b      	str	r3, [r1, #8]
        CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
 8003c64:	4b3c      	ldr	r3, [pc, #240]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c66:	68da      	ldr	r2, [r3, #12]
 8003c68:	693b      	ldr	r3, [r7, #16]
 8003c6a:	43db      	mvns	r3, r3
 8003c6c:	493a      	ldr	r1, [pc, #232]	; (8003d58 <HAL_GPIO_DeInit+0x1bc>)
 8003c6e:	4013      	ands	r3, r2
 8003c70:	60cb      	str	r3, [r1, #12]

        tmp = (0x0FU) << (4 * (position & 0x03));
 8003c72:	697b      	ldr	r3, [r7, #20]
 8003c74:	f003 0303 	and.w	r3, r3, #3
 8003c78:	009b      	lsls	r3, r3, #2
 8003c7a:	220f      	movs	r2, #15
 8003c7c:	fa02 f303 	lsl.w	r3, r2, r3
 8003c80:	60fb      	str	r3, [r7, #12]
        CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
 8003c82:	4a2f      	ldr	r2, [pc, #188]	; (8003d40 <HAL_GPIO_DeInit+0x1a4>)
 8003c84:	697b      	ldr	r3, [r7, #20]
 8003c86:	089b      	lsrs	r3, r3, #2
 8003c88:	3302      	adds	r3, #2
 8003c8a:	f852 1023 	ldr.w	r1, [r2, r3, lsl #2]
 8003c8e:	68fb      	ldr	r3, [r7, #12]
 8003c90:	43da      	mvns	r2, r3
 8003c92:	482b      	ldr	r0, [pc, #172]	; (8003d40 <HAL_GPIO_DeInit+0x1a4>)
 8003c94:	697b      	ldr	r3, [r7, #20]
 8003c96:	089b      	lsrs	r3, r3, #2
 8003c98:	400a      	ands	r2, r1
 8003c9a:	3302      	adds	r3, #2
 8003c9c:	f840 2023 	str.w	r2, [r0, r3, lsl #2]
      }

      /*------------------------- GPIO Mode Configuration --------------------*/
      /* Configure IO Direction in Input Floting Mode */
      CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2));
 8003ca0:	687b      	ldr	r3, [r7, #4]
 8003ca2:	681a      	ldr	r2, [r3, #0]
 8003ca4:	697b      	ldr	r3, [r7, #20]
 8003ca6:	005b      	lsls	r3, r3, #1
 8003ca8:	2103      	movs	r1, #3
 8003caa:	fa01 f303 	lsl.w	r3, r1, r3
 8003cae:	43db      	mvns	r3, r3
 8003cb0:	401a      	ands	r2, r3
 8003cb2:	687b      	ldr	r3, [r7, #4]
 8003cb4:	601a      	str	r2, [r3, #0]

      /* Configure the default Alternate Function in current IO */
      CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;
 8003cb6:	697b      	ldr	r3, [r7, #20]
 8003cb8:	08da      	lsrs	r2, r3, #3
 8003cba:	687b      	ldr	r3, [r7, #4]
 8003cbc:	3208      	adds	r2, #8
 8003cbe:	f853 1022 	ldr.w	r1, [r3, r2, lsl #2]
 8003cc2:	697b      	ldr	r3, [r7, #20]
 8003cc4:	f003 0307 	and.w	r3, r3, #7
 8003cc8:	009b      	lsls	r3, r3, #2
 8003cca:	220f      	movs	r2, #15
 8003ccc:	fa02 f303 	lsl.w	r3, r2, r3
 8003cd0:	43db      	mvns	r3, r3
 8003cd2:	697a      	ldr	r2, [r7, #20]
 8003cd4:	08d2      	lsrs	r2, r2, #3
 8003cd6:	4019      	ands	r1, r3
 8003cd8:	687b      	ldr	r3, [r7, #4]
 8003cda:	3208      	adds	r2, #8
 8003cdc:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
      CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2));
 8003ce0:	687b      	ldr	r3, [r7, #4]
 8003ce2:	68da      	ldr	r2, [r3, #12]
 8003ce4:	697b      	ldr	r3, [r7, #20]
 8003ce6:	005b      	lsls	r3, r3, #1
 8003ce8:	2103      	movs	r1, #3
 8003cea:	fa01 f303 	lsl.w	r3, r1, r3
 8003cee:	43db      	mvns	r3, r3
 8003cf0:	401a      	ands	r2, r3
 8003cf2:	687b      	ldr	r3, [r7, #4]
 8003cf4:	60da      	str	r2, [r3, #12]

      /* Configure the default value IO Output Type */
      CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
 8003cf6:	687b      	ldr	r3, [r7, #4]
 8003cf8:	685a      	ldr	r2, [r3, #4]
 8003cfa:	2101      	movs	r1, #1
 8003cfc:	697b      	ldr	r3, [r7, #20]
 8003cfe:	fa01 f303 	lsl.w	r3, r1, r3
 8003d02:	43db      	mvns	r3, r3
 8003d04:	401a      	ands	r2, r3
 8003d06:	687b      	ldr	r3, [r7, #4]
 8003d08:	605a      	str	r2, [r3, #4]

      /* Configure the default value for IO Speed */
      CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
 8003d0a:	687b      	ldr	r3, [r7, #4]
 8003d0c:	689a      	ldr	r2, [r3, #8]
 8003d0e:	697b      	ldr	r3, [r7, #20]
 8003d10:	005b      	lsls	r3, r3, #1
 8003d12:	2103      	movs	r1, #3
 8003d14:	fa01 f303 	lsl.w	r3, r1, r3
 8003d18:	43db      	mvns	r3, r3
 8003d1a:	401a      	ands	r2, r3
 8003d1c:	687b      	ldr	r3, [r7, #4]
 8003d1e:	609a      	str	r2, [r3, #8]
    }

    position++;
 8003d20:	697b      	ldr	r3, [r7, #20]
 8003d22:	3301      	adds	r3, #1
 8003d24:	617b      	str	r3, [r7, #20]
  while ((GPIO_Pin >> position) != 0)
 8003d26:	683a      	ldr	r2, [r7, #0]
 8003d28:	697b      	ldr	r3, [r7, #20]
 8003d2a:	fa22 f303 	lsr.w	r3, r2, r3
 8003d2e:	2b00      	cmp	r3, #0
 8003d30:	f47f af40 	bne.w	8003bb4 <HAL_GPIO_DeInit+0x18>
  }
}
 8003d34:	bf00      	nop
 8003d36:	bf00      	nop
 8003d38:	371c      	adds	r7, #28
 8003d3a:	46bd      	mov	sp, r7
 8003d3c:	bc80      	pop	{r7}
 8003d3e:	4770      	bx	lr
 8003d40:	40010000 	.word	0x40010000
 8003d44:	40020000 	.word	0x40020000
 8003d48:	40020400 	.word	0x40020400
 8003d4c:	40020800 	.word	0x40020800
 8003d50:	40020c00 	.word	0x40020c00
 8003d54:	40021000 	.word	0x40021000
 8003d58:	40010400 	.word	0x40010400

08003d5c <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8003d5c:	b480      	push	{r7}
 8003d5e:	b083      	sub	sp, #12
 8003d60:	af00      	add	r7, sp, #0
 8003d62:	6078      	str	r0, [r7, #4]
 8003d64:	460b      	mov	r3, r1
 8003d66:	807b      	strh	r3, [r7, #2]
 8003d68:	4613      	mov	r3, r2
 8003d6a:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8003d6c:	787b      	ldrb	r3, [r7, #1]
 8003d6e:	2b00      	cmp	r3, #0
 8003d70:	d003      	beq.n	8003d7a <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8003d72:	887a      	ldrh	r2, [r7, #2]
 8003d74:	687b      	ldr	r3, [r7, #4]
 8003d76:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
  }
}
 8003d78:	e003      	b.n	8003d82 <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
 8003d7a:	887b      	ldrh	r3, [r7, #2]
 8003d7c:	041a      	lsls	r2, r3, #16
 8003d7e:	687b      	ldr	r3, [r7, #4]
 8003d80:	619a      	str	r2, [r3, #24]
}
 8003d82:	bf00      	nop
 8003d84:	370c      	adds	r7, #12
 8003d86:	46bd      	mov	sp, r7
 8003d88:	bc80      	pop	{r7}
 8003d8a:	4770      	bx	lr

08003d8c <HAL_GPIO_EXTI_IRQHandler>:
  * @brief  This function handles EXTI interrupt request.
  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
  * @retval None
  */
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
 8003d8c:	b580      	push	{r7, lr}
 8003d8e:	b082      	sub	sp, #8
 8003d90:	af00      	add	r7, sp, #0
 8003d92:	4603      	mov	r3, r0
 8003d94:	80fb      	strh	r3, [r7, #6]
  /* EXTI line interrupt detected */
  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
 8003d96:	4b08      	ldr	r3, [pc, #32]	; (8003db8 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
 8003d98:	695a      	ldr	r2, [r3, #20]
 8003d9a:	88fb      	ldrh	r3, [r7, #6]
 8003d9c:	4013      	ands	r3, r2
 8003d9e:	2b00      	cmp	r3, #0
 8003da0:	d006      	beq.n	8003db0 <HAL_GPIO_EXTI_IRQHandler+0x24>
  {
    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
 8003da2:	4a05      	ldr	r2, [pc, #20]	; (8003db8 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
 8003da4:	88fb      	ldrh	r3, [r7, #6]
 8003da6:	6153      	str	r3, [r2, #20]
    HAL_GPIO_EXTI_Callback(GPIO_Pin);
 8003da8:	88fb      	ldrh	r3, [r7, #6]
 8003daa:	4618      	mov	r0, r3
 8003dac:	f7fd f91e 	bl	8000fec <HAL_GPIO_EXTI_Callback>
  }
}
 8003db0:	bf00      	nop
 8003db2:	3708      	adds	r7, #8
 8003db4:	46bd      	mov	sp, r7
 8003db6:	bd80      	pop	{r7, pc}
 8003db8:	40010400 	.word	0x40010400

08003dbc <HAL_I2C_Init>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
 8003dbc:	b580      	push	{r7, lr}
 8003dbe:	b084      	sub	sp, #16
 8003dc0:	af00      	add	r7, sp, #0
 8003dc2:	6078      	str	r0, [r7, #4]
  uint32_t freqrange;
  uint32_t pclk1;

  /* Check the I2C handle allocation */
  if (hi2c == NULL)
 8003dc4:	687b      	ldr	r3, [r7, #4]
 8003dc6:	2b00      	cmp	r3, #0
 8003dc8:	d101      	bne.n	8003dce <HAL_I2C_Init+0x12>
  {
    return HAL_ERROR;
 8003dca:	2301      	movs	r3, #1
 8003dcc:	e12b      	b.n	8004026 <HAL_I2C_Init+0x26a>
  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if (hi2c->State == HAL_I2C_STATE_RESET)
 8003dce:	687b      	ldr	r3, [r7, #4]
 8003dd0:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8003dd4:	b2db      	uxtb	r3, r3
 8003dd6:	2b00      	cmp	r3, #0
 8003dd8:	d106      	bne.n	8003de8 <HAL_I2C_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    hi2c->Lock = HAL_UNLOCKED;
 8003dda:	687b      	ldr	r3, [r7, #4]
 8003ddc:	2200      	movs	r2, #0
 8003dde:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    hi2c->MspInitCallback(hi2c);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_I2C_MspInit(hi2c);
 8003de2:	6878      	ldr	r0, [r7, #4]
 8003de4:	f7fd ffd4 	bl	8001d90 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
  }

  hi2c->State = HAL_I2C_STATE_BUSY;
 8003de8:	687b      	ldr	r3, [r7, #4]
 8003dea:	2224      	movs	r2, #36	; 0x24
 8003dec:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);
 8003df0:	687b      	ldr	r3, [r7, #4]
 8003df2:	681b      	ldr	r3, [r3, #0]
 8003df4:	681a      	ldr	r2, [r3, #0]
 8003df6:	687b      	ldr	r3, [r7, #4]
 8003df8:	681b      	ldr	r3, [r3, #0]
 8003dfa:	f022 0201 	bic.w	r2, r2, #1
 8003dfe:	601a      	str	r2, [r3, #0]

  /*Reset I2C*/
  hi2c->Instance->CR1 |= I2C_CR1_SWRST;
 8003e00:	687b      	ldr	r3, [r7, #4]
 8003e02:	681b      	ldr	r3, [r3, #0]
 8003e04:	681a      	ldr	r2, [r3, #0]
 8003e06:	687b      	ldr	r3, [r7, #4]
 8003e08:	681b      	ldr	r3, [r3, #0]
 8003e0a:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
 8003e0e:	601a      	str	r2, [r3, #0]
  hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
 8003e10:	687b      	ldr	r3, [r7, #4]
 8003e12:	681b      	ldr	r3, [r3, #0]
 8003e14:	681a      	ldr	r2, [r3, #0]
 8003e16:	687b      	ldr	r3, [r7, #4]
 8003e18:	681b      	ldr	r3, [r3, #0]
 8003e1a:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
 8003e1e:	601a      	str	r2, [r3, #0]

  /* Get PCLK1 frequency */
  pclk1 = HAL_RCC_GetPCLK1Freq();
 8003e20:	f001 f9be 	bl	80051a0 <HAL_RCC_GetPCLK1Freq>
 8003e24:	60f8      	str	r0, [r7, #12]

  /* Check the minimum allowed PCLK1 frequency */
  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
 8003e26:	687b      	ldr	r3, [r7, #4]
 8003e28:	685b      	ldr	r3, [r3, #4]
 8003e2a:	4a81      	ldr	r2, [pc, #516]	; (8004030 <HAL_I2C_Init+0x274>)
 8003e2c:	4293      	cmp	r3, r2
 8003e2e:	d807      	bhi.n	8003e40 <HAL_I2C_Init+0x84>
 8003e30:	68fb      	ldr	r3, [r7, #12]
 8003e32:	4a80      	ldr	r2, [pc, #512]	; (8004034 <HAL_I2C_Init+0x278>)
 8003e34:	4293      	cmp	r3, r2
 8003e36:	bf94      	ite	ls
 8003e38:	2301      	movls	r3, #1
 8003e3a:	2300      	movhi	r3, #0
 8003e3c:	b2db      	uxtb	r3, r3
 8003e3e:	e006      	b.n	8003e4e <HAL_I2C_Init+0x92>
 8003e40:	68fb      	ldr	r3, [r7, #12]
 8003e42:	4a7d      	ldr	r2, [pc, #500]	; (8004038 <HAL_I2C_Init+0x27c>)
 8003e44:	4293      	cmp	r3, r2
 8003e46:	bf94      	ite	ls
 8003e48:	2301      	movls	r3, #1
 8003e4a:	2300      	movhi	r3, #0
 8003e4c:	b2db      	uxtb	r3, r3
 8003e4e:	2b00      	cmp	r3, #0
 8003e50:	d001      	beq.n	8003e56 <HAL_I2C_Init+0x9a>
  {
    return HAL_ERROR;
 8003e52:	2301      	movs	r3, #1
 8003e54:	e0e7      	b.n	8004026 <HAL_I2C_Init+0x26a>
  }

  /* Calculate frequency range */
  freqrange = I2C_FREQRANGE(pclk1);
 8003e56:	68fb      	ldr	r3, [r7, #12]
 8003e58:	4a78      	ldr	r2, [pc, #480]	; (800403c <HAL_I2C_Init+0x280>)
 8003e5a:	fba2 2303 	umull	r2, r3, r2, r3
 8003e5e:	0c9b      	lsrs	r3, r3, #18
 8003e60:	60bb      	str	r3, [r7, #8]

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Frequency range */
  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
 8003e62:	687b      	ldr	r3, [r7, #4]
 8003e64:	681b      	ldr	r3, [r3, #0]
 8003e66:	685b      	ldr	r3, [r3, #4]
 8003e68:	f023 013f 	bic.w	r1, r3, #63	; 0x3f
 8003e6c:	687b      	ldr	r3, [r7, #4]
 8003e6e:	681b      	ldr	r3, [r3, #0]
 8003e70:	68ba      	ldr	r2, [r7, #8]
 8003e72:	430a      	orrs	r2, r1
 8003e74:	605a      	str	r2, [r3, #4]

  /*---------------------------- I2Cx TRISE Configuration --------------------*/
  /* Configure I2Cx: Rise Time */
  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
 8003e76:	687b      	ldr	r3, [r7, #4]
 8003e78:	681b      	ldr	r3, [r3, #0]
 8003e7a:	6a1b      	ldr	r3, [r3, #32]
 8003e7c:	f023 013f 	bic.w	r1, r3, #63	; 0x3f
 8003e80:	687b      	ldr	r3, [r7, #4]
 8003e82:	685b      	ldr	r3, [r3, #4]
 8003e84:	4a6a      	ldr	r2, [pc, #424]	; (8004030 <HAL_I2C_Init+0x274>)
 8003e86:	4293      	cmp	r3, r2
 8003e88:	d802      	bhi.n	8003e90 <HAL_I2C_Init+0xd4>
 8003e8a:	68bb      	ldr	r3, [r7, #8]
 8003e8c:	3301      	adds	r3, #1
 8003e8e:	e009      	b.n	8003ea4 <HAL_I2C_Init+0xe8>
 8003e90:	68bb      	ldr	r3, [r7, #8]
 8003e92:	f44f 7296 	mov.w	r2, #300	; 0x12c
 8003e96:	fb02 f303 	mul.w	r3, r2, r3
 8003e9a:	4a69      	ldr	r2, [pc, #420]	; (8004040 <HAL_I2C_Init+0x284>)
 8003e9c:	fba2 2303 	umull	r2, r3, r2, r3
 8003ea0:	099b      	lsrs	r3, r3, #6
 8003ea2:	3301      	adds	r3, #1
 8003ea4:	687a      	ldr	r2, [r7, #4]
 8003ea6:	6812      	ldr	r2, [r2, #0]
 8003ea8:	430b      	orrs	r3, r1
 8003eaa:	6213      	str	r3, [r2, #32]

  /*---------------------------- I2Cx CCR Configuration ----------------------*/
  /* Configure I2Cx: Speed */
  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
 8003eac:	687b      	ldr	r3, [r7, #4]
 8003eae:	681b      	ldr	r3, [r3, #0]
 8003eb0:	69db      	ldr	r3, [r3, #28]
 8003eb2:	f423 424f 	bic.w	r2, r3, #52992	; 0xcf00
 8003eb6:	f022 02ff 	bic.w	r2, r2, #255	; 0xff
 8003eba:	687b      	ldr	r3, [r7, #4]
 8003ebc:	685b      	ldr	r3, [r3, #4]
 8003ebe:	495c      	ldr	r1, [pc, #368]	; (8004030 <HAL_I2C_Init+0x274>)
 8003ec0:	428b      	cmp	r3, r1
 8003ec2:	d819      	bhi.n	8003ef8 <HAL_I2C_Init+0x13c>
 8003ec4:	68fb      	ldr	r3, [r7, #12]
 8003ec6:	1e59      	subs	r1, r3, #1
 8003ec8:	687b      	ldr	r3, [r7, #4]
 8003eca:	685b      	ldr	r3, [r3, #4]
 8003ecc:	005b      	lsls	r3, r3, #1
 8003ece:	fbb1 f3f3 	udiv	r3, r1, r3
 8003ed2:	1c59      	adds	r1, r3, #1
 8003ed4:	f640 73fc 	movw	r3, #4092	; 0xffc
 8003ed8:	400b      	ands	r3, r1
 8003eda:	2b00      	cmp	r3, #0
 8003edc:	d00a      	beq.n	8003ef4 <HAL_I2C_Init+0x138>
 8003ede:	68fb      	ldr	r3, [r7, #12]
 8003ee0:	1e59      	subs	r1, r3, #1
 8003ee2:	687b      	ldr	r3, [r7, #4]
 8003ee4:	685b      	ldr	r3, [r3, #4]
 8003ee6:	005b      	lsls	r3, r3, #1
 8003ee8:	fbb1 f3f3 	udiv	r3, r1, r3
 8003eec:	3301      	adds	r3, #1
 8003eee:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8003ef2:	e051      	b.n	8003f98 <HAL_I2C_Init+0x1dc>
 8003ef4:	2304      	movs	r3, #4
 8003ef6:	e04f      	b.n	8003f98 <HAL_I2C_Init+0x1dc>
 8003ef8:	687b      	ldr	r3, [r7, #4]
 8003efa:	689b      	ldr	r3, [r3, #8]
 8003efc:	2b00      	cmp	r3, #0
 8003efe:	d111      	bne.n	8003f24 <HAL_I2C_Init+0x168>
 8003f00:	68fb      	ldr	r3, [r7, #12]
 8003f02:	1e58      	subs	r0, r3, #1
 8003f04:	687b      	ldr	r3, [r7, #4]
 8003f06:	6859      	ldr	r1, [r3, #4]
 8003f08:	460b      	mov	r3, r1
 8003f0a:	005b      	lsls	r3, r3, #1
 8003f0c:	440b      	add	r3, r1
 8003f0e:	fbb0 f3f3 	udiv	r3, r0, r3
 8003f12:	3301      	adds	r3, #1
 8003f14:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8003f18:	2b00      	cmp	r3, #0
 8003f1a:	bf0c      	ite	eq
 8003f1c:	2301      	moveq	r3, #1
 8003f1e:	2300      	movne	r3, #0
 8003f20:	b2db      	uxtb	r3, r3
 8003f22:	e012      	b.n	8003f4a <HAL_I2C_Init+0x18e>
 8003f24:	68fb      	ldr	r3, [r7, #12]
 8003f26:	1e58      	subs	r0, r3, #1
 8003f28:	687b      	ldr	r3, [r7, #4]
 8003f2a:	6859      	ldr	r1, [r3, #4]
 8003f2c:	460b      	mov	r3, r1
 8003f2e:	009b      	lsls	r3, r3, #2
 8003f30:	440b      	add	r3, r1
 8003f32:	0099      	lsls	r1, r3, #2
 8003f34:	440b      	add	r3, r1
 8003f36:	fbb0 f3f3 	udiv	r3, r0, r3
 8003f3a:	3301      	adds	r3, #1
 8003f3c:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8003f40:	2b00      	cmp	r3, #0
 8003f42:	bf0c      	ite	eq
 8003f44:	2301      	moveq	r3, #1
 8003f46:	2300      	movne	r3, #0
 8003f48:	b2db      	uxtb	r3, r3
 8003f4a:	2b00      	cmp	r3, #0
 8003f4c:	d001      	beq.n	8003f52 <HAL_I2C_Init+0x196>
 8003f4e:	2301      	movs	r3, #1
 8003f50:	e022      	b.n	8003f98 <HAL_I2C_Init+0x1dc>
 8003f52:	687b      	ldr	r3, [r7, #4]
 8003f54:	689b      	ldr	r3, [r3, #8]
 8003f56:	2b00      	cmp	r3, #0
 8003f58:	d10e      	bne.n	8003f78 <HAL_I2C_Init+0x1bc>
 8003f5a:	68fb      	ldr	r3, [r7, #12]
 8003f5c:	1e58      	subs	r0, r3, #1
 8003f5e:	687b      	ldr	r3, [r7, #4]
 8003f60:	6859      	ldr	r1, [r3, #4]
 8003f62:	460b      	mov	r3, r1
 8003f64:	005b      	lsls	r3, r3, #1
 8003f66:	440b      	add	r3, r1
 8003f68:	fbb0 f3f3 	udiv	r3, r0, r3
 8003f6c:	3301      	adds	r3, #1
 8003f6e:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8003f72:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 8003f76:	e00f      	b.n	8003f98 <HAL_I2C_Init+0x1dc>
 8003f78:	68fb      	ldr	r3, [r7, #12]
 8003f7a:	1e58      	subs	r0, r3, #1
 8003f7c:	687b      	ldr	r3, [r7, #4]
 8003f7e:	6859      	ldr	r1, [r3, #4]
 8003f80:	460b      	mov	r3, r1
 8003f82:	009b      	lsls	r3, r3, #2
 8003f84:	440b      	add	r3, r1
 8003f86:	0099      	lsls	r1, r3, #2
 8003f88:	440b      	add	r3, r1
 8003f8a:	fbb0 f3f3 	udiv	r3, r0, r3
 8003f8e:	3301      	adds	r3, #1
 8003f90:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8003f94:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
 8003f98:	6879      	ldr	r1, [r7, #4]
 8003f9a:	6809      	ldr	r1, [r1, #0]
 8003f9c:	4313      	orrs	r3, r2
 8003f9e:	61cb      	str	r3, [r1, #28]

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
 8003fa0:	687b      	ldr	r3, [r7, #4]
 8003fa2:	681b      	ldr	r3, [r3, #0]
 8003fa4:	681b      	ldr	r3, [r3, #0]
 8003fa6:	f023 01c0 	bic.w	r1, r3, #192	; 0xc0
 8003faa:	687b      	ldr	r3, [r7, #4]
 8003fac:	69da      	ldr	r2, [r3, #28]
 8003fae:	687b      	ldr	r3, [r7, #4]
 8003fb0:	6a1b      	ldr	r3, [r3, #32]
 8003fb2:	431a      	orrs	r2, r3
 8003fb4:	687b      	ldr	r3, [r7, #4]
 8003fb6:	681b      	ldr	r3, [r3, #0]
 8003fb8:	430a      	orrs	r2, r1
 8003fba:	601a      	str	r2, [r3, #0]

  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
  /* Configure I2Cx: Own Address1 and addressing mode */
  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
 8003fbc:	687b      	ldr	r3, [r7, #4]
 8003fbe:	681b      	ldr	r3, [r3, #0]
 8003fc0:	689b      	ldr	r3, [r3, #8]
 8003fc2:	f423 4303 	bic.w	r3, r3, #33536	; 0x8300
 8003fc6:	f023 03ff 	bic.w	r3, r3, #255	; 0xff
 8003fca:	687a      	ldr	r2, [r7, #4]
 8003fcc:	6911      	ldr	r1, [r2, #16]
 8003fce:	687a      	ldr	r2, [r7, #4]
 8003fd0:	68d2      	ldr	r2, [r2, #12]
 8003fd2:	4311      	orrs	r1, r2
 8003fd4:	687a      	ldr	r2, [r7, #4]
 8003fd6:	6812      	ldr	r2, [r2, #0]
 8003fd8:	430b      	orrs	r3, r1
 8003fda:	6093      	str	r3, [r2, #8]

  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
  /* Configure I2Cx: Dual mode and Own Address2 */
  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
 8003fdc:	687b      	ldr	r3, [r7, #4]
 8003fde:	681b      	ldr	r3, [r3, #0]
 8003fe0:	68db      	ldr	r3, [r3, #12]
 8003fe2:	f023 01ff 	bic.w	r1, r3, #255	; 0xff
 8003fe6:	687b      	ldr	r3, [r7, #4]
 8003fe8:	695a      	ldr	r2, [r3, #20]
 8003fea:	687b      	ldr	r3, [r7, #4]
 8003fec:	699b      	ldr	r3, [r3, #24]
 8003fee:	431a      	orrs	r2, r3
 8003ff0:	687b      	ldr	r3, [r7, #4]
 8003ff2:	681b      	ldr	r3, [r3, #0]
 8003ff4:	430a      	orrs	r2, r1
 8003ff6:	60da      	str	r2, [r3, #12]

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);
 8003ff8:	687b      	ldr	r3, [r7, #4]
 8003ffa:	681b      	ldr	r3, [r3, #0]
 8003ffc:	681a      	ldr	r2, [r3, #0]
 8003ffe:	687b      	ldr	r3, [r7, #4]
 8004000:	681b      	ldr	r3, [r3, #0]
 8004002:	f042 0201 	orr.w	r2, r2, #1
 8004006:	601a      	str	r2, [r3, #0]

  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 8004008:	687b      	ldr	r3, [r7, #4]
 800400a:	2200      	movs	r2, #0
 800400c:	641a      	str	r2, [r3, #64]	; 0x40
  hi2c->State = HAL_I2C_STATE_READY;
 800400e:	687b      	ldr	r3, [r7, #4]
 8004010:	2220      	movs	r2, #32
 8004012:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
  hi2c->PreviousState = I2C_STATE_NONE;
 8004016:	687b      	ldr	r3, [r7, #4]
 8004018:	2200      	movs	r2, #0
 800401a:	631a      	str	r2, [r3, #48]	; 0x30
  hi2c->Mode = HAL_I2C_MODE_NONE;
 800401c:	687b      	ldr	r3, [r7, #4]
 800401e:	2200      	movs	r2, #0
 8004020:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  return HAL_OK;
 8004024:	2300      	movs	r3, #0
}
 8004026:	4618      	mov	r0, r3
 8004028:	3710      	adds	r7, #16
 800402a:	46bd      	mov	sp, r7
 800402c:	bd80      	pop	{r7, pc}
 800402e:	bf00      	nop
 8004030:	000186a0 	.word	0x000186a0
 8004034:	001e847f 	.word	0x001e847f
 8004038:	003d08ff 	.word	0x003d08ff
 800403c:	431bde83 	.word	0x431bde83
 8004040:	10624dd3 	.word	0x10624dd3

08004044 <HAL_I2C_DeInit>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *         the configuration information for the specified I2C.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
 8004044:	b580      	push	{r7, lr}
 8004046:	b082      	sub	sp, #8
 8004048:	af00      	add	r7, sp, #0
 800404a:	6078      	str	r0, [r7, #4]
  /* Check the I2C handle allocation */
  if (hi2c == NULL)
 800404c:	687b      	ldr	r3, [r7, #4]
 800404e:	2b00      	cmp	r3, #0
 8004050:	d101      	bne.n	8004056 <HAL_I2C_DeInit+0x12>
  {
    return HAL_ERROR;
 8004052:	2301      	movs	r3, #1
 8004054:	e021      	b.n	800409a <HAL_I2C_DeInit+0x56>
  }

  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));

  hi2c->State = HAL_I2C_STATE_BUSY;
 8004056:	687b      	ldr	r3, [r7, #4]
 8004058:	2224      	movs	r2, #36	; 0x24
 800405a:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Disable the I2C Peripheral Clock */
  __HAL_I2C_DISABLE(hi2c);
 800405e:	687b      	ldr	r3, [r7, #4]
 8004060:	681b      	ldr	r3, [r3, #0]
 8004062:	681a      	ldr	r2, [r3, #0]
 8004064:	687b      	ldr	r3, [r7, #4]
 8004066:	681b      	ldr	r3, [r3, #0]
 8004068:	f022 0201 	bic.w	r2, r2, #1
 800406c:	601a      	str	r2, [r3, #0]

  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  hi2c->MspDeInitCallback(hi2c);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  HAL_I2C_MspDeInit(hi2c);
 800406e:	6878      	ldr	r0, [r7, #4]
 8004070:	f7fd ff02 	bl	8001e78 <HAL_I2C_MspDeInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */

  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
 8004074:	687b      	ldr	r3, [r7, #4]
 8004076:	2200      	movs	r2, #0
 8004078:	641a      	str	r2, [r3, #64]	; 0x40
  hi2c->State         = HAL_I2C_STATE_RESET;
 800407a:	687b      	ldr	r3, [r7, #4]
 800407c:	2200      	movs	r2, #0
 800407e:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
  hi2c->PreviousState = I2C_STATE_NONE;
 8004082:	687b      	ldr	r3, [r7, #4]
 8004084:	2200      	movs	r2, #0
 8004086:	631a      	str	r2, [r3, #48]	; 0x30
  hi2c->Mode          = HAL_I2C_MODE_NONE;
 8004088:	687b      	ldr	r3, [r7, #4]
 800408a:	2200      	movs	r2, #0
 800408c:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  /* Release Lock */
  __HAL_UNLOCK(hi2c);
 8004090:	687b      	ldr	r3, [r7, #4]
 8004092:	2200      	movs	r2, #0
 8004094:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

  return HAL_OK;
 8004098:	2300      	movs	r3, #0
}
 800409a:	4618      	mov	r0, r3
 800409c:	3708      	adds	r7, #8
 800409e:	46bd      	mov	sp, r7
 80040a0:	bd80      	pop	{r7, pc}
	...

080040a4 <HAL_I2C_Mem_Write>:
  * @param  Size Amount of data to be sent
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 80040a4:	b580      	push	{r7, lr}
 80040a6:	b088      	sub	sp, #32
 80040a8:	af02      	add	r7, sp, #8
 80040aa:	60f8      	str	r0, [r7, #12]
 80040ac:	4608      	mov	r0, r1
 80040ae:	4611      	mov	r1, r2
 80040b0:	461a      	mov	r2, r3
 80040b2:	4603      	mov	r3, r0
 80040b4:	817b      	strh	r3, [r7, #10]
 80040b6:	460b      	mov	r3, r1
 80040b8:	813b      	strh	r3, [r7, #8]
 80040ba:	4613      	mov	r3, r2
 80040bc:	80fb      	strh	r3, [r7, #6]
  /* Init tickstart for timeout management*/
  uint32_t tickstart = HAL_GetTick();
 80040be:	f7fe f9c3 	bl	8002448 <HAL_GetTick>
 80040c2:	6178      	str	r0, [r7, #20]

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY)
 80040c4:	68fb      	ldr	r3, [r7, #12]
 80040c6:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 80040ca:	b2db      	uxtb	r3, r3
 80040cc:	2b20      	cmp	r3, #32
 80040ce:	f040 80d9 	bne.w	8004284 <HAL_I2C_Mem_Write+0x1e0>
  {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
 80040d2:	697b      	ldr	r3, [r7, #20]
 80040d4:	9300      	str	r3, [sp, #0]
 80040d6:	2319      	movs	r3, #25
 80040d8:	2201      	movs	r2, #1
 80040da:	496d      	ldr	r1, [pc, #436]	; (8004290 <HAL_I2C_Mem_Write+0x1ec>)
 80040dc:	68f8      	ldr	r0, [r7, #12]
 80040de:	f000 f971 	bl	80043c4 <I2C_WaitOnFlagUntilTimeout>
 80040e2:	4603      	mov	r3, r0
 80040e4:	2b00      	cmp	r3, #0
 80040e6:	d001      	beq.n	80040ec <HAL_I2C_Mem_Write+0x48>
    {
      return HAL_BUSY;
 80040e8:	2302      	movs	r3, #2
 80040ea:	e0cc      	b.n	8004286 <HAL_I2C_Mem_Write+0x1e2>
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);
 80040ec:	68fb      	ldr	r3, [r7, #12]
 80040ee:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 80040f2:	2b01      	cmp	r3, #1
 80040f4:	d101      	bne.n	80040fa <HAL_I2C_Mem_Write+0x56>
 80040f6:	2302      	movs	r3, #2
 80040f8:	e0c5      	b.n	8004286 <HAL_I2C_Mem_Write+0x1e2>
 80040fa:	68fb      	ldr	r3, [r7, #12]
 80040fc:	2201      	movs	r2, #1
 80040fe:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
 8004102:	68fb      	ldr	r3, [r7, #12]
 8004104:	681b      	ldr	r3, [r3, #0]
 8004106:	681b      	ldr	r3, [r3, #0]
 8004108:	f003 0301 	and.w	r3, r3, #1
 800410c:	2b01      	cmp	r3, #1
 800410e:	d007      	beq.n	8004120 <HAL_I2C_Mem_Write+0x7c>
    {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
 8004110:	68fb      	ldr	r3, [r7, #12]
 8004112:	681b      	ldr	r3, [r3, #0]
 8004114:	681a      	ldr	r2, [r3, #0]
 8004116:	68fb      	ldr	r3, [r7, #12]
 8004118:	681b      	ldr	r3, [r3, #0]
 800411a:	f042 0201 	orr.w	r2, r2, #1
 800411e:	601a      	str	r2, [r3, #0]
    }

    /* Disable Pos */
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 8004120:	68fb      	ldr	r3, [r7, #12]
 8004122:	681b      	ldr	r3, [r3, #0]
 8004124:	681a      	ldr	r2, [r3, #0]
 8004126:	68fb      	ldr	r3, [r7, #12]
 8004128:	681b      	ldr	r3, [r3, #0]
 800412a:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
 800412e:	601a      	str	r2, [r3, #0]

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
 8004130:	68fb      	ldr	r3, [r7, #12]
 8004132:	2221      	movs	r2, #33	; 0x21
 8004134:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
    hi2c->Mode      = HAL_I2C_MODE_MEM;
 8004138:	68fb      	ldr	r3, [r7, #12]
 800413a:	2240      	movs	r2, #64	; 0x40
 800413c:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 8004140:	68fb      	ldr	r3, [r7, #12]
 8004142:	2200      	movs	r2, #0
 8004144:	641a      	str	r2, [r3, #64]	; 0x40

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
 8004146:	68fb      	ldr	r3, [r7, #12]
 8004148:	6a3a      	ldr	r2, [r7, #32]
 800414a:	625a      	str	r2, [r3, #36]	; 0x24
    hi2c->XferCount   = Size;
 800414c:	68fb      	ldr	r3, [r7, #12]
 800414e:	8cba      	ldrh	r2, [r7, #36]	; 0x24
 8004150:	855a      	strh	r2, [r3, #42]	; 0x2a
    hi2c->XferSize    = hi2c->XferCount;
 8004152:	68fb      	ldr	r3, [r7, #12]
 8004154:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
 8004156:	b29a      	uxth	r2, r3
 8004158:	68fb      	ldr	r3, [r7, #12]
 800415a:	851a      	strh	r2, [r3, #40]	; 0x28
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 800415c:	68fb      	ldr	r3, [r7, #12]
 800415e:	4a4d      	ldr	r2, [pc, #308]	; (8004294 <HAL_I2C_Mem_Write+0x1f0>)
 8004160:	62da      	str	r2, [r3, #44]	; 0x2c

    /* Send Slave Address and Memory Address */
    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
 8004162:	88f8      	ldrh	r0, [r7, #6]
 8004164:	893a      	ldrh	r2, [r7, #8]
 8004166:	8979      	ldrh	r1, [r7, #10]
 8004168:	697b      	ldr	r3, [r7, #20]
 800416a:	9301      	str	r3, [sp, #4]
 800416c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800416e:	9300      	str	r3, [sp, #0]
 8004170:	4603      	mov	r3, r0
 8004172:	68f8      	ldr	r0, [r7, #12]
 8004174:	f000 f890 	bl	8004298 <I2C_RequestMemoryWrite>
 8004178:	4603      	mov	r3, r0
 800417a:	2b00      	cmp	r3, #0
 800417c:	d052      	beq.n	8004224 <HAL_I2C_Mem_Write+0x180>
    {
      return HAL_ERROR;
 800417e:	2301      	movs	r3, #1
 8004180:	e081      	b.n	8004286 <HAL_I2C_Mem_Write+0x1e2>
    }

    while (hi2c->XferSize > 0U)
    {
      /* Wait until TXE flag is set */
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 8004182:	697a      	ldr	r2, [r7, #20]
 8004184:	6ab9      	ldr	r1, [r7, #40]	; 0x28
 8004186:	68f8      	ldr	r0, [r7, #12]
 8004188:	f000 f9f2 	bl	8004570 <I2C_WaitOnTXEFlagUntilTimeout>
 800418c:	4603      	mov	r3, r0
 800418e:	2b00      	cmp	r3, #0
 8004190:	d00d      	beq.n	80041ae <HAL_I2C_Mem_Write+0x10a>
      {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
 8004192:	68fb      	ldr	r3, [r7, #12]
 8004194:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004196:	2b04      	cmp	r3, #4
 8004198:	d107      	bne.n	80041aa <HAL_I2C_Mem_Write+0x106>
        {
          /* Generate Stop */
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 800419a:	68fb      	ldr	r3, [r7, #12]
 800419c:	681b      	ldr	r3, [r3, #0]
 800419e:	681a      	ldr	r2, [r3, #0]
 80041a0:	68fb      	ldr	r3, [r7, #12]
 80041a2:	681b      	ldr	r3, [r3, #0]
 80041a4:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 80041a8:	601a      	str	r2, [r3, #0]
        }
        return HAL_ERROR;
 80041aa:	2301      	movs	r3, #1
 80041ac:	e06b      	b.n	8004286 <HAL_I2C_Mem_Write+0x1e2>
      }

      /* Write data to DR */
      hi2c->Instance->DR = *hi2c->pBuffPtr;
 80041ae:	68fb      	ldr	r3, [r7, #12]
 80041b0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80041b2:	781a      	ldrb	r2, [r3, #0]
 80041b4:	68fb      	ldr	r3, [r7, #12]
 80041b6:	681b      	ldr	r3, [r3, #0]
 80041b8:	611a      	str	r2, [r3, #16]

      /* Increment Buffer pointer */
      hi2c->pBuffPtr++;
 80041ba:	68fb      	ldr	r3, [r7, #12]
 80041bc:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80041be:	1c5a      	adds	r2, r3, #1
 80041c0:	68fb      	ldr	r3, [r7, #12]
 80041c2:	625a      	str	r2, [r3, #36]	; 0x24

      /* Update counter */
      hi2c->XferSize--;
 80041c4:	68fb      	ldr	r3, [r7, #12]
 80041c6:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 80041c8:	3b01      	subs	r3, #1
 80041ca:	b29a      	uxth	r2, r3
 80041cc:	68fb      	ldr	r3, [r7, #12]
 80041ce:	851a      	strh	r2, [r3, #40]	; 0x28
      hi2c->XferCount--;
 80041d0:	68fb      	ldr	r3, [r7, #12]
 80041d2:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
 80041d4:	b29b      	uxth	r3, r3
 80041d6:	3b01      	subs	r3, #1
 80041d8:	b29a      	uxth	r2, r3
 80041da:	68fb      	ldr	r3, [r7, #12]
 80041dc:	855a      	strh	r2, [r3, #42]	; 0x2a

      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
 80041de:	68fb      	ldr	r3, [r7, #12]
 80041e0:	681b      	ldr	r3, [r3, #0]
 80041e2:	695b      	ldr	r3, [r3, #20]
 80041e4:	f003 0304 	and.w	r3, r3, #4
 80041e8:	2b04      	cmp	r3, #4
 80041ea:	d11b      	bne.n	8004224 <HAL_I2C_Mem_Write+0x180>
 80041ec:	68fb      	ldr	r3, [r7, #12]
 80041ee:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 80041f0:	2b00      	cmp	r3, #0
 80041f2:	d017      	beq.n	8004224 <HAL_I2C_Mem_Write+0x180>
      {
        /* Write data to DR */
        hi2c->Instance->DR = *hi2c->pBuffPtr;
 80041f4:	68fb      	ldr	r3, [r7, #12]
 80041f6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80041f8:	781a      	ldrb	r2, [r3, #0]
 80041fa:	68fb      	ldr	r3, [r7, #12]
 80041fc:	681b      	ldr	r3, [r3, #0]
 80041fe:	611a      	str	r2, [r3, #16]

        /* Increment Buffer pointer */
        hi2c->pBuffPtr++;
 8004200:	68fb      	ldr	r3, [r7, #12]
 8004202:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004204:	1c5a      	adds	r2, r3, #1
 8004206:	68fb      	ldr	r3, [r7, #12]
 8004208:	625a      	str	r2, [r3, #36]	; 0x24

        /* Update counter */
        hi2c->XferSize--;
 800420a:	68fb      	ldr	r3, [r7, #12]
 800420c:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 800420e:	3b01      	subs	r3, #1
 8004210:	b29a      	uxth	r2, r3
 8004212:	68fb      	ldr	r3, [r7, #12]
 8004214:	851a      	strh	r2, [r3, #40]	; 0x28
        hi2c->XferCount--;
 8004216:	68fb      	ldr	r3, [r7, #12]
 8004218:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
 800421a:	b29b      	uxth	r3, r3
 800421c:	3b01      	subs	r3, #1
 800421e:	b29a      	uxth	r2, r3
 8004220:	68fb      	ldr	r3, [r7, #12]
 8004222:	855a      	strh	r2, [r3, #42]	; 0x2a
    while (hi2c->XferSize > 0U)
 8004224:	68fb      	ldr	r3, [r7, #12]
 8004226:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 8004228:	2b00      	cmp	r3, #0
 800422a:	d1aa      	bne.n	8004182 <HAL_I2C_Mem_Write+0xde>
      }
    }

    /* Wait until BTF flag is set */
    if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 800422c:	697a      	ldr	r2, [r7, #20]
 800422e:	6ab9      	ldr	r1, [r7, #40]	; 0x28
 8004230:	68f8      	ldr	r0, [r7, #12]
 8004232:	f000 f9de 	bl	80045f2 <I2C_WaitOnBTFFlagUntilTimeout>
 8004236:	4603      	mov	r3, r0
 8004238:	2b00      	cmp	r3, #0
 800423a:	d00d      	beq.n	8004258 <HAL_I2C_Mem_Write+0x1b4>
    {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
 800423c:	68fb      	ldr	r3, [r7, #12]
 800423e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004240:	2b04      	cmp	r3, #4
 8004242:	d107      	bne.n	8004254 <HAL_I2C_Mem_Write+0x1b0>
      {
        /* Generate Stop */
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 8004244:	68fb      	ldr	r3, [r7, #12]
 8004246:	681b      	ldr	r3, [r3, #0]
 8004248:	681a      	ldr	r2, [r3, #0]
 800424a:	68fb      	ldr	r3, [r7, #12]
 800424c:	681b      	ldr	r3, [r3, #0]
 800424e:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8004252:	601a      	str	r2, [r3, #0]
      }
      return HAL_ERROR;
 8004254:	2301      	movs	r3, #1
 8004256:	e016      	b.n	8004286 <HAL_I2C_Mem_Write+0x1e2>
    }

    /* Generate Stop */
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 8004258:	68fb      	ldr	r3, [r7, #12]
 800425a:	681b      	ldr	r3, [r3, #0]
 800425c:	681a      	ldr	r2, [r3, #0]
 800425e:	68fb      	ldr	r3, [r7, #12]
 8004260:	681b      	ldr	r3, [r3, #0]
 8004262:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8004266:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 8004268:	68fb      	ldr	r3, [r7, #12]
 800426a:	2220      	movs	r2, #32
 800426c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
    hi2c->Mode = HAL_I2C_MODE_NONE;
 8004270:	68fb      	ldr	r3, [r7, #12]
 8004272:	2200      	movs	r2, #0
 8004274:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8004278:	68fb      	ldr	r3, [r7, #12]
 800427a:	2200      	movs	r2, #0
 800427c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    return HAL_OK;
 8004280:	2300      	movs	r3, #0
 8004282:	e000      	b.n	8004286 <HAL_I2C_Mem_Write+0x1e2>
  }
  else
  {
    return HAL_BUSY;
 8004284:	2302      	movs	r3, #2
  }
}
 8004286:	4618      	mov	r0, r3
 8004288:	3718      	adds	r7, #24
 800428a:	46bd      	mov	sp, r7
 800428c:	bd80      	pop	{r7, pc}
 800428e:	bf00      	nop
 8004290:	00100002 	.word	0x00100002
 8004294:	ffff0000 	.word	0xffff0000

08004298 <I2C_RequestMemoryWrite>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
 8004298:	b580      	push	{r7, lr}
 800429a:	b088      	sub	sp, #32
 800429c:	af02      	add	r7, sp, #8
 800429e:	60f8      	str	r0, [r7, #12]
 80042a0:	4608      	mov	r0, r1
 80042a2:	4611      	mov	r1, r2
 80042a4:	461a      	mov	r2, r3
 80042a6:	4603      	mov	r3, r0
 80042a8:	817b      	strh	r3, [r7, #10]
 80042aa:	460b      	mov	r3, r1
 80042ac:	813b      	strh	r3, [r7, #8]
 80042ae:	4613      	mov	r3, r2
 80042b0:	80fb      	strh	r3, [r7, #6]
  /* Generate Start */
  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 80042b2:	68fb      	ldr	r3, [r7, #12]
 80042b4:	681b      	ldr	r3, [r3, #0]
 80042b6:	681a      	ldr	r2, [r3, #0]
 80042b8:	68fb      	ldr	r3, [r7, #12]
 80042ba:	681b      	ldr	r3, [r3, #0]
 80042bc:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 80042c0:	601a      	str	r2, [r3, #0]

  /* Wait until SB flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
 80042c2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80042c4:	9300      	str	r3, [sp, #0]
 80042c6:	6a3b      	ldr	r3, [r7, #32]
 80042c8:	2200      	movs	r2, #0
 80042ca:	f04f 1101 	mov.w	r1, #65537	; 0x10001
 80042ce:	68f8      	ldr	r0, [r7, #12]
 80042d0:	f000 f878 	bl	80043c4 <I2C_WaitOnFlagUntilTimeout>
 80042d4:	4603      	mov	r3, r0
 80042d6:	2b00      	cmp	r3, #0
 80042d8:	d00d      	beq.n	80042f6 <I2C_RequestMemoryWrite+0x5e>
  {
    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
 80042da:	68fb      	ldr	r3, [r7, #12]
 80042dc:	681b      	ldr	r3, [r3, #0]
 80042de:	681b      	ldr	r3, [r3, #0]
 80042e0:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80042e4:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 80042e8:	d103      	bne.n	80042f2 <I2C_RequestMemoryWrite+0x5a>
    {
      hi2c->ErrorCode = HAL_I2C_WRONG_START;
 80042ea:	68fb      	ldr	r3, [r7, #12]
 80042ec:	f44f 7200 	mov.w	r2, #512	; 0x200
 80042f0:	641a      	str	r2, [r3, #64]	; 0x40
    }
    return HAL_TIMEOUT;
 80042f2:	2303      	movs	r3, #3
 80042f4:	e05f      	b.n	80043b6 <I2C_RequestMemoryWrite+0x11e>
  }

  /* Send slave address */
  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
 80042f6:	897b      	ldrh	r3, [r7, #10]
 80042f8:	b2db      	uxtb	r3, r3
 80042fa:	461a      	mov	r2, r3
 80042fc:	68fb      	ldr	r3, [r7, #12]
 80042fe:	681b      	ldr	r3, [r3, #0]
 8004300:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
 8004304:	611a      	str	r2, [r3, #16]

  /* Wait until ADDR flag is set */
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
 8004306:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8004308:	6a3a      	ldr	r2, [r7, #32]
 800430a:	492d      	ldr	r1, [pc, #180]	; (80043c0 <I2C_RequestMemoryWrite+0x128>)
 800430c:	68f8      	ldr	r0, [r7, #12]
 800430e:	f000 f8b0 	bl	8004472 <I2C_WaitOnMasterAddressFlagUntilTimeout>
 8004312:	4603      	mov	r3, r0
 8004314:	2b00      	cmp	r3, #0
 8004316:	d001      	beq.n	800431c <I2C_RequestMemoryWrite+0x84>
  {
    return HAL_ERROR;
 8004318:	2301      	movs	r3, #1
 800431a:	e04c      	b.n	80043b6 <I2C_RequestMemoryWrite+0x11e>
  }

  /* Clear ADDR flag */
  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 800431c:	2300      	movs	r3, #0
 800431e:	617b      	str	r3, [r7, #20]
 8004320:	68fb      	ldr	r3, [r7, #12]
 8004322:	681b      	ldr	r3, [r3, #0]
 8004324:	695b      	ldr	r3, [r3, #20]
 8004326:	617b      	str	r3, [r7, #20]
 8004328:	68fb      	ldr	r3, [r7, #12]
 800432a:	681b      	ldr	r3, [r3, #0]
 800432c:	699b      	ldr	r3, [r3, #24]
 800432e:	617b      	str	r3, [r7, #20]
 8004330:	697b      	ldr	r3, [r7, #20]

  /* Wait until TXE flag is set */
  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
 8004332:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8004334:	6a39      	ldr	r1, [r7, #32]
 8004336:	68f8      	ldr	r0, [r7, #12]
 8004338:	f000 f91a 	bl	8004570 <I2C_WaitOnTXEFlagUntilTimeout>
 800433c:	4603      	mov	r3, r0
 800433e:	2b00      	cmp	r3, #0
 8004340:	d00d      	beq.n	800435e <I2C_RequestMemoryWrite+0xc6>
  {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
 8004342:	68fb      	ldr	r3, [r7, #12]
 8004344:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004346:	2b04      	cmp	r3, #4
 8004348:	d107      	bne.n	800435a <I2C_RequestMemoryWrite+0xc2>
    {
      /* Generate Stop */
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 800434a:	68fb      	ldr	r3, [r7, #12]
 800434c:	681b      	ldr	r3, [r3, #0]
 800434e:	681a      	ldr	r2, [r3, #0]
 8004350:	68fb      	ldr	r3, [r7, #12]
 8004352:	681b      	ldr	r3, [r3, #0]
 8004354:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8004358:	601a      	str	r2, [r3, #0]
    }
    return HAL_ERROR;
 800435a:	2301      	movs	r3, #1
 800435c:	e02b      	b.n	80043b6 <I2C_RequestMemoryWrite+0x11e>
  }

  /* If Memory address size is 8Bit */
  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
 800435e:	88fb      	ldrh	r3, [r7, #6]
 8004360:	2b01      	cmp	r3, #1
 8004362:	d105      	bne.n	8004370 <I2C_RequestMemoryWrite+0xd8>
  {
    /* Send Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
 8004364:	893b      	ldrh	r3, [r7, #8]
 8004366:	b2da      	uxtb	r2, r3
 8004368:	68fb      	ldr	r3, [r7, #12]
 800436a:	681b      	ldr	r3, [r3, #0]
 800436c:	611a      	str	r2, [r3, #16]
 800436e:	e021      	b.n	80043b4 <I2C_RequestMemoryWrite+0x11c>
  }
  /* If Memory address size is 16Bit */
  else
  {
    /* Send MSB of Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
 8004370:	893b      	ldrh	r3, [r7, #8]
 8004372:	0a1b      	lsrs	r3, r3, #8
 8004374:	b29b      	uxth	r3, r3
 8004376:	b2da      	uxtb	r2, r3
 8004378:	68fb      	ldr	r3, [r7, #12]
 800437a:	681b      	ldr	r3, [r3, #0]
 800437c:	611a      	str	r2, [r3, #16]

    /* Wait until TXE flag is set */
    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
 800437e:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8004380:	6a39      	ldr	r1, [r7, #32]
 8004382:	68f8      	ldr	r0, [r7, #12]
 8004384:	f000 f8f4 	bl	8004570 <I2C_WaitOnTXEFlagUntilTimeout>
 8004388:	4603      	mov	r3, r0
 800438a:	2b00      	cmp	r3, #0
 800438c:	d00d      	beq.n	80043aa <I2C_RequestMemoryWrite+0x112>
    {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
 800438e:	68fb      	ldr	r3, [r7, #12]
 8004390:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004392:	2b04      	cmp	r3, #4
 8004394:	d107      	bne.n	80043a6 <I2C_RequestMemoryWrite+0x10e>
      {
        /* Generate Stop */
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 8004396:	68fb      	ldr	r3, [r7, #12]
 8004398:	681b      	ldr	r3, [r3, #0]
 800439a:	681a      	ldr	r2, [r3, #0]
 800439c:	68fb      	ldr	r3, [r7, #12]
 800439e:	681b      	ldr	r3, [r3, #0]
 80043a0:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 80043a4:	601a      	str	r2, [r3, #0]
      }
      return HAL_ERROR;
 80043a6:	2301      	movs	r3, #1
 80043a8:	e005      	b.n	80043b6 <I2C_RequestMemoryWrite+0x11e>
    }

    /* Send LSB of Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
 80043aa:	893b      	ldrh	r3, [r7, #8]
 80043ac:	b2da      	uxtb	r2, r3
 80043ae:	68fb      	ldr	r3, [r7, #12]
 80043b0:	681b      	ldr	r3, [r3, #0]
 80043b2:	611a      	str	r2, [r3, #16]
  }

  return HAL_OK;
 80043b4:	2300      	movs	r3, #0
}
 80043b6:	4618      	mov	r0, r3
 80043b8:	3718      	adds	r7, #24
 80043ba:	46bd      	mov	sp, r7
 80043bc:	bd80      	pop	{r7, pc}
 80043be:	bf00      	nop
 80043c0:	00010002 	.word	0x00010002

080043c4 <I2C_WaitOnFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
 80043c4:	b580      	push	{r7, lr}
 80043c6:	b084      	sub	sp, #16
 80043c8:	af00      	add	r7, sp, #0
 80043ca:	60f8      	str	r0, [r7, #12]
 80043cc:	60b9      	str	r1, [r7, #8]
 80043ce:	603b      	str	r3, [r7, #0]
 80043d0:	4613      	mov	r3, r2
 80043d2:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
 80043d4:	e025      	b.n	8004422 <I2C_WaitOnFlagUntilTimeout+0x5e>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 80043d6:	683b      	ldr	r3, [r7, #0]
 80043d8:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 80043dc:	d021      	beq.n	8004422 <I2C_WaitOnFlagUntilTimeout+0x5e>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 80043de:	f7fe f833 	bl	8002448 <HAL_GetTick>
 80043e2:	4602      	mov	r2, r0
 80043e4:	69bb      	ldr	r3, [r7, #24]
 80043e6:	1ad3      	subs	r3, r2, r3
 80043e8:	683a      	ldr	r2, [r7, #0]
 80043ea:	429a      	cmp	r2, r3
 80043ec:	d302      	bcc.n	80043f4 <I2C_WaitOnFlagUntilTimeout+0x30>
 80043ee:	683b      	ldr	r3, [r7, #0]
 80043f0:	2b00      	cmp	r3, #0
 80043f2:	d116      	bne.n	8004422 <I2C_WaitOnFlagUntilTimeout+0x5e>
      {
        hi2c->PreviousState     = I2C_STATE_NONE;
 80043f4:	68fb      	ldr	r3, [r7, #12]
 80043f6:	2200      	movs	r2, #0
 80043f8:	631a      	str	r2, [r3, #48]	; 0x30
        hi2c->State             = HAL_I2C_STATE_READY;
 80043fa:	68fb      	ldr	r3, [r7, #12]
 80043fc:	2220      	movs	r2, #32
 80043fe:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
        hi2c->Mode              = HAL_I2C_MODE_NONE;
 8004402:	68fb      	ldr	r3, [r7, #12]
 8004404:	2200      	movs	r2, #0
 8004406:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
        hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;
 800440a:	68fb      	ldr	r3, [r7, #12]
 800440c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800440e:	f043 0220 	orr.w	r2, r3, #32
 8004412:	68fb      	ldr	r3, [r7, #12]
 8004414:	641a      	str	r2, [r3, #64]	; 0x40

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
 8004416:	68fb      	ldr	r3, [r7, #12]
 8004418:	2200      	movs	r2, #0
 800441a:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

        return HAL_ERROR;
 800441e:	2301      	movs	r3, #1
 8004420:	e023      	b.n	800446a <I2C_WaitOnFlagUntilTimeout+0xa6>
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
 8004422:	68bb      	ldr	r3, [r7, #8]
 8004424:	0c1b      	lsrs	r3, r3, #16
 8004426:	b2db      	uxtb	r3, r3
 8004428:	2b01      	cmp	r3, #1
 800442a:	d10d      	bne.n	8004448 <I2C_WaitOnFlagUntilTimeout+0x84>
 800442c:	68fb      	ldr	r3, [r7, #12]
 800442e:	681b      	ldr	r3, [r3, #0]
 8004430:	695b      	ldr	r3, [r3, #20]
 8004432:	43da      	mvns	r2, r3
 8004434:	68bb      	ldr	r3, [r7, #8]
 8004436:	4013      	ands	r3, r2
 8004438:	b29b      	uxth	r3, r3
 800443a:	2b00      	cmp	r3, #0
 800443c:	bf0c      	ite	eq
 800443e:	2301      	moveq	r3, #1
 8004440:	2300      	movne	r3, #0
 8004442:	b2db      	uxtb	r3, r3
 8004444:	461a      	mov	r2, r3
 8004446:	e00c      	b.n	8004462 <I2C_WaitOnFlagUntilTimeout+0x9e>
 8004448:	68fb      	ldr	r3, [r7, #12]
 800444a:	681b      	ldr	r3, [r3, #0]
 800444c:	699b      	ldr	r3, [r3, #24]
 800444e:	43da      	mvns	r2, r3
 8004450:	68bb      	ldr	r3, [r7, #8]
 8004452:	4013      	ands	r3, r2
 8004454:	b29b      	uxth	r3, r3
 8004456:	2b00      	cmp	r3, #0
 8004458:	bf0c      	ite	eq
 800445a:	2301      	moveq	r3, #1
 800445c:	2300      	movne	r3, #0
 800445e:	b2db      	uxtb	r3, r3
 8004460:	461a      	mov	r2, r3
 8004462:	79fb      	ldrb	r3, [r7, #7]
 8004464:	429a      	cmp	r2, r3
 8004466:	d0b6      	beq.n	80043d6 <I2C_WaitOnFlagUntilTimeout+0x12>
      }
    }
  }
  return HAL_OK;
 8004468:	2300      	movs	r3, #0
}
 800446a:	4618      	mov	r0, r3
 800446c:	3710      	adds	r7, #16
 800446e:	46bd      	mov	sp, r7
 8004470:	bd80      	pop	{r7, pc}

08004472 <I2C_WaitOnMasterAddressFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
 8004472:	b580      	push	{r7, lr}
 8004474:	b084      	sub	sp, #16
 8004476:	af00      	add	r7, sp, #0
 8004478:	60f8      	str	r0, [r7, #12]
 800447a:	60b9      	str	r1, [r7, #8]
 800447c:	607a      	str	r2, [r7, #4]
 800447e:	603b      	str	r3, [r7, #0]
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
 8004480:	e051      	b.n	8004526 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xb4>
  {
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
 8004482:	68fb      	ldr	r3, [r7, #12]
 8004484:	681b      	ldr	r3, [r3, #0]
 8004486:	695b      	ldr	r3, [r3, #20]
 8004488:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 800448c:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 8004490:	d123      	bne.n	80044da <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
    {
      /* Generate Stop */
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 8004492:	68fb      	ldr	r3, [r7, #12]
 8004494:	681b      	ldr	r3, [r3, #0]
 8004496:	681a      	ldr	r2, [r3, #0]
 8004498:	68fb      	ldr	r3, [r7, #12]
 800449a:	681b      	ldr	r3, [r3, #0]
 800449c:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 80044a0:	601a      	str	r2, [r3, #0]

      /* Clear AF Flag */
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 80044a2:	68fb      	ldr	r3, [r7, #12]
 80044a4:	681b      	ldr	r3, [r3, #0]
 80044a6:	f46f 6280 	mvn.w	r2, #1024	; 0x400
 80044aa:	615a      	str	r2, [r3, #20]

      hi2c->PreviousState       = I2C_STATE_NONE;
 80044ac:	68fb      	ldr	r3, [r7, #12]
 80044ae:	2200      	movs	r2, #0
 80044b0:	631a      	str	r2, [r3, #48]	; 0x30
      hi2c->State               = HAL_I2C_STATE_READY;
 80044b2:	68fb      	ldr	r3, [r7, #12]
 80044b4:	2220      	movs	r2, #32
 80044b6:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
      hi2c->Mode                = HAL_I2C_MODE_NONE;
 80044ba:	68fb      	ldr	r3, [r7, #12]
 80044bc:	2200      	movs	r2, #0
 80044be:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
      hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
 80044c2:	68fb      	ldr	r3, [r7, #12]
 80044c4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80044c6:	f043 0204 	orr.w	r2, r3, #4
 80044ca:	68fb      	ldr	r3, [r7, #12]
 80044cc:	641a      	str	r2, [r3, #64]	; 0x40

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);
 80044ce:	68fb      	ldr	r3, [r7, #12]
 80044d0:	2200      	movs	r2, #0
 80044d2:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

      return HAL_ERROR;
 80044d6:	2301      	movs	r3, #1
 80044d8:	e046      	b.n	8004568 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf6>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 80044da:	687b      	ldr	r3, [r7, #4]
 80044dc:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 80044e0:	d021      	beq.n	8004526 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xb4>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 80044e2:	f7fd ffb1 	bl	8002448 <HAL_GetTick>
 80044e6:	4602      	mov	r2, r0
 80044e8:	683b      	ldr	r3, [r7, #0]
 80044ea:	1ad3      	subs	r3, r2, r3
 80044ec:	687a      	ldr	r2, [r7, #4]
 80044ee:	429a      	cmp	r2, r3
 80044f0:	d302      	bcc.n	80044f8 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
 80044f2:	687b      	ldr	r3, [r7, #4]
 80044f4:	2b00      	cmp	r3, #0
 80044f6:	d116      	bne.n	8004526 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xb4>
      {
        hi2c->PreviousState       = I2C_STATE_NONE;
 80044f8:	68fb      	ldr	r3, [r7, #12]
 80044fa:	2200      	movs	r2, #0
 80044fc:	631a      	str	r2, [r3, #48]	; 0x30
        hi2c->State               = HAL_I2C_STATE_READY;
 80044fe:	68fb      	ldr	r3, [r7, #12]
 8004500:	2220      	movs	r2, #32
 8004502:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
        hi2c->Mode                = HAL_I2C_MODE_NONE;
 8004506:	68fb      	ldr	r3, [r7, #12]
 8004508:	2200      	movs	r2, #0
 800450a:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 800450e:	68fb      	ldr	r3, [r7, #12]
 8004510:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004512:	f043 0220 	orr.w	r2, r3, #32
 8004516:	68fb      	ldr	r3, [r7, #12]
 8004518:	641a      	str	r2, [r3, #64]	; 0x40

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
 800451a:	68fb      	ldr	r3, [r7, #12]
 800451c:	2200      	movs	r2, #0
 800451e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

        return HAL_ERROR;
 8004522:	2301      	movs	r3, #1
 8004524:	e020      	b.n	8004568 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf6>
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
 8004526:	68bb      	ldr	r3, [r7, #8]
 8004528:	0c1b      	lsrs	r3, r3, #16
 800452a:	b2db      	uxtb	r3, r3
 800452c:	2b01      	cmp	r3, #1
 800452e:	d10c      	bne.n	800454a <I2C_WaitOnMasterAddressFlagUntilTimeout+0xd8>
 8004530:	68fb      	ldr	r3, [r7, #12]
 8004532:	681b      	ldr	r3, [r3, #0]
 8004534:	695b      	ldr	r3, [r3, #20]
 8004536:	43da      	mvns	r2, r3
 8004538:	68bb      	ldr	r3, [r7, #8]
 800453a:	4013      	ands	r3, r2
 800453c:	b29b      	uxth	r3, r3
 800453e:	2b00      	cmp	r3, #0
 8004540:	bf14      	ite	ne
 8004542:	2301      	movne	r3, #1
 8004544:	2300      	moveq	r3, #0
 8004546:	b2db      	uxtb	r3, r3
 8004548:	e00b      	b.n	8004562 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf0>
 800454a:	68fb      	ldr	r3, [r7, #12]
 800454c:	681b      	ldr	r3, [r3, #0]
 800454e:	699b      	ldr	r3, [r3, #24]
 8004550:	43da      	mvns	r2, r3
 8004552:	68bb      	ldr	r3, [r7, #8]
 8004554:	4013      	ands	r3, r2
 8004556:	b29b      	uxth	r3, r3
 8004558:	2b00      	cmp	r3, #0
 800455a:	bf14      	ite	ne
 800455c:	2301      	movne	r3, #1
 800455e:	2300      	moveq	r3, #0
 8004560:	b2db      	uxtb	r3, r3
 8004562:	2b00      	cmp	r3, #0
 8004564:	d18d      	bne.n	8004482 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
      }
    }
  }
  return HAL_OK;
 8004566:	2300      	movs	r3, #0
}
 8004568:	4618      	mov	r0, r3
 800456a:	3710      	adds	r7, #16
 800456c:	46bd      	mov	sp, r7
 800456e:	bd80      	pop	{r7, pc}

08004570 <I2C_WaitOnTXEFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
 8004570:	b580      	push	{r7, lr}
 8004572:	b084      	sub	sp, #16
 8004574:	af00      	add	r7, sp, #0
 8004576:	60f8      	str	r0, [r7, #12]
 8004578:	60b9      	str	r1, [r7, #8]
 800457a:	607a      	str	r2, [r7, #4]
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
 800457c:	e02d      	b.n	80045da <I2C_WaitOnTXEFlagUntilTimeout+0x6a>
  {
    /* Check if a NACK is detected */
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
 800457e:	68f8      	ldr	r0, [r7, #12]
 8004580:	f000 f878 	bl	8004674 <I2C_IsAcknowledgeFailed>
 8004584:	4603      	mov	r3, r0
 8004586:	2b00      	cmp	r3, #0
 8004588:	d001      	beq.n	800458e <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
    {
      return HAL_ERROR;
 800458a:	2301      	movs	r3, #1
 800458c:	e02d      	b.n	80045ea <I2C_WaitOnTXEFlagUntilTimeout+0x7a>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 800458e:	68bb      	ldr	r3, [r7, #8]
 8004590:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8004594:	d021      	beq.n	80045da <I2C_WaitOnTXEFlagUntilTimeout+0x6a>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8004596:	f7fd ff57 	bl	8002448 <HAL_GetTick>
 800459a:	4602      	mov	r2, r0
 800459c:	687b      	ldr	r3, [r7, #4]
 800459e:	1ad3      	subs	r3, r2, r3
 80045a0:	68ba      	ldr	r2, [r7, #8]
 80045a2:	429a      	cmp	r2, r3
 80045a4:	d302      	bcc.n	80045ac <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
 80045a6:	68bb      	ldr	r3, [r7, #8]
 80045a8:	2b00      	cmp	r3, #0
 80045aa:	d116      	bne.n	80045da <I2C_WaitOnTXEFlagUntilTimeout+0x6a>
      {
        hi2c->PreviousState       = I2C_STATE_NONE;
 80045ac:	68fb      	ldr	r3, [r7, #12]
 80045ae:	2200      	movs	r2, #0
 80045b0:	631a      	str	r2, [r3, #48]	; 0x30
        hi2c->State               = HAL_I2C_STATE_READY;
 80045b2:	68fb      	ldr	r3, [r7, #12]
 80045b4:	2220      	movs	r2, #32
 80045b6:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
        hi2c->Mode                = HAL_I2C_MODE_NONE;
 80045ba:	68fb      	ldr	r3, [r7, #12]
 80045bc:	2200      	movs	r2, #0
 80045be:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 80045c2:	68fb      	ldr	r3, [r7, #12]
 80045c4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80045c6:	f043 0220 	orr.w	r2, r3, #32
 80045ca:	68fb      	ldr	r3, [r7, #12]
 80045cc:	641a      	str	r2, [r3, #64]	; 0x40

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
 80045ce:	68fb      	ldr	r3, [r7, #12]
 80045d0:	2200      	movs	r2, #0
 80045d2:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

        return HAL_ERROR;
 80045d6:	2301      	movs	r3, #1
 80045d8:	e007      	b.n	80045ea <I2C_WaitOnTXEFlagUntilTimeout+0x7a>
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
 80045da:	68fb      	ldr	r3, [r7, #12]
 80045dc:	681b      	ldr	r3, [r3, #0]
 80045de:	695b      	ldr	r3, [r3, #20]
 80045e0:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80045e4:	2b80      	cmp	r3, #128	; 0x80
 80045e6:	d1ca      	bne.n	800457e <I2C_WaitOnTXEFlagUntilTimeout+0xe>
      }
    }
  }
  return HAL_OK;
 80045e8:	2300      	movs	r3, #0
}
 80045ea:	4618      	mov	r0, r3
 80045ec:	3710      	adds	r7, #16
 80045ee:	46bd      	mov	sp, r7
 80045f0:	bd80      	pop	{r7, pc}

080045f2 <I2C_WaitOnBTFFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
 80045f2:	b580      	push	{r7, lr}
 80045f4:	b084      	sub	sp, #16
 80045f6:	af00      	add	r7, sp, #0
 80045f8:	60f8      	str	r0, [r7, #12]
 80045fa:	60b9      	str	r1, [r7, #8]
 80045fc:	607a      	str	r2, [r7, #4]
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
 80045fe:	e02d      	b.n	800465c <I2C_WaitOnBTFFlagUntilTimeout+0x6a>
  {
    /* Check if a NACK is detected */
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
 8004600:	68f8      	ldr	r0, [r7, #12]
 8004602:	f000 f837 	bl	8004674 <I2C_IsAcknowledgeFailed>
 8004606:	4603      	mov	r3, r0
 8004608:	2b00      	cmp	r3, #0
 800460a:	d001      	beq.n	8004610 <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
    {
      return HAL_ERROR;
 800460c:	2301      	movs	r3, #1
 800460e:	e02d      	b.n	800466c <I2C_WaitOnBTFFlagUntilTimeout+0x7a>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8004610:	68bb      	ldr	r3, [r7, #8]
 8004612:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8004616:	d021      	beq.n	800465c <I2C_WaitOnBTFFlagUntilTimeout+0x6a>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8004618:	f7fd ff16 	bl	8002448 <HAL_GetTick>
 800461c:	4602      	mov	r2, r0
 800461e:	687b      	ldr	r3, [r7, #4]
 8004620:	1ad3      	subs	r3, r2, r3
 8004622:	68ba      	ldr	r2, [r7, #8]
 8004624:	429a      	cmp	r2, r3
 8004626:	d302      	bcc.n	800462e <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
 8004628:	68bb      	ldr	r3, [r7, #8]
 800462a:	2b00      	cmp	r3, #0
 800462c:	d116      	bne.n	800465c <I2C_WaitOnBTFFlagUntilTimeout+0x6a>
      {
        hi2c->PreviousState       = I2C_STATE_NONE;
 800462e:	68fb      	ldr	r3, [r7, #12]
 8004630:	2200      	movs	r2, #0
 8004632:	631a      	str	r2, [r3, #48]	; 0x30
        hi2c->State               = HAL_I2C_STATE_READY;
 8004634:	68fb      	ldr	r3, [r7, #12]
 8004636:	2220      	movs	r2, #32
 8004638:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
        hi2c->Mode                = HAL_I2C_MODE_NONE;
 800463c:	68fb      	ldr	r3, [r7, #12]
 800463e:	2200      	movs	r2, #0
 8004640:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 8004644:	68fb      	ldr	r3, [r7, #12]
 8004646:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004648:	f043 0220 	orr.w	r2, r3, #32
 800464c:	68fb      	ldr	r3, [r7, #12]
 800464e:	641a      	str	r2, [r3, #64]	; 0x40

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
 8004650:	68fb      	ldr	r3, [r7, #12]
 8004652:	2200      	movs	r2, #0
 8004654:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

        return HAL_ERROR;
 8004658:	2301      	movs	r3, #1
 800465a:	e007      	b.n	800466c <I2C_WaitOnBTFFlagUntilTimeout+0x7a>
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
 800465c:	68fb      	ldr	r3, [r7, #12]
 800465e:	681b      	ldr	r3, [r3, #0]
 8004660:	695b      	ldr	r3, [r3, #20]
 8004662:	f003 0304 	and.w	r3, r3, #4
 8004666:	2b04      	cmp	r3, #4
 8004668:	d1ca      	bne.n	8004600 <I2C_WaitOnBTFFlagUntilTimeout+0xe>
      }
    }
  }
  return HAL_OK;
 800466a:	2300      	movs	r3, #0
}
 800466c:	4618      	mov	r0, r3
 800466e:	3710      	adds	r7, #16
 8004670:	46bd      	mov	sp, r7
 8004672:	bd80      	pop	{r7, pc}

08004674 <I2C_IsAcknowledgeFailed>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
{
 8004674:	b480      	push	{r7}
 8004676:	b083      	sub	sp, #12
 8004678:	af00      	add	r7, sp, #0
 800467a:	6078      	str	r0, [r7, #4]
  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
 800467c:	687b      	ldr	r3, [r7, #4]
 800467e:	681b      	ldr	r3, [r3, #0]
 8004680:	695b      	ldr	r3, [r3, #20]
 8004682:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8004686:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 800468a:	d11b      	bne.n	80046c4 <I2C_IsAcknowledgeFailed+0x50>
  {
    /* Clear NACKF Flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 800468c:	687b      	ldr	r3, [r7, #4]
 800468e:	681b      	ldr	r3, [r3, #0]
 8004690:	f46f 6280 	mvn.w	r2, #1024	; 0x400
 8004694:	615a      	str	r2, [r3, #20]

    hi2c->PreviousState       = I2C_STATE_NONE;
 8004696:	687b      	ldr	r3, [r7, #4]
 8004698:	2200      	movs	r2, #0
 800469a:	631a      	str	r2, [r3, #48]	; 0x30
    hi2c->State               = HAL_I2C_STATE_READY;
 800469c:	687b      	ldr	r3, [r7, #4]
 800469e:	2220      	movs	r2, #32
 80046a0:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
    hi2c->Mode                = HAL_I2C_MODE_NONE;
 80046a4:	687b      	ldr	r3, [r7, #4]
 80046a6:	2200      	movs	r2, #0
 80046a8:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
    hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
 80046ac:	687b      	ldr	r3, [r7, #4]
 80046ae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80046b0:	f043 0204 	orr.w	r2, r3, #4
 80046b4:	687b      	ldr	r3, [r7, #4]
 80046b6:	641a      	str	r2, [r3, #64]	; 0x40

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 80046b8:	687b      	ldr	r3, [r7, #4]
 80046ba:	2200      	movs	r2, #0
 80046bc:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    return HAL_ERROR;
 80046c0:	2301      	movs	r3, #1
 80046c2:	e000      	b.n	80046c6 <I2C_IsAcknowledgeFailed+0x52>
  }
  return HAL_OK;
 80046c4:	2300      	movs	r3, #0
}
 80046c6:	4618      	mov	r0, r3
 80046c8:	370c      	adds	r7, #12
 80046ca:	46bd      	mov	sp, r7
 80046cc:	bc80      	pop	{r7}
 80046ce:	4770      	bx	lr

080046d0 <HAL_PWR_EnterSTOPMode>:
  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
  * @retval None
  */
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
 80046d0:	b480      	push	{r7}
 80046d2:	b083      	sub	sp, #12
 80046d4:	af00      	add	r7, sp, #0
 80046d6:	6078      	str	r0, [r7, #4]
 80046d8:	460b      	mov	r3, r1
 80046da:	70fb      	strb	r3, [r7, #3]
  /* Check the parameters */
  assert_param(IS_PWR_REGULATOR(Regulator));
  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));

  /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
 80046dc:	4b10      	ldr	r3, [pc, #64]	; (8004720 <HAL_PWR_EnterSTOPMode+0x50>)
 80046de:	681b      	ldr	r3, [r3, #0]
 80046e0:	f023 0203 	bic.w	r2, r3, #3
 80046e4:	490e      	ldr	r1, [pc, #56]	; (8004720 <HAL_PWR_EnterSTOPMode+0x50>)
 80046e6:	687b      	ldr	r3, [r7, #4]
 80046e8:	4313      	orrs	r3, r2
 80046ea:	600b      	str	r3, [r1, #0]

  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 80046ec:	4b0d      	ldr	r3, [pc, #52]	; (8004724 <HAL_PWR_EnterSTOPMode+0x54>)
 80046ee:	691b      	ldr	r3, [r3, #16]
 80046f0:	4a0c      	ldr	r2, [pc, #48]	; (8004724 <HAL_PWR_EnterSTOPMode+0x54>)
 80046f2:	f043 0304 	orr.w	r3, r3, #4
 80046f6:	6113      	str	r3, [r2, #16]

  /* Select Stop mode entry --------------------------------------------------*/
  if(STOPEntry == PWR_STOPENTRY_WFI)
 80046f8:	78fb      	ldrb	r3, [r7, #3]
 80046fa:	2b01      	cmp	r3, #1
 80046fc:	d101      	bne.n	8004702 <HAL_PWR_EnterSTOPMode+0x32>
  {
    /* Request Wait For Interrupt */
    __WFI();
 80046fe:	bf30      	wfi
 8004700:	e002      	b.n	8004708 <HAL_PWR_EnterSTOPMode+0x38>
  }
  else
  {
    /* Request Wait For Event */
    __SEV();
 8004702:	bf40      	sev
    __WFE();
 8004704:	bf20      	wfe
    __WFE();
 8004706:	bf20      	wfe
  }
  /* Reset SLEEPDEEP bit of Cortex System Control Register */
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 8004708:	4b06      	ldr	r3, [pc, #24]	; (8004724 <HAL_PWR_EnterSTOPMode+0x54>)
 800470a:	691b      	ldr	r3, [r3, #16]
 800470c:	4a05      	ldr	r2, [pc, #20]	; (8004724 <HAL_PWR_EnterSTOPMode+0x54>)
 800470e:	f023 0304 	bic.w	r3, r3, #4
 8004712:	6113      	str	r3, [r2, #16]
}
 8004714:	bf00      	nop
 8004716:	370c      	adds	r7, #12
 8004718:	46bd      	mov	sp, r7
 800471a:	bc80      	pop	{r7}
 800471c:	4770      	bx	lr
 800471e:	bf00      	nop
 8004720:	40007000 	.word	0x40007000
 8004724:	e000ed00 	.word	0xe000ed00

08004728 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8004728:	b580      	push	{r7, lr}
 800472a:	b088      	sub	sp, #32
 800472c:	af00      	add	r7, sp, #0
 800472e:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  HAL_StatusTypeDef status;
  uint32_t sysclk_source, pll_config;

  /* Check the parameters */
  if(RCC_OscInitStruct == NULL)
 8004730:	687b      	ldr	r3, [r7, #4]
 8004732:	2b00      	cmp	r3, #0
 8004734:	d101      	bne.n	800473a <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 8004736:	2301      	movs	r3, #1
 8004738:	e31d      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
  }

  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 800473a:	4b94      	ldr	r3, [pc, #592]	; (800498c <HAL_RCC_OscConfig+0x264>)
 800473c:	689b      	ldr	r3, [r3, #8]
 800473e:	f003 030c 	and.w	r3, r3, #12
 8004742:	61bb      	str	r3, [r7, #24]
  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
 8004744:	4b91      	ldr	r3, [pc, #580]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004746:	689b      	ldr	r3, [r3, #8]
 8004748:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 800474c:	617b      	str	r3, [r7, #20]

  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 800474e:	687b      	ldr	r3, [r7, #4]
 8004750:	681b      	ldr	r3, [r3, #0]
 8004752:	f003 0301 	and.w	r3, r3, #1
 8004756:	2b00      	cmp	r3, #0
 8004758:	d07b      	beq.n	8004852 <HAL_RCC_OscConfig+0x12a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
 800475a:	69bb      	ldr	r3, [r7, #24]
 800475c:	2b08      	cmp	r3, #8
 800475e:	d006      	beq.n	800476e <HAL_RCC_OscConfig+0x46>
       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
 8004760:	69bb      	ldr	r3, [r7, #24]
 8004762:	2b0c      	cmp	r3, #12
 8004764:	d10f      	bne.n	8004786 <HAL_RCC_OscConfig+0x5e>
 8004766:	697b      	ldr	r3, [r7, #20]
 8004768:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 800476c:	d10b      	bne.n	8004786 <HAL_RCC_OscConfig+0x5e>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 800476e:	4b87      	ldr	r3, [pc, #540]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004770:	681b      	ldr	r3, [r3, #0]
 8004772:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8004776:	2b00      	cmp	r3, #0
 8004778:	d06a      	beq.n	8004850 <HAL_RCC_OscConfig+0x128>
 800477a:	687b      	ldr	r3, [r7, #4]
 800477c:	685b      	ldr	r3, [r3, #4]
 800477e:	2b00      	cmp	r3, #0
 8004780:	d166      	bne.n	8004850 <HAL_RCC_OscConfig+0x128>
      {
        return HAL_ERROR;
 8004782:	2301      	movs	r3, #1
 8004784:	e2f7      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004786:	687b      	ldr	r3, [r7, #4]
 8004788:	685b      	ldr	r3, [r3, #4]
 800478a:	2b01      	cmp	r3, #1
 800478c:	d106      	bne.n	800479c <HAL_RCC_OscConfig+0x74>
 800478e:	4b7f      	ldr	r3, [pc, #508]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004790:	681b      	ldr	r3, [r3, #0]
 8004792:	4a7e      	ldr	r2, [pc, #504]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004794:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8004798:	6013      	str	r3, [r2, #0]
 800479a:	e02d      	b.n	80047f8 <HAL_RCC_OscConfig+0xd0>
 800479c:	687b      	ldr	r3, [r7, #4]
 800479e:	685b      	ldr	r3, [r3, #4]
 80047a0:	2b00      	cmp	r3, #0
 80047a2:	d10c      	bne.n	80047be <HAL_RCC_OscConfig+0x96>
 80047a4:	4b79      	ldr	r3, [pc, #484]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047a6:	681b      	ldr	r3, [r3, #0]
 80047a8:	4a78      	ldr	r2, [pc, #480]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047aa:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 80047ae:	6013      	str	r3, [r2, #0]
 80047b0:	4b76      	ldr	r3, [pc, #472]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047b2:	681b      	ldr	r3, [r3, #0]
 80047b4:	4a75      	ldr	r2, [pc, #468]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047b6:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 80047ba:	6013      	str	r3, [r2, #0]
 80047bc:	e01c      	b.n	80047f8 <HAL_RCC_OscConfig+0xd0>
 80047be:	687b      	ldr	r3, [r7, #4]
 80047c0:	685b      	ldr	r3, [r3, #4]
 80047c2:	2b05      	cmp	r3, #5
 80047c4:	d10c      	bne.n	80047e0 <HAL_RCC_OscConfig+0xb8>
 80047c6:	4b71      	ldr	r3, [pc, #452]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047c8:	681b      	ldr	r3, [r3, #0]
 80047ca:	4a70      	ldr	r2, [pc, #448]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047cc:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 80047d0:	6013      	str	r3, [r2, #0]
 80047d2:	4b6e      	ldr	r3, [pc, #440]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047d4:	681b      	ldr	r3, [r3, #0]
 80047d6:	4a6d      	ldr	r2, [pc, #436]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047d8:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 80047dc:	6013      	str	r3, [r2, #0]
 80047de:	e00b      	b.n	80047f8 <HAL_RCC_OscConfig+0xd0>
 80047e0:	4b6a      	ldr	r3, [pc, #424]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047e2:	681b      	ldr	r3, [r3, #0]
 80047e4:	4a69      	ldr	r2, [pc, #420]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047e6:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 80047ea:	6013      	str	r3, [r2, #0]
 80047ec:	4b67      	ldr	r3, [pc, #412]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047ee:	681b      	ldr	r3, [r3, #0]
 80047f0:	4a66      	ldr	r2, [pc, #408]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80047f2:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 80047f6:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 80047f8:	687b      	ldr	r3, [r7, #4]
 80047fa:	685b      	ldr	r3, [r3, #4]
 80047fc:	2b00      	cmp	r3, #0
 80047fe:	d013      	beq.n	8004828 <HAL_RCC_OscConfig+0x100>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004800:	f7fd fe22 	bl	8002448 <HAL_GetTick>
 8004804:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 8004806:	e008      	b.n	800481a <HAL_RCC_OscConfig+0xf2>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8004808:	f7fd fe1e 	bl	8002448 <HAL_GetTick>
 800480c:	4602      	mov	r2, r0
 800480e:	693b      	ldr	r3, [r7, #16]
 8004810:	1ad3      	subs	r3, r2, r3
 8004812:	2b64      	cmp	r3, #100	; 0x64
 8004814:	d901      	bls.n	800481a <HAL_RCC_OscConfig+0xf2>
          {
            return HAL_TIMEOUT;
 8004816:	2303      	movs	r3, #3
 8004818:	e2ad      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 800481a:	4b5c      	ldr	r3, [pc, #368]	; (800498c <HAL_RCC_OscConfig+0x264>)
 800481c:	681b      	ldr	r3, [r3, #0]
 800481e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8004822:	2b00      	cmp	r3, #0
 8004824:	d0f0      	beq.n	8004808 <HAL_RCC_OscConfig+0xe0>
 8004826:	e014      	b.n	8004852 <HAL_RCC_OscConfig+0x12a>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004828:	f7fd fe0e 	bl	8002448 <HAL_GetTick>
 800482c:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 800482e:	e008      	b.n	8004842 <HAL_RCC_OscConfig+0x11a>
        {
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8004830:	f7fd fe0a 	bl	8002448 <HAL_GetTick>
 8004834:	4602      	mov	r2, r0
 8004836:	693b      	ldr	r3, [r7, #16]
 8004838:	1ad3      	subs	r3, r2, r3
 800483a:	2b64      	cmp	r3, #100	; 0x64
 800483c:	d901      	bls.n	8004842 <HAL_RCC_OscConfig+0x11a>
          {
            return HAL_TIMEOUT;
 800483e:	2303      	movs	r3, #3
 8004840:	e299      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 8004842:	4b52      	ldr	r3, [pc, #328]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004844:	681b      	ldr	r3, [r3, #0]
 8004846:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800484a:	2b00      	cmp	r3, #0
 800484c:	d1f0      	bne.n	8004830 <HAL_RCC_OscConfig+0x108>
 800484e:	e000      	b.n	8004852 <HAL_RCC_OscConfig+0x12a>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8004850:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8004852:	687b      	ldr	r3, [r7, #4]
 8004854:	681b      	ldr	r3, [r3, #0]
 8004856:	f003 0302 	and.w	r3, r3, #2
 800485a:	2b00      	cmp	r3, #0
 800485c:	d05a      	beq.n	8004914 <HAL_RCC_OscConfig+0x1ec>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
 800485e:	69bb      	ldr	r3, [r7, #24]
 8004860:	2b04      	cmp	r3, #4
 8004862:	d005      	beq.n	8004870 <HAL_RCC_OscConfig+0x148>
       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
 8004864:	69bb      	ldr	r3, [r7, #24]
 8004866:	2b0c      	cmp	r3, #12
 8004868:	d119      	bne.n	800489e <HAL_RCC_OscConfig+0x176>
 800486a:	697b      	ldr	r3, [r7, #20]
 800486c:	2b00      	cmp	r3, #0
 800486e:	d116      	bne.n	800489e <HAL_RCC_OscConfig+0x176>
    {
      /* When HSI is used as system clock it will not disabled */
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8004870:	4b46      	ldr	r3, [pc, #280]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004872:	681b      	ldr	r3, [r3, #0]
 8004874:	f003 0302 	and.w	r3, r3, #2
 8004878:	2b00      	cmp	r3, #0
 800487a:	d005      	beq.n	8004888 <HAL_RCC_OscConfig+0x160>
 800487c:	687b      	ldr	r3, [r7, #4]
 800487e:	68db      	ldr	r3, [r3, #12]
 8004880:	2b01      	cmp	r3, #1
 8004882:	d001      	beq.n	8004888 <HAL_RCC_OscConfig+0x160>
      {
        return HAL_ERROR;
 8004884:	2301      	movs	r3, #1
 8004886:	e276      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8004888:	4b40      	ldr	r3, [pc, #256]	; (800498c <HAL_RCC_OscConfig+0x264>)
 800488a:	685b      	ldr	r3, [r3, #4]
 800488c:	f423 52f8 	bic.w	r2, r3, #7936	; 0x1f00
 8004890:	687b      	ldr	r3, [r7, #4]
 8004892:	691b      	ldr	r3, [r3, #16]
 8004894:	021b      	lsls	r3, r3, #8
 8004896:	493d      	ldr	r1, [pc, #244]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004898:	4313      	orrs	r3, r2
 800489a:	604b      	str	r3, [r1, #4]
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 800489c:	e03a      	b.n	8004914 <HAL_RCC_OscConfig+0x1ec>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 800489e:	687b      	ldr	r3, [r7, #4]
 80048a0:	68db      	ldr	r3, [r3, #12]
 80048a2:	2b00      	cmp	r3, #0
 80048a4:	d020      	beq.n	80048e8 <HAL_RCC_OscConfig+0x1c0>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 80048a6:	4b3a      	ldr	r3, [pc, #232]	; (8004990 <HAL_RCC_OscConfig+0x268>)
 80048a8:	2201      	movs	r2, #1
 80048aa:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80048ac:	f7fd fdcc 	bl	8002448 <HAL_GetTick>
 80048b0:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 80048b2:	e008      	b.n	80048c6 <HAL_RCC_OscConfig+0x19e>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 80048b4:	f7fd fdc8 	bl	8002448 <HAL_GetTick>
 80048b8:	4602      	mov	r2, r0
 80048ba:	693b      	ldr	r3, [r7, #16]
 80048bc:	1ad3      	subs	r3, r2, r3
 80048be:	2b02      	cmp	r3, #2
 80048c0:	d901      	bls.n	80048c6 <HAL_RCC_OscConfig+0x19e>
          {
            return HAL_TIMEOUT;
 80048c2:	2303      	movs	r3, #3
 80048c4:	e257      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 80048c6:	4b31      	ldr	r3, [pc, #196]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80048c8:	681b      	ldr	r3, [r3, #0]
 80048ca:	f003 0302 	and.w	r3, r3, #2
 80048ce:	2b00      	cmp	r3, #0
 80048d0:	d0f0      	beq.n	80048b4 <HAL_RCC_OscConfig+0x18c>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80048d2:	4b2e      	ldr	r3, [pc, #184]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80048d4:	685b      	ldr	r3, [r3, #4]
 80048d6:	f423 52f8 	bic.w	r2, r3, #7936	; 0x1f00
 80048da:	687b      	ldr	r3, [r7, #4]
 80048dc:	691b      	ldr	r3, [r3, #16]
 80048de:	021b      	lsls	r3, r3, #8
 80048e0:	492a      	ldr	r1, [pc, #168]	; (800498c <HAL_RCC_OscConfig+0x264>)
 80048e2:	4313      	orrs	r3, r2
 80048e4:	604b      	str	r3, [r1, #4]
 80048e6:	e015      	b.n	8004914 <HAL_RCC_OscConfig+0x1ec>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 80048e8:	4b29      	ldr	r3, [pc, #164]	; (8004990 <HAL_RCC_OscConfig+0x268>)
 80048ea:	2200      	movs	r2, #0
 80048ec:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80048ee:	f7fd fdab 	bl	8002448 <HAL_GetTick>
 80048f2:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 80048f4:	e008      	b.n	8004908 <HAL_RCC_OscConfig+0x1e0>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 80048f6:	f7fd fda7 	bl	8002448 <HAL_GetTick>
 80048fa:	4602      	mov	r2, r0
 80048fc:	693b      	ldr	r3, [r7, #16]
 80048fe:	1ad3      	subs	r3, r2, r3
 8004900:	2b02      	cmp	r3, #2
 8004902:	d901      	bls.n	8004908 <HAL_RCC_OscConfig+0x1e0>
          {
            return HAL_TIMEOUT;
 8004904:	2303      	movs	r3, #3
 8004906:	e236      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 8004908:	4b20      	ldr	r3, [pc, #128]	; (800498c <HAL_RCC_OscConfig+0x264>)
 800490a:	681b      	ldr	r3, [r3, #0]
 800490c:	f003 0302 	and.w	r3, r3, #2
 8004910:	2b00      	cmp	r3, #0
 8004912:	d1f0      	bne.n	80048f6 <HAL_RCC_OscConfig+0x1ce>
        }
      }
    }
  }
  /*----------------------------- MSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
 8004914:	687b      	ldr	r3, [r7, #4]
 8004916:	681b      	ldr	r3, [r3, #0]
 8004918:	f003 0310 	and.w	r3, r3, #16
 800491c:	2b00      	cmp	r3, #0
 800491e:	f000 80b8 	beq.w	8004a92 <HAL_RCC_OscConfig+0x36a>
  {
    /* When the MSI is used as system clock it will not be disabled */
    if(sysclk_source == RCC_CFGR_SWS_MSI)
 8004922:	69bb      	ldr	r3, [r7, #24]
 8004924:	2b00      	cmp	r3, #0
 8004926:	d170      	bne.n	8004a0a <HAL_RCC_OscConfig+0x2e2>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 8004928:	4b18      	ldr	r3, [pc, #96]	; (800498c <HAL_RCC_OscConfig+0x264>)
 800492a:	681b      	ldr	r3, [r3, #0]
 800492c:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8004930:	2b00      	cmp	r3, #0
 8004932:	d005      	beq.n	8004940 <HAL_RCC_OscConfig+0x218>
 8004934:	687b      	ldr	r3, [r7, #4]
 8004936:	699b      	ldr	r3, [r3, #24]
 8004938:	2b00      	cmp	r3, #0
 800493a:	d101      	bne.n	8004940 <HAL_RCC_OscConfig+0x218>
      {
        return HAL_ERROR;
 800493c:	2301      	movs	r3, #1
 800493e:	e21a      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
           must be correctly programmed according to the frequency of the CPU clock
           (HCLK) and the supply voltage of the device. */
        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
 8004940:	687b      	ldr	r3, [r7, #4]
 8004942:	6a1a      	ldr	r2, [r3, #32]
 8004944:	4b11      	ldr	r3, [pc, #68]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004946:	685b      	ldr	r3, [r3, #4]
 8004948:	f403 4360 	and.w	r3, r3, #57344	; 0xe000
 800494c:	429a      	cmp	r2, r3
 800494e:	d921      	bls.n	8004994 <HAL_RCC_OscConfig+0x26c>
        {
          /* First increase number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 8004950:	687b      	ldr	r3, [r7, #4]
 8004952:	6a1b      	ldr	r3, [r3, #32]
 8004954:	4618      	mov	r0, r3
 8004956:	f000 fc4b 	bl	80051f0 <RCC_SetFlashLatencyFromMSIRange>
 800495a:	4603      	mov	r3, r0
 800495c:	2b00      	cmp	r3, #0
 800495e:	d001      	beq.n	8004964 <HAL_RCC_OscConfig+0x23c>
          {
            return HAL_ERROR;
 8004960:	2301      	movs	r3, #1
 8004962:	e208      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
          }

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8004964:	4b09      	ldr	r3, [pc, #36]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004966:	685b      	ldr	r3, [r3, #4]
 8004968:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 800496c:	687b      	ldr	r3, [r7, #4]
 800496e:	6a1b      	ldr	r3, [r3, #32]
 8004970:	4906      	ldr	r1, [pc, #24]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004972:	4313      	orrs	r3, r2
 8004974:	604b      	str	r3, [r1, #4]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8004976:	4b05      	ldr	r3, [pc, #20]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004978:	685b      	ldr	r3, [r3, #4]
 800497a:	f023 427f 	bic.w	r2, r3, #4278190080	; 0xff000000
 800497e:	687b      	ldr	r3, [r7, #4]
 8004980:	69db      	ldr	r3, [r3, #28]
 8004982:	061b      	lsls	r3, r3, #24
 8004984:	4901      	ldr	r1, [pc, #4]	; (800498c <HAL_RCC_OscConfig+0x264>)
 8004986:	4313      	orrs	r3, r2
 8004988:	604b      	str	r3, [r1, #4]
 800498a:	e020      	b.n	80049ce <HAL_RCC_OscConfig+0x2a6>
 800498c:	40023800 	.word	0x40023800
 8004990:	42470000 	.word	0x42470000
        }
        else
        {
          /* Else, keep current flash latency while decreasing applies */
          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8004994:	4ba4      	ldr	r3, [pc, #656]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004996:	685b      	ldr	r3, [r3, #4]
 8004998:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 800499c:	687b      	ldr	r3, [r7, #4]
 800499e:	6a1b      	ldr	r3, [r3, #32]
 80049a0:	49a1      	ldr	r1, [pc, #644]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 80049a2:	4313      	orrs	r3, r2
 80049a4:	604b      	str	r3, [r1, #4]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 80049a6:	4ba0      	ldr	r3, [pc, #640]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 80049a8:	685b      	ldr	r3, [r3, #4]
 80049aa:	f023 427f 	bic.w	r2, r3, #4278190080	; 0xff000000
 80049ae:	687b      	ldr	r3, [r7, #4]
 80049b0:	69db      	ldr	r3, [r3, #28]
 80049b2:	061b      	lsls	r3, r3, #24
 80049b4:	499c      	ldr	r1, [pc, #624]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 80049b6:	4313      	orrs	r3, r2
 80049b8:	604b      	str	r3, [r1, #4]

          /* Decrease number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 80049ba:	687b      	ldr	r3, [r7, #4]
 80049bc:	6a1b      	ldr	r3, [r3, #32]
 80049be:	4618      	mov	r0, r3
 80049c0:	f000 fc16 	bl	80051f0 <RCC_SetFlashLatencyFromMSIRange>
 80049c4:	4603      	mov	r3, r0
 80049c6:	2b00      	cmp	r3, #0
 80049c8:	d001      	beq.n	80049ce <HAL_RCC_OscConfig+0x2a6>
          {
            return HAL_ERROR;
 80049ca:	2301      	movs	r3, #1
 80049cc:	e1d3      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
          }
        }

        /* Update the SystemCoreClock global variable */
        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
 80049ce:	687b      	ldr	r3, [r7, #4]
 80049d0:	6a1b      	ldr	r3, [r3, #32]
 80049d2:	0b5b      	lsrs	r3, r3, #13
 80049d4:	3301      	adds	r3, #1
 80049d6:	f44f 4200 	mov.w	r2, #32768	; 0x8000
 80049da:	fa02 f303 	lsl.w	r3, r2, r3
                           >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
 80049de:	4a92      	ldr	r2, [pc, #584]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 80049e0:	6892      	ldr	r2, [r2, #8]
 80049e2:	0912      	lsrs	r2, r2, #4
 80049e4:	f002 020f 	and.w	r2, r2, #15
 80049e8:	4990      	ldr	r1, [pc, #576]	; (8004c2c <HAL_RCC_OscConfig+0x504>)
 80049ea:	5c8a      	ldrb	r2, [r1, r2]
 80049ec:	40d3      	lsrs	r3, r2
        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
 80049ee:	4a90      	ldr	r2, [pc, #576]	; (8004c30 <HAL_RCC_OscConfig+0x508>)
 80049f0:	6013      	str	r3, [r2, #0]

        /* Configure the source of time base considering new system clocks settings*/
        status = HAL_InitTick(uwTickPrio);
 80049f2:	4b90      	ldr	r3, [pc, #576]	; (8004c34 <HAL_RCC_OscConfig+0x50c>)
 80049f4:	681b      	ldr	r3, [r3, #0]
 80049f6:	4618      	mov	r0, r3
 80049f8:	f7fd fcda 	bl	80023b0 <HAL_InitTick>
 80049fc:	4603      	mov	r3, r0
 80049fe:	73fb      	strb	r3, [r7, #15]
        if(status != HAL_OK)
 8004a00:	7bfb      	ldrb	r3, [r7, #15]
 8004a02:	2b00      	cmp	r3, #0
 8004a04:	d045      	beq.n	8004a92 <HAL_RCC_OscConfig+0x36a>
        {
          return status;
 8004a06:	7bfb      	ldrb	r3, [r7, #15]
 8004a08:	e1b5      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
    {
      /* Check MSI State */
      assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));

      /* Check the MSI State */
      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
 8004a0a:	687b      	ldr	r3, [r7, #4]
 8004a0c:	699b      	ldr	r3, [r3, #24]
 8004a0e:	2b00      	cmp	r3, #0
 8004a10:	d029      	beq.n	8004a66 <HAL_RCC_OscConfig+0x33e>
      {
        /* Enable the Multi Speed oscillator (MSI). */
        __HAL_RCC_MSI_ENABLE();
 8004a12:	4b89      	ldr	r3, [pc, #548]	; (8004c38 <HAL_RCC_OscConfig+0x510>)
 8004a14:	2201      	movs	r2, #1
 8004a16:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004a18:	f7fd fd16 	bl	8002448 <HAL_GetTick>
 8004a1c:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 8004a1e:	e008      	b.n	8004a32 <HAL_RCC_OscConfig+0x30a>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8004a20:	f7fd fd12 	bl	8002448 <HAL_GetTick>
 8004a24:	4602      	mov	r2, r0
 8004a26:	693b      	ldr	r3, [r7, #16]
 8004a28:	1ad3      	subs	r3, r2, r3
 8004a2a:	2b02      	cmp	r3, #2
 8004a2c:	d901      	bls.n	8004a32 <HAL_RCC_OscConfig+0x30a>
          {
            return HAL_TIMEOUT;
 8004a2e:	2303      	movs	r3, #3
 8004a30:	e1a1      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 8004a32:	4b7d      	ldr	r3, [pc, #500]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004a34:	681b      	ldr	r3, [r3, #0]
 8004a36:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8004a3a:	2b00      	cmp	r3, #0
 8004a3c:	d0f0      	beq.n	8004a20 <HAL_RCC_OscConfig+0x2f8>
        /* Check MSICalibrationValue and MSIClockRange input parameters */
        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8004a3e:	4b7a      	ldr	r3, [pc, #488]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004a40:	685b      	ldr	r3, [r3, #4]
 8004a42:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 8004a46:	687b      	ldr	r3, [r7, #4]
 8004a48:	6a1b      	ldr	r3, [r3, #32]
 8004a4a:	4977      	ldr	r1, [pc, #476]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004a4c:	4313      	orrs	r3, r2
 8004a4e:	604b      	str	r3, [r1, #4]
         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8004a50:	4b75      	ldr	r3, [pc, #468]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004a52:	685b      	ldr	r3, [r3, #4]
 8004a54:	f023 427f 	bic.w	r2, r3, #4278190080	; 0xff000000
 8004a58:	687b      	ldr	r3, [r7, #4]
 8004a5a:	69db      	ldr	r3, [r3, #28]
 8004a5c:	061b      	lsls	r3, r3, #24
 8004a5e:	4972      	ldr	r1, [pc, #456]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004a60:	4313      	orrs	r3, r2
 8004a62:	604b      	str	r3, [r1, #4]
 8004a64:	e015      	b.n	8004a92 <HAL_RCC_OscConfig+0x36a>

      }
      else
      {
        /* Disable the Multi Speed oscillator (MSI). */
        __HAL_RCC_MSI_DISABLE();
 8004a66:	4b74      	ldr	r3, [pc, #464]	; (8004c38 <HAL_RCC_OscConfig+0x510>)
 8004a68:	2200      	movs	r2, #0
 8004a6a:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004a6c:	f7fd fcec 	bl	8002448 <HAL_GetTick>
 8004a70:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
 8004a72:	e008      	b.n	8004a86 <HAL_RCC_OscConfig+0x35e>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8004a74:	f7fd fce8 	bl	8002448 <HAL_GetTick>
 8004a78:	4602      	mov	r2, r0
 8004a7a:	693b      	ldr	r3, [r7, #16]
 8004a7c:	1ad3      	subs	r3, r2, r3
 8004a7e:	2b02      	cmp	r3, #2
 8004a80:	d901      	bls.n	8004a86 <HAL_RCC_OscConfig+0x35e>
          {
            return HAL_TIMEOUT;
 8004a82:	2303      	movs	r3, #3
 8004a84:	e177      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
 8004a86:	4b68      	ldr	r3, [pc, #416]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004a88:	681b      	ldr	r3, [r3, #0]
 8004a8a:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8004a8e:	2b00      	cmp	r3, #0
 8004a90:	d1f0      	bne.n	8004a74 <HAL_RCC_OscConfig+0x34c>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8004a92:	687b      	ldr	r3, [r7, #4]
 8004a94:	681b      	ldr	r3, [r3, #0]
 8004a96:	f003 0308 	and.w	r3, r3, #8
 8004a9a:	2b00      	cmp	r3, #0
 8004a9c:	d030      	beq.n	8004b00 <HAL_RCC_OscConfig+0x3d8>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8004a9e:	687b      	ldr	r3, [r7, #4]
 8004aa0:	695b      	ldr	r3, [r3, #20]
 8004aa2:	2b00      	cmp	r3, #0
 8004aa4:	d016      	beq.n	8004ad4 <HAL_RCC_OscConfig+0x3ac>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8004aa6:	4b65      	ldr	r3, [pc, #404]	; (8004c3c <HAL_RCC_OscConfig+0x514>)
 8004aa8:	2201      	movs	r2, #1
 8004aaa:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8004aac:	f7fd fccc 	bl	8002448 <HAL_GetTick>
 8004ab0:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 8004ab2:	e008      	b.n	8004ac6 <HAL_RCC_OscConfig+0x39e>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8004ab4:	f7fd fcc8 	bl	8002448 <HAL_GetTick>
 8004ab8:	4602      	mov	r2, r0
 8004aba:	693b      	ldr	r3, [r7, #16]
 8004abc:	1ad3      	subs	r3, r2, r3
 8004abe:	2b02      	cmp	r3, #2
 8004ac0:	d901      	bls.n	8004ac6 <HAL_RCC_OscConfig+0x39e>
        {
          return HAL_TIMEOUT;
 8004ac2:	2303      	movs	r3, #3
 8004ac4:	e157      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 8004ac6:	4b58      	ldr	r3, [pc, #352]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004ac8:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004aca:	f003 0302 	and.w	r3, r3, #2
 8004ace:	2b00      	cmp	r3, #0
 8004ad0:	d0f0      	beq.n	8004ab4 <HAL_RCC_OscConfig+0x38c>
 8004ad2:	e015      	b.n	8004b00 <HAL_RCC_OscConfig+0x3d8>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8004ad4:	4b59      	ldr	r3, [pc, #356]	; (8004c3c <HAL_RCC_OscConfig+0x514>)
 8004ad6:	2200      	movs	r2, #0
 8004ad8:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8004ada:	f7fd fcb5 	bl	8002448 <HAL_GetTick>
 8004ade:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8004ae0:	e008      	b.n	8004af4 <HAL_RCC_OscConfig+0x3cc>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8004ae2:	f7fd fcb1 	bl	8002448 <HAL_GetTick>
 8004ae6:	4602      	mov	r2, r0
 8004ae8:	693b      	ldr	r3, [r7, #16]
 8004aea:	1ad3      	subs	r3, r2, r3
 8004aec:	2b02      	cmp	r3, #2
 8004aee:	d901      	bls.n	8004af4 <HAL_RCC_OscConfig+0x3cc>
        {
          return HAL_TIMEOUT;
 8004af0:	2303      	movs	r3, #3
 8004af2:	e140      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8004af4:	4b4c      	ldr	r3, [pc, #304]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004af6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004af8:	f003 0302 	and.w	r3, r3, #2
 8004afc:	2b00      	cmp	r3, #0
 8004afe:	d1f0      	bne.n	8004ae2 <HAL_RCC_OscConfig+0x3ba>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8004b00:	687b      	ldr	r3, [r7, #4]
 8004b02:	681b      	ldr	r3, [r3, #0]
 8004b04:	f003 0304 	and.w	r3, r3, #4
 8004b08:	2b00      	cmp	r3, #0
 8004b0a:	f000 80b5 	beq.w	8004c78 <HAL_RCC_OscConfig+0x550>
  {
    FlagStatus       pwrclkchanged = RESET;
 8004b0e:	2300      	movs	r3, #0
 8004b10:	77fb      	strb	r3, [r7, #31]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8004b12:	4b45      	ldr	r3, [pc, #276]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b14:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004b16:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8004b1a:	2b00      	cmp	r3, #0
 8004b1c:	d10d      	bne.n	8004b3a <HAL_RCC_OscConfig+0x412>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8004b1e:	4b42      	ldr	r3, [pc, #264]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b20:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004b22:	4a41      	ldr	r2, [pc, #260]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b24:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8004b28:	6253      	str	r3, [r2, #36]	; 0x24
 8004b2a:	4b3f      	ldr	r3, [pc, #252]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b2c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004b2e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8004b32:	60bb      	str	r3, [r7, #8]
 8004b34:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8004b36:	2301      	movs	r3, #1
 8004b38:	77fb      	strb	r3, [r7, #31]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004b3a:	4b41      	ldr	r3, [pc, #260]	; (8004c40 <HAL_RCC_OscConfig+0x518>)
 8004b3c:	681b      	ldr	r3, [r3, #0]
 8004b3e:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8004b42:	2b00      	cmp	r3, #0
 8004b44:	d118      	bne.n	8004b78 <HAL_RCC_OscConfig+0x450>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8004b46:	4b3e      	ldr	r3, [pc, #248]	; (8004c40 <HAL_RCC_OscConfig+0x518>)
 8004b48:	681b      	ldr	r3, [r3, #0]
 8004b4a:	4a3d      	ldr	r2, [pc, #244]	; (8004c40 <HAL_RCC_OscConfig+0x518>)
 8004b4c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8004b50:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8004b52:	f7fd fc79 	bl	8002448 <HAL_GetTick>
 8004b56:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004b58:	e008      	b.n	8004b6c <HAL_RCC_OscConfig+0x444>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8004b5a:	f7fd fc75 	bl	8002448 <HAL_GetTick>
 8004b5e:	4602      	mov	r2, r0
 8004b60:	693b      	ldr	r3, [r7, #16]
 8004b62:	1ad3      	subs	r3, r2, r3
 8004b64:	2b64      	cmp	r3, #100	; 0x64
 8004b66:	d901      	bls.n	8004b6c <HAL_RCC_OscConfig+0x444>
        {
          return HAL_TIMEOUT;
 8004b68:	2303      	movs	r3, #3
 8004b6a:	e104      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004b6c:	4b34      	ldr	r3, [pc, #208]	; (8004c40 <HAL_RCC_OscConfig+0x518>)
 8004b6e:	681b      	ldr	r3, [r3, #0]
 8004b70:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8004b74:	2b00      	cmp	r3, #0
 8004b76:	d0f0      	beq.n	8004b5a <HAL_RCC_OscConfig+0x432>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004b78:	687b      	ldr	r3, [r7, #4]
 8004b7a:	689b      	ldr	r3, [r3, #8]
 8004b7c:	2b01      	cmp	r3, #1
 8004b7e:	d106      	bne.n	8004b8e <HAL_RCC_OscConfig+0x466>
 8004b80:	4b29      	ldr	r3, [pc, #164]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b82:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004b84:	4a28      	ldr	r2, [pc, #160]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b86:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8004b8a:	6353      	str	r3, [r2, #52]	; 0x34
 8004b8c:	e02d      	b.n	8004bea <HAL_RCC_OscConfig+0x4c2>
 8004b8e:	687b      	ldr	r3, [r7, #4]
 8004b90:	689b      	ldr	r3, [r3, #8]
 8004b92:	2b00      	cmp	r3, #0
 8004b94:	d10c      	bne.n	8004bb0 <HAL_RCC_OscConfig+0x488>
 8004b96:	4b24      	ldr	r3, [pc, #144]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b98:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004b9a:	4a23      	ldr	r2, [pc, #140]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004b9c:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 8004ba0:	6353      	str	r3, [r2, #52]	; 0x34
 8004ba2:	4b21      	ldr	r3, [pc, #132]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004ba4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004ba6:	4a20      	ldr	r2, [pc, #128]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004ba8:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
 8004bac:	6353      	str	r3, [r2, #52]	; 0x34
 8004bae:	e01c      	b.n	8004bea <HAL_RCC_OscConfig+0x4c2>
 8004bb0:	687b      	ldr	r3, [r7, #4]
 8004bb2:	689b      	ldr	r3, [r3, #8]
 8004bb4:	2b05      	cmp	r3, #5
 8004bb6:	d10c      	bne.n	8004bd2 <HAL_RCC_OscConfig+0x4aa>
 8004bb8:	4b1b      	ldr	r3, [pc, #108]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004bba:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004bbc:	4a1a      	ldr	r2, [pc, #104]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004bbe:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
 8004bc2:	6353      	str	r3, [r2, #52]	; 0x34
 8004bc4:	4b18      	ldr	r3, [pc, #96]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004bc6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004bc8:	4a17      	ldr	r2, [pc, #92]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004bca:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8004bce:	6353      	str	r3, [r2, #52]	; 0x34
 8004bd0:	e00b      	b.n	8004bea <HAL_RCC_OscConfig+0x4c2>
 8004bd2:	4b15      	ldr	r3, [pc, #84]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004bd4:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004bd6:	4a14      	ldr	r2, [pc, #80]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004bd8:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 8004bdc:	6353      	str	r3, [r2, #52]	; 0x34
 8004bde:	4b12      	ldr	r3, [pc, #72]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004be0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004be2:	4a11      	ldr	r2, [pc, #68]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004be4:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
 8004be8:	6353      	str	r3, [r2, #52]	; 0x34
    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8004bea:	687b      	ldr	r3, [r7, #4]
 8004bec:	689b      	ldr	r3, [r3, #8]
 8004bee:	2b00      	cmp	r3, #0
 8004bf0:	d015      	beq.n	8004c1e <HAL_RCC_OscConfig+0x4f6>
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8004bf2:	f7fd fc29 	bl	8002448 <HAL_GetTick>
 8004bf6:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8004bf8:	e00a      	b.n	8004c10 <HAL_RCC_OscConfig+0x4e8>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004bfa:	f7fd fc25 	bl	8002448 <HAL_GetTick>
 8004bfe:	4602      	mov	r2, r0
 8004c00:	693b      	ldr	r3, [r7, #16]
 8004c02:	1ad3      	subs	r3, r2, r3
 8004c04:	f241 3288 	movw	r2, #5000	; 0x1388
 8004c08:	4293      	cmp	r3, r2
 8004c0a:	d901      	bls.n	8004c10 <HAL_RCC_OscConfig+0x4e8>
        {
          return HAL_TIMEOUT;
 8004c0c:	2303      	movs	r3, #3
 8004c0e:	e0b2      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8004c10:	4b05      	ldr	r3, [pc, #20]	; (8004c28 <HAL_RCC_OscConfig+0x500>)
 8004c12:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004c14:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8004c18:	2b00      	cmp	r3, #0
 8004c1a:	d0ee      	beq.n	8004bfa <HAL_RCC_OscConfig+0x4d2>
 8004c1c:	e023      	b.n	8004c66 <HAL_RCC_OscConfig+0x53e>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8004c1e:	f7fd fc13 	bl	8002448 <HAL_GetTick>
 8004c22:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 8004c24:	e019      	b.n	8004c5a <HAL_RCC_OscConfig+0x532>
 8004c26:	bf00      	nop
 8004c28:	40023800 	.word	0x40023800
 8004c2c:	080098e0 	.word	0x080098e0
 8004c30:	20000000 	.word	0x20000000
 8004c34:	20000004 	.word	0x20000004
 8004c38:	42470020 	.word	0x42470020
 8004c3c:	42470680 	.word	0x42470680
 8004c40:	40007000 	.word	0x40007000
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004c44:	f7fd fc00 	bl	8002448 <HAL_GetTick>
 8004c48:	4602      	mov	r2, r0
 8004c4a:	693b      	ldr	r3, [r7, #16]
 8004c4c:	1ad3      	subs	r3, r2, r3
 8004c4e:	f241 3288 	movw	r2, #5000	; 0x1388
 8004c52:	4293      	cmp	r3, r2
 8004c54:	d901      	bls.n	8004c5a <HAL_RCC_OscConfig+0x532>
        {
          return HAL_TIMEOUT;
 8004c56:	2303      	movs	r3, #3
 8004c58:	e08d      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 8004c5a:	4b49      	ldr	r3, [pc, #292]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004c5c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004c5e:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8004c62:	2b00      	cmp	r3, #0
 8004c64:	d1ee      	bne.n	8004c44 <HAL_RCC_OscConfig+0x51c>
        }
      }
    }

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 8004c66:	7ffb      	ldrb	r3, [r7, #31]
 8004c68:	2b01      	cmp	r3, #1
 8004c6a:	d105      	bne.n	8004c78 <HAL_RCC_OscConfig+0x550>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8004c6c:	4b44      	ldr	r3, [pc, #272]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004c6e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004c70:	4a43      	ldr	r2, [pc, #268]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004c72:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8004c76:	6253      	str	r3, [r2, #36]	; 0x24
  }

  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8004c78:	687b      	ldr	r3, [r7, #4]
 8004c7a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004c7c:	2b00      	cmp	r3, #0
 8004c7e:	d079      	beq.n	8004d74 <HAL_RCC_OscConfig+0x64c>
  {
    /* Check if the PLL is used as system clock or not */
    if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8004c80:	69bb      	ldr	r3, [r7, #24]
 8004c82:	2b0c      	cmp	r3, #12
 8004c84:	d056      	beq.n	8004d34 <HAL_RCC_OscConfig+0x60c>
    {
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004c86:	687b      	ldr	r3, [r7, #4]
 8004c88:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004c8a:	2b02      	cmp	r3, #2
 8004c8c:	d13b      	bne.n	8004d06 <HAL_RCC_OscConfig+0x5de>
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8004c8e:	4b3d      	ldr	r3, [pc, #244]	; (8004d84 <HAL_RCC_OscConfig+0x65c>)
 8004c90:	2200      	movs	r2, #0
 8004c92:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004c94:	f7fd fbd8 	bl	8002448 <HAL_GetTick>
 8004c98:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8004c9a:	e008      	b.n	8004cae <HAL_RCC_OscConfig+0x586>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004c9c:	f7fd fbd4 	bl	8002448 <HAL_GetTick>
 8004ca0:	4602      	mov	r2, r0
 8004ca2:	693b      	ldr	r3, [r7, #16]
 8004ca4:	1ad3      	subs	r3, r2, r3
 8004ca6:	2b02      	cmp	r3, #2
 8004ca8:	d901      	bls.n	8004cae <HAL_RCC_OscConfig+0x586>
          {
            return HAL_TIMEOUT;
 8004caa:	2303      	movs	r3, #3
 8004cac:	e063      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8004cae:	4b34      	ldr	r3, [pc, #208]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004cb0:	681b      	ldr	r3, [r3, #0]
 8004cb2:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8004cb6:	2b00      	cmp	r3, #0
 8004cb8:	d1f0      	bne.n	8004c9c <HAL_RCC_OscConfig+0x574>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8004cba:	4b31      	ldr	r3, [pc, #196]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004cbc:	689b      	ldr	r3, [r3, #8]
 8004cbe:	f423 027d 	bic.w	r2, r3, #16580608	; 0xfd0000
 8004cc2:	687b      	ldr	r3, [r7, #4]
 8004cc4:	6a99      	ldr	r1, [r3, #40]	; 0x28
 8004cc6:	687b      	ldr	r3, [r7, #4]
 8004cc8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004cca:	4319      	orrs	r1, r3
 8004ccc:	687b      	ldr	r3, [r7, #4]
 8004cce:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8004cd0:	430b      	orrs	r3, r1
 8004cd2:	492b      	ldr	r1, [pc, #172]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004cd4:	4313      	orrs	r3, r2
 8004cd6:	608b      	str	r3, [r1, #8]
                             RCC_OscInitStruct->PLL.PLLMUL,
                             RCC_OscInitStruct->PLL.PLLDIV);
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 8004cd8:	4b2a      	ldr	r3, [pc, #168]	; (8004d84 <HAL_RCC_OscConfig+0x65c>)
 8004cda:	2201      	movs	r2, #1
 8004cdc:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004cde:	f7fd fbb3 	bl	8002448 <HAL_GetTick>
 8004ce2:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8004ce4:	e008      	b.n	8004cf8 <HAL_RCC_OscConfig+0x5d0>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004ce6:	f7fd fbaf 	bl	8002448 <HAL_GetTick>
 8004cea:	4602      	mov	r2, r0
 8004cec:	693b      	ldr	r3, [r7, #16]
 8004cee:	1ad3      	subs	r3, r2, r3
 8004cf0:	2b02      	cmp	r3, #2
 8004cf2:	d901      	bls.n	8004cf8 <HAL_RCC_OscConfig+0x5d0>
          {
            return HAL_TIMEOUT;
 8004cf4:	2303      	movs	r3, #3
 8004cf6:	e03e      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8004cf8:	4b21      	ldr	r3, [pc, #132]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004cfa:	681b      	ldr	r3, [r3, #0]
 8004cfc:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8004d00:	2b00      	cmp	r3, #0
 8004d02:	d0f0      	beq.n	8004ce6 <HAL_RCC_OscConfig+0x5be>
 8004d04:	e036      	b.n	8004d74 <HAL_RCC_OscConfig+0x64c>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8004d06:	4b1f      	ldr	r3, [pc, #124]	; (8004d84 <HAL_RCC_OscConfig+0x65c>)
 8004d08:	2200      	movs	r2, #0
 8004d0a:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8004d0c:	f7fd fb9c 	bl	8002448 <HAL_GetTick>
 8004d10:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8004d12:	e008      	b.n	8004d26 <HAL_RCC_OscConfig+0x5fe>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004d14:	f7fd fb98 	bl	8002448 <HAL_GetTick>
 8004d18:	4602      	mov	r2, r0
 8004d1a:	693b      	ldr	r3, [r7, #16]
 8004d1c:	1ad3      	subs	r3, r2, r3
 8004d1e:	2b02      	cmp	r3, #2
 8004d20:	d901      	bls.n	8004d26 <HAL_RCC_OscConfig+0x5fe>
          {
            return HAL_TIMEOUT;
 8004d22:	2303      	movs	r3, #3
 8004d24:	e027      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8004d26:	4b16      	ldr	r3, [pc, #88]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004d28:	681b      	ldr	r3, [r3, #0]
 8004d2a:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8004d2e:	2b00      	cmp	r3, #0
 8004d30:	d1f0      	bne.n	8004d14 <HAL_RCC_OscConfig+0x5ec>
 8004d32:	e01f      	b.n	8004d74 <HAL_RCC_OscConfig+0x64c>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8004d34:	687b      	ldr	r3, [r7, #4]
 8004d36:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004d38:	2b01      	cmp	r3, #1
 8004d3a:	d101      	bne.n	8004d40 <HAL_RCC_OscConfig+0x618>
      {
        return HAL_ERROR;
 8004d3c:	2301      	movs	r3, #1
 8004d3e:	e01a      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->CFGR;
 8004d40:	4b0f      	ldr	r3, [pc, #60]	; (8004d80 <HAL_RCC_OscConfig+0x658>)
 8004d42:	689b      	ldr	r3, [r3, #8]
 8004d44:	617b      	str	r3, [r7, #20]
        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8004d46:	697b      	ldr	r3, [r7, #20]
 8004d48:	f403 3280 	and.w	r2, r3, #65536	; 0x10000
 8004d4c:	687b      	ldr	r3, [r7, #4]
 8004d4e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8004d50:	429a      	cmp	r2, r3
 8004d52:	d10d      	bne.n	8004d70 <HAL_RCC_OscConfig+0x648>
           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
 8004d54:	697b      	ldr	r3, [r7, #20]
 8004d56:	f403 1270 	and.w	r2, r3, #3932160	; 0x3c0000
 8004d5a:	687b      	ldr	r3, [r7, #4]
 8004d5c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8004d5e:	429a      	cmp	r2, r3
 8004d60:	d106      	bne.n	8004d70 <HAL_RCC_OscConfig+0x648>
           (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
 8004d62:	697b      	ldr	r3, [r7, #20]
 8004d64:	f403 0240 	and.w	r2, r3, #12582912	; 0xc00000
 8004d68:	687b      	ldr	r3, [r7, #4]
 8004d6a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
 8004d6c:	429a      	cmp	r2, r3
 8004d6e:	d001      	beq.n	8004d74 <HAL_RCC_OscConfig+0x64c>
        {
          return HAL_ERROR;
 8004d70:	2301      	movs	r3, #1
 8004d72:	e000      	b.n	8004d76 <HAL_RCC_OscConfig+0x64e>
        }
      }
    }
  }

  return HAL_OK;
 8004d74:	2300      	movs	r3, #0
}
 8004d76:	4618      	mov	r0, r3
 8004d78:	3720      	adds	r7, #32
 8004d7a:	46bd      	mov	sp, r7
 8004d7c:	bd80      	pop	{r7, pc}
 8004d7e:	bf00      	nop
 8004d80:	40023800 	.word	0x40023800
 8004d84:	42470060 	.word	0x42470060

08004d88 <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8004d88:	b580      	push	{r7, lr}
 8004d8a:	b084      	sub	sp, #16
 8004d8c:	af00      	add	r7, sp, #0
 8004d8e:	6078      	str	r0, [r7, #4]
 8004d90:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status;

  /* Check the parameters */
  if(RCC_ClkInitStruct == NULL)
 8004d92:	687b      	ldr	r3, [r7, #4]
 8004d94:	2b00      	cmp	r3, #0
 8004d96:	d101      	bne.n	8004d9c <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8004d98:	2301      	movs	r3, #1
 8004d9a:	e11a      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  must be correctly programmed according to the frequency of the CPU clock
  (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8004d9c:	4b8f      	ldr	r3, [pc, #572]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004d9e:	681b      	ldr	r3, [r3, #0]
 8004da0:	f003 0301 	and.w	r3, r3, #1
 8004da4:	683a      	ldr	r2, [r7, #0]
 8004da6:	429a      	cmp	r2, r3
 8004da8:	d919      	bls.n	8004dde <HAL_RCC_ClockConfig+0x56>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8004daa:	683b      	ldr	r3, [r7, #0]
 8004dac:	2b01      	cmp	r3, #1
 8004dae:	d105      	bne.n	8004dbc <HAL_RCC_ClockConfig+0x34>
 8004db0:	4b8a      	ldr	r3, [pc, #552]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004db2:	681b      	ldr	r3, [r3, #0]
 8004db4:	4a89      	ldr	r2, [pc, #548]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004db6:	f043 0304 	orr.w	r3, r3, #4
 8004dba:	6013      	str	r3, [r2, #0]
 8004dbc:	4b87      	ldr	r3, [pc, #540]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004dbe:	681b      	ldr	r3, [r3, #0]
 8004dc0:	f023 0201 	bic.w	r2, r3, #1
 8004dc4:	4985      	ldr	r1, [pc, #532]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004dc6:	683b      	ldr	r3, [r7, #0]
 8004dc8:	4313      	orrs	r3, r2
 8004dca:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8004dcc:	4b83      	ldr	r3, [pc, #524]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004dce:	681b      	ldr	r3, [r3, #0]
 8004dd0:	f003 0301 	and.w	r3, r3, #1
 8004dd4:	683a      	ldr	r2, [r7, #0]
 8004dd6:	429a      	cmp	r2, r3
 8004dd8:	d001      	beq.n	8004dde <HAL_RCC_ClockConfig+0x56>
    {
      return HAL_ERROR;
 8004dda:	2301      	movs	r3, #1
 8004ddc:	e0f9      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8004dde:	687b      	ldr	r3, [r7, #4]
 8004de0:	681b      	ldr	r3, [r3, #0]
 8004de2:	f003 0302 	and.w	r3, r3, #2
 8004de6:	2b00      	cmp	r3, #0
 8004de8:	d008      	beq.n	8004dfc <HAL_RCC_ClockConfig+0x74>
  {
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8004dea:	4b7d      	ldr	r3, [pc, #500]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004dec:	689b      	ldr	r3, [r3, #8]
 8004dee:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8004df2:	687b      	ldr	r3, [r7, #4]
 8004df4:	689b      	ldr	r3, [r3, #8]
 8004df6:	497a      	ldr	r1, [pc, #488]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004df8:	4313      	orrs	r3, r2
 8004dfa:	608b      	str	r3, [r1, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8004dfc:	687b      	ldr	r3, [r7, #4]
 8004dfe:	681b      	ldr	r3, [r3, #0]
 8004e00:	f003 0301 	and.w	r3, r3, #1
 8004e04:	2b00      	cmp	r3, #0
 8004e06:	f000 808e 	beq.w	8004f26 <HAL_RCC_ClockConfig+0x19e>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004e0a:	687b      	ldr	r3, [r7, #4]
 8004e0c:	685b      	ldr	r3, [r3, #4]
 8004e0e:	2b02      	cmp	r3, #2
 8004e10:	d107      	bne.n	8004e22 <HAL_RCC_ClockConfig+0x9a>
    {
      /* Check the HSE ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 8004e12:	4b73      	ldr	r3, [pc, #460]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004e14:	681b      	ldr	r3, [r3, #0]
 8004e16:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8004e1a:	2b00      	cmp	r3, #0
 8004e1c:	d121      	bne.n	8004e62 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 8004e1e:	2301      	movs	r3, #1
 8004e20:	e0d7      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
      }
    }
    /* PLL is selected as System Clock Source */
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8004e22:	687b      	ldr	r3, [r7, #4]
 8004e24:	685b      	ldr	r3, [r3, #4]
 8004e26:	2b03      	cmp	r3, #3
 8004e28:	d107      	bne.n	8004e3a <HAL_RCC_ClockConfig+0xb2>
    {
      /* Check the PLL ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8004e2a:	4b6d      	ldr	r3, [pc, #436]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004e2c:	681b      	ldr	r3, [r3, #0]
 8004e2e:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8004e32:	2b00      	cmp	r3, #0
 8004e34:	d115      	bne.n	8004e62 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 8004e36:	2301      	movs	r3, #1
 8004e38:	e0cb      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
      }
    }
    /* HSI is selected as System Clock Source */
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
 8004e3a:	687b      	ldr	r3, [r7, #4]
 8004e3c:	685b      	ldr	r3, [r3, #4]
 8004e3e:	2b01      	cmp	r3, #1
 8004e40:	d107      	bne.n	8004e52 <HAL_RCC_ClockConfig+0xca>
    {
      /* Check the HSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 8004e42:	4b67      	ldr	r3, [pc, #412]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004e44:	681b      	ldr	r3, [r3, #0]
 8004e46:	f003 0302 	and.w	r3, r3, #2
 8004e4a:	2b00      	cmp	r3, #0
 8004e4c:	d109      	bne.n	8004e62 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 8004e4e:	2301      	movs	r3, #1
 8004e50:	e0bf      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
    }
    /* MSI is selected as System Clock Source */
    else
    {
      /* Check the MSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 8004e52:	4b63      	ldr	r3, [pc, #396]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004e54:	681b      	ldr	r3, [r3, #0]
 8004e56:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8004e5a:	2b00      	cmp	r3, #0
 8004e5c:	d101      	bne.n	8004e62 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 8004e5e:	2301      	movs	r3, #1
 8004e60:	e0b7      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
      }
    }
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8004e62:	4b5f      	ldr	r3, [pc, #380]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004e64:	689b      	ldr	r3, [r3, #8]
 8004e66:	f023 0203 	bic.w	r2, r3, #3
 8004e6a:	687b      	ldr	r3, [r7, #4]
 8004e6c:	685b      	ldr	r3, [r3, #4]
 8004e6e:	495c      	ldr	r1, [pc, #368]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004e70:	4313      	orrs	r3, r2
 8004e72:	608b      	str	r3, [r1, #8]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 8004e74:	f7fd fae8 	bl	8002448 <HAL_GetTick>
 8004e78:	60f8      	str	r0, [r7, #12]

    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004e7a:	687b      	ldr	r3, [r7, #4]
 8004e7c:	685b      	ldr	r3, [r3, #4]
 8004e7e:	2b02      	cmp	r3, #2
 8004e80:	d112      	bne.n	8004ea8 <HAL_RCC_ClockConfig+0x120>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 8004e82:	e00a      	b.n	8004e9a <HAL_RCC_ClockConfig+0x112>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004e84:	f7fd fae0 	bl	8002448 <HAL_GetTick>
 8004e88:	4602      	mov	r2, r0
 8004e8a:	68fb      	ldr	r3, [r7, #12]
 8004e8c:	1ad3      	subs	r3, r2, r3
 8004e8e:	f241 3288 	movw	r2, #5000	; 0x1388
 8004e92:	4293      	cmp	r3, r2
 8004e94:	d901      	bls.n	8004e9a <HAL_RCC_ClockConfig+0x112>
        {
          return HAL_TIMEOUT;
 8004e96:	2303      	movs	r3, #3
 8004e98:	e09b      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 8004e9a:	4b51      	ldr	r3, [pc, #324]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004e9c:	689b      	ldr	r3, [r3, #8]
 8004e9e:	f003 030c 	and.w	r3, r3, #12
 8004ea2:	2b08      	cmp	r3, #8
 8004ea4:	d1ee      	bne.n	8004e84 <HAL_RCC_ClockConfig+0xfc>
 8004ea6:	e03e      	b.n	8004f26 <HAL_RCC_ClockConfig+0x19e>
        }
      }
    }
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8004ea8:	687b      	ldr	r3, [r7, #4]
 8004eaa:	685b      	ldr	r3, [r3, #4]
 8004eac:	2b03      	cmp	r3, #3
 8004eae:	d112      	bne.n	8004ed6 <HAL_RCC_ClockConfig+0x14e>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8004eb0:	e00a      	b.n	8004ec8 <HAL_RCC_ClockConfig+0x140>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004eb2:	f7fd fac9 	bl	8002448 <HAL_GetTick>
 8004eb6:	4602      	mov	r2, r0
 8004eb8:	68fb      	ldr	r3, [r7, #12]
 8004eba:	1ad3      	subs	r3, r2, r3
 8004ebc:	f241 3288 	movw	r2, #5000	; 0x1388
 8004ec0:	4293      	cmp	r3, r2
 8004ec2:	d901      	bls.n	8004ec8 <HAL_RCC_ClockConfig+0x140>
        {
          return HAL_TIMEOUT;
 8004ec4:	2303      	movs	r3, #3
 8004ec6:	e084      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8004ec8:	4b45      	ldr	r3, [pc, #276]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004eca:	689b      	ldr	r3, [r3, #8]
 8004ecc:	f003 030c 	and.w	r3, r3, #12
 8004ed0:	2b0c      	cmp	r3, #12
 8004ed2:	d1ee      	bne.n	8004eb2 <HAL_RCC_ClockConfig+0x12a>
 8004ed4:	e027      	b.n	8004f26 <HAL_RCC_ClockConfig+0x19e>
        }
      }
    }
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
 8004ed6:	687b      	ldr	r3, [r7, #4]
 8004ed8:	685b      	ldr	r3, [r3, #4]
 8004eda:	2b01      	cmp	r3, #1
 8004edc:	d11d      	bne.n	8004f1a <HAL_RCC_ClockConfig+0x192>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 8004ede:	e00a      	b.n	8004ef6 <HAL_RCC_ClockConfig+0x16e>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004ee0:	f7fd fab2 	bl	8002448 <HAL_GetTick>
 8004ee4:	4602      	mov	r2, r0
 8004ee6:	68fb      	ldr	r3, [r7, #12]
 8004ee8:	1ad3      	subs	r3, r2, r3
 8004eea:	f241 3288 	movw	r2, #5000	; 0x1388
 8004eee:	4293      	cmp	r3, r2
 8004ef0:	d901      	bls.n	8004ef6 <HAL_RCC_ClockConfig+0x16e>
        {
          return HAL_TIMEOUT;
 8004ef2:	2303      	movs	r3, #3
 8004ef4:	e06d      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 8004ef6:	4b3a      	ldr	r3, [pc, #232]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004ef8:	689b      	ldr	r3, [r3, #8]
 8004efa:	f003 030c 	and.w	r3, r3, #12
 8004efe:	2b04      	cmp	r3, #4
 8004f00:	d1ee      	bne.n	8004ee0 <HAL_RCC_ClockConfig+0x158>
 8004f02:	e010      	b.n	8004f26 <HAL_RCC_ClockConfig+0x19e>
    }
    else
    {
      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004f04:	f7fd faa0 	bl	8002448 <HAL_GetTick>
 8004f08:	4602      	mov	r2, r0
 8004f0a:	68fb      	ldr	r3, [r7, #12]
 8004f0c:	1ad3      	subs	r3, r2, r3
 8004f0e:	f241 3288 	movw	r2, #5000	; 0x1388
 8004f12:	4293      	cmp	r3, r2
 8004f14:	d901      	bls.n	8004f1a <HAL_RCC_ClockConfig+0x192>
        {
          return HAL_TIMEOUT;
 8004f16:	2303      	movs	r3, #3
 8004f18:	e05b      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
 8004f1a:	4b31      	ldr	r3, [pc, #196]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004f1c:	689b      	ldr	r3, [r3, #8]
 8004f1e:	f003 030c 	and.w	r3, r3, #12
 8004f22:	2b00      	cmp	r3, #0
 8004f24:	d1ee      	bne.n	8004f04 <HAL_RCC_ClockConfig+0x17c>
        }
      }
    }
  }
  /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8004f26:	4b2d      	ldr	r3, [pc, #180]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004f28:	681b      	ldr	r3, [r3, #0]
 8004f2a:	f003 0301 	and.w	r3, r3, #1
 8004f2e:	683a      	ldr	r2, [r7, #0]
 8004f30:	429a      	cmp	r2, r3
 8004f32:	d219      	bcs.n	8004f68 <HAL_RCC_ClockConfig+0x1e0>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8004f34:	683b      	ldr	r3, [r7, #0]
 8004f36:	2b01      	cmp	r3, #1
 8004f38:	d105      	bne.n	8004f46 <HAL_RCC_ClockConfig+0x1be>
 8004f3a:	4b28      	ldr	r3, [pc, #160]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004f3c:	681b      	ldr	r3, [r3, #0]
 8004f3e:	4a27      	ldr	r2, [pc, #156]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004f40:	f043 0304 	orr.w	r3, r3, #4
 8004f44:	6013      	str	r3, [r2, #0]
 8004f46:	4b25      	ldr	r3, [pc, #148]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004f48:	681b      	ldr	r3, [r3, #0]
 8004f4a:	f023 0201 	bic.w	r2, r3, #1
 8004f4e:	4923      	ldr	r1, [pc, #140]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004f50:	683b      	ldr	r3, [r7, #0]
 8004f52:	4313      	orrs	r3, r2
 8004f54:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8004f56:	4b21      	ldr	r3, [pc, #132]	; (8004fdc <HAL_RCC_ClockConfig+0x254>)
 8004f58:	681b      	ldr	r3, [r3, #0]
 8004f5a:	f003 0301 	and.w	r3, r3, #1
 8004f5e:	683a      	ldr	r2, [r7, #0]
 8004f60:	429a      	cmp	r2, r3
 8004f62:	d001      	beq.n	8004f68 <HAL_RCC_ClockConfig+0x1e0>
    {
      return HAL_ERROR;
 8004f64:	2301      	movs	r3, #1
 8004f66:	e034      	b.n	8004fd2 <HAL_RCC_ClockConfig+0x24a>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8004f68:	687b      	ldr	r3, [r7, #4]
 8004f6a:	681b      	ldr	r3, [r3, #0]
 8004f6c:	f003 0304 	and.w	r3, r3, #4
 8004f70:	2b00      	cmp	r3, #0
 8004f72:	d008      	beq.n	8004f86 <HAL_RCC_ClockConfig+0x1fe>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8004f74:	4b1a      	ldr	r3, [pc, #104]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004f76:	689b      	ldr	r3, [r3, #8]
 8004f78:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
 8004f7c:	687b      	ldr	r3, [r7, #4]
 8004f7e:	68db      	ldr	r3, [r3, #12]
 8004f80:	4917      	ldr	r1, [pc, #92]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004f82:	4313      	orrs	r3, r2
 8004f84:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8004f86:	687b      	ldr	r3, [r7, #4]
 8004f88:	681b      	ldr	r3, [r3, #0]
 8004f8a:	f003 0308 	and.w	r3, r3, #8
 8004f8e:	2b00      	cmp	r3, #0
 8004f90:	d009      	beq.n	8004fa6 <HAL_RCC_ClockConfig+0x21e>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8004f92:	4b13      	ldr	r3, [pc, #76]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004f94:	689b      	ldr	r3, [r3, #8]
 8004f96:	f423 5260 	bic.w	r2, r3, #14336	; 0x3800
 8004f9a:	687b      	ldr	r3, [r7, #4]
 8004f9c:	691b      	ldr	r3, [r3, #16]
 8004f9e:	00db      	lsls	r3, r3, #3
 8004fa0:	490f      	ldr	r1, [pc, #60]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004fa2:	4313      	orrs	r3, r2
 8004fa4:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8004fa6:	f000 f823 	bl	8004ff0 <HAL_RCC_GetSysClockFreq>
 8004faa:	4602      	mov	r2, r0
 8004fac:	4b0c      	ldr	r3, [pc, #48]	; (8004fe0 <HAL_RCC_ClockConfig+0x258>)
 8004fae:	689b      	ldr	r3, [r3, #8]
 8004fb0:	091b      	lsrs	r3, r3, #4
 8004fb2:	f003 030f 	and.w	r3, r3, #15
 8004fb6:	490b      	ldr	r1, [pc, #44]	; (8004fe4 <HAL_RCC_ClockConfig+0x25c>)
 8004fb8:	5ccb      	ldrb	r3, [r1, r3]
 8004fba:	fa22 f303 	lsr.w	r3, r2, r3
 8004fbe:	4a0a      	ldr	r2, [pc, #40]	; (8004fe8 <HAL_RCC_ClockConfig+0x260>)
 8004fc0:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  status = HAL_InitTick(uwTickPrio);
 8004fc2:	4b0a      	ldr	r3, [pc, #40]	; (8004fec <HAL_RCC_ClockConfig+0x264>)
 8004fc4:	681b      	ldr	r3, [r3, #0]
 8004fc6:	4618      	mov	r0, r3
 8004fc8:	f7fd f9f2 	bl	80023b0 <HAL_InitTick>
 8004fcc:	4603      	mov	r3, r0
 8004fce:	72fb      	strb	r3, [r7, #11]

  return status;
 8004fd0:	7afb      	ldrb	r3, [r7, #11]
}
 8004fd2:	4618      	mov	r0, r3
 8004fd4:	3710      	adds	r7, #16
 8004fd6:	46bd      	mov	sp, r7
 8004fd8:	bd80      	pop	{r7, pc}
 8004fda:	bf00      	nop
 8004fdc:	40023c00 	.word	0x40023c00
 8004fe0:	40023800 	.word	0x40023800
 8004fe4:	080098e0 	.word	0x080098e0
 8004fe8:	20000000 	.word	0x20000000
 8004fec:	20000004 	.word	0x20000004

08004ff0 <HAL_RCC_GetSysClockFreq>:
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8004ff0:	b5b0      	push	{r4, r5, r7, lr}
 8004ff2:	b086      	sub	sp, #24
 8004ff4:	af00      	add	r7, sp, #0
  uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;

  tmpreg = RCC->CFGR;
 8004ff6:	4b61      	ldr	r3, [pc, #388]	; (800517c <HAL_RCC_GetSysClockFreq+0x18c>)
 8004ff8:	689b      	ldr	r3, [r3, #8]
 8004ffa:	60fb      	str	r3, [r7, #12]

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS)
 8004ffc:	68fb      	ldr	r3, [r7, #12]
 8004ffe:	f003 030c 	and.w	r3, r3, #12
 8005002:	2b0c      	cmp	r3, #12
 8005004:	d00d      	beq.n	8005022 <HAL_RCC_GetSysClockFreq+0x32>
 8005006:	2b0c      	cmp	r3, #12
 8005008:	f200 80a4 	bhi.w	8005154 <HAL_RCC_GetSysClockFreq+0x164>
 800500c:	2b04      	cmp	r3, #4
 800500e:	d002      	beq.n	8005016 <HAL_RCC_GetSysClockFreq+0x26>
 8005010:	2b08      	cmp	r3, #8
 8005012:	d003      	beq.n	800501c <HAL_RCC_GetSysClockFreq+0x2c>
 8005014:	e09e      	b.n	8005154 <HAL_RCC_GetSysClockFreq+0x164>
  {
    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
    {
      sysclockfreq = HSI_VALUE;
 8005016:	4b5a      	ldr	r3, [pc, #360]	; (8005180 <HAL_RCC_GetSysClockFreq+0x190>)
 8005018:	613b      	str	r3, [r7, #16]
      break;
 800501a:	e0a9      	b.n	8005170 <HAL_RCC_GetSysClockFreq+0x180>
    }
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
    {
      sysclockfreq = HSE_VALUE;
 800501c:	4b59      	ldr	r3, [pc, #356]	; (8005184 <HAL_RCC_GetSysClockFreq+0x194>)
 800501e:	613b      	str	r3, [r7, #16]
      break;
 8005020:	e0a6      	b.n	8005170 <HAL_RCC_GetSysClockFreq+0x180>
    }
    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
    {
      pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
 8005022:	68fb      	ldr	r3, [r7, #12]
 8005024:	0c9b      	lsrs	r3, r3, #18
 8005026:	f003 030f 	and.w	r3, r3, #15
 800502a:	4a57      	ldr	r2, [pc, #348]	; (8005188 <HAL_RCC_GetSysClockFreq+0x198>)
 800502c:	5cd3      	ldrb	r3, [r2, r3]
 800502e:	60bb      	str	r3, [r7, #8]
      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
 8005030:	68fb      	ldr	r3, [r7, #12]
 8005032:	0d9b      	lsrs	r3, r3, #22
 8005034:	f003 0303 	and.w	r3, r3, #3
 8005038:	3301      	adds	r3, #1
 800503a:	607b      	str	r3, [r7, #4]
      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 800503c:	4b4f      	ldr	r3, [pc, #316]	; (800517c <HAL_RCC_GetSysClockFreq+0x18c>)
 800503e:	689b      	ldr	r3, [r3, #8]
 8005040:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8005044:	2b00      	cmp	r3, #0
 8005046:	d041      	beq.n	80050cc <HAL_RCC_GetSysClockFreq+0xdc>
      {
        /* HSE used as PLL clock source */
        pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
 8005048:	68bb      	ldr	r3, [r7, #8]
 800504a:	461c      	mov	r4, r3
 800504c:	f04f 0500 	mov.w	r5, #0
 8005050:	4620      	mov	r0, r4
 8005052:	4629      	mov	r1, r5
 8005054:	f04f 0200 	mov.w	r2, #0
 8005058:	f04f 0300 	mov.w	r3, #0
 800505c:	014b      	lsls	r3, r1, #5
 800505e:	ea43 63d0 	orr.w	r3, r3, r0, lsr #27
 8005062:	0142      	lsls	r2, r0, #5
 8005064:	4610      	mov	r0, r2
 8005066:	4619      	mov	r1, r3
 8005068:	1b00      	subs	r0, r0, r4
 800506a:	eb61 0105 	sbc.w	r1, r1, r5
 800506e:	f04f 0200 	mov.w	r2, #0
 8005072:	f04f 0300 	mov.w	r3, #0
 8005076:	018b      	lsls	r3, r1, #6
 8005078:	ea43 6390 	orr.w	r3, r3, r0, lsr #26
 800507c:	0182      	lsls	r2, r0, #6
 800507e:	1a12      	subs	r2, r2, r0
 8005080:	eb63 0301 	sbc.w	r3, r3, r1
 8005084:	f04f 0000 	mov.w	r0, #0
 8005088:	f04f 0100 	mov.w	r1, #0
 800508c:	00d9      	lsls	r1, r3, #3
 800508e:	ea41 7152 	orr.w	r1, r1, r2, lsr #29
 8005092:	00d0      	lsls	r0, r2, #3
 8005094:	4602      	mov	r2, r0
 8005096:	460b      	mov	r3, r1
 8005098:	1912      	adds	r2, r2, r4
 800509a:	eb45 0303 	adc.w	r3, r5, r3
 800509e:	f04f 0000 	mov.w	r0, #0
 80050a2:	f04f 0100 	mov.w	r1, #0
 80050a6:	0259      	lsls	r1, r3, #9
 80050a8:	ea41 51d2 	orr.w	r1, r1, r2, lsr #23
 80050ac:	0250      	lsls	r0, r2, #9
 80050ae:	4602      	mov	r2, r0
 80050b0:	460b      	mov	r3, r1
 80050b2:	4610      	mov	r0, r2
 80050b4:	4619      	mov	r1, r3
 80050b6:	687b      	ldr	r3, [r7, #4]
 80050b8:	461a      	mov	r2, r3
 80050ba:	f04f 0300 	mov.w	r3, #0
 80050be:	f7fb fe09 	bl	8000cd4 <__aeabi_uldivmod>
 80050c2:	4602      	mov	r2, r0
 80050c4:	460b      	mov	r3, r1
 80050c6:	4613      	mov	r3, r2
 80050c8:	617b      	str	r3, [r7, #20]
 80050ca:	e040      	b.n	800514e <HAL_RCC_GetSysClockFreq+0x15e>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
 80050cc:	68bb      	ldr	r3, [r7, #8]
 80050ce:	461c      	mov	r4, r3
 80050d0:	f04f 0500 	mov.w	r5, #0
 80050d4:	4620      	mov	r0, r4
 80050d6:	4629      	mov	r1, r5
 80050d8:	f04f 0200 	mov.w	r2, #0
 80050dc:	f04f 0300 	mov.w	r3, #0
 80050e0:	014b      	lsls	r3, r1, #5
 80050e2:	ea43 63d0 	orr.w	r3, r3, r0, lsr #27
 80050e6:	0142      	lsls	r2, r0, #5
 80050e8:	4610      	mov	r0, r2
 80050ea:	4619      	mov	r1, r3
 80050ec:	1b00      	subs	r0, r0, r4
 80050ee:	eb61 0105 	sbc.w	r1, r1, r5
 80050f2:	f04f 0200 	mov.w	r2, #0
 80050f6:	f04f 0300 	mov.w	r3, #0
 80050fa:	018b      	lsls	r3, r1, #6
 80050fc:	ea43 6390 	orr.w	r3, r3, r0, lsr #26
 8005100:	0182      	lsls	r2, r0, #6
 8005102:	1a12      	subs	r2, r2, r0
 8005104:	eb63 0301 	sbc.w	r3, r3, r1
 8005108:	f04f 0000 	mov.w	r0, #0
 800510c:	f04f 0100 	mov.w	r1, #0
 8005110:	00d9      	lsls	r1, r3, #3
 8005112:	ea41 7152 	orr.w	r1, r1, r2, lsr #29
 8005116:	00d0      	lsls	r0, r2, #3
 8005118:	4602      	mov	r2, r0
 800511a:	460b      	mov	r3, r1
 800511c:	1912      	adds	r2, r2, r4
 800511e:	eb45 0303 	adc.w	r3, r5, r3
 8005122:	f04f 0000 	mov.w	r0, #0
 8005126:	f04f 0100 	mov.w	r1, #0
 800512a:	0299      	lsls	r1, r3, #10
 800512c:	ea41 5192 	orr.w	r1, r1, r2, lsr #22
 8005130:	0290      	lsls	r0, r2, #10
 8005132:	4602      	mov	r2, r0
 8005134:	460b      	mov	r3, r1
 8005136:	4610      	mov	r0, r2
 8005138:	4619      	mov	r1, r3
 800513a:	687b      	ldr	r3, [r7, #4]
 800513c:	461a      	mov	r2, r3
 800513e:	f04f 0300 	mov.w	r3, #0
 8005142:	f7fb fdc7 	bl	8000cd4 <__aeabi_uldivmod>
 8005146:	4602      	mov	r2, r0
 8005148:	460b      	mov	r3, r1
 800514a:	4613      	mov	r3, r2
 800514c:	617b      	str	r3, [r7, #20]
      }
      sysclockfreq = pllvco;
 800514e:	697b      	ldr	r3, [r7, #20]
 8005150:	613b      	str	r3, [r7, #16]
      break;
 8005152:	e00d      	b.n	8005170 <HAL_RCC_GetSysClockFreq+0x180>
    }
    case RCC_SYSCLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
    default: /* MSI used as system clock */
    {
      msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
 8005154:	4b09      	ldr	r3, [pc, #36]	; (800517c <HAL_RCC_GetSysClockFreq+0x18c>)
 8005156:	685b      	ldr	r3, [r3, #4]
 8005158:	0b5b      	lsrs	r3, r3, #13
 800515a:	f003 0307 	and.w	r3, r3, #7
 800515e:	603b      	str	r3, [r7, #0]
      sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
 8005160:	683b      	ldr	r3, [r7, #0]
 8005162:	3301      	adds	r3, #1
 8005164:	f44f 4200 	mov.w	r2, #32768	; 0x8000
 8005168:	fa02 f303 	lsl.w	r3, r2, r3
 800516c:	613b      	str	r3, [r7, #16]
      break;
 800516e:	bf00      	nop
    }
  }
  return sysclockfreq;
 8005170:	693b      	ldr	r3, [r7, #16]
}
 8005172:	4618      	mov	r0, r3
 8005174:	3718      	adds	r7, #24
 8005176:	46bd      	mov	sp, r7
 8005178:	bdb0      	pop	{r4, r5, r7, pc}
 800517a:	bf00      	nop
 800517c:	40023800 	.word	0x40023800
 8005180:	00f42400 	.word	0x00f42400
 8005184:	007a1200 	.word	0x007a1200
 8005188:	080098d4 	.word	0x080098d4

0800518c <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 800518c:	b480      	push	{r7}
 800518e:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8005190:	4b02      	ldr	r3, [pc, #8]	; (800519c <HAL_RCC_GetHCLKFreq+0x10>)
 8005192:	681b      	ldr	r3, [r3, #0]
}
 8005194:	4618      	mov	r0, r3
 8005196:	46bd      	mov	sp, r7
 8005198:	bc80      	pop	{r7}
 800519a:	4770      	bx	lr
 800519c:	20000000 	.word	0x20000000

080051a0 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 80051a0:	b580      	push	{r7, lr}
 80051a2:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 80051a4:	f7ff fff2 	bl	800518c <HAL_RCC_GetHCLKFreq>
 80051a8:	4602      	mov	r2, r0
 80051aa:	4b05      	ldr	r3, [pc, #20]	; (80051c0 <HAL_RCC_GetPCLK1Freq+0x20>)
 80051ac:	689b      	ldr	r3, [r3, #8]
 80051ae:	0a1b      	lsrs	r3, r3, #8
 80051b0:	f003 0307 	and.w	r3, r3, #7
 80051b4:	4903      	ldr	r1, [pc, #12]	; (80051c4 <HAL_RCC_GetPCLK1Freq+0x24>)
 80051b6:	5ccb      	ldrb	r3, [r1, r3]
 80051b8:	fa22 f303 	lsr.w	r3, r2, r3
}
 80051bc:	4618      	mov	r0, r3
 80051be:	bd80      	pop	{r7, pc}
 80051c0:	40023800 	.word	0x40023800
 80051c4:	080098f0 	.word	0x080098f0

080051c8 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 80051c8:	b580      	push	{r7, lr}
 80051ca:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 80051cc:	f7ff ffde 	bl	800518c <HAL_RCC_GetHCLKFreq>
 80051d0:	4602      	mov	r2, r0
 80051d2:	4b05      	ldr	r3, [pc, #20]	; (80051e8 <HAL_RCC_GetPCLK2Freq+0x20>)
 80051d4:	689b      	ldr	r3, [r3, #8]
 80051d6:	0adb      	lsrs	r3, r3, #11
 80051d8:	f003 0307 	and.w	r3, r3, #7
 80051dc:	4903      	ldr	r1, [pc, #12]	; (80051ec <HAL_RCC_GetPCLK2Freq+0x24>)
 80051de:	5ccb      	ldrb	r3, [r1, r3]
 80051e0:	fa22 f303 	lsr.w	r3, r2, r3
}
 80051e4:	4618      	mov	r0, r3
 80051e6:	bd80      	pop	{r7, pc}
 80051e8:	40023800 	.word	0x40023800
 80051ec:	080098f0 	.word	0x080098f0

080051f0 <RCC_SetFlashLatencyFromMSIRange>:
            voltage range
  * @param  MSIrange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
  * @retval HAL status
  */
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
 80051f0:	b480      	push	{r7}
 80051f2:	b087      	sub	sp, #28
 80051f4:	af00      	add	r7, sp, #0
 80051f6:	6078      	str	r0, [r7, #4]
  uint32_t vos;
  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
 80051f8:	2300      	movs	r3, #0
 80051fa:	613b      	str	r3, [r7, #16]

  /* HCLK can reach 4 MHz only if AHB prescaler = 1 */
  if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
 80051fc:	4b29      	ldr	r3, [pc, #164]	; (80052a4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 80051fe:	689b      	ldr	r3, [r3, #8]
 8005200:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8005204:	2b00      	cmp	r3, #0
 8005206:	d12c      	bne.n	8005262 <RCC_SetFlashLatencyFromMSIRange+0x72>
  {
    if(__HAL_RCC_PWR_IS_CLK_ENABLED())
 8005208:	4b26      	ldr	r3, [pc, #152]	; (80052a4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 800520a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800520c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8005210:	2b00      	cmp	r3, #0
 8005212:	d005      	beq.n	8005220 <RCC_SetFlashLatencyFromMSIRange+0x30>
    {
      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
 8005214:	4b24      	ldr	r3, [pc, #144]	; (80052a8 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8005216:	681b      	ldr	r3, [r3, #0]
 8005218:	f403 53c0 	and.w	r3, r3, #6144	; 0x1800
 800521c:	617b      	str	r3, [r7, #20]
 800521e:	e016      	b.n	800524e <RCC_SetFlashLatencyFromMSIRange+0x5e>
    }
    else
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8005220:	4b20      	ldr	r3, [pc, #128]	; (80052a4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8005222:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8005224:	4a1f      	ldr	r2, [pc, #124]	; (80052a4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8005226:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 800522a:	6253      	str	r3, [r2, #36]	; 0x24
 800522c:	4b1d      	ldr	r3, [pc, #116]	; (80052a4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 800522e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8005230:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8005234:	60fb      	str	r3, [r7, #12]
 8005236:	68fb      	ldr	r3, [r7, #12]
      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
 8005238:	4b1b      	ldr	r3, [pc, #108]	; (80052a8 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800523a:	681b      	ldr	r3, [r3, #0]
 800523c:	f403 53c0 	and.w	r3, r3, #6144	; 0x1800
 8005240:	617b      	str	r3, [r7, #20]
      __HAL_RCC_PWR_CLK_DISABLE();
 8005242:	4b18      	ldr	r3, [pc, #96]	; (80052a4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8005244:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8005246:	4a17      	ldr	r2, [pc, #92]	; (80052a4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8005248:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 800524c:	6253      	str	r3, [r2, #36]	; 0x24
    }

    /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
    if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
 800524e:	697b      	ldr	r3, [r7, #20]
 8005250:	f5b3 5fc0 	cmp.w	r3, #6144	; 0x1800
 8005254:	d105      	bne.n	8005262 <RCC_SetFlashLatencyFromMSIRange+0x72>
 8005256:	687b      	ldr	r3, [r7, #4]
 8005258:	f5b3 4f40 	cmp.w	r3, #49152	; 0xc000
 800525c:	d101      	bne.n	8005262 <RCC_SetFlashLatencyFromMSIRange+0x72>
    {
      latency = FLASH_LATENCY_1; /* 1WS */
 800525e:	2301      	movs	r3, #1
 8005260:	613b      	str	r3, [r7, #16]
    }
  }

  __HAL_FLASH_SET_LATENCY(latency);
 8005262:	693b      	ldr	r3, [r7, #16]
 8005264:	2b01      	cmp	r3, #1
 8005266:	d105      	bne.n	8005274 <RCC_SetFlashLatencyFromMSIRange+0x84>
 8005268:	4b10      	ldr	r3, [pc, #64]	; (80052ac <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 800526a:	681b      	ldr	r3, [r3, #0]
 800526c:	4a0f      	ldr	r2, [pc, #60]	; (80052ac <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 800526e:	f043 0304 	orr.w	r3, r3, #4
 8005272:	6013      	str	r3, [r2, #0]
 8005274:	4b0d      	ldr	r3, [pc, #52]	; (80052ac <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8005276:	681b      	ldr	r3, [r3, #0]
 8005278:	f023 0201 	bic.w	r2, r3, #1
 800527c:	490b      	ldr	r1, [pc, #44]	; (80052ac <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 800527e:	693b      	ldr	r3, [r7, #16]
 8005280:	4313      	orrs	r3, r2
 8005282:	600b      	str	r3, [r1, #0]

  /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
  if(__HAL_FLASH_GET_LATENCY() != latency)
 8005284:	4b09      	ldr	r3, [pc, #36]	; (80052ac <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8005286:	681b      	ldr	r3, [r3, #0]
 8005288:	f003 0301 	and.w	r3, r3, #1
 800528c:	693a      	ldr	r2, [r7, #16]
 800528e:	429a      	cmp	r2, r3
 8005290:	d001      	beq.n	8005296 <RCC_SetFlashLatencyFromMSIRange+0xa6>
  {
    return HAL_ERROR;
 8005292:	2301      	movs	r3, #1
 8005294:	e000      	b.n	8005298 <RCC_SetFlashLatencyFromMSIRange+0xa8>
  }

  return HAL_OK;
 8005296:	2300      	movs	r3, #0
}
 8005298:	4618      	mov	r0, r3
 800529a:	371c      	adds	r7, #28
 800529c:	46bd      	mov	sp, r7
 800529e:	bc80      	pop	{r7}
 80052a0:	4770      	bx	lr
 80052a2:	bf00      	nop
 80052a4:	40023800 	.word	0x40023800
 80052a8:	40007000 	.word	0x40007000
 80052ac:	40023c00 	.word	0x40023c00

080052b0 <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 80052b0:	b580      	push	{r7, lr}
 80052b2:	b082      	sub	sp, #8
 80052b4:	af00      	add	r7, sp, #0
 80052b6:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 80052b8:	687b      	ldr	r3, [r7, #4]
 80052ba:	2b00      	cmp	r3, #0
 80052bc:	d101      	bne.n	80052c2 <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 80052be:	2301      	movs	r3, #1
 80052c0:	e031      	b.n	8005326 <HAL_TIM_Base_Init+0x76>
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 80052c2:	687b      	ldr	r3, [r7, #4]
 80052c4:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 80052c8:	b2db      	uxtb	r3, r3
 80052ca:	2b00      	cmp	r3, #0
 80052cc:	d106      	bne.n	80052dc <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 80052ce:	687b      	ldr	r3, [r7, #4]
 80052d0:	2200      	movs	r2, #0
 80052d2:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 80052d6:	6878      	ldr	r0, [r7, #4]
 80052d8:	f7fc fe08 	bl	8001eec <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 80052dc:	687b      	ldr	r3, [r7, #4]
 80052de:	2202      	movs	r2, #2
 80052e0:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80052e4:	687b      	ldr	r3, [r7, #4]
 80052e6:	681a      	ldr	r2, [r3, #0]
 80052e8:	687b      	ldr	r3, [r7, #4]
 80052ea:	3304      	adds	r3, #4
 80052ec:	4619      	mov	r1, r3
 80052ee:	4610      	mov	r0, r2
 80052f0:	f000 fccc 	bl	8005c8c <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 80052f4:	687b      	ldr	r3, [r7, #4]
 80052f6:	2201      	movs	r2, #1
 80052f8:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 80052fc:	687b      	ldr	r3, [r7, #4]
 80052fe:	2201      	movs	r2, #1
 8005300:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a
 8005304:	687b      	ldr	r3, [r7, #4]
 8005306:	2201      	movs	r2, #1
 8005308:	f883 203b 	strb.w	r2, [r3, #59]	; 0x3b
 800530c:	687b      	ldr	r3, [r7, #4]
 800530e:	2201      	movs	r2, #1
 8005310:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
 8005314:	687b      	ldr	r3, [r7, #4]
 8005316:	2201      	movs	r2, #1
 8005318:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 800531c:	687b      	ldr	r3, [r7, #4]
 800531e:	2201      	movs	r2, #1
 8005320:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  return HAL_OK;
 8005324:	2300      	movs	r3, #0
}
 8005326:	4618      	mov	r0, r3
 8005328:	3708      	adds	r7, #8
 800532a:	46bd      	mov	sp, r7
 800532c:	bd80      	pop	{r7, pc}
	...

08005330 <HAL_TIM_Base_Start>:
  * @brief  Starts the TIM Base generation.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
 8005330:	b480      	push	{r7}
 8005332:	b085      	sub	sp, #20
 8005334:	af00      	add	r7, sp, #0
 8005336:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 8005338:	687b      	ldr	r3, [r7, #4]
 800533a:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 800533e:	b2db      	uxtb	r3, r3
 8005340:	2b01      	cmp	r3, #1
 8005342:	d001      	beq.n	8005348 <HAL_TIM_Base_Start+0x18>
  {
    return HAL_ERROR;
 8005344:	2301      	movs	r3, #1
 8005346:	e032      	b.n	80053ae <HAL_TIM_Base_Start+0x7e>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8005348:	687b      	ldr	r3, [r7, #4]
 800534a:	2202      	movs	r2, #2
 800534c:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8005350:	687b      	ldr	r3, [r7, #4]
 8005352:	681b      	ldr	r3, [r3, #0]
 8005354:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8005358:	d00e      	beq.n	8005378 <HAL_TIM_Base_Start+0x48>
 800535a:	687b      	ldr	r3, [r7, #4]
 800535c:	681b      	ldr	r3, [r3, #0]
 800535e:	4a16      	ldr	r2, [pc, #88]	; (80053b8 <HAL_TIM_Base_Start+0x88>)
 8005360:	4293      	cmp	r3, r2
 8005362:	d009      	beq.n	8005378 <HAL_TIM_Base_Start+0x48>
 8005364:	687b      	ldr	r3, [r7, #4]
 8005366:	681b      	ldr	r3, [r3, #0]
 8005368:	4a14      	ldr	r2, [pc, #80]	; (80053bc <HAL_TIM_Base_Start+0x8c>)
 800536a:	4293      	cmp	r3, r2
 800536c:	d004      	beq.n	8005378 <HAL_TIM_Base_Start+0x48>
 800536e:	687b      	ldr	r3, [r7, #4]
 8005370:	681b      	ldr	r3, [r3, #0]
 8005372:	4a13      	ldr	r2, [pc, #76]	; (80053c0 <HAL_TIM_Base_Start+0x90>)
 8005374:	4293      	cmp	r3, r2
 8005376:	d111      	bne.n	800539c <HAL_TIM_Base_Start+0x6c>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8005378:	687b      	ldr	r3, [r7, #4]
 800537a:	681b      	ldr	r3, [r3, #0]
 800537c:	689b      	ldr	r3, [r3, #8]
 800537e:	f003 0307 	and.w	r3, r3, #7
 8005382:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8005384:	68fb      	ldr	r3, [r7, #12]
 8005386:	2b06      	cmp	r3, #6
 8005388:	d010      	beq.n	80053ac <HAL_TIM_Base_Start+0x7c>
    {
      __HAL_TIM_ENABLE(htim);
 800538a:	687b      	ldr	r3, [r7, #4]
 800538c:	681b      	ldr	r3, [r3, #0]
 800538e:	681a      	ldr	r2, [r3, #0]
 8005390:	687b      	ldr	r3, [r7, #4]
 8005392:	681b      	ldr	r3, [r3, #0]
 8005394:	f042 0201 	orr.w	r2, r2, #1
 8005398:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800539a:	e007      	b.n	80053ac <HAL_TIM_Base_Start+0x7c>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 800539c:	687b      	ldr	r3, [r7, #4]
 800539e:	681b      	ldr	r3, [r3, #0]
 80053a0:	681a      	ldr	r2, [r3, #0]
 80053a2:	687b      	ldr	r3, [r7, #4]
 80053a4:	681b      	ldr	r3, [r3, #0]
 80053a6:	f042 0201 	orr.w	r2, r2, #1
 80053aa:	601a      	str	r2, [r3, #0]
  }

  /* Return function status */
  return HAL_OK;
 80053ac:	2300      	movs	r3, #0
}
 80053ae:	4618      	mov	r0, r3
 80053b0:	3714      	adds	r7, #20
 80053b2:	46bd      	mov	sp, r7
 80053b4:	bc80      	pop	{r7}
 80053b6:	4770      	bx	lr
 80053b8:	40000400 	.word	0x40000400
 80053bc:	40000800 	.word	0x40000800
 80053c0:	40010800 	.word	0x40010800

080053c4 <HAL_TIM_Base_Stop>:
  * @brief  Stops the TIM Base generation.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
{
 80053c4:	b480      	push	{r7}
 80053c6:	b083      	sub	sp, #12
 80053c8:	af00      	add	r7, sp, #0
 80053ca:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);
 80053cc:	687b      	ldr	r3, [r7, #4]
 80053ce:	681b      	ldr	r3, [r3, #0]
 80053d0:	6a1a      	ldr	r2, [r3, #32]
 80053d2:	f241 1311 	movw	r3, #4369	; 0x1111
 80053d6:	4013      	ands	r3, r2
 80053d8:	2b00      	cmp	r3, #0
 80053da:	d107      	bne.n	80053ec <HAL_TIM_Base_Stop+0x28>
 80053dc:	687b      	ldr	r3, [r7, #4]
 80053de:	681b      	ldr	r3, [r3, #0]
 80053e0:	681a      	ldr	r2, [r3, #0]
 80053e2:	687b      	ldr	r3, [r7, #4]
 80053e4:	681b      	ldr	r3, [r3, #0]
 80053e6:	f022 0201 	bic.w	r2, r2, #1
 80053ea:	601a      	str	r2, [r3, #0]

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_READY;
 80053ec:	687b      	ldr	r3, [r7, #4]
 80053ee:	2201      	movs	r2, #1
 80053f0:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Return function status */
  return HAL_OK;
 80053f4:	2300      	movs	r3, #0
}
 80053f6:	4618      	mov	r0, r3
 80053f8:	370c      	adds	r7, #12
 80053fa:	46bd      	mov	sp, r7
 80053fc:	bc80      	pop	{r7}
 80053fe:	4770      	bx	lr

08005400 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 8005400:	b480      	push	{r7}
 8005402:	b085      	sub	sp, #20
 8005404:	af00      	add	r7, sp, #0
 8005406:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 8005408:	687b      	ldr	r3, [r7, #4]
 800540a:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 800540e:	b2db      	uxtb	r3, r3
 8005410:	2b01      	cmp	r3, #1
 8005412:	d001      	beq.n	8005418 <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 8005414:	2301      	movs	r3, #1
 8005416:	e03a      	b.n	800548e <HAL_TIM_Base_Start_IT+0x8e>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8005418:	687b      	ldr	r3, [r7, #4]
 800541a:	2202      	movs	r2, #2
 800541c:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8005420:	687b      	ldr	r3, [r7, #4]
 8005422:	681b      	ldr	r3, [r3, #0]
 8005424:	68da      	ldr	r2, [r3, #12]
 8005426:	687b      	ldr	r3, [r7, #4]
 8005428:	681b      	ldr	r3, [r3, #0]
 800542a:	f042 0201 	orr.w	r2, r2, #1
 800542e:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8005430:	687b      	ldr	r3, [r7, #4]
 8005432:	681b      	ldr	r3, [r3, #0]
 8005434:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8005438:	d00e      	beq.n	8005458 <HAL_TIM_Base_Start_IT+0x58>
 800543a:	687b      	ldr	r3, [r7, #4]
 800543c:	681b      	ldr	r3, [r3, #0]
 800543e:	4a16      	ldr	r2, [pc, #88]	; (8005498 <HAL_TIM_Base_Start_IT+0x98>)
 8005440:	4293      	cmp	r3, r2
 8005442:	d009      	beq.n	8005458 <HAL_TIM_Base_Start_IT+0x58>
 8005444:	687b      	ldr	r3, [r7, #4]
 8005446:	681b      	ldr	r3, [r3, #0]
 8005448:	4a14      	ldr	r2, [pc, #80]	; (800549c <HAL_TIM_Base_Start_IT+0x9c>)
 800544a:	4293      	cmp	r3, r2
 800544c:	d004      	beq.n	8005458 <HAL_TIM_Base_Start_IT+0x58>
 800544e:	687b      	ldr	r3, [r7, #4]
 8005450:	681b      	ldr	r3, [r3, #0]
 8005452:	4a13      	ldr	r2, [pc, #76]	; (80054a0 <HAL_TIM_Base_Start_IT+0xa0>)
 8005454:	4293      	cmp	r3, r2
 8005456:	d111      	bne.n	800547c <HAL_TIM_Base_Start_IT+0x7c>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8005458:	687b      	ldr	r3, [r7, #4]
 800545a:	681b      	ldr	r3, [r3, #0]
 800545c:	689b      	ldr	r3, [r3, #8]
 800545e:	f003 0307 	and.w	r3, r3, #7
 8005462:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8005464:	68fb      	ldr	r3, [r7, #12]
 8005466:	2b06      	cmp	r3, #6
 8005468:	d010      	beq.n	800548c <HAL_TIM_Base_Start_IT+0x8c>
    {
      __HAL_TIM_ENABLE(htim);
 800546a:	687b      	ldr	r3, [r7, #4]
 800546c:	681b      	ldr	r3, [r3, #0]
 800546e:	681a      	ldr	r2, [r3, #0]
 8005470:	687b      	ldr	r3, [r7, #4]
 8005472:	681b      	ldr	r3, [r3, #0]
 8005474:	f042 0201 	orr.w	r2, r2, #1
 8005478:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800547a:	e007      	b.n	800548c <HAL_TIM_Base_Start_IT+0x8c>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 800547c:	687b      	ldr	r3, [r7, #4]
 800547e:	681b      	ldr	r3, [r3, #0]
 8005480:	681a      	ldr	r2, [r3, #0]
 8005482:	687b      	ldr	r3, [r7, #4]
 8005484:	681b      	ldr	r3, [r3, #0]
 8005486:	f042 0201 	orr.w	r2, r2, #1
 800548a:	601a      	str	r2, [r3, #0]
  }

  /* Return function status */
  return HAL_OK;
 800548c:	2300      	movs	r3, #0
}
 800548e:	4618      	mov	r0, r3
 8005490:	3714      	adds	r7, #20
 8005492:	46bd      	mov	sp, r7
 8005494:	bc80      	pop	{r7}
 8005496:	4770      	bx	lr
 8005498:	40000400 	.word	0x40000400
 800549c:	40000800 	.word	0x40000800
 80054a0:	40010800 	.word	0x40010800

080054a4 <HAL_TIM_OC_Start>:
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
 80054a4:	b580      	push	{r7, lr}
 80054a6:	b084      	sub	sp, #16
 80054a8:	af00      	add	r7, sp, #0
 80054aa:	6078      	str	r0, [r7, #4]
 80054ac:	6039      	str	r1, [r7, #0]

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
 80054ae:	683b      	ldr	r3, [r7, #0]
 80054b0:	2b00      	cmp	r3, #0
 80054b2:	d109      	bne.n	80054c8 <HAL_TIM_OC_Start+0x24>
 80054b4:	687b      	ldr	r3, [r7, #4]
 80054b6:	f893 303a 	ldrb.w	r3, [r3, #58]	; 0x3a
 80054ba:	b2db      	uxtb	r3, r3
 80054bc:	2b01      	cmp	r3, #1
 80054be:	bf14      	ite	ne
 80054c0:	2301      	movne	r3, #1
 80054c2:	2300      	moveq	r3, #0
 80054c4:	b2db      	uxtb	r3, r3
 80054c6:	e022      	b.n	800550e <HAL_TIM_OC_Start+0x6a>
 80054c8:	683b      	ldr	r3, [r7, #0]
 80054ca:	2b04      	cmp	r3, #4
 80054cc:	d109      	bne.n	80054e2 <HAL_TIM_OC_Start+0x3e>
 80054ce:	687b      	ldr	r3, [r7, #4]
 80054d0:	f893 303b 	ldrb.w	r3, [r3, #59]	; 0x3b
 80054d4:	b2db      	uxtb	r3, r3
 80054d6:	2b01      	cmp	r3, #1
 80054d8:	bf14      	ite	ne
 80054da:	2301      	movne	r3, #1
 80054dc:	2300      	moveq	r3, #0
 80054de:	b2db      	uxtb	r3, r3
 80054e0:	e015      	b.n	800550e <HAL_TIM_OC_Start+0x6a>
 80054e2:	683b      	ldr	r3, [r7, #0]
 80054e4:	2b08      	cmp	r3, #8
 80054e6:	d109      	bne.n	80054fc <HAL_TIM_OC_Start+0x58>
 80054e8:	687b      	ldr	r3, [r7, #4]
 80054ea:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 80054ee:	b2db      	uxtb	r3, r3
 80054f0:	2b01      	cmp	r3, #1
 80054f2:	bf14      	ite	ne
 80054f4:	2301      	movne	r3, #1
 80054f6:	2300      	moveq	r3, #0
 80054f8:	b2db      	uxtb	r3, r3
 80054fa:	e008      	b.n	800550e <HAL_TIM_OC_Start+0x6a>
 80054fc:	687b      	ldr	r3, [r7, #4]
 80054fe:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8005502:	b2db      	uxtb	r3, r3
 8005504:	2b01      	cmp	r3, #1
 8005506:	bf14      	ite	ne
 8005508:	2301      	movne	r3, #1
 800550a:	2300      	moveq	r3, #0
 800550c:	b2db      	uxtb	r3, r3
 800550e:	2b00      	cmp	r3, #0
 8005510:	d001      	beq.n	8005516 <HAL_TIM_OC_Start+0x72>
  {
    return HAL_ERROR;
 8005512:	2301      	movs	r3, #1
 8005514:	e051      	b.n	80055ba <HAL_TIM_OC_Start+0x116>
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 8005516:	683b      	ldr	r3, [r7, #0]
 8005518:	2b00      	cmp	r3, #0
 800551a:	d104      	bne.n	8005526 <HAL_TIM_OC_Start+0x82>
 800551c:	687b      	ldr	r3, [r7, #4]
 800551e:	2202      	movs	r2, #2
 8005520:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a
 8005524:	e013      	b.n	800554e <HAL_TIM_OC_Start+0xaa>
 8005526:	683b      	ldr	r3, [r7, #0]
 8005528:	2b04      	cmp	r3, #4
 800552a:	d104      	bne.n	8005536 <HAL_TIM_OC_Start+0x92>
 800552c:	687b      	ldr	r3, [r7, #4]
 800552e:	2202      	movs	r2, #2
 8005530:	f883 203b 	strb.w	r2, [r3, #59]	; 0x3b
 8005534:	e00b      	b.n	800554e <HAL_TIM_OC_Start+0xaa>
 8005536:	683b      	ldr	r3, [r7, #0]
 8005538:	2b08      	cmp	r3, #8
 800553a:	d104      	bne.n	8005546 <HAL_TIM_OC_Start+0xa2>
 800553c:	687b      	ldr	r3, [r7, #4]
 800553e:	2202      	movs	r2, #2
 8005540:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
 8005544:	e003      	b.n	800554e <HAL_TIM_OC_Start+0xaa>
 8005546:	687b      	ldr	r3, [r7, #4]
 8005548:	2202      	movs	r2, #2
 800554a:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Enable the Output compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 800554e:	687b      	ldr	r3, [r7, #4]
 8005550:	681b      	ldr	r3, [r3, #0]
 8005552:	2201      	movs	r2, #1
 8005554:	6839      	ldr	r1, [r7, #0]
 8005556:	4618      	mov	r0, r3
 8005558:	f000 fe13 	bl	8006182 <TIM_CCxChannelCmd>

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800555c:	687b      	ldr	r3, [r7, #4]
 800555e:	681b      	ldr	r3, [r3, #0]
 8005560:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8005564:	d00e      	beq.n	8005584 <HAL_TIM_OC_Start+0xe0>
 8005566:	687b      	ldr	r3, [r7, #4]
 8005568:	681b      	ldr	r3, [r3, #0]
 800556a:	4a16      	ldr	r2, [pc, #88]	; (80055c4 <HAL_TIM_OC_Start+0x120>)
 800556c:	4293      	cmp	r3, r2
 800556e:	d009      	beq.n	8005584 <HAL_TIM_OC_Start+0xe0>
 8005570:	687b      	ldr	r3, [r7, #4]
 8005572:	681b      	ldr	r3, [r3, #0]
 8005574:	4a14      	ldr	r2, [pc, #80]	; (80055c8 <HAL_TIM_OC_Start+0x124>)
 8005576:	4293      	cmp	r3, r2
 8005578:	d004      	beq.n	8005584 <HAL_TIM_OC_Start+0xe0>
 800557a:	687b      	ldr	r3, [r7, #4]
 800557c:	681b      	ldr	r3, [r3, #0]
 800557e:	4a13      	ldr	r2, [pc, #76]	; (80055cc <HAL_TIM_OC_Start+0x128>)
 8005580:	4293      	cmp	r3, r2
 8005582:	d111      	bne.n	80055a8 <HAL_TIM_OC_Start+0x104>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8005584:	687b      	ldr	r3, [r7, #4]
 8005586:	681b      	ldr	r3, [r3, #0]
 8005588:	689b      	ldr	r3, [r3, #8]
 800558a:	f003 0307 	and.w	r3, r3, #7
 800558e:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8005590:	68fb      	ldr	r3, [r7, #12]
 8005592:	2b06      	cmp	r3, #6
 8005594:	d010      	beq.n	80055b8 <HAL_TIM_OC_Start+0x114>
    {
      __HAL_TIM_ENABLE(htim);
 8005596:	687b      	ldr	r3, [r7, #4]
 8005598:	681b      	ldr	r3, [r3, #0]
 800559a:	681a      	ldr	r2, [r3, #0]
 800559c:	687b      	ldr	r3, [r7, #4]
 800559e:	681b      	ldr	r3, [r3, #0]
 80055a0:	f042 0201 	orr.w	r2, r2, #1
 80055a4:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 80055a6:	e007      	b.n	80055b8 <HAL_TIM_OC_Start+0x114>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 80055a8:	687b      	ldr	r3, [r7, #4]
 80055aa:	681b      	ldr	r3, [r3, #0]
 80055ac:	681a      	ldr	r2, [r3, #0]
 80055ae:	687b      	ldr	r3, [r7, #4]
 80055b0:	681b      	ldr	r3, [r3, #0]
 80055b2:	f042 0201 	orr.w	r2, r2, #1
 80055b6:	601a      	str	r2, [r3, #0]
  }

  /* Return function status */
  return HAL_OK;
 80055b8:	2300      	movs	r3, #0
}
 80055ba:	4618      	mov	r0, r3
 80055bc:	3710      	adds	r7, #16
 80055be:	46bd      	mov	sp, r7
 80055c0:	bd80      	pop	{r7, pc}
 80055c2:	bf00      	nop
 80055c4:	40000400 	.word	0x40000400
 80055c8:	40000800 	.word	0x40000800
 80055cc:	40010800 	.word	0x40010800

080055d0 <HAL_TIM_PWM_Init>:
  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
  * @param  htim TIM PWM handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
 80055d0:	b580      	push	{r7, lr}
 80055d2:	b082      	sub	sp, #8
 80055d4:	af00      	add	r7, sp, #0
 80055d6:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 80055d8:	687b      	ldr	r3, [r7, #4]
 80055da:	2b00      	cmp	r3, #0
 80055dc:	d101      	bne.n	80055e2 <HAL_TIM_PWM_Init+0x12>
  {
    return HAL_ERROR;
 80055de:	2301      	movs	r3, #1
 80055e0:	e031      	b.n	8005646 <HAL_TIM_PWM_Init+0x76>
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 80055e2:	687b      	ldr	r3, [r7, #4]
 80055e4:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 80055e8:	b2db      	uxtb	r3, r3
 80055ea:	2b00      	cmp	r3, #0
 80055ec:	d106      	bne.n	80055fc <HAL_TIM_PWM_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 80055ee:	687b      	ldr	r3, [r7, #4]
 80055f0:	2200      	movs	r2, #0
 80055f2:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->PWM_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_PWM_MspInit(htim);
 80055f6:	6878      	ldr	r0, [r7, #4]
 80055f8:	f000 f829 	bl	800564e <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 80055fc:	687b      	ldr	r3, [r7, #4]
 80055fe:	2202      	movs	r2, #2
 8005600:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Init the base time for the PWM */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8005604:	687b      	ldr	r3, [r7, #4]
 8005606:	681a      	ldr	r2, [r3, #0]
 8005608:	687b      	ldr	r3, [r7, #4]
 800560a:	3304      	adds	r3, #4
 800560c:	4619      	mov	r1, r3
 800560e:	4610      	mov	r0, r2
 8005610:	f000 fb3c 	bl	8005c8c <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8005614:	687b      	ldr	r3, [r7, #4]
 8005616:	2201      	movs	r2, #1
 8005618:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800561c:	687b      	ldr	r3, [r7, #4]
 800561e:	2201      	movs	r2, #1
 8005620:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a
 8005624:	687b      	ldr	r3, [r7, #4]
 8005626:	2201      	movs	r2, #1
 8005628:	f883 203b 	strb.w	r2, [r3, #59]	; 0x3b
 800562c:	687b      	ldr	r3, [r7, #4]
 800562e:	2201      	movs	r2, #1
 8005630:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
 8005634:	687b      	ldr	r3, [r7, #4]
 8005636:	2201      	movs	r2, #1
 8005638:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 800563c:	687b      	ldr	r3, [r7, #4]
 800563e:	2201      	movs	r2, #1
 8005640:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  return HAL_OK;
 8005644:	2300      	movs	r3, #0
}
 8005646:	4618      	mov	r0, r3
 8005648:	3708      	adds	r7, #8
 800564a:	46bd      	mov	sp, r7
 800564c:	bd80      	pop	{r7, pc}

0800564e <HAL_TIM_PWM_MspInit>:
  * @brief  Initializes the TIM PWM MSP.
  * @param  htim TIM PWM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
 800564e:	b480      	push	{r7}
 8005650:	b083      	sub	sp, #12
 8005652:	af00      	add	r7, sp, #0
 8005654:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_MspInit could be implemented in the user file
   */
}
 8005656:	bf00      	nop
 8005658:	370c      	adds	r7, #12
 800565a:	46bd      	mov	sp, r7
 800565c:	bc80      	pop	{r7}
 800565e:	4770      	bx	lr

08005660 <HAL_TIM_OnePulse_Init>:
  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
{
 8005660:	b580      	push	{r7, lr}
 8005662:	b082      	sub	sp, #8
 8005664:	af00      	add	r7, sp, #0
 8005666:	6078      	str	r0, [r7, #4]
 8005668:	6039      	str	r1, [r7, #0]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 800566a:	687b      	ldr	r3, [r7, #4]
 800566c:	2b00      	cmp	r3, #0
 800566e:	d101      	bne.n	8005674 <HAL_TIM_OnePulse_Init+0x14>
  {
    return HAL_ERROR;
 8005670:	2301      	movs	r3, #1
 8005672:	e039      	b.n	80056e8 <HAL_TIM_OnePulse_Init+0x88>
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8005674:	687b      	ldr	r3, [r7, #4]
 8005676:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 800567a:	b2db      	uxtb	r3, r3
 800567c:	2b00      	cmp	r3, #0
 800567e:	d106      	bne.n	800568e <HAL_TIM_OnePulse_Init+0x2e>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8005680:	687b      	ldr	r3, [r7, #4]
 8005682:	2200      	movs	r2, #0
 8005684:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->OnePulse_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_OnePulse_MspInit(htim);
 8005688:	6878      	ldr	r0, [r7, #4]
 800568a:	f000 f831 	bl	80056f0 <HAL_TIM_OnePulse_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 800568e:	687b      	ldr	r3, [r7, #4]
 8005690:	2202      	movs	r2, #2
 8005692:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Configure the Time base in the One Pulse Mode */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8005696:	687b      	ldr	r3, [r7, #4]
 8005698:	681a      	ldr	r2, [r3, #0]
 800569a:	687b      	ldr	r3, [r7, #4]
 800569c:	3304      	adds	r3, #4
 800569e:	4619      	mov	r1, r3
 80056a0:	4610      	mov	r0, r2
 80056a2:	f000 faf3 	bl	8005c8c <TIM_Base_SetConfig>

  /* Reset the OPM Bit */
  htim->Instance->CR1 &= ~TIM_CR1_OPM;
 80056a6:	687b      	ldr	r3, [r7, #4]
 80056a8:	681b      	ldr	r3, [r3, #0]
 80056aa:	681a      	ldr	r2, [r3, #0]
 80056ac:	687b      	ldr	r3, [r7, #4]
 80056ae:	681b      	ldr	r3, [r3, #0]
 80056b0:	f022 0208 	bic.w	r2, r2, #8
 80056b4:	601a      	str	r2, [r3, #0]

  /* Configure the OPM Mode */
  htim->Instance->CR1 |= OnePulseMode;
 80056b6:	687b      	ldr	r3, [r7, #4]
 80056b8:	681b      	ldr	r3, [r3, #0]
 80056ba:	6819      	ldr	r1, [r3, #0]
 80056bc:	687b      	ldr	r3, [r7, #4]
 80056be:	681b      	ldr	r3, [r3, #0]
 80056c0:	683a      	ldr	r2, [r7, #0]
 80056c2:	430a      	orrs	r2, r1
 80056c4:	601a      	str	r2, [r3, #0]

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 80056c6:	687b      	ldr	r3, [r7, #4]
 80056c8:	2201      	movs	r2, #1
 80056ca:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
 80056ce:	687b      	ldr	r3, [r7, #4]
 80056d0:	2201      	movs	r2, #1
 80056d2:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
 80056d6:	687b      	ldr	r3, [r7, #4]
 80056d8:	2201      	movs	r2, #1
 80056da:	f883 203b 	strb.w	r2, [r3, #59]	; 0x3b

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 80056de:	687b      	ldr	r3, [r7, #4]
 80056e0:	2201      	movs	r2, #1
 80056e2:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  return HAL_OK;
 80056e6:	2300      	movs	r3, #0
}
 80056e8:	4618      	mov	r0, r3
 80056ea:	3708      	adds	r7, #8
 80056ec:	46bd      	mov	sp, r7
 80056ee:	bd80      	pop	{r7, pc}

080056f0 <HAL_TIM_OnePulse_MspInit>:
  * @brief  Initializes the TIM One Pulse MSP.
  * @param  htim TIM One Pulse handle
  * @retval None
  */
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
{
 80056f0:	b480      	push	{r7}
 80056f2:	b083      	sub	sp, #12
 80056f4:	af00      	add	r7, sp, #0
 80056f6:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
   */
}
 80056f8:	bf00      	nop
 80056fa:	370c      	adds	r7, #12
 80056fc:	46bd      	mov	sp, r7
 80056fe:	bc80      	pop	{r7}
 8005700:	4770      	bx	lr

08005702 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 8005702:	b580      	push	{r7, lr}
 8005704:	b082      	sub	sp, #8
 8005706:	af00      	add	r7, sp, #0
 8005708:	6078      	str	r0, [r7, #4]
  /* Capture compare 1 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 800570a:	687b      	ldr	r3, [r7, #4]
 800570c:	681b      	ldr	r3, [r3, #0]
 800570e:	691b      	ldr	r3, [r3, #16]
 8005710:	f003 0302 	and.w	r3, r3, #2
 8005714:	2b02      	cmp	r3, #2
 8005716:	d122      	bne.n	800575e <HAL_TIM_IRQHandler+0x5c>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
 8005718:	687b      	ldr	r3, [r7, #4]
 800571a:	681b      	ldr	r3, [r3, #0]
 800571c:	68db      	ldr	r3, [r3, #12]
 800571e:	f003 0302 	and.w	r3, r3, #2
 8005722:	2b02      	cmp	r3, #2
 8005724:	d11b      	bne.n	800575e <HAL_TIM_IRQHandler+0x5c>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 8005726:	687b      	ldr	r3, [r7, #4]
 8005728:	681b      	ldr	r3, [r3, #0]
 800572a:	f06f 0202 	mvn.w	r2, #2
 800572e:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 8005730:	687b      	ldr	r3, [r7, #4]
 8005732:	2201      	movs	r2, #1
 8005734:	761a      	strb	r2, [r3, #24]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 8005736:	687b      	ldr	r3, [r7, #4]
 8005738:	681b      	ldr	r3, [r3, #0]
 800573a:	699b      	ldr	r3, [r3, #24]
 800573c:	f003 0303 	and.w	r3, r3, #3
 8005740:	2b00      	cmp	r3, #0
 8005742:	d003      	beq.n	800574c <HAL_TIM_IRQHandler+0x4a>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 8005744:	6878      	ldr	r0, [r7, #4]
 8005746:	f000 fa86 	bl	8005c56 <HAL_TIM_IC_CaptureCallback>
 800574a:	e005      	b.n	8005758 <HAL_TIM_IRQHandler+0x56>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 800574c:	6878      	ldr	r0, [r7, #4]
 800574e:	f000 fa79 	bl	8005c44 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 8005752:	6878      	ldr	r0, [r7, #4]
 8005754:	f000 fa88 	bl	8005c68 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005758:	687b      	ldr	r3, [r7, #4]
 800575a:	2200      	movs	r2, #0
 800575c:	761a      	strb	r2, [r3, #24]
      }
    }
  }
  /* Capture compare 2 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 800575e:	687b      	ldr	r3, [r7, #4]
 8005760:	681b      	ldr	r3, [r3, #0]
 8005762:	691b      	ldr	r3, [r3, #16]
 8005764:	f003 0304 	and.w	r3, r3, #4
 8005768:	2b04      	cmp	r3, #4
 800576a:	d122      	bne.n	80057b2 <HAL_TIM_IRQHandler+0xb0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
 800576c:	687b      	ldr	r3, [r7, #4]
 800576e:	681b      	ldr	r3, [r3, #0]
 8005770:	68db      	ldr	r3, [r3, #12]
 8005772:	f003 0304 	and.w	r3, r3, #4
 8005776:	2b04      	cmp	r3, #4
 8005778:	d11b      	bne.n	80057b2 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 800577a:	687b      	ldr	r3, [r7, #4]
 800577c:	681b      	ldr	r3, [r3, #0]
 800577e:	f06f 0204 	mvn.w	r2, #4
 8005782:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8005784:	687b      	ldr	r3, [r7, #4]
 8005786:	2202      	movs	r2, #2
 8005788:	761a      	strb	r2, [r3, #24]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800578a:	687b      	ldr	r3, [r7, #4]
 800578c:	681b      	ldr	r3, [r3, #0]
 800578e:	699b      	ldr	r3, [r3, #24]
 8005790:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8005794:	2b00      	cmp	r3, #0
 8005796:	d003      	beq.n	80057a0 <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8005798:	6878      	ldr	r0, [r7, #4]
 800579a:	f000 fa5c 	bl	8005c56 <HAL_TIM_IC_CaptureCallback>
 800579e:	e005      	b.n	80057ac <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80057a0:	6878      	ldr	r0, [r7, #4]
 80057a2:	f000 fa4f 	bl	8005c44 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80057a6:	6878      	ldr	r0, [r7, #4]
 80057a8:	f000 fa5e 	bl	8005c68 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80057ac:	687b      	ldr	r3, [r7, #4]
 80057ae:	2200      	movs	r2, #0
 80057b0:	761a      	strb	r2, [r3, #24]
    }
  }
  /* Capture compare 3 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 80057b2:	687b      	ldr	r3, [r7, #4]
 80057b4:	681b      	ldr	r3, [r3, #0]
 80057b6:	691b      	ldr	r3, [r3, #16]
 80057b8:	f003 0308 	and.w	r3, r3, #8
 80057bc:	2b08      	cmp	r3, #8
 80057be:	d122      	bne.n	8005806 <HAL_TIM_IRQHandler+0x104>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
 80057c0:	687b      	ldr	r3, [r7, #4]
 80057c2:	681b      	ldr	r3, [r3, #0]
 80057c4:	68db      	ldr	r3, [r3, #12]
 80057c6:	f003 0308 	and.w	r3, r3, #8
 80057ca:	2b08      	cmp	r3, #8
 80057cc:	d11b      	bne.n	8005806 <HAL_TIM_IRQHandler+0x104>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 80057ce:	687b      	ldr	r3, [r7, #4]
 80057d0:	681b      	ldr	r3, [r3, #0]
 80057d2:	f06f 0208 	mvn.w	r2, #8
 80057d6:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 80057d8:	687b      	ldr	r3, [r7, #4]
 80057da:	2204      	movs	r2, #4
 80057dc:	761a      	strb	r2, [r3, #24]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 80057de:	687b      	ldr	r3, [r7, #4]
 80057e0:	681b      	ldr	r3, [r3, #0]
 80057e2:	69db      	ldr	r3, [r3, #28]
 80057e4:	f003 0303 	and.w	r3, r3, #3
 80057e8:	2b00      	cmp	r3, #0
 80057ea:	d003      	beq.n	80057f4 <HAL_TIM_IRQHandler+0xf2>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 80057ec:	6878      	ldr	r0, [r7, #4]
 80057ee:	f000 fa32 	bl	8005c56 <HAL_TIM_IC_CaptureCallback>
 80057f2:	e005      	b.n	8005800 <HAL_TIM_IRQHandler+0xfe>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80057f4:	6878      	ldr	r0, [r7, #4]
 80057f6:	f000 fa25 	bl	8005c44 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80057fa:	6878      	ldr	r0, [r7, #4]
 80057fc:	f000 fa34 	bl	8005c68 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005800:	687b      	ldr	r3, [r7, #4]
 8005802:	2200      	movs	r2, #0
 8005804:	761a      	strb	r2, [r3, #24]
    }
  }
  /* Capture compare 4 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 8005806:	687b      	ldr	r3, [r7, #4]
 8005808:	681b      	ldr	r3, [r3, #0]
 800580a:	691b      	ldr	r3, [r3, #16]
 800580c:	f003 0310 	and.w	r3, r3, #16
 8005810:	2b10      	cmp	r3, #16
 8005812:	d122      	bne.n	800585a <HAL_TIM_IRQHandler+0x158>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
 8005814:	687b      	ldr	r3, [r7, #4]
 8005816:	681b      	ldr	r3, [r3, #0]
 8005818:	68db      	ldr	r3, [r3, #12]
 800581a:	f003 0310 	and.w	r3, r3, #16
 800581e:	2b10      	cmp	r3, #16
 8005820:	d11b      	bne.n	800585a <HAL_TIM_IRQHandler+0x158>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 8005822:	687b      	ldr	r3, [r7, #4]
 8005824:	681b      	ldr	r3, [r3, #0]
 8005826:	f06f 0210 	mvn.w	r2, #16
 800582a:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800582c:	687b      	ldr	r3, [r7, #4]
 800582e:	2208      	movs	r2, #8
 8005830:	761a      	strb	r2, [r3, #24]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8005832:	687b      	ldr	r3, [r7, #4]
 8005834:	681b      	ldr	r3, [r3, #0]
 8005836:	69db      	ldr	r3, [r3, #28]
 8005838:	f403 7340 	and.w	r3, r3, #768	; 0x300
 800583c:	2b00      	cmp	r3, #0
 800583e:	d003      	beq.n	8005848 <HAL_TIM_IRQHandler+0x146>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8005840:	6878      	ldr	r0, [r7, #4]
 8005842:	f000 fa08 	bl	8005c56 <HAL_TIM_IC_CaptureCallback>
 8005846:	e005      	b.n	8005854 <HAL_TIM_IRQHandler+0x152>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8005848:	6878      	ldr	r0, [r7, #4]
 800584a:	f000 f9fb 	bl	8005c44 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800584e:	6878      	ldr	r0, [r7, #4]
 8005850:	f000 fa0a 	bl	8005c68 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005854:	687b      	ldr	r3, [r7, #4]
 8005856:	2200      	movs	r2, #0
 8005858:	761a      	strb	r2, [r3, #24]
    }
  }
  /* TIM Update event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 800585a:	687b      	ldr	r3, [r7, #4]
 800585c:	681b      	ldr	r3, [r3, #0]
 800585e:	691b      	ldr	r3, [r3, #16]
 8005860:	f003 0301 	and.w	r3, r3, #1
 8005864:	2b01      	cmp	r3, #1
 8005866:	d10e      	bne.n	8005886 <HAL_TIM_IRQHandler+0x184>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
 8005868:	687b      	ldr	r3, [r7, #4]
 800586a:	681b      	ldr	r3, [r3, #0]
 800586c:	68db      	ldr	r3, [r3, #12]
 800586e:	f003 0301 	and.w	r3, r3, #1
 8005872:	2b01      	cmp	r3, #1
 8005874:	d107      	bne.n	8005886 <HAL_TIM_IRQHandler+0x184>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8005876:	687b      	ldr	r3, [r7, #4]
 8005878:	681b      	ldr	r3, [r3, #0]
 800587a:	f06f 0201 	mvn.w	r2, #1
 800587e:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 8005880:	6878      	ldr	r0, [r7, #4]
 8005882:	f7fb fbc7 	bl	8001014 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 8005886:	687b      	ldr	r3, [r7, #4]
 8005888:	681b      	ldr	r3, [r3, #0]
 800588a:	691b      	ldr	r3, [r3, #16]
 800588c:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8005890:	2b40      	cmp	r3, #64	; 0x40
 8005892:	d10e      	bne.n	80058b2 <HAL_TIM_IRQHandler+0x1b0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
 8005894:	687b      	ldr	r3, [r7, #4]
 8005896:	681b      	ldr	r3, [r3, #0]
 8005898:	68db      	ldr	r3, [r3, #12]
 800589a:	f003 0340 	and.w	r3, r3, #64	; 0x40
 800589e:	2b40      	cmp	r3, #64	; 0x40
 80058a0:	d107      	bne.n	80058b2 <HAL_TIM_IRQHandler+0x1b0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80058a2:	687b      	ldr	r3, [r7, #4]
 80058a4:	681b      	ldr	r3, [r3, #0]
 80058a6:	f06f 0240 	mvn.w	r2, #64	; 0x40
 80058aa:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 80058ac:	6878      	ldr	r0, [r7, #4]
 80058ae:	f000 f9e4 	bl	8005c7a <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 80058b2:	bf00      	nop
 80058b4:	3708      	adds	r7, #8
 80058b6:	46bd      	mov	sp, r7
 80058b8:	bd80      	pop	{r7, pc}
	...

080058bc <HAL_TIM_PWM_ConfigChannel>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
                                            TIM_OC_InitTypeDef *sConfig,
                                            uint32_t Channel)
{
 80058bc:	b580      	push	{r7, lr}
 80058be:	b084      	sub	sp, #16
 80058c0:	af00      	add	r7, sp, #0
 80058c2:	60f8      	str	r0, [r7, #12]
 80058c4:	60b9      	str	r1, [r7, #8]
 80058c6:	607a      	str	r2, [r7, #4]
  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));

  /* Process Locked */
  __HAL_LOCK(htim);
 80058c8:	68fb      	ldr	r3, [r7, #12]
 80058ca:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 80058ce:	2b01      	cmp	r3, #1
 80058d0:	d101      	bne.n	80058d6 <HAL_TIM_PWM_ConfigChannel+0x1a>
 80058d2:	2302      	movs	r3, #2
 80058d4:	e0ac      	b.n	8005a30 <HAL_TIM_PWM_ConfigChannel+0x174>
 80058d6:	68fb      	ldr	r3, [r7, #12]
 80058d8:	2201      	movs	r2, #1
 80058da:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
 80058de:	687b      	ldr	r3, [r7, #4]
 80058e0:	2b0c      	cmp	r3, #12
 80058e2:	f200 809f 	bhi.w	8005a24 <HAL_TIM_PWM_ConfigChannel+0x168>
 80058e6:	a201      	add	r2, pc, #4	; (adr r2, 80058ec <HAL_TIM_PWM_ConfigChannel+0x30>)
 80058e8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 80058ec:	08005921 	.word	0x08005921
 80058f0:	08005a25 	.word	0x08005a25
 80058f4:	08005a25 	.word	0x08005a25
 80058f8:	08005a25 	.word	0x08005a25
 80058fc:	08005961 	.word	0x08005961
 8005900:	08005a25 	.word	0x08005a25
 8005904:	08005a25 	.word	0x08005a25
 8005908:	08005a25 	.word	0x08005a25
 800590c:	080059a3 	.word	0x080059a3
 8005910:	08005a25 	.word	0x08005a25
 8005914:	08005a25 	.word	0x08005a25
 8005918:	08005a25 	.word	0x08005a25
 800591c:	080059e3 	.word	0x080059e3
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

      /* Configure the Channel 1 in PWM mode */
      TIM_OC1_SetConfig(htim->Instance, sConfig);
 8005920:	68fb      	ldr	r3, [r7, #12]
 8005922:	681b      	ldr	r3, [r3, #0]
 8005924:	68b9      	ldr	r1, [r7, #8]
 8005926:	4618      	mov	r0, r3
 8005928:	f000 fa12 	bl	8005d50 <TIM_OC1_SetConfig>

      /* Set the Preload enable bit for channel1 */
      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
 800592c:	68fb      	ldr	r3, [r7, #12]
 800592e:	681b      	ldr	r3, [r3, #0]
 8005930:	699a      	ldr	r2, [r3, #24]
 8005932:	68fb      	ldr	r3, [r7, #12]
 8005934:	681b      	ldr	r3, [r3, #0]
 8005936:	f042 0208 	orr.w	r2, r2, #8
 800593a:	619a      	str	r2, [r3, #24]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
 800593c:	68fb      	ldr	r3, [r7, #12]
 800593e:	681b      	ldr	r3, [r3, #0]
 8005940:	699a      	ldr	r2, [r3, #24]
 8005942:	68fb      	ldr	r3, [r7, #12]
 8005944:	681b      	ldr	r3, [r3, #0]
 8005946:	f022 0204 	bic.w	r2, r2, #4
 800594a:	619a      	str	r2, [r3, #24]
      htim->Instance->CCMR1 |= sConfig->OCFastMode;
 800594c:	68fb      	ldr	r3, [r7, #12]
 800594e:	681b      	ldr	r3, [r3, #0]
 8005950:	6999      	ldr	r1, [r3, #24]
 8005952:	68bb      	ldr	r3, [r7, #8]
 8005954:	68da      	ldr	r2, [r3, #12]
 8005956:	68fb      	ldr	r3, [r7, #12]
 8005958:	681b      	ldr	r3, [r3, #0]
 800595a:	430a      	orrs	r2, r1
 800595c:	619a      	str	r2, [r3, #24]
      break;
 800595e:	e062      	b.n	8005a26 <HAL_TIM_PWM_ConfigChannel+0x16a>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

      /* Configure the Channel 2 in PWM mode */
      TIM_OC2_SetConfig(htim->Instance, sConfig);
 8005960:	68fb      	ldr	r3, [r7, #12]
 8005962:	681b      	ldr	r3, [r3, #0]
 8005964:	68b9      	ldr	r1, [r7, #8]
 8005966:	4618      	mov	r0, r3
 8005968:	f000 fa2e 	bl	8005dc8 <TIM_OC2_SetConfig>

      /* Set the Preload enable bit for channel2 */
      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
 800596c:	68fb      	ldr	r3, [r7, #12]
 800596e:	681b      	ldr	r3, [r3, #0]
 8005970:	699a      	ldr	r2, [r3, #24]
 8005972:	68fb      	ldr	r3, [r7, #12]
 8005974:	681b      	ldr	r3, [r3, #0]
 8005976:	f442 6200 	orr.w	r2, r2, #2048	; 0x800
 800597a:	619a      	str	r2, [r3, #24]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
 800597c:	68fb      	ldr	r3, [r7, #12]
 800597e:	681b      	ldr	r3, [r3, #0]
 8005980:	699a      	ldr	r2, [r3, #24]
 8005982:	68fb      	ldr	r3, [r7, #12]
 8005984:	681b      	ldr	r3, [r3, #0]
 8005986:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
 800598a:	619a      	str	r2, [r3, #24]
      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
 800598c:	68fb      	ldr	r3, [r7, #12]
 800598e:	681b      	ldr	r3, [r3, #0]
 8005990:	6999      	ldr	r1, [r3, #24]
 8005992:	68bb      	ldr	r3, [r7, #8]
 8005994:	68db      	ldr	r3, [r3, #12]
 8005996:	021a      	lsls	r2, r3, #8
 8005998:	68fb      	ldr	r3, [r7, #12]
 800599a:	681b      	ldr	r3, [r3, #0]
 800599c:	430a      	orrs	r2, r1
 800599e:	619a      	str	r2, [r3, #24]
      break;
 80059a0:	e041      	b.n	8005a26 <HAL_TIM_PWM_ConfigChannel+0x16a>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

      /* Configure the Channel 3 in PWM mode */
      TIM_OC3_SetConfig(htim->Instance, sConfig);
 80059a2:	68fb      	ldr	r3, [r7, #12]
 80059a4:	681b      	ldr	r3, [r3, #0]
 80059a6:	68b9      	ldr	r1, [r7, #8]
 80059a8:	4618      	mov	r0, r3
 80059aa:	f000 fa4b 	bl	8005e44 <TIM_OC3_SetConfig>

      /* Set the Preload enable bit for channel3 */
      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
 80059ae:	68fb      	ldr	r3, [r7, #12]
 80059b0:	681b      	ldr	r3, [r3, #0]
 80059b2:	69da      	ldr	r2, [r3, #28]
 80059b4:	68fb      	ldr	r3, [r7, #12]
 80059b6:	681b      	ldr	r3, [r3, #0]
 80059b8:	f042 0208 	orr.w	r2, r2, #8
 80059bc:	61da      	str	r2, [r3, #28]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
 80059be:	68fb      	ldr	r3, [r7, #12]
 80059c0:	681b      	ldr	r3, [r3, #0]
 80059c2:	69da      	ldr	r2, [r3, #28]
 80059c4:	68fb      	ldr	r3, [r7, #12]
 80059c6:	681b      	ldr	r3, [r3, #0]
 80059c8:	f022 0204 	bic.w	r2, r2, #4
 80059cc:	61da      	str	r2, [r3, #28]
      htim->Instance->CCMR2 |= sConfig->OCFastMode;
 80059ce:	68fb      	ldr	r3, [r7, #12]
 80059d0:	681b      	ldr	r3, [r3, #0]
 80059d2:	69d9      	ldr	r1, [r3, #28]
 80059d4:	68bb      	ldr	r3, [r7, #8]
 80059d6:	68da      	ldr	r2, [r3, #12]
 80059d8:	68fb      	ldr	r3, [r7, #12]
 80059da:	681b      	ldr	r3, [r3, #0]
 80059dc:	430a      	orrs	r2, r1
 80059de:	61da      	str	r2, [r3, #28]
      break;
 80059e0:	e021      	b.n	8005a26 <HAL_TIM_PWM_ConfigChannel+0x16a>
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

      /* Configure the Channel 4 in PWM mode */
      TIM_OC4_SetConfig(htim->Instance, sConfig);
 80059e2:	68fb      	ldr	r3, [r7, #12]
 80059e4:	681b      	ldr	r3, [r3, #0]
 80059e6:	68b9      	ldr	r1, [r7, #8]
 80059e8:	4618      	mov	r0, r3
 80059ea:	f000 fa68 	bl	8005ebe <TIM_OC4_SetConfig>

      /* Set the Preload enable bit for channel4 */
      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
 80059ee:	68fb      	ldr	r3, [r7, #12]
 80059f0:	681b      	ldr	r3, [r3, #0]
 80059f2:	69da      	ldr	r2, [r3, #28]
 80059f4:	68fb      	ldr	r3, [r7, #12]
 80059f6:	681b      	ldr	r3, [r3, #0]
 80059f8:	f442 6200 	orr.w	r2, r2, #2048	; 0x800
 80059fc:	61da      	str	r2, [r3, #28]

      /* Configure the Output Fast mode */
      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
 80059fe:	68fb      	ldr	r3, [r7, #12]
 8005a00:	681b      	ldr	r3, [r3, #0]
 8005a02:	69da      	ldr	r2, [r3, #28]
 8005a04:	68fb      	ldr	r3, [r7, #12]
 8005a06:	681b      	ldr	r3, [r3, #0]
 8005a08:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
 8005a0c:	61da      	str	r2, [r3, #28]
      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
 8005a0e:	68fb      	ldr	r3, [r7, #12]
 8005a10:	681b      	ldr	r3, [r3, #0]
 8005a12:	69d9      	ldr	r1, [r3, #28]
 8005a14:	68bb      	ldr	r3, [r7, #8]
 8005a16:	68db      	ldr	r3, [r3, #12]
 8005a18:	021a      	lsls	r2, r3, #8
 8005a1a:	68fb      	ldr	r3, [r7, #12]
 8005a1c:	681b      	ldr	r3, [r3, #0]
 8005a1e:	430a      	orrs	r2, r1
 8005a20:	61da      	str	r2, [r3, #28]
      break;
 8005a22:	e000      	b.n	8005a26 <HAL_TIM_PWM_ConfigChannel+0x16a>
    }

    default:
      break;
 8005a24:	bf00      	nop
  }

  __HAL_UNLOCK(htim);
 8005a26:	68fb      	ldr	r3, [r7, #12]
 8005a28:	2200      	movs	r2, #0
 8005a2a:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

  return HAL_OK;
 8005a2e:	2300      	movs	r3, #0
}
 8005a30:	4618      	mov	r0, r3
 8005a32:	3710      	adds	r7, #16
 8005a34:	46bd      	mov	sp, r7
 8005a36:	bd80      	pop	{r7, pc}

08005a38 <HAL_TIM_ConfigClockSource>:
  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  *         contains the clock source information for the TIM peripheral.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
 8005a38:	b580      	push	{r7, lr}
 8005a3a:	b084      	sub	sp, #16
 8005a3c:	af00      	add	r7, sp, #0
 8005a3e:	6078      	str	r0, [r7, #4]
 8005a40:	6039      	str	r1, [r7, #0]
  uint32_t tmpsmcr;

  /* Process Locked */
  __HAL_LOCK(htim);
 8005a42:	687b      	ldr	r3, [r7, #4]
 8005a44:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 8005a48:	2b01      	cmp	r3, #1
 8005a4a:	d101      	bne.n	8005a50 <HAL_TIM_ConfigClockSource+0x18>
 8005a4c:	2302      	movs	r3, #2
 8005a4e:	e0b3      	b.n	8005bb8 <HAL_TIM_ConfigClockSource+0x180>
 8005a50:	687b      	ldr	r3, [r7, #4]
 8005a52:	2201      	movs	r2, #1
 8005a54:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

  htim->State = HAL_TIM_STATE_BUSY;
 8005a58:	687b      	ldr	r3, [r7, #4]
 8005a5a:	2202      	movs	r2, #2
 8005a5c:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Check the parameters */
  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));

  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  tmpsmcr = htim->Instance->SMCR;
 8005a60:	687b      	ldr	r3, [r7, #4]
 8005a62:	681b      	ldr	r3, [r3, #0]
 8005a64:	689b      	ldr	r3, [r3, #8]
 8005a66:	60fb      	str	r3, [r7, #12]
  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
 8005a68:	68fb      	ldr	r3, [r7, #12]
 8005a6a:	f023 0377 	bic.w	r3, r3, #119	; 0x77
 8005a6e:	60fb      	str	r3, [r7, #12]
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 8005a70:	68fb      	ldr	r3, [r7, #12]
 8005a72:	f423 437f 	bic.w	r3, r3, #65280	; 0xff00
 8005a76:	60fb      	str	r3, [r7, #12]
  htim->Instance->SMCR = tmpsmcr;
 8005a78:	687b      	ldr	r3, [r7, #4]
 8005a7a:	681b      	ldr	r3, [r3, #0]
 8005a7c:	68fa      	ldr	r2, [r7, #12]
 8005a7e:	609a      	str	r2, [r3, #8]

  switch (sClockSourceConfig->ClockSource)
 8005a80:	683b      	ldr	r3, [r7, #0]
 8005a82:	681b      	ldr	r3, [r3, #0]
 8005a84:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
 8005a88:	d03e      	beq.n	8005b08 <HAL_TIM_ConfigClockSource+0xd0>
 8005a8a:	f5b3 5f00 	cmp.w	r3, #8192	; 0x2000
 8005a8e:	f200 8087 	bhi.w	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005a92:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8005a96:	f000 8085 	beq.w	8005ba4 <HAL_TIM_ConfigClockSource+0x16c>
 8005a9a:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8005a9e:	d87f      	bhi.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005aa0:	2b70      	cmp	r3, #112	; 0x70
 8005aa2:	d01a      	beq.n	8005ada <HAL_TIM_ConfigClockSource+0xa2>
 8005aa4:	2b70      	cmp	r3, #112	; 0x70
 8005aa6:	d87b      	bhi.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005aa8:	2b60      	cmp	r3, #96	; 0x60
 8005aaa:	d050      	beq.n	8005b4e <HAL_TIM_ConfigClockSource+0x116>
 8005aac:	2b60      	cmp	r3, #96	; 0x60
 8005aae:	d877      	bhi.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005ab0:	2b50      	cmp	r3, #80	; 0x50
 8005ab2:	d03c      	beq.n	8005b2e <HAL_TIM_ConfigClockSource+0xf6>
 8005ab4:	2b50      	cmp	r3, #80	; 0x50
 8005ab6:	d873      	bhi.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005ab8:	2b40      	cmp	r3, #64	; 0x40
 8005aba:	d058      	beq.n	8005b6e <HAL_TIM_ConfigClockSource+0x136>
 8005abc:	2b40      	cmp	r3, #64	; 0x40
 8005abe:	d86f      	bhi.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005ac0:	2b30      	cmp	r3, #48	; 0x30
 8005ac2:	d064      	beq.n	8005b8e <HAL_TIM_ConfigClockSource+0x156>
 8005ac4:	2b30      	cmp	r3, #48	; 0x30
 8005ac6:	d86b      	bhi.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005ac8:	2b20      	cmp	r3, #32
 8005aca:	d060      	beq.n	8005b8e <HAL_TIM_ConfigClockSource+0x156>
 8005acc:	2b20      	cmp	r3, #32
 8005ace:	d867      	bhi.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
 8005ad0:	2b00      	cmp	r3, #0
 8005ad2:	d05c      	beq.n	8005b8e <HAL_TIM_ConfigClockSource+0x156>
 8005ad4:	2b10      	cmp	r3, #16
 8005ad6:	d05a      	beq.n	8005b8e <HAL_TIM_ConfigClockSource+0x156>
        TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
        break;
      }

    default:
      break;
 8005ad8:	e062      	b.n	8005ba0 <HAL_TIM_ConfigClockSource+0x168>
      TIM_ETR_SetConfig(htim->Instance,
 8005ada:	687b      	ldr	r3, [r7, #4]
 8005adc:	6818      	ldr	r0, [r3, #0]
 8005ade:	683b      	ldr	r3, [r7, #0]
 8005ae0:	6899      	ldr	r1, [r3, #8]
 8005ae2:	683b      	ldr	r3, [r7, #0]
 8005ae4:	685a      	ldr	r2, [r3, #4]
 8005ae6:	683b      	ldr	r3, [r7, #0]
 8005ae8:	68db      	ldr	r3, [r3, #12]
 8005aea:	f000 fb2b 	bl	8006144 <TIM_ETR_SetConfig>
      tmpsmcr = htim->Instance->SMCR;
 8005aee:	687b      	ldr	r3, [r7, #4]
 8005af0:	681b      	ldr	r3, [r3, #0]
 8005af2:	689b      	ldr	r3, [r3, #8]
 8005af4:	60fb      	str	r3, [r7, #12]
      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
 8005af6:	68fb      	ldr	r3, [r7, #12]
 8005af8:	f043 0377 	orr.w	r3, r3, #119	; 0x77
 8005afc:	60fb      	str	r3, [r7, #12]
      htim->Instance->SMCR = tmpsmcr;
 8005afe:	687b      	ldr	r3, [r7, #4]
 8005b00:	681b      	ldr	r3, [r3, #0]
 8005b02:	68fa      	ldr	r2, [r7, #12]
 8005b04:	609a      	str	r2, [r3, #8]
      break;
 8005b06:	e04e      	b.n	8005ba6 <HAL_TIM_ConfigClockSource+0x16e>
      TIM_ETR_SetConfig(htim->Instance,
 8005b08:	687b      	ldr	r3, [r7, #4]
 8005b0a:	6818      	ldr	r0, [r3, #0]
 8005b0c:	683b      	ldr	r3, [r7, #0]
 8005b0e:	6899      	ldr	r1, [r3, #8]
 8005b10:	683b      	ldr	r3, [r7, #0]
 8005b12:	685a      	ldr	r2, [r3, #4]
 8005b14:	683b      	ldr	r3, [r7, #0]
 8005b16:	68db      	ldr	r3, [r3, #12]
 8005b18:	f000 fb14 	bl	8006144 <TIM_ETR_SetConfig>
      htim->Instance->SMCR |= TIM_SMCR_ECE;
 8005b1c:	687b      	ldr	r3, [r7, #4]
 8005b1e:	681b      	ldr	r3, [r3, #0]
 8005b20:	689a      	ldr	r2, [r3, #8]
 8005b22:	687b      	ldr	r3, [r7, #4]
 8005b24:	681b      	ldr	r3, [r3, #0]
 8005b26:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 8005b2a:	609a      	str	r2, [r3, #8]
      break;
 8005b2c:	e03b      	b.n	8005ba6 <HAL_TIM_ConfigClockSource+0x16e>
      TIM_TI1_ConfigInputStage(htim->Instance,
 8005b2e:	687b      	ldr	r3, [r7, #4]
 8005b30:	6818      	ldr	r0, [r3, #0]
 8005b32:	683b      	ldr	r3, [r7, #0]
 8005b34:	6859      	ldr	r1, [r3, #4]
 8005b36:	683b      	ldr	r3, [r7, #0]
 8005b38:	68db      	ldr	r3, [r3, #12]
 8005b3a:	461a      	mov	r2, r3
 8005b3c:	f000 fa8b 	bl	8006056 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
 8005b40:	687b      	ldr	r3, [r7, #4]
 8005b42:	681b      	ldr	r3, [r3, #0]
 8005b44:	2150      	movs	r1, #80	; 0x50
 8005b46:	4618      	mov	r0, r3
 8005b48:	f000 fae2 	bl	8006110 <TIM_ITRx_SetConfig>
      break;
 8005b4c:	e02b      	b.n	8005ba6 <HAL_TIM_ConfigClockSource+0x16e>
      TIM_TI2_ConfigInputStage(htim->Instance,
 8005b4e:	687b      	ldr	r3, [r7, #4]
 8005b50:	6818      	ldr	r0, [r3, #0]
 8005b52:	683b      	ldr	r3, [r7, #0]
 8005b54:	6859      	ldr	r1, [r3, #4]
 8005b56:	683b      	ldr	r3, [r7, #0]
 8005b58:	68db      	ldr	r3, [r3, #12]
 8005b5a:	461a      	mov	r2, r3
 8005b5c:	f000 faa9 	bl	80060b2 <TIM_TI2_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
 8005b60:	687b      	ldr	r3, [r7, #4]
 8005b62:	681b      	ldr	r3, [r3, #0]
 8005b64:	2160      	movs	r1, #96	; 0x60
 8005b66:	4618      	mov	r0, r3
 8005b68:	f000 fad2 	bl	8006110 <TIM_ITRx_SetConfig>
      break;
 8005b6c:	e01b      	b.n	8005ba6 <HAL_TIM_ConfigClockSource+0x16e>
      TIM_TI1_ConfigInputStage(htim->Instance,
 8005b6e:	687b      	ldr	r3, [r7, #4]
 8005b70:	6818      	ldr	r0, [r3, #0]
 8005b72:	683b      	ldr	r3, [r7, #0]
 8005b74:	6859      	ldr	r1, [r3, #4]
 8005b76:	683b      	ldr	r3, [r7, #0]
 8005b78:	68db      	ldr	r3, [r3, #12]
 8005b7a:	461a      	mov	r2, r3
 8005b7c:	f000 fa6b 	bl	8006056 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
 8005b80:	687b      	ldr	r3, [r7, #4]
 8005b82:	681b      	ldr	r3, [r3, #0]
 8005b84:	2140      	movs	r1, #64	; 0x40
 8005b86:	4618      	mov	r0, r3
 8005b88:	f000 fac2 	bl	8006110 <TIM_ITRx_SetConfig>
      break;
 8005b8c:	e00b      	b.n	8005ba6 <HAL_TIM_ConfigClockSource+0x16e>
        TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
 8005b8e:	687b      	ldr	r3, [r7, #4]
 8005b90:	681a      	ldr	r2, [r3, #0]
 8005b92:	683b      	ldr	r3, [r7, #0]
 8005b94:	681b      	ldr	r3, [r3, #0]
 8005b96:	4619      	mov	r1, r3
 8005b98:	4610      	mov	r0, r2
 8005b9a:	f000 fab9 	bl	8006110 <TIM_ITRx_SetConfig>
        break;
 8005b9e:	e002      	b.n	8005ba6 <HAL_TIM_ConfigClockSource+0x16e>
      break;
 8005ba0:	bf00      	nop
 8005ba2:	e000      	b.n	8005ba6 <HAL_TIM_ConfigClockSource+0x16e>
      break;
 8005ba4:	bf00      	nop
  }
  htim->State = HAL_TIM_STATE_READY;
 8005ba6:	687b      	ldr	r3, [r7, #4]
 8005ba8:	2201      	movs	r2, #1
 8005baa:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  __HAL_UNLOCK(htim);
 8005bae:	687b      	ldr	r3, [r7, #4]
 8005bb0:	2200      	movs	r2, #0
 8005bb2:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

  return HAL_OK;
 8005bb6:	2300      	movs	r3, #0
}
 8005bb8:	4618      	mov	r0, r3
 8005bba:	3710      	adds	r7, #16
 8005bbc:	46bd      	mov	sp, r7
 8005bbe:	bd80      	pop	{r7, pc}

08005bc0 <HAL_TIM_SlaveConfigSynchro>:
  *         timer input or external trigger input) and the Slave mode
  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
 8005bc0:	b580      	push	{r7, lr}
 8005bc2:	b082      	sub	sp, #8
 8005bc4:	af00      	add	r7, sp, #0
 8005bc6:	6078      	str	r0, [r7, #4]
 8005bc8:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));

  __HAL_LOCK(htim);
 8005bca:	687b      	ldr	r3, [r7, #4]
 8005bcc:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 8005bd0:	2b01      	cmp	r3, #1
 8005bd2:	d101      	bne.n	8005bd8 <HAL_TIM_SlaveConfigSynchro+0x18>
 8005bd4:	2302      	movs	r3, #2
 8005bd6:	e031      	b.n	8005c3c <HAL_TIM_SlaveConfigSynchro+0x7c>
 8005bd8:	687b      	ldr	r3, [r7, #4]
 8005bda:	2201      	movs	r2, #1
 8005bdc:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

  htim->State = HAL_TIM_STATE_BUSY;
 8005be0:	687b      	ldr	r3, [r7, #4]
 8005be2:	2202      	movs	r2, #2
 8005be4:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
 8005be8:	6839      	ldr	r1, [r7, #0]
 8005bea:	6878      	ldr	r0, [r7, #4]
 8005bec:	f000 f9a5 	bl	8005f3a <TIM_SlaveTimer_SetConfig>
 8005bf0:	4603      	mov	r3, r0
 8005bf2:	2b00      	cmp	r3, #0
 8005bf4:	d009      	beq.n	8005c0a <HAL_TIM_SlaveConfigSynchro+0x4a>
  {
    htim->State = HAL_TIM_STATE_READY;
 8005bf6:	687b      	ldr	r3, [r7, #4]
 8005bf8:	2201      	movs	r2, #1
 8005bfa:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
    __HAL_UNLOCK(htim);
 8005bfe:	687b      	ldr	r3, [r7, #4]
 8005c00:	2200      	movs	r2, #0
 8005c02:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38
    return HAL_ERROR;
 8005c06:	2301      	movs	r3, #1
 8005c08:	e018      	b.n	8005c3c <HAL_TIM_SlaveConfigSynchro+0x7c>
  }

  /* Disable Trigger Interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
 8005c0a:	687b      	ldr	r3, [r7, #4]
 8005c0c:	681b      	ldr	r3, [r3, #0]
 8005c0e:	68da      	ldr	r2, [r3, #12]
 8005c10:	687b      	ldr	r3, [r7, #4]
 8005c12:	681b      	ldr	r3, [r3, #0]
 8005c14:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8005c18:	60da      	str	r2, [r3, #12]

  /* Disable Trigger DMA request */
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
 8005c1a:	687b      	ldr	r3, [r7, #4]
 8005c1c:	681b      	ldr	r3, [r3, #0]
 8005c1e:	68da      	ldr	r2, [r3, #12]
 8005c20:	687b      	ldr	r3, [r7, #4]
 8005c22:	681b      	ldr	r3, [r3, #0]
 8005c24:	f422 4280 	bic.w	r2, r2, #16384	; 0x4000
 8005c28:	60da      	str	r2, [r3, #12]

  htim->State = HAL_TIM_STATE_READY;
 8005c2a:	687b      	ldr	r3, [r7, #4]
 8005c2c:	2201      	movs	r2, #1
 8005c2e:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  __HAL_UNLOCK(htim);
 8005c32:	687b      	ldr	r3, [r7, #4]
 8005c34:	2200      	movs	r2, #0
 8005c36:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

  return HAL_OK;
 8005c3a:	2300      	movs	r3, #0
}
 8005c3c:	4618      	mov	r0, r3
 8005c3e:	3708      	adds	r7, #8
 8005c40:	46bd      	mov	sp, r7
 8005c42:	bd80      	pop	{r7, pc}

08005c44 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 8005c44:	b480      	push	{r7}
 8005c46:	b083      	sub	sp, #12
 8005c48:	af00      	add	r7, sp, #0
 8005c4a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 8005c4c:	bf00      	nop
 8005c4e:	370c      	adds	r7, #12
 8005c50:	46bd      	mov	sp, r7
 8005c52:	bc80      	pop	{r7}
 8005c54:	4770      	bx	lr

08005c56 <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 8005c56:	b480      	push	{r7}
 8005c58:	b083      	sub	sp, #12
 8005c5a:	af00      	add	r7, sp, #0
 8005c5c:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 8005c5e:	bf00      	nop
 8005c60:	370c      	adds	r7, #12
 8005c62:	46bd      	mov	sp, r7
 8005c64:	bc80      	pop	{r7}
 8005c66:	4770      	bx	lr

08005c68 <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 8005c68:	b480      	push	{r7}
 8005c6a:	b083      	sub	sp, #12
 8005c6c:	af00      	add	r7, sp, #0
 8005c6e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 8005c70:	bf00      	nop
 8005c72:	370c      	adds	r7, #12
 8005c74:	46bd      	mov	sp, r7
 8005c76:	bc80      	pop	{r7}
 8005c78:	4770      	bx	lr

08005c7a <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 8005c7a:	b480      	push	{r7}
 8005c7c:	b083      	sub	sp, #12
 8005c7e:	af00      	add	r7, sp, #0
 8005c80:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 8005c82:	bf00      	nop
 8005c84:	370c      	adds	r7, #12
 8005c86:	46bd      	mov	sp, r7
 8005c88:	bc80      	pop	{r7}
 8005c8a:	4770      	bx	lr

08005c8c <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
 8005c8c:	b480      	push	{r7}
 8005c8e:	b085      	sub	sp, #20
 8005c90:	af00      	add	r7, sp, #0
 8005c92:	6078      	str	r0, [r7, #4]
 8005c94:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 8005c96:	687b      	ldr	r3, [r7, #4]
 8005c98:	681b      	ldr	r3, [r3, #0]
 8005c9a:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8005c9c:	687b      	ldr	r3, [r7, #4]
 8005c9e:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8005ca2:	d007      	beq.n	8005cb4 <TIM_Base_SetConfig+0x28>
 8005ca4:	687b      	ldr	r3, [r7, #4]
 8005ca6:	4a25      	ldr	r2, [pc, #148]	; (8005d3c <TIM_Base_SetConfig+0xb0>)
 8005ca8:	4293      	cmp	r3, r2
 8005caa:	d003      	beq.n	8005cb4 <TIM_Base_SetConfig+0x28>
 8005cac:	687b      	ldr	r3, [r7, #4]
 8005cae:	4a24      	ldr	r2, [pc, #144]	; (8005d40 <TIM_Base_SetConfig+0xb4>)
 8005cb0:	4293      	cmp	r3, r2
 8005cb2:	d108      	bne.n	8005cc6 <TIM_Base_SetConfig+0x3a>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8005cb4:	68fb      	ldr	r3, [r7, #12]
 8005cb6:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8005cba:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 8005cbc:	683b      	ldr	r3, [r7, #0]
 8005cbe:	685b      	ldr	r3, [r3, #4]
 8005cc0:	68fa      	ldr	r2, [r7, #12]
 8005cc2:	4313      	orrs	r3, r2
 8005cc4:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8005cc6:	687b      	ldr	r3, [r7, #4]
 8005cc8:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8005ccc:	d013      	beq.n	8005cf6 <TIM_Base_SetConfig+0x6a>
 8005cce:	687b      	ldr	r3, [r7, #4]
 8005cd0:	4a1a      	ldr	r2, [pc, #104]	; (8005d3c <TIM_Base_SetConfig+0xb0>)
 8005cd2:	4293      	cmp	r3, r2
 8005cd4:	d00f      	beq.n	8005cf6 <TIM_Base_SetConfig+0x6a>
 8005cd6:	687b      	ldr	r3, [r7, #4]
 8005cd8:	4a19      	ldr	r2, [pc, #100]	; (8005d40 <TIM_Base_SetConfig+0xb4>)
 8005cda:	4293      	cmp	r3, r2
 8005cdc:	d00b      	beq.n	8005cf6 <TIM_Base_SetConfig+0x6a>
 8005cde:	687b      	ldr	r3, [r7, #4]
 8005ce0:	4a18      	ldr	r2, [pc, #96]	; (8005d44 <TIM_Base_SetConfig+0xb8>)
 8005ce2:	4293      	cmp	r3, r2
 8005ce4:	d007      	beq.n	8005cf6 <TIM_Base_SetConfig+0x6a>
 8005ce6:	687b      	ldr	r3, [r7, #4]
 8005ce8:	4a17      	ldr	r2, [pc, #92]	; (8005d48 <TIM_Base_SetConfig+0xbc>)
 8005cea:	4293      	cmp	r3, r2
 8005cec:	d003      	beq.n	8005cf6 <TIM_Base_SetConfig+0x6a>
 8005cee:	687b      	ldr	r3, [r7, #4]
 8005cf0:	4a16      	ldr	r2, [pc, #88]	; (8005d4c <TIM_Base_SetConfig+0xc0>)
 8005cf2:	4293      	cmp	r3, r2
 8005cf4:	d108      	bne.n	8005d08 <TIM_Base_SetConfig+0x7c>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 8005cf6:	68fb      	ldr	r3, [r7, #12]
 8005cf8:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8005cfc:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8005cfe:	683b      	ldr	r3, [r7, #0]
 8005d00:	68db      	ldr	r3, [r3, #12]
 8005d02:	68fa      	ldr	r2, [r7, #12]
 8005d04:	4313      	orrs	r3, r2
 8005d06:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8005d08:	68fb      	ldr	r3, [r7, #12]
 8005d0a:	f023 0280 	bic.w	r2, r3, #128	; 0x80
 8005d0e:	683b      	ldr	r3, [r7, #0]
 8005d10:	691b      	ldr	r3, [r3, #16]
 8005d12:	4313      	orrs	r3, r2
 8005d14:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 8005d16:	687b      	ldr	r3, [r7, #4]
 8005d18:	68fa      	ldr	r2, [r7, #12]
 8005d1a:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8005d1c:	683b      	ldr	r3, [r7, #0]
 8005d1e:	689a      	ldr	r2, [r3, #8]
 8005d20:	687b      	ldr	r3, [r7, #4]
 8005d22:	62da      	str	r2, [r3, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 8005d24:	683b      	ldr	r3, [r7, #0]
 8005d26:	681a      	ldr	r2, [r3, #0]
 8005d28:	687b      	ldr	r3, [r7, #4]
 8005d2a:	629a      	str	r2, [r3, #40]	; 0x28

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 8005d2c:	687b      	ldr	r3, [r7, #4]
 8005d2e:	2201      	movs	r2, #1
 8005d30:	615a      	str	r2, [r3, #20]
}
 8005d32:	bf00      	nop
 8005d34:	3714      	adds	r7, #20
 8005d36:	46bd      	mov	sp, r7
 8005d38:	bc80      	pop	{r7}
 8005d3a:	4770      	bx	lr
 8005d3c:	40000400 	.word	0x40000400
 8005d40:	40000800 	.word	0x40000800
 8005d44:	40010800 	.word	0x40010800
 8005d48:	40010c00 	.word	0x40010c00
 8005d4c:	40011000 	.word	0x40011000

08005d50 <TIM_OC1_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
 8005d50:	b480      	push	{r7}
 8005d52:	b087      	sub	sp, #28
 8005d54:	af00      	add	r7, sp, #0
 8005d56:	6078      	str	r0, [r7, #4]
 8005d58:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= ~TIM_CCER_CC1E;
 8005d5a:	687b      	ldr	r3, [r7, #4]
 8005d5c:	6a1b      	ldr	r3, [r3, #32]
 8005d5e:	f023 0201 	bic.w	r2, r3, #1
 8005d62:	687b      	ldr	r3, [r7, #4]
 8005d64:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 8005d66:	687b      	ldr	r3, [r7, #4]
 8005d68:	6a1b      	ldr	r3, [r3, #32]
 8005d6a:	617b      	str	r3, [r7, #20]
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 8005d6c:	687b      	ldr	r3, [r7, #4]
 8005d6e:	685b      	ldr	r3, [r3, #4]
 8005d70:	613b      	str	r3, [r7, #16]

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;
 8005d72:	687b      	ldr	r3, [r7, #4]
 8005d74:	699b      	ldr	r3, [r3, #24]
 8005d76:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~TIM_CCMR1_OC1M;
 8005d78:	68fb      	ldr	r3, [r7, #12]
 8005d7a:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8005d7e:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR1_CC1S;
 8005d80:	68fb      	ldr	r3, [r7, #12]
 8005d82:	f023 0303 	bic.w	r3, r3, #3
 8005d86:	60fb      	str	r3, [r7, #12]
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;
 8005d88:	683b      	ldr	r3, [r7, #0]
 8005d8a:	681b      	ldr	r3, [r3, #0]
 8005d8c:	68fa      	ldr	r2, [r7, #12]
 8005d8e:	4313      	orrs	r3, r2
 8005d90:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC1P;
 8005d92:	697b      	ldr	r3, [r7, #20]
 8005d94:	f023 0302 	bic.w	r3, r3, #2
 8005d98:	617b      	str	r3, [r7, #20]
  /* Set the Output Compare Polarity */
  tmpccer |= OC_Config->OCPolarity;
 8005d9a:	683b      	ldr	r3, [r7, #0]
 8005d9c:	689b      	ldr	r3, [r3, #8]
 8005d9e:	697a      	ldr	r2, [r7, #20]
 8005da0:	4313      	orrs	r3, r2
 8005da2:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 8005da4:	687b      	ldr	r3, [r7, #4]
 8005da6:	693a      	ldr	r2, [r7, #16]
 8005da8:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;
 8005daa:	687b      	ldr	r3, [r7, #4]
 8005dac:	68fa      	ldr	r2, [r7, #12]
 8005dae:	619a      	str	r2, [r3, #24]

  /* Set the Capture Compare Register value */
  TIMx->CCR1 = OC_Config->Pulse;
 8005db0:	683b      	ldr	r3, [r7, #0]
 8005db2:	685a      	ldr	r2, [r3, #4]
 8005db4:	687b      	ldr	r3, [r7, #4]
 8005db6:	635a      	str	r2, [r3, #52]	; 0x34

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 8005db8:	687b      	ldr	r3, [r7, #4]
 8005dba:	697a      	ldr	r2, [r7, #20]
 8005dbc:	621a      	str	r2, [r3, #32]
}
 8005dbe:	bf00      	nop
 8005dc0:	371c      	adds	r7, #28
 8005dc2:	46bd      	mov	sp, r7
 8005dc4:	bc80      	pop	{r7}
 8005dc6:	4770      	bx	lr

08005dc8 <TIM_OC2_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
 8005dc8:	b480      	push	{r7}
 8005dca:	b087      	sub	sp, #28
 8005dcc:	af00      	add	r7, sp, #0
 8005dce:	6078      	str	r0, [r7, #4]
 8005dd0:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
 8005dd2:	687b      	ldr	r3, [r7, #4]
 8005dd4:	6a1b      	ldr	r3, [r3, #32]
 8005dd6:	f023 0210 	bic.w	r2, r3, #16
 8005dda:	687b      	ldr	r3, [r7, #4]
 8005ddc:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 8005dde:	687b      	ldr	r3, [r7, #4]
 8005de0:	6a1b      	ldr	r3, [r3, #32]
 8005de2:	617b      	str	r3, [r7, #20]
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 8005de4:	687b      	ldr	r3, [r7, #4]
 8005de6:	685b      	ldr	r3, [r3, #4]
 8005de8:	613b      	str	r3, [r7, #16]

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;
 8005dea:	687b      	ldr	r3, [r7, #4]
 8005dec:	699b      	ldr	r3, [r3, #24]
 8005dee:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR1_OC2M;
 8005df0:	68fb      	ldr	r3, [r7, #12]
 8005df2:	f423 43e0 	bic.w	r3, r3, #28672	; 0x7000
 8005df6:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR1_CC2S;
 8005df8:	68fb      	ldr	r3, [r7, #12]
 8005dfa:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8005dfe:	60fb      	str	r3, [r7, #12]

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);
 8005e00:	683b      	ldr	r3, [r7, #0]
 8005e02:	681b      	ldr	r3, [r3, #0]
 8005e04:	021b      	lsls	r3, r3, #8
 8005e06:	68fa      	ldr	r2, [r7, #12]
 8005e08:	4313      	orrs	r3, r2
 8005e0a:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC2P;
 8005e0c:	697b      	ldr	r3, [r7, #20]
 8005e0e:	f023 0320 	bic.w	r3, r3, #32
 8005e12:	617b      	str	r3, [r7, #20]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 4U);
 8005e14:	683b      	ldr	r3, [r7, #0]
 8005e16:	689b      	ldr	r3, [r3, #8]
 8005e18:	011b      	lsls	r3, r3, #4
 8005e1a:	697a      	ldr	r2, [r7, #20]
 8005e1c:	4313      	orrs	r3, r2
 8005e1e:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 8005e20:	687b      	ldr	r3, [r7, #4]
 8005e22:	693a      	ldr	r2, [r7, #16]
 8005e24:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;
 8005e26:	687b      	ldr	r3, [r7, #4]
 8005e28:	68fa      	ldr	r2, [r7, #12]
 8005e2a:	619a      	str	r2, [r3, #24]

  /* Set the Capture Compare Register value */
  TIMx->CCR2 = OC_Config->Pulse;
 8005e2c:	683b      	ldr	r3, [r7, #0]
 8005e2e:	685a      	ldr	r2, [r3, #4]
 8005e30:	687b      	ldr	r3, [r7, #4]
 8005e32:	639a      	str	r2, [r3, #56]	; 0x38

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 8005e34:	687b      	ldr	r3, [r7, #4]
 8005e36:	697a      	ldr	r2, [r7, #20]
 8005e38:	621a      	str	r2, [r3, #32]
}
 8005e3a:	bf00      	nop
 8005e3c:	371c      	adds	r7, #28
 8005e3e:	46bd      	mov	sp, r7
 8005e40:	bc80      	pop	{r7}
 8005e42:	4770      	bx	lr

08005e44 <TIM_OC3_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
 8005e44:	b480      	push	{r7}
 8005e46:	b087      	sub	sp, #28
 8005e48:	af00      	add	r7, sp, #0
 8005e4a:	6078      	str	r0, [r7, #4]
 8005e4c:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 3: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC3E;
 8005e4e:	687b      	ldr	r3, [r7, #4]
 8005e50:	6a1b      	ldr	r3, [r3, #32]
 8005e52:	f423 7280 	bic.w	r2, r3, #256	; 0x100
 8005e56:	687b      	ldr	r3, [r7, #4]
 8005e58:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 8005e5a:	687b      	ldr	r3, [r7, #4]
 8005e5c:	6a1b      	ldr	r3, [r3, #32]
 8005e5e:	617b      	str	r3, [r7, #20]
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 8005e60:	687b      	ldr	r3, [r7, #4]
 8005e62:	685b      	ldr	r3, [r3, #4]
 8005e64:	613b      	str	r3, [r7, #16]

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;
 8005e66:	687b      	ldr	r3, [r7, #4]
 8005e68:	69db      	ldr	r3, [r3, #28]
 8005e6a:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC3M;
 8005e6c:	68fb      	ldr	r3, [r7, #12]
 8005e6e:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8005e72:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR2_CC3S;
 8005e74:	68fb      	ldr	r3, [r7, #12]
 8005e76:	f023 0303 	bic.w	r3, r3, #3
 8005e7a:	60fb      	str	r3, [r7, #12]
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;
 8005e7c:	683b      	ldr	r3, [r7, #0]
 8005e7e:	681b      	ldr	r3, [r3, #0]
 8005e80:	68fa      	ldr	r2, [r7, #12]
 8005e82:	4313      	orrs	r3, r2
 8005e84:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC3P;
 8005e86:	697b      	ldr	r3, [r7, #20]
 8005e88:	f423 7300 	bic.w	r3, r3, #512	; 0x200
 8005e8c:	617b      	str	r3, [r7, #20]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 8U);
 8005e8e:	683b      	ldr	r3, [r7, #0]
 8005e90:	689b      	ldr	r3, [r3, #8]
 8005e92:	021b      	lsls	r3, r3, #8
 8005e94:	697a      	ldr	r2, [r7, #20]
 8005e96:	4313      	orrs	r3, r2
 8005e98:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 8005e9a:	687b      	ldr	r3, [r7, #4]
 8005e9c:	693a      	ldr	r2, [r7, #16]
 8005e9e:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;
 8005ea0:	687b      	ldr	r3, [r7, #4]
 8005ea2:	68fa      	ldr	r2, [r7, #12]
 8005ea4:	61da      	str	r2, [r3, #28]

  /* Set the Capture Compare Register value */
  TIMx->CCR3 = OC_Config->Pulse;
 8005ea6:	683b      	ldr	r3, [r7, #0]
 8005ea8:	685a      	ldr	r2, [r3, #4]
 8005eaa:	687b      	ldr	r3, [r7, #4]
 8005eac:	63da      	str	r2, [r3, #60]	; 0x3c

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 8005eae:	687b      	ldr	r3, [r7, #4]
 8005eb0:	697a      	ldr	r2, [r7, #20]
 8005eb2:	621a      	str	r2, [r3, #32]
}
 8005eb4:	bf00      	nop
 8005eb6:	371c      	adds	r7, #28
 8005eb8:	46bd      	mov	sp, r7
 8005eba:	bc80      	pop	{r7}
 8005ebc:	4770      	bx	lr

08005ebe <TIM_OC4_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
 8005ebe:	b480      	push	{r7}
 8005ec0:	b087      	sub	sp, #28
 8005ec2:	af00      	add	r7, sp, #0
 8005ec4:	6078      	str	r0, [r7, #4]
 8005ec6:	6039      	str	r1, [r7, #0]
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 4: Reset the CC4E Bit */
  TIMx->CCER &= ~TIM_CCER_CC4E;
 8005ec8:	687b      	ldr	r3, [r7, #4]
 8005eca:	6a1b      	ldr	r3, [r3, #32]
 8005ecc:	f423 5280 	bic.w	r2, r3, #4096	; 0x1000
 8005ed0:	687b      	ldr	r3, [r7, #4]
 8005ed2:	621a      	str	r2, [r3, #32]

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 8005ed4:	687b      	ldr	r3, [r7, #4]
 8005ed6:	6a1b      	ldr	r3, [r3, #32]
 8005ed8:	617b      	str	r3, [r7, #20]
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 8005eda:	687b      	ldr	r3, [r7, #4]
 8005edc:	685b      	ldr	r3, [r3, #4]
 8005ede:	613b      	str	r3, [r7, #16]

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;
 8005ee0:	687b      	ldr	r3, [r7, #4]
 8005ee2:	69db      	ldr	r3, [r3, #28]
 8005ee4:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC4M;
 8005ee6:	68fb      	ldr	r3, [r7, #12]
 8005ee8:	f423 43e0 	bic.w	r3, r3, #28672	; 0x7000
 8005eec:	60fb      	str	r3, [r7, #12]
  tmpccmrx &= ~TIM_CCMR2_CC4S;
 8005eee:	68fb      	ldr	r3, [r7, #12]
 8005ef0:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8005ef4:	60fb      	str	r3, [r7, #12]

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);
 8005ef6:	683b      	ldr	r3, [r7, #0]
 8005ef8:	681b      	ldr	r3, [r3, #0]
 8005efa:	021b      	lsls	r3, r3, #8
 8005efc:	68fa      	ldr	r2, [r7, #12]
 8005efe:	4313      	orrs	r3, r2
 8005f00:	60fb      	str	r3, [r7, #12]

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC4P;
 8005f02:	697b      	ldr	r3, [r7, #20]
 8005f04:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 8005f08:	617b      	str	r3, [r7, #20]
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 12U);
 8005f0a:	683b      	ldr	r3, [r7, #0]
 8005f0c:	689b      	ldr	r3, [r3, #8]
 8005f0e:	031b      	lsls	r3, r3, #12
 8005f10:	697a      	ldr	r2, [r7, #20]
 8005f12:	4313      	orrs	r3, r2
 8005f14:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 8005f16:	687b      	ldr	r3, [r7, #4]
 8005f18:	693a      	ldr	r2, [r7, #16]
 8005f1a:	605a      	str	r2, [r3, #4]

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;
 8005f1c:	687b      	ldr	r3, [r7, #4]
 8005f1e:	68fa      	ldr	r2, [r7, #12]
 8005f20:	61da      	str	r2, [r3, #28]

  /* Set the Capture Compare Register value */
  TIMx->CCR4 = OC_Config->Pulse;
 8005f22:	683b      	ldr	r3, [r7, #0]
 8005f24:	685a      	ldr	r2, [r3, #4]
 8005f26:	687b      	ldr	r3, [r7, #4]
 8005f28:	641a      	str	r2, [r3, #64]	; 0x40

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 8005f2a:	687b      	ldr	r3, [r7, #4]
 8005f2c:	697a      	ldr	r2, [r7, #20]
 8005f2e:	621a      	str	r2, [r3, #32]
}
 8005f30:	bf00      	nop
 8005f32:	371c      	adds	r7, #28
 8005f34:	46bd      	mov	sp, r7
 8005f36:	bc80      	pop	{r7}
 8005f38:	4770      	bx	lr

08005f3a <TIM_SlaveTimer_SetConfig>:
  * @param  sSlaveConfig Slave timer configuration
  * @retval None
  */
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
{
 8005f3a:	b580      	push	{r7, lr}
 8005f3c:	b086      	sub	sp, #24
 8005f3e:	af00      	add	r7, sp, #0
 8005f40:	6078      	str	r0, [r7, #4]
 8005f42:	6039      	str	r1, [r7, #0]
  uint32_t tmpsmcr;
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 8005f44:	687b      	ldr	r3, [r7, #4]
 8005f46:	681b      	ldr	r3, [r3, #0]
 8005f48:	689b      	ldr	r3, [r3, #8]
 8005f4a:	617b      	str	r3, [r7, #20]

  /* Reset the Trigger Selection Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
 8005f4c:	697b      	ldr	r3, [r7, #20]
 8005f4e:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8005f52:	617b      	str	r3, [r7, #20]
  /* Set the Input Trigger source */
  tmpsmcr |= sSlaveConfig->InputTrigger;
 8005f54:	683b      	ldr	r3, [r7, #0]
 8005f56:	685b      	ldr	r3, [r3, #4]
 8005f58:	697a      	ldr	r2, [r7, #20]
 8005f5a:	4313      	orrs	r3, r2
 8005f5c:	617b      	str	r3, [r7, #20]

  /* Reset the slave mode Bits */
  tmpsmcr &= ~TIM_SMCR_SMS;
 8005f5e:	697b      	ldr	r3, [r7, #20]
 8005f60:	f023 0307 	bic.w	r3, r3, #7
 8005f64:	617b      	str	r3, [r7, #20]
  /* Set the slave mode */
  tmpsmcr |= sSlaveConfig->SlaveMode;
 8005f66:	683b      	ldr	r3, [r7, #0]
 8005f68:	681b      	ldr	r3, [r3, #0]
 8005f6a:	697a      	ldr	r2, [r7, #20]
 8005f6c:	4313      	orrs	r3, r2
 8005f6e:	617b      	str	r3, [r7, #20]

  /* Write to TIMx SMCR */
  htim->Instance->SMCR = tmpsmcr;
 8005f70:	687b      	ldr	r3, [r7, #4]
 8005f72:	681b      	ldr	r3, [r3, #0]
 8005f74:	697a      	ldr	r2, [r7, #20]
 8005f76:	609a      	str	r2, [r3, #8]

  /* Configure the trigger prescaler, filter, and polarity */
  switch (sSlaveConfig->InputTrigger)
 8005f78:	683b      	ldr	r3, [r7, #0]
 8005f7a:	685b      	ldr	r3, [r3, #4]
 8005f7c:	2b70      	cmp	r3, #112	; 0x70
 8005f7e:	d01a      	beq.n	8005fb6 <TIM_SlaveTimer_SetConfig+0x7c>
 8005f80:	2b70      	cmp	r3, #112	; 0x70
 8005f82:	d860      	bhi.n	8006046 <TIM_SlaveTimer_SetConfig+0x10c>
 8005f84:	2b60      	cmp	r3, #96	; 0x60
 8005f86:	d054      	beq.n	8006032 <TIM_SlaveTimer_SetConfig+0xf8>
 8005f88:	2b60      	cmp	r3, #96	; 0x60
 8005f8a:	d85c      	bhi.n	8006046 <TIM_SlaveTimer_SetConfig+0x10c>
 8005f8c:	2b50      	cmp	r3, #80	; 0x50
 8005f8e:	d046      	beq.n	800601e <TIM_SlaveTimer_SetConfig+0xe4>
 8005f90:	2b50      	cmp	r3, #80	; 0x50
 8005f92:	d858      	bhi.n	8006046 <TIM_SlaveTimer_SetConfig+0x10c>
 8005f94:	2b40      	cmp	r3, #64	; 0x40
 8005f96:	d019      	beq.n	8005fcc <TIM_SlaveTimer_SetConfig+0x92>
 8005f98:	2b40      	cmp	r3, #64	; 0x40
 8005f9a:	d854      	bhi.n	8006046 <TIM_SlaveTimer_SetConfig+0x10c>
 8005f9c:	2b30      	cmp	r3, #48	; 0x30
 8005f9e:	d054      	beq.n	800604a <TIM_SlaveTimer_SetConfig+0x110>
 8005fa0:	2b30      	cmp	r3, #48	; 0x30
 8005fa2:	d850      	bhi.n	8006046 <TIM_SlaveTimer_SetConfig+0x10c>
 8005fa4:	2b20      	cmp	r3, #32
 8005fa6:	d050      	beq.n	800604a <TIM_SlaveTimer_SetConfig+0x110>
 8005fa8:	2b20      	cmp	r3, #32
 8005faa:	d84c      	bhi.n	8006046 <TIM_SlaveTimer_SetConfig+0x10c>
 8005fac:	2b00      	cmp	r3, #0
 8005fae:	d04c      	beq.n	800604a <TIM_SlaveTimer_SetConfig+0x110>
 8005fb0:	2b10      	cmp	r3, #16
 8005fb2:	d04a      	beq.n	800604a <TIM_SlaveTimer_SetConfig+0x110>
        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
        break;
      }

    default:
      break;
 8005fb4:	e047      	b.n	8006046 <TIM_SlaveTimer_SetConfig+0x10c>
      TIM_ETR_SetConfig(htim->Instance,
 8005fb6:	687b      	ldr	r3, [r7, #4]
 8005fb8:	6818      	ldr	r0, [r3, #0]
 8005fba:	683b      	ldr	r3, [r7, #0]
 8005fbc:	68d9      	ldr	r1, [r3, #12]
 8005fbe:	683b      	ldr	r3, [r7, #0]
 8005fc0:	689a      	ldr	r2, [r3, #8]
 8005fc2:	683b      	ldr	r3, [r7, #0]
 8005fc4:	691b      	ldr	r3, [r3, #16]
 8005fc6:	f000 f8bd 	bl	8006144 <TIM_ETR_SetConfig>
      break;
 8005fca:	e03f      	b.n	800604c <TIM_SlaveTimer_SetConfig+0x112>
      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
 8005fcc:	683b      	ldr	r3, [r7, #0]
 8005fce:	681b      	ldr	r3, [r3, #0]
 8005fd0:	2b05      	cmp	r3, #5
 8005fd2:	d101      	bne.n	8005fd8 <TIM_SlaveTimer_SetConfig+0x9e>
        return HAL_ERROR;
 8005fd4:	2301      	movs	r3, #1
 8005fd6:	e03a      	b.n	800604e <TIM_SlaveTimer_SetConfig+0x114>
      tmpccer = htim->Instance->CCER;
 8005fd8:	687b      	ldr	r3, [r7, #4]
 8005fda:	681b      	ldr	r3, [r3, #0]
 8005fdc:	6a1b      	ldr	r3, [r3, #32]
 8005fde:	613b      	str	r3, [r7, #16]
      htim->Instance->CCER &= ~TIM_CCER_CC1E;
 8005fe0:	687b      	ldr	r3, [r7, #4]
 8005fe2:	681b      	ldr	r3, [r3, #0]
 8005fe4:	6a1a      	ldr	r2, [r3, #32]
 8005fe6:	687b      	ldr	r3, [r7, #4]
 8005fe8:	681b      	ldr	r3, [r3, #0]
 8005fea:	f022 0201 	bic.w	r2, r2, #1
 8005fee:	621a      	str	r2, [r3, #32]
      tmpccmr1 = htim->Instance->CCMR1;
 8005ff0:	687b      	ldr	r3, [r7, #4]
 8005ff2:	681b      	ldr	r3, [r3, #0]
 8005ff4:	699b      	ldr	r3, [r3, #24]
 8005ff6:	60fb      	str	r3, [r7, #12]
      tmpccmr1 &= ~TIM_CCMR1_IC1F;
 8005ff8:	68fb      	ldr	r3, [r7, #12]
 8005ffa:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
 8005ffe:	60fb      	str	r3, [r7, #12]
      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
 8006000:	683b      	ldr	r3, [r7, #0]
 8006002:	691b      	ldr	r3, [r3, #16]
 8006004:	011b      	lsls	r3, r3, #4
 8006006:	68fa      	ldr	r2, [r7, #12]
 8006008:	4313      	orrs	r3, r2
 800600a:	60fb      	str	r3, [r7, #12]
      htim->Instance->CCMR1 = tmpccmr1;
 800600c:	687b      	ldr	r3, [r7, #4]
 800600e:	681b      	ldr	r3, [r3, #0]
 8006010:	68fa      	ldr	r2, [r7, #12]
 8006012:	619a      	str	r2, [r3, #24]
      htim->Instance->CCER = tmpccer;
 8006014:	687b      	ldr	r3, [r7, #4]
 8006016:	681b      	ldr	r3, [r3, #0]
 8006018:	693a      	ldr	r2, [r7, #16]
 800601a:	621a      	str	r2, [r3, #32]
      break;
 800601c:	e016      	b.n	800604c <TIM_SlaveTimer_SetConfig+0x112>
      TIM_TI1_ConfigInputStage(htim->Instance,
 800601e:	687b      	ldr	r3, [r7, #4]
 8006020:	6818      	ldr	r0, [r3, #0]
 8006022:	683b      	ldr	r3, [r7, #0]
 8006024:	6899      	ldr	r1, [r3, #8]
 8006026:	683b      	ldr	r3, [r7, #0]
 8006028:	691b      	ldr	r3, [r3, #16]
 800602a:	461a      	mov	r2, r3
 800602c:	f000 f813 	bl	8006056 <TIM_TI1_ConfigInputStage>
      break;
 8006030:	e00c      	b.n	800604c <TIM_SlaveTimer_SetConfig+0x112>
      TIM_TI2_ConfigInputStage(htim->Instance,
 8006032:	687b      	ldr	r3, [r7, #4]
 8006034:	6818      	ldr	r0, [r3, #0]
 8006036:	683b      	ldr	r3, [r7, #0]
 8006038:	6899      	ldr	r1, [r3, #8]
 800603a:	683b      	ldr	r3, [r7, #0]
 800603c:	691b      	ldr	r3, [r3, #16]
 800603e:	461a      	mov	r2, r3
 8006040:	f000 f837 	bl	80060b2 <TIM_TI2_ConfigInputStage>
      break;
 8006044:	e002      	b.n	800604c <TIM_SlaveTimer_SetConfig+0x112>
      break;
 8006046:	bf00      	nop
 8006048:	e000      	b.n	800604c <TIM_SlaveTimer_SetConfig+0x112>
        break;
 800604a:	bf00      	nop
  }
  return HAL_OK;
 800604c:	2300      	movs	r3, #0
}
 800604e:	4618      	mov	r0, r3
 8006050:	3718      	adds	r7, #24
 8006052:	46bd      	mov	sp, r7
 8006054:	bd80      	pop	{r7, pc}

08006056 <TIM_TI1_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 8006056:	b480      	push	{r7}
 8006058:	b087      	sub	sp, #28
 800605a:	af00      	add	r7, sp, #0
 800605c:	60f8      	str	r0, [r7, #12]
 800605e:	60b9      	str	r1, [r7, #8]
 8006060:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 8006062:	68fb      	ldr	r3, [r7, #12]
 8006064:	6a1b      	ldr	r3, [r3, #32]
 8006066:	617b      	str	r3, [r7, #20]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 8006068:	68fb      	ldr	r3, [r7, #12]
 800606a:	6a1b      	ldr	r3, [r3, #32]
 800606c:	f023 0201 	bic.w	r2, r3, #1
 8006070:	68fb      	ldr	r3, [r7, #12]
 8006072:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 8006074:	68fb      	ldr	r3, [r7, #12]
 8006076:	699b      	ldr	r3, [r3, #24]
 8006078:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 800607a:	693b      	ldr	r3, [r7, #16]
 800607c:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
 8006080:	613b      	str	r3, [r7, #16]
  tmpccmr1 |= (TIM_ICFilter << 4U);
 8006082:	687b      	ldr	r3, [r7, #4]
 8006084:	011b      	lsls	r3, r3, #4
 8006086:	693a      	ldr	r2, [r7, #16]
 8006088:	4313      	orrs	r3, r2
 800608a:	613b      	str	r3, [r7, #16]

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 800608c:	697b      	ldr	r3, [r7, #20]
 800608e:	f023 030a 	bic.w	r3, r3, #10
 8006092:	617b      	str	r3, [r7, #20]
  tmpccer |= TIM_ICPolarity;
 8006094:	697a      	ldr	r2, [r7, #20]
 8006096:	68bb      	ldr	r3, [r7, #8]
 8006098:	4313      	orrs	r3, r2
 800609a:	617b      	str	r3, [r7, #20]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 800609c:	68fb      	ldr	r3, [r7, #12]
 800609e:	693a      	ldr	r2, [r7, #16]
 80060a0:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 80060a2:	68fb      	ldr	r3, [r7, #12]
 80060a4:	697a      	ldr	r2, [r7, #20]
 80060a6:	621a      	str	r2, [r3, #32]
}
 80060a8:	bf00      	nop
 80060aa:	371c      	adds	r7, #28
 80060ac:	46bd      	mov	sp, r7
 80060ae:	bc80      	pop	{r7}
 80060b0:	4770      	bx	lr

080060b2 <TIM_TI2_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 80060b2:	b480      	push	{r7}
 80060b4:	b087      	sub	sp, #28
 80060b6:	af00      	add	r7, sp, #0
 80060b8:	60f8      	str	r0, [r7, #12]
 80060ba:	60b9      	str	r1, [r7, #8]
 80060bc:	607a      	str	r2, [r7, #4]
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
 80060be:	68fb      	ldr	r3, [r7, #12]
 80060c0:	6a1b      	ldr	r3, [r3, #32]
 80060c2:	f023 0210 	bic.w	r2, r3, #16
 80060c6:	68fb      	ldr	r3, [r7, #12]
 80060c8:	621a      	str	r2, [r3, #32]
  tmpccmr1 = TIMx->CCMR1;
 80060ca:	68fb      	ldr	r3, [r7, #12]
 80060cc:	699b      	ldr	r3, [r3, #24]
 80060ce:	617b      	str	r3, [r7, #20]
  tmpccer = TIMx->CCER;
 80060d0:	68fb      	ldr	r3, [r7, #12]
 80060d2:	6a1b      	ldr	r3, [r3, #32]
 80060d4:	613b      	str	r3, [r7, #16]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 80060d6:	697b      	ldr	r3, [r7, #20]
 80060d8:	f423 4370 	bic.w	r3, r3, #61440	; 0xf000
 80060dc:	617b      	str	r3, [r7, #20]
  tmpccmr1 |= (TIM_ICFilter << 12U);
 80060de:	687b      	ldr	r3, [r7, #4]
 80060e0:	031b      	lsls	r3, r3, #12
 80060e2:	697a      	ldr	r2, [r7, #20]
 80060e4:	4313      	orrs	r3, r2
 80060e6:	617b      	str	r3, [r7, #20]

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 80060e8:	693b      	ldr	r3, [r7, #16]
 80060ea:	f023 03a0 	bic.w	r3, r3, #160	; 0xa0
 80060ee:	613b      	str	r3, [r7, #16]
  tmpccer |= (TIM_ICPolarity << 4U);
 80060f0:	68bb      	ldr	r3, [r7, #8]
 80060f2:	011b      	lsls	r3, r3, #4
 80060f4:	693a      	ldr	r2, [r7, #16]
 80060f6:	4313      	orrs	r3, r2
 80060f8:	613b      	str	r3, [r7, #16]

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 80060fa:	68fb      	ldr	r3, [r7, #12]
 80060fc:	697a      	ldr	r2, [r7, #20]
 80060fe:	619a      	str	r2, [r3, #24]
  TIMx->CCER = tmpccer;
 8006100:	68fb      	ldr	r3, [r7, #12]
 8006102:	693a      	ldr	r2, [r7, #16]
 8006104:	621a      	str	r2, [r3, #32]
}
 8006106:	bf00      	nop
 8006108:	371c      	adds	r7, #28
 800610a:	46bd      	mov	sp, r7
 800610c:	bc80      	pop	{r7}
 800610e:	4770      	bx	lr

08006110 <TIM_ITRx_SetConfig>:
  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  *            @arg TIM_TS_ETRF: External Trigger input
  * @retval None
  */
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
 8006110:	b480      	push	{r7}
 8006112:	b085      	sub	sp, #20
 8006114:	af00      	add	r7, sp, #0
 8006116:	6078      	str	r0, [r7, #4]
 8006118:	6039      	str	r1, [r7, #0]
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
 800611a:	687b      	ldr	r3, [r7, #4]
 800611c:	689b      	ldr	r3, [r3, #8]
 800611e:	60fb      	str	r3, [r7, #12]
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
 8006120:	68fb      	ldr	r3, [r7, #12]
 8006122:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8006126:	60fb      	str	r3, [r7, #12]
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
 8006128:	683a      	ldr	r2, [r7, #0]
 800612a:	68fb      	ldr	r3, [r7, #12]
 800612c:	4313      	orrs	r3, r2
 800612e:	f043 0307 	orr.w	r3, r3, #7
 8006132:	60fb      	str	r3, [r7, #12]
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8006134:	687b      	ldr	r3, [r7, #4]
 8006136:	68fa      	ldr	r2, [r7, #12]
 8006138:	609a      	str	r2, [r3, #8]
}
 800613a:	bf00      	nop
 800613c:	3714      	adds	r7, #20
 800613e:	46bd      	mov	sp, r7
 8006140:	bc80      	pop	{r7}
 8006142:	4770      	bx	lr

08006144 <TIM_ETR_SetConfig>:
  *          This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
 8006144:	b480      	push	{r7}
 8006146:	b087      	sub	sp, #28
 8006148:	af00      	add	r7, sp, #0
 800614a:	60f8      	str	r0, [r7, #12]
 800614c:	60b9      	str	r1, [r7, #8]
 800614e:	607a      	str	r2, [r7, #4]
 8006150:	603b      	str	r3, [r7, #0]
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;
 8006152:	68fb      	ldr	r3, [r7, #12]
 8006154:	689b      	ldr	r3, [r3, #8]
 8006156:	617b      	str	r3, [r7, #20]

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 8006158:	697b      	ldr	r3, [r7, #20]
 800615a:	f423 437f 	bic.w	r3, r3, #65280	; 0xff00
 800615e:	617b      	str	r3, [r7, #20]

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
 8006160:	683b      	ldr	r3, [r7, #0]
 8006162:	021a      	lsls	r2, r3, #8
 8006164:	687b      	ldr	r3, [r7, #4]
 8006166:	431a      	orrs	r2, r3
 8006168:	68bb      	ldr	r3, [r7, #8]
 800616a:	4313      	orrs	r3, r2
 800616c:	697a      	ldr	r2, [r7, #20]
 800616e:	4313      	orrs	r3, r2
 8006170:	617b      	str	r3, [r7, #20]

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8006172:	68fb      	ldr	r3, [r7, #12]
 8006174:	697a      	ldr	r2, [r7, #20]
 8006176:	609a      	str	r2, [r3, #8]
}
 8006178:	bf00      	nop
 800617a:	371c      	adds	r7, #28
 800617c:	46bd      	mov	sp, r7
 800617e:	bc80      	pop	{r7}
 8006180:	4770      	bx	lr

08006182 <TIM_CCxChannelCmd>:
  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  * @retval None
  */
static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
 8006182:	b480      	push	{r7}
 8006184:	b087      	sub	sp, #28
 8006186:	af00      	add	r7, sp, #0
 8006188:	60f8      	str	r0, [r7, #12]
 800618a:	60b9      	str	r1, [r7, #8]
 800618c:	607a      	str	r2, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  assert_param(IS_TIM_CHANNELS(Channel));

  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
 800618e:	68bb      	ldr	r3, [r7, #8]
 8006190:	f003 031f 	and.w	r3, r3, #31
 8006194:	2201      	movs	r2, #1
 8006196:	fa02 f303 	lsl.w	r3, r2, r3
 800619a:	617b      	str	r3, [r7, #20]

  /* Reset the CCxE Bit */
  TIMx->CCER &= ~tmp;
 800619c:	68fb      	ldr	r3, [r7, #12]
 800619e:	6a1a      	ldr	r2, [r3, #32]
 80061a0:	697b      	ldr	r3, [r7, #20]
 80061a2:	43db      	mvns	r3, r3
 80061a4:	401a      	ands	r2, r3
 80061a6:	68fb      	ldr	r3, [r7, #12]
 80061a8:	621a      	str	r2, [r3, #32]

  /* Set or reset the CCxE Bit */
  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
 80061aa:	68fb      	ldr	r3, [r7, #12]
 80061ac:	6a1a      	ldr	r2, [r3, #32]
 80061ae:	68bb      	ldr	r3, [r7, #8]
 80061b0:	f003 031f 	and.w	r3, r3, #31
 80061b4:	6879      	ldr	r1, [r7, #4]
 80061b6:	fa01 f303 	lsl.w	r3, r1, r3
 80061ba:	431a      	orrs	r2, r3
 80061bc:	68fb      	ldr	r3, [r7, #12]
 80061be:	621a      	str	r2, [r3, #32]
}
 80061c0:	bf00      	nop
 80061c2:	371c      	adds	r7, #28
 80061c4:	46bd      	mov	sp, r7
 80061c6:	bc80      	pop	{r7}
 80061c8:	4770      	bx	lr
	...

080061cc <HAL_TIMEx_MasterConfigSynchronization>:
  *         mode.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        TIM_MasterConfigTypeDef *sMasterConfig)
{
 80061cc:	b480      	push	{r7}
 80061ce:	b085      	sub	sp, #20
 80061d0:	af00      	add	r7, sp, #0
 80061d2:	6078      	str	r0, [r7, #4]
 80061d4:	6039      	str	r1, [r7, #0]
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 80061d6:	687b      	ldr	r3, [r7, #4]
 80061d8:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 80061dc:	2b01      	cmp	r3, #1
 80061de:	d101      	bne.n	80061e4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
 80061e0:	2302      	movs	r3, #2
 80061e2:	e046      	b.n	8006272 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
 80061e4:	687b      	ldr	r3, [r7, #4]
 80061e6:	2201      	movs	r2, #1
 80061e8:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;
 80061ec:	687b      	ldr	r3, [r7, #4]
 80061ee:	2202      	movs	r2, #2
 80061f0:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 80061f4:	687b      	ldr	r3, [r7, #4]
 80061f6:	681b      	ldr	r3, [r3, #0]
 80061f8:	685b      	ldr	r3, [r3, #4]
 80061fa:	60fb      	str	r3, [r7, #12]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 80061fc:	687b      	ldr	r3, [r7, #4]
 80061fe:	681b      	ldr	r3, [r3, #0]
 8006200:	689b      	ldr	r3, [r3, #8]
 8006202:	60bb      	str	r3, [r7, #8]

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
 8006204:	68fb      	ldr	r3, [r7, #12]
 8006206:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 800620a:	60fb      	str	r3, [r7, #12]
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 800620c:	683b      	ldr	r3, [r7, #0]
 800620e:	681b      	ldr	r3, [r3, #0]
 8006210:	68fa      	ldr	r2, [r7, #12]
 8006212:	4313      	orrs	r3, r2
 8006214:	60fb      	str	r3, [r7, #12]

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 8006216:	687b      	ldr	r3, [r7, #4]
 8006218:	681b      	ldr	r3, [r3, #0]
 800621a:	68fa      	ldr	r2, [r7, #12]
 800621c:	605a      	str	r2, [r3, #4]

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800621e:	687b      	ldr	r3, [r7, #4]
 8006220:	681b      	ldr	r3, [r3, #0]
 8006222:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8006226:	d00e      	beq.n	8006246 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
 8006228:	687b      	ldr	r3, [r7, #4]
 800622a:	681b      	ldr	r3, [r3, #0]
 800622c:	4a13      	ldr	r2, [pc, #76]	; (800627c <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
 800622e:	4293      	cmp	r3, r2
 8006230:	d009      	beq.n	8006246 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
 8006232:	687b      	ldr	r3, [r7, #4]
 8006234:	681b      	ldr	r3, [r3, #0]
 8006236:	4a12      	ldr	r2, [pc, #72]	; (8006280 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
 8006238:	4293      	cmp	r3, r2
 800623a:	d004      	beq.n	8006246 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
 800623c:	687b      	ldr	r3, [r7, #4]
 800623e:	681b      	ldr	r3, [r3, #0]
 8006240:	4a10      	ldr	r2, [pc, #64]	; (8006284 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
 8006242:	4293      	cmp	r3, r2
 8006244:	d10c      	bne.n	8006260 <HAL_TIMEx_MasterConfigSynchronization+0x94>
  {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
 8006246:	68bb      	ldr	r3, [r7, #8]
 8006248:	f023 0380 	bic.w	r3, r3, #128	; 0x80
 800624c:	60bb      	str	r3, [r7, #8]
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 800624e:	683b      	ldr	r3, [r7, #0]
 8006250:	685b      	ldr	r3, [r3, #4]
 8006252:	68ba      	ldr	r2, [r7, #8]
 8006254:	4313      	orrs	r3, r2
 8006256:	60bb      	str	r3, [r7, #8]

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
 8006258:	687b      	ldr	r3, [r7, #4]
 800625a:	681b      	ldr	r3, [r3, #0]
 800625c:	68ba      	ldr	r2, [r7, #8]
 800625e:	609a      	str	r2, [r3, #8]
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 8006260:	687b      	ldr	r3, [r7, #4]
 8006262:	2201      	movs	r2, #1
 8006264:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  __HAL_UNLOCK(htim);
 8006268:	687b      	ldr	r3, [r7, #4]
 800626a:	2200      	movs	r2, #0
 800626c:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

  return HAL_OK;
 8006270:	2300      	movs	r3, #0
}
 8006272:	4618      	mov	r0, r3
 8006274:	3714      	adds	r7, #20
 8006276:	46bd      	mov	sp, r7
 8006278:	bc80      	pop	{r7}
 800627a:	4770      	bx	lr
 800627c:	40000400 	.word	0x40000400
 8006280:	40000800 	.word	0x40000800
 8006284:	40010800 	.word	0x40010800

08006288 <HAL_UART_Init>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8006288:	b580      	push	{r7, lr}
 800628a:	b082      	sub	sp, #8
 800628c:	af00      	add	r7, sp, #0
 800628e:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8006290:	687b      	ldr	r3, [r7, #4]
 8006292:	2b00      	cmp	r3, #0
 8006294:	d101      	bne.n	800629a <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 8006296:	2301      	movs	r3, #1
 8006298:	e03f      	b.n	800631a <HAL_UART_Init+0x92>
    assert_param(IS_UART_INSTANCE(huart->Instance));
  }
  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));

  if (huart->gState == HAL_UART_STATE_RESET)
 800629a:	687b      	ldr	r3, [r7, #4]
 800629c:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 80062a0:	b2db      	uxtb	r3, r3
 80062a2:	2b00      	cmp	r3, #0
 80062a4:	d106      	bne.n	80062b4 <HAL_UART_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 80062a6:	687b      	ldr	r3, [r7, #4]
 80062a8:	2200      	movs	r2, #0
 80062aa:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 80062ae:	6878      	ldr	r0, [r7, #4]
 80062b0:	f7fb febc 	bl	800202c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 80062b4:	687b      	ldr	r3, [r7, #4]
 80062b6:	2224      	movs	r2, #36	; 0x24
 80062b8:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Disable the peripheral */
  __HAL_UART_DISABLE(huart);
 80062bc:	687b      	ldr	r3, [r7, #4]
 80062be:	681b      	ldr	r3, [r3, #0]
 80062c0:	68da      	ldr	r2, [r3, #12]
 80062c2:	687b      	ldr	r3, [r7, #4]
 80062c4:	681b      	ldr	r3, [r3, #0]
 80062c6:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 80062ca:	60da      	str	r2, [r3, #12]

  /* Set the UART Communication parameters */
  UART_SetConfig(huart);
 80062cc:	6878      	ldr	r0, [r7, #4]
 80062ce:	f000 f857 	bl	8006380 <UART_SetConfig>

  /* In asynchronous mode, the following bits must be kept cleared:
     - LINEN and CLKEN bits in the USART_CR2 register,
     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 80062d2:	687b      	ldr	r3, [r7, #4]
 80062d4:	681b      	ldr	r3, [r3, #0]
 80062d6:	691a      	ldr	r2, [r3, #16]
 80062d8:	687b      	ldr	r3, [r7, #4]
 80062da:	681b      	ldr	r3, [r3, #0]
 80062dc:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 80062e0:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 80062e2:	687b      	ldr	r3, [r7, #4]
 80062e4:	681b      	ldr	r3, [r3, #0]
 80062e6:	695a      	ldr	r2, [r3, #20]
 80062e8:	687b      	ldr	r3, [r7, #4]
 80062ea:	681b      	ldr	r3, [r3, #0]
 80062ec:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 80062f0:	615a      	str	r2, [r3, #20]

  /* Enable the peripheral */
  __HAL_UART_ENABLE(huart);
 80062f2:	687b      	ldr	r3, [r7, #4]
 80062f4:	681b      	ldr	r3, [r3, #0]
 80062f6:	68da      	ldr	r2, [r3, #12]
 80062f8:	687b      	ldr	r3, [r7, #4]
 80062fa:	681b      	ldr	r3, [r3, #0]
 80062fc:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8006300:	60da      	str	r2, [r3, #12]

  /* Initialize the UART state */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8006302:	687b      	ldr	r3, [r7, #4]
 8006304:	2200      	movs	r2, #0
 8006306:	641a      	str	r2, [r3, #64]	; 0x40
  huart->gState = HAL_UART_STATE_READY;
 8006308:	687b      	ldr	r3, [r7, #4]
 800630a:	2220      	movs	r2, #32
 800630c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
  huart->RxState = HAL_UART_STATE_READY;
 8006310:	687b      	ldr	r3, [r7, #4]
 8006312:	2220      	movs	r2, #32
 8006314:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  return HAL_OK;
 8006318:	2300      	movs	r3, #0
}
 800631a:	4618      	mov	r0, r3
 800631c:	3708      	adds	r7, #8
 800631e:	46bd      	mov	sp, r7
 8006320:	bd80      	pop	{r7, pc}

08006322 <HAL_UART_DeInit>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
{
 8006322:	b580      	push	{r7, lr}
 8006324:	b082      	sub	sp, #8
 8006326:	af00      	add	r7, sp, #0
 8006328:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 800632a:	687b      	ldr	r3, [r7, #4]
 800632c:	2b00      	cmp	r3, #0
 800632e:	d101      	bne.n	8006334 <HAL_UART_DeInit+0x12>
  {
    return HAL_ERROR;
 8006330:	2301      	movs	r3, #1
 8006332:	e021      	b.n	8006378 <HAL_UART_DeInit+0x56>
  }

  /* Check the parameters */
  assert_param(IS_UART_INSTANCE(huart->Instance));

  huart->gState = HAL_UART_STATE_BUSY;
 8006334:	687b      	ldr	r3, [r7, #4]
 8006336:	2224      	movs	r2, #36	; 0x24
 8006338:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Disable the Peripheral */
  __HAL_UART_DISABLE(huart);
 800633c:	687b      	ldr	r3, [r7, #4]
 800633e:	681b      	ldr	r3, [r3, #0]
 8006340:	68da      	ldr	r2, [r3, #12]
 8006342:	687b      	ldr	r3, [r7, #4]
 8006344:	681b      	ldr	r3, [r3, #0]
 8006346:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 800634a:	60da      	str	r2, [r3, #12]
  }
  /* DeInit the low level hardware */
  huart->MspDeInitCallback(huart);
#else
  /* DeInit the low level hardware */
  HAL_UART_MspDeInit(huart);
 800634c:	6878      	ldr	r0, [r7, #4]
 800634e:	f7fb feb1 	bl	80020b4 <HAL_UART_MspDeInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */

  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8006352:	687b      	ldr	r3, [r7, #4]
 8006354:	2200      	movs	r2, #0
 8006356:	641a      	str	r2, [r3, #64]	; 0x40
  huart->gState = HAL_UART_STATE_RESET;
 8006358:	687b      	ldr	r3, [r7, #4]
 800635a:	2200      	movs	r2, #0
 800635c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
  huart->RxState = HAL_UART_STATE_RESET;
 8006360:	687b      	ldr	r3, [r7, #4]
 8006362:	2200      	movs	r2, #0
 8006364:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8006368:	687b      	ldr	r3, [r7, #4]
 800636a:	2200      	movs	r2, #0
 800636c:	631a      	str	r2, [r3, #48]	; 0x30

  /* Process Unlock */
  __HAL_UNLOCK(huart);
 800636e:	687b      	ldr	r3, [r7, #4]
 8006370:	2200      	movs	r2, #0
 8006372:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

  return HAL_OK;
 8006376:	2300      	movs	r3, #0
}
 8006378:	4618      	mov	r0, r3
 800637a:	3708      	adds	r7, #8
 800637c:	46bd      	mov	sp, r7
 800637e:	bd80      	pop	{r7, pc}

08006380 <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8006380:	b580      	push	{r7, lr}
 8006382:	b084      	sub	sp, #16
 8006384:	af00      	add	r7, sp, #0
 8006386:	6078      	str	r0, [r7, #4]
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8006388:	687b      	ldr	r3, [r7, #4]
 800638a:	681b      	ldr	r3, [r3, #0]
 800638c:	691b      	ldr	r3, [r3, #16]
 800638e:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
 8006392:	687b      	ldr	r3, [r7, #4]
 8006394:	68da      	ldr	r2, [r3, #12]
 8006396:	687b      	ldr	r3, [r7, #4]
 8006398:	681b      	ldr	r3, [r3, #0]
 800639a:	430a      	orrs	r2, r1
 800639c:	611a      	str	r2, [r3, #16]
     Set the M bits according to huart->Init.WordLength value
     Set PCE and PS bits according to huart->Init.Parity value
     Set TE and RE bits according to huart->Init.Mode value
     Set OVER8 bit according to huart->Init.OverSampling value */

  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
 800639e:	687b      	ldr	r3, [r7, #4]
 80063a0:	689a      	ldr	r2, [r3, #8]
 80063a2:	687b      	ldr	r3, [r7, #4]
 80063a4:	691b      	ldr	r3, [r3, #16]
 80063a6:	431a      	orrs	r2, r3
 80063a8:	687b      	ldr	r3, [r7, #4]
 80063aa:	695b      	ldr	r3, [r3, #20]
 80063ac:	431a      	orrs	r2, r3
 80063ae:	687b      	ldr	r3, [r7, #4]
 80063b0:	69db      	ldr	r3, [r3, #28]
 80063b2:	4313      	orrs	r3, r2
 80063b4:	60bb      	str	r3, [r7, #8]
  MODIFY_REG(huart->Instance->CR1,
 80063b6:	687b      	ldr	r3, [r7, #4]
 80063b8:	681b      	ldr	r3, [r3, #0]
 80063ba:	68db      	ldr	r3, [r3, #12]
 80063bc:	f423 4316 	bic.w	r3, r3, #38400	; 0x9600
 80063c0:	f023 030c 	bic.w	r3, r3, #12
 80063c4:	687a      	ldr	r2, [r7, #4]
 80063c6:	6812      	ldr	r2, [r2, #0]
 80063c8:	68b9      	ldr	r1, [r7, #8]
 80063ca:	430b      	orrs	r3, r1
 80063cc:	60d3      	str	r3, [r2, #12]
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
             tmpreg);

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 80063ce:	687b      	ldr	r3, [r7, #4]
 80063d0:	681b      	ldr	r3, [r3, #0]
 80063d2:	695b      	ldr	r3, [r3, #20]
 80063d4:	f423 7140 	bic.w	r1, r3, #768	; 0x300
 80063d8:	687b      	ldr	r3, [r7, #4]
 80063da:	699a      	ldr	r2, [r3, #24]
 80063dc:	687b      	ldr	r3, [r7, #4]
 80063de:	681b      	ldr	r3, [r3, #0]
 80063e0:	430a      	orrs	r2, r1
 80063e2:	615a      	str	r2, [r3, #20]


  if((huart->Instance == USART1))
 80063e4:	687b      	ldr	r3, [r7, #4]
 80063e6:	681b      	ldr	r3, [r3, #0]
 80063e8:	4a55      	ldr	r2, [pc, #340]	; (8006540 <UART_SetConfig+0x1c0>)
 80063ea:	4293      	cmp	r3, r2
 80063ec:	d103      	bne.n	80063f6 <UART_SetConfig+0x76>
  {
    pclk = HAL_RCC_GetPCLK2Freq();
 80063ee:	f7fe feeb 	bl	80051c8 <HAL_RCC_GetPCLK2Freq>
 80063f2:	60f8      	str	r0, [r7, #12]
 80063f4:	e002      	b.n	80063fc <UART_SetConfig+0x7c>
  }
  else
  {
    pclk = HAL_RCC_GetPCLK1Freq();
 80063f6:	f7fe fed3 	bl	80051a0 <HAL_RCC_GetPCLK1Freq>
 80063fa:	60f8      	str	r0, [r7, #12]
  }

  /*-------------------------- USART BRR Configuration ---------------------*/
  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 80063fc:	687b      	ldr	r3, [r7, #4]
 80063fe:	69db      	ldr	r3, [r3, #28]
 8006400:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
 8006404:	d14c      	bne.n	80064a0 <UART_SetConfig+0x120>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 8006406:	68fa      	ldr	r2, [r7, #12]
 8006408:	4613      	mov	r3, r2
 800640a:	009b      	lsls	r3, r3, #2
 800640c:	4413      	add	r3, r2
 800640e:	009a      	lsls	r2, r3, #2
 8006410:	441a      	add	r2, r3
 8006412:	687b      	ldr	r3, [r7, #4]
 8006414:	685b      	ldr	r3, [r3, #4]
 8006416:	005b      	lsls	r3, r3, #1
 8006418:	fbb2 f3f3 	udiv	r3, r2, r3
 800641c:	4a49      	ldr	r2, [pc, #292]	; (8006544 <UART_SetConfig+0x1c4>)
 800641e:	fba2 2303 	umull	r2, r3, r2, r3
 8006422:	095b      	lsrs	r3, r3, #5
 8006424:	0119      	lsls	r1, r3, #4
 8006426:	68fa      	ldr	r2, [r7, #12]
 8006428:	4613      	mov	r3, r2
 800642a:	009b      	lsls	r3, r3, #2
 800642c:	4413      	add	r3, r2
 800642e:	009a      	lsls	r2, r3, #2
 8006430:	441a      	add	r2, r3
 8006432:	687b      	ldr	r3, [r7, #4]
 8006434:	685b      	ldr	r3, [r3, #4]
 8006436:	005b      	lsls	r3, r3, #1
 8006438:	fbb2 f2f3 	udiv	r2, r2, r3
 800643c:	4b41      	ldr	r3, [pc, #260]	; (8006544 <UART_SetConfig+0x1c4>)
 800643e:	fba3 0302 	umull	r0, r3, r3, r2
 8006442:	095b      	lsrs	r3, r3, #5
 8006444:	2064      	movs	r0, #100	; 0x64
 8006446:	fb00 f303 	mul.w	r3, r0, r3
 800644a:	1ad3      	subs	r3, r2, r3
 800644c:	00db      	lsls	r3, r3, #3
 800644e:	3332      	adds	r3, #50	; 0x32
 8006450:	4a3c      	ldr	r2, [pc, #240]	; (8006544 <UART_SetConfig+0x1c4>)
 8006452:	fba2 2303 	umull	r2, r3, r2, r3
 8006456:	095b      	lsrs	r3, r3, #5
 8006458:	005b      	lsls	r3, r3, #1
 800645a:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 800645e:	4419      	add	r1, r3
 8006460:	68fa      	ldr	r2, [r7, #12]
 8006462:	4613      	mov	r3, r2
 8006464:	009b      	lsls	r3, r3, #2
 8006466:	4413      	add	r3, r2
 8006468:	009a      	lsls	r2, r3, #2
 800646a:	441a      	add	r2, r3
 800646c:	687b      	ldr	r3, [r7, #4]
 800646e:	685b      	ldr	r3, [r3, #4]
 8006470:	005b      	lsls	r3, r3, #1
 8006472:	fbb2 f2f3 	udiv	r2, r2, r3
 8006476:	4b33      	ldr	r3, [pc, #204]	; (8006544 <UART_SetConfig+0x1c4>)
 8006478:	fba3 0302 	umull	r0, r3, r3, r2
 800647c:	095b      	lsrs	r3, r3, #5
 800647e:	2064      	movs	r0, #100	; 0x64
 8006480:	fb00 f303 	mul.w	r3, r0, r3
 8006484:	1ad3      	subs	r3, r2, r3
 8006486:	00db      	lsls	r3, r3, #3
 8006488:	3332      	adds	r3, #50	; 0x32
 800648a:	4a2e      	ldr	r2, [pc, #184]	; (8006544 <UART_SetConfig+0x1c4>)
 800648c:	fba2 2303 	umull	r2, r3, r2, r3
 8006490:	095b      	lsrs	r3, r3, #5
 8006492:	f003 0207 	and.w	r2, r3, #7
 8006496:	687b      	ldr	r3, [r7, #4]
 8006498:	681b      	ldr	r3, [r3, #0]
 800649a:	440a      	add	r2, r1
 800649c:	609a      	str	r2, [r3, #8]
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  }
}
 800649e:	e04a      	b.n	8006536 <UART_SetConfig+0x1b6>
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 80064a0:	68fa      	ldr	r2, [r7, #12]
 80064a2:	4613      	mov	r3, r2
 80064a4:	009b      	lsls	r3, r3, #2
 80064a6:	4413      	add	r3, r2
 80064a8:	009a      	lsls	r2, r3, #2
 80064aa:	441a      	add	r2, r3
 80064ac:	687b      	ldr	r3, [r7, #4]
 80064ae:	685b      	ldr	r3, [r3, #4]
 80064b0:	009b      	lsls	r3, r3, #2
 80064b2:	fbb2 f3f3 	udiv	r3, r2, r3
 80064b6:	4a23      	ldr	r2, [pc, #140]	; (8006544 <UART_SetConfig+0x1c4>)
 80064b8:	fba2 2303 	umull	r2, r3, r2, r3
 80064bc:	095b      	lsrs	r3, r3, #5
 80064be:	0119      	lsls	r1, r3, #4
 80064c0:	68fa      	ldr	r2, [r7, #12]
 80064c2:	4613      	mov	r3, r2
 80064c4:	009b      	lsls	r3, r3, #2
 80064c6:	4413      	add	r3, r2
 80064c8:	009a      	lsls	r2, r3, #2
 80064ca:	441a      	add	r2, r3
 80064cc:	687b      	ldr	r3, [r7, #4]
 80064ce:	685b      	ldr	r3, [r3, #4]
 80064d0:	009b      	lsls	r3, r3, #2
 80064d2:	fbb2 f2f3 	udiv	r2, r2, r3
 80064d6:	4b1b      	ldr	r3, [pc, #108]	; (8006544 <UART_SetConfig+0x1c4>)
 80064d8:	fba3 0302 	umull	r0, r3, r3, r2
 80064dc:	095b      	lsrs	r3, r3, #5
 80064de:	2064      	movs	r0, #100	; 0x64
 80064e0:	fb00 f303 	mul.w	r3, r0, r3
 80064e4:	1ad3      	subs	r3, r2, r3
 80064e6:	011b      	lsls	r3, r3, #4
 80064e8:	3332      	adds	r3, #50	; 0x32
 80064ea:	4a16      	ldr	r2, [pc, #88]	; (8006544 <UART_SetConfig+0x1c4>)
 80064ec:	fba2 2303 	umull	r2, r3, r2, r3
 80064f0:	095b      	lsrs	r3, r3, #5
 80064f2:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 80064f6:	4419      	add	r1, r3
 80064f8:	68fa      	ldr	r2, [r7, #12]
 80064fa:	4613      	mov	r3, r2
 80064fc:	009b      	lsls	r3, r3, #2
 80064fe:	4413      	add	r3, r2
 8006500:	009a      	lsls	r2, r3, #2
 8006502:	441a      	add	r2, r3
 8006504:	687b      	ldr	r3, [r7, #4]
 8006506:	685b      	ldr	r3, [r3, #4]
 8006508:	009b      	lsls	r3, r3, #2
 800650a:	fbb2 f2f3 	udiv	r2, r2, r3
 800650e:	4b0d      	ldr	r3, [pc, #52]	; (8006544 <UART_SetConfig+0x1c4>)
 8006510:	fba3 0302 	umull	r0, r3, r3, r2
 8006514:	095b      	lsrs	r3, r3, #5
 8006516:	2064      	movs	r0, #100	; 0x64
 8006518:	fb00 f303 	mul.w	r3, r0, r3
 800651c:	1ad3      	subs	r3, r2, r3
 800651e:	011b      	lsls	r3, r3, #4
 8006520:	3332      	adds	r3, #50	; 0x32
 8006522:	4a08      	ldr	r2, [pc, #32]	; (8006544 <UART_SetConfig+0x1c4>)
 8006524:	fba2 2303 	umull	r2, r3, r2, r3
 8006528:	095b      	lsrs	r3, r3, #5
 800652a:	f003 020f 	and.w	r2, r3, #15
 800652e:	687b      	ldr	r3, [r7, #4]
 8006530:	681b      	ldr	r3, [r3, #0]
 8006532:	440a      	add	r2, r1
 8006534:	609a      	str	r2, [r3, #8]
}
 8006536:	bf00      	nop
 8006538:	3710      	adds	r7, #16
 800653a:	46bd      	mov	sp, r7
 800653c:	bd80      	pop	{r7, pc}
 800653e:	bf00      	nop
 8006540:	40013800 	.word	0x40013800
 8006544:	51eb851f 	.word	0x51eb851f

08006548 <ssd1306_Reset>:
#include <stdlib.h>
#include <string.h>  // For memcpy

#if defined(SSD1306_USE_I2C)

void ssd1306_Reset(void) {
 8006548:	b480      	push	{r7}
 800654a:	af00      	add	r7, sp, #0
    /* for I2C - do nothing */
}
 800654c:	bf00      	nop
 800654e:	46bd      	mov	sp, r7
 8006550:	bc80      	pop	{r7}
 8006552:	4770      	bx	lr

08006554 <ssd1306_WriteCommand>:

// Send a byte to the command register
void ssd1306_WriteCommand(uint8_t byte) {
 8006554:	b580      	push	{r7, lr}
 8006556:	b086      	sub	sp, #24
 8006558:	af04      	add	r7, sp, #16
 800655a:	4603      	mov	r3, r0
 800655c:	71fb      	strb	r3, [r7, #7]
    HAL_I2C_Mem_Write(&SSD1306_I2C_PORT, SSD1306_I2C_ADDR, 0x00, 1, &byte, 1, HAL_MAX_DELAY);
 800655e:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
 8006562:	9302      	str	r3, [sp, #8]
 8006564:	2301      	movs	r3, #1
 8006566:	9301      	str	r3, [sp, #4]
 8006568:	1dfb      	adds	r3, r7, #7
 800656a:	9300      	str	r3, [sp, #0]
 800656c:	2301      	movs	r3, #1
 800656e:	2200      	movs	r2, #0
 8006570:	2178      	movs	r1, #120	; 0x78
 8006572:	4803      	ldr	r0, [pc, #12]	; (8006580 <ssd1306_WriteCommand+0x2c>)
 8006574:	f7fd fd96 	bl	80040a4 <HAL_I2C_Mem_Write>
}
 8006578:	bf00      	nop
 800657a:	3708      	adds	r7, #8
 800657c:	46bd      	mov	sp, r7
 800657e:	bd80      	pop	{r7, pc}
 8006580:	200004ac 	.word	0x200004ac

08006584 <ssd1306_WriteData>:

// Send data
void ssd1306_WriteData(uint8_t* buffer, size_t buff_size) {
 8006584:	b580      	push	{r7, lr}
 8006586:	b086      	sub	sp, #24
 8006588:	af04      	add	r7, sp, #16
 800658a:	6078      	str	r0, [r7, #4]
 800658c:	6039      	str	r1, [r7, #0]
    HAL_I2C_Mem_Write(&SSD1306_I2C_PORT, SSD1306_I2C_ADDR, 0x40, 1, buffer, buff_size, HAL_MAX_DELAY);
 800658e:	683b      	ldr	r3, [r7, #0]
 8006590:	b29b      	uxth	r3, r3
 8006592:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8006596:	9202      	str	r2, [sp, #8]
 8006598:	9301      	str	r3, [sp, #4]
 800659a:	687b      	ldr	r3, [r7, #4]
 800659c:	9300      	str	r3, [sp, #0]
 800659e:	2301      	movs	r3, #1
 80065a0:	2240      	movs	r2, #64	; 0x40
 80065a2:	2178      	movs	r1, #120	; 0x78
 80065a4:	4803      	ldr	r0, [pc, #12]	; (80065b4 <ssd1306_WriteData+0x30>)
 80065a6:	f7fd fd7d 	bl	80040a4 <HAL_I2C_Mem_Write>
}
 80065aa:	bf00      	nop
 80065ac:	3708      	adds	r7, #8
 80065ae:	46bd      	mov	sp, r7
 80065b0:	bd80      	pop	{r7, pc}
 80065b2:	bf00      	nop
 80065b4:	200004ac 	.word	0x200004ac

080065b8 <ssd1306_Init>:
    }
    return ret;
}

// Initialize the oled screen
void ssd1306_Init(void) {
 80065b8:	b580      	push	{r7, lr}
 80065ba:	af00      	add	r7, sp, #0
    // Reset OLED
    ssd1306_Reset();
 80065bc:	f7ff ffc4 	bl	8006548 <ssd1306_Reset>

    // Wait for the screen to boot
    HAL_Delay(100);
 80065c0:	2064      	movs	r0, #100	; 0x64
 80065c2:	f7fb ff4b 	bl	800245c <HAL_Delay>

    // Init OLED
    ssd1306_SetDisplayOn(0); //display off
 80065c6:	2000      	movs	r0, #0
 80065c8:	f000 fa86 	bl	8006ad8 <ssd1306_SetDisplayOn>

    ssd1306_WriteCommand(0x20); //Set Memory Addressing Mode
 80065cc:	2020      	movs	r0, #32
 80065ce:	f7ff ffc1 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x00); // 00b,Horizontal Addressing Mode; 01b,Vertical Addressing Mode;
 80065d2:	2000      	movs	r0, #0
 80065d4:	f7ff ffbe 	bl	8006554 <ssd1306_WriteCommand>
                                // 10b,Page Addressing Mode (RESET); 11b,Invalid

    ssd1306_WriteCommand(0xB0); //Set Page Start Address for Page Addressing Mode,0-7
 80065d8:	20b0      	movs	r0, #176	; 0xb0
 80065da:	f7ff ffbb 	bl	8006554 <ssd1306_WriteCommand>

#ifdef SSD1306_MIRROR_VERT
    ssd1306_WriteCommand(0xC0); // Mirror vertically
#else
    ssd1306_WriteCommand(0xC8); //Set COM Output Scan Direction
 80065de:	20c8      	movs	r0, #200	; 0xc8
 80065e0:	f7ff ffb8 	bl	8006554 <ssd1306_WriteCommand>
#endif

    ssd1306_WriteCommand(0x00); //---set low column address
 80065e4:	2000      	movs	r0, #0
 80065e6:	f7ff ffb5 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x10); //---set high column address
 80065ea:	2010      	movs	r0, #16
 80065ec:	f7ff ffb2 	bl	8006554 <ssd1306_WriteCommand>

    ssd1306_WriteCommand(0x40); //--set start line address - CHECK
 80065f0:	2040      	movs	r0, #64	; 0x40
 80065f2:	f7ff ffaf 	bl	8006554 <ssd1306_WriteCommand>

    ssd1306_SetContrast(0xFF);
 80065f6:	20ff      	movs	r0, #255	; 0xff
 80065f8:	f000 fa5b 	bl	8006ab2 <ssd1306_SetContrast>

#ifdef SSD1306_MIRROR_HORIZ
    ssd1306_WriteCommand(0xA0); // Mirror horizontally
#else
    ssd1306_WriteCommand(0xA1); //--set segment re-map 0 to 127 - CHECK
 80065fc:	20a1      	movs	r0, #161	; 0xa1
 80065fe:	f7ff ffa9 	bl	8006554 <ssd1306_WriteCommand>
#endif

#ifdef SSD1306_INVERSE_COLOR
    ssd1306_WriteCommand(0xA7); //--set inverse color
#else
    ssd1306_WriteCommand(0xA6); //--set normal color
 8006602:	20a6      	movs	r0, #166	; 0xa6
 8006604:	f7ff ffa6 	bl	8006554 <ssd1306_WriteCommand>
// Set multiplex ratio.
#if (SSD1306_HEIGHT == 128)
    // Found in the Luma Python lib for SH1106.
    ssd1306_WriteCommand(0xFF);
#else
    ssd1306_WriteCommand(0xA8); //--set multiplex ratio(1 to 64) - CHECK
 8006608:	20a8      	movs	r0, #168	; 0xa8
 800660a:	f7ff ffa3 	bl	8006554 <ssd1306_WriteCommand>
#endif

#if (SSD1306_HEIGHT == 32)
    ssd1306_WriteCommand(0x1F); //
 800660e:	201f      	movs	r0, #31
 8006610:	f7ff ffa0 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x3F); // Seems to work for 128px high displays too.
#else
#error "Only 32, 64, or 128 lines of height are supported!"
#endif

    ssd1306_WriteCommand(0xA4); //0xa4,Output follows RAM content;0xa5,Output ignores RAM content
 8006614:	20a4      	movs	r0, #164	; 0xa4
 8006616:	f7ff ff9d 	bl	8006554 <ssd1306_WriteCommand>

    ssd1306_WriteCommand(0xD3); //-set display offset - CHECK
 800661a:	20d3      	movs	r0, #211	; 0xd3
 800661c:	f7ff ff9a 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x00); //-not offset
 8006620:	2000      	movs	r0, #0
 8006622:	f7ff ff97 	bl	8006554 <ssd1306_WriteCommand>

    ssd1306_WriteCommand(0xD5); //--set display clock divide ratio/oscillator frequency
 8006626:	20d5      	movs	r0, #213	; 0xd5
 8006628:	f7ff ff94 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0xF0); //--set divide ratio
 800662c:	20f0      	movs	r0, #240	; 0xf0
 800662e:	f7ff ff91 	bl	8006554 <ssd1306_WriteCommand>

    ssd1306_WriteCommand(0xD9); //--set pre-charge period
 8006632:	20d9      	movs	r0, #217	; 0xd9
 8006634:	f7ff ff8e 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x22); //
 8006638:	2022      	movs	r0, #34	; 0x22
 800663a:	f7ff ff8b 	bl	8006554 <ssd1306_WriteCommand>

    ssd1306_WriteCommand(0xDA); //--set com pins hardware configuration - CHECK
 800663e:	20da      	movs	r0, #218	; 0xda
 8006640:	f7ff ff88 	bl	8006554 <ssd1306_WriteCommand>
#if (SSD1306_HEIGHT == 32)
    ssd1306_WriteCommand(0x02);
 8006644:	2002      	movs	r0, #2
 8006646:	f7ff ff85 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x12);
#else
#error "Only 32, 64, or 128 lines of height are supported!"
#endif

    ssd1306_WriteCommand(0xDB); //--set vcomh
 800664a:	20db      	movs	r0, #219	; 0xdb
 800664c:	f7ff ff82 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x20); //0x20,0.77xVcc
 8006650:	2020      	movs	r0, #32
 8006652:	f7ff ff7f 	bl	8006554 <ssd1306_WriteCommand>

    ssd1306_WriteCommand(0x8D); //--set DC-DC enable
 8006656:	208d      	movs	r0, #141	; 0x8d
 8006658:	f7ff ff7c 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(0x14); //
 800665c:	2014      	movs	r0, #20
 800665e:	f7ff ff79 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_SetDisplayOn(1); //--turn on SSD1306 panel
 8006662:	2001      	movs	r0, #1
 8006664:	f000 fa38 	bl	8006ad8 <ssd1306_SetDisplayOn>

    // Clear screen
    ssd1306_Fill(Black);
 8006668:	2000      	movs	r0, #0
 800666a:	f000 f80f 	bl	800668c <ssd1306_Fill>
    
    // Flush buffer to screen
    ssd1306_UpdateScreen();
 800666e:	f000 f82f 	bl	80066d0 <ssd1306_UpdateScreen>
    
    // Set default values for screen object
    SSD1306.CurrentX = 0;
 8006672:	4b05      	ldr	r3, [pc, #20]	; (8006688 <ssd1306_Init+0xd0>)
 8006674:	2200      	movs	r2, #0
 8006676:	801a      	strh	r2, [r3, #0]
    SSD1306.CurrentY = 0;
 8006678:	4b03      	ldr	r3, [pc, #12]	; (8006688 <ssd1306_Init+0xd0>)
 800667a:	2200      	movs	r2, #0
 800667c:	805a      	strh	r2, [r3, #2]
    
    SSD1306.Initialized = 1;
 800667e:	4b02      	ldr	r3, [pc, #8]	; (8006688 <ssd1306_Init+0xd0>)
 8006680:	2201      	movs	r2, #1
 8006682:	715a      	strb	r2, [r3, #5]
}
 8006684:	bf00      	nop
 8006686:	bd80      	pop	{r7, pc}
 8006688:	20000408 	.word	0x20000408

0800668c <ssd1306_Fill>:

// Fill the whole screen with the given color
void ssd1306_Fill(SSD1306_COLOR color) {
 800668c:	b480      	push	{r7}
 800668e:	b085      	sub	sp, #20
 8006690:	af00      	add	r7, sp, #0
 8006692:	4603      	mov	r3, r0
 8006694:	71fb      	strb	r3, [r7, #7]
    /* Set memory */
    uint32_t i;

    for(i = 0; i < sizeof(SSD1306_Buffer); i++) {
 8006696:	2300      	movs	r3, #0
 8006698:	60fb      	str	r3, [r7, #12]
 800669a:	e00d      	b.n	80066b8 <ssd1306_Fill+0x2c>
        SSD1306_Buffer[i] = (color == Black) ? 0x00 : 0xFF;
 800669c:	79fb      	ldrb	r3, [r7, #7]
 800669e:	2b00      	cmp	r3, #0
 80066a0:	d101      	bne.n	80066a6 <ssd1306_Fill+0x1a>
 80066a2:	2100      	movs	r1, #0
 80066a4:	e000      	b.n	80066a8 <ssd1306_Fill+0x1c>
 80066a6:	21ff      	movs	r1, #255	; 0xff
 80066a8:	4a08      	ldr	r2, [pc, #32]	; (80066cc <ssd1306_Fill+0x40>)
 80066aa:	68fb      	ldr	r3, [r7, #12]
 80066ac:	4413      	add	r3, r2
 80066ae:	460a      	mov	r2, r1
 80066b0:	701a      	strb	r2, [r3, #0]
    for(i = 0; i < sizeof(SSD1306_Buffer); i++) {
 80066b2:	68fb      	ldr	r3, [r7, #12]
 80066b4:	3301      	adds	r3, #1
 80066b6:	60fb      	str	r3, [r7, #12]
 80066b8:	68fb      	ldr	r3, [r7, #12]
 80066ba:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 80066be:	d3ed      	bcc.n	800669c <ssd1306_Fill+0x10>
    }
}
 80066c0:	bf00      	nop
 80066c2:	bf00      	nop
 80066c4:	3714      	adds	r7, #20
 80066c6:	46bd      	mov	sp, r7
 80066c8:	bc80      	pop	{r7}
 80066ca:	4770      	bx	lr
 80066cc:	20000208 	.word	0x20000208

080066d0 <ssd1306_UpdateScreen>:

// Write the screenbuffer with changed to the screen
void ssd1306_UpdateScreen(void) {
 80066d0:	b580      	push	{r7, lr}
 80066d2:	b082      	sub	sp, #8
 80066d4:	af00      	add	r7, sp, #0
    // depends on the screen height:
    //
    //  * 32px   ==  4 pages
    //  * 64px   ==  8 pages
    //  * 128px  ==  16 pages
    for(uint8_t i = 0; i < SSD1306_HEIGHT/8; i++) {
 80066d6:	2300      	movs	r3, #0
 80066d8:	71fb      	strb	r3, [r7, #7]
 80066da:	e016      	b.n	800670a <ssd1306_UpdateScreen+0x3a>
        ssd1306_WriteCommand(0xB0 + i); // Set the current RAM page address.
 80066dc:	79fb      	ldrb	r3, [r7, #7]
 80066de:	3b50      	subs	r3, #80	; 0x50
 80066e0:	b2db      	uxtb	r3, r3
 80066e2:	4618      	mov	r0, r3
 80066e4:	f7ff ff36 	bl	8006554 <ssd1306_WriteCommand>
        ssd1306_WriteCommand(0x00);
 80066e8:	2000      	movs	r0, #0
 80066ea:	f7ff ff33 	bl	8006554 <ssd1306_WriteCommand>
        ssd1306_WriteCommand(0x10);
 80066ee:	2010      	movs	r0, #16
 80066f0:	f7ff ff30 	bl	8006554 <ssd1306_WriteCommand>
        ssd1306_WriteData(&SSD1306_Buffer[SSD1306_WIDTH*i],SSD1306_WIDTH);
 80066f4:	79fb      	ldrb	r3, [r7, #7]
 80066f6:	01db      	lsls	r3, r3, #7
 80066f8:	4a08      	ldr	r2, [pc, #32]	; (800671c <ssd1306_UpdateScreen+0x4c>)
 80066fa:	4413      	add	r3, r2
 80066fc:	2180      	movs	r1, #128	; 0x80
 80066fe:	4618      	mov	r0, r3
 8006700:	f7ff ff40 	bl	8006584 <ssd1306_WriteData>
    for(uint8_t i = 0; i < SSD1306_HEIGHT/8; i++) {
 8006704:	79fb      	ldrb	r3, [r7, #7]
 8006706:	3301      	adds	r3, #1
 8006708:	71fb      	strb	r3, [r7, #7]
 800670a:	79fb      	ldrb	r3, [r7, #7]
 800670c:	2b03      	cmp	r3, #3
 800670e:	d9e5      	bls.n	80066dc <ssd1306_UpdateScreen+0xc>
    }
}
 8006710:	bf00      	nop
 8006712:	bf00      	nop
 8006714:	3708      	adds	r7, #8
 8006716:	46bd      	mov	sp, r7
 8006718:	bd80      	pop	{r7, pc}
 800671a:	bf00      	nop
 800671c:	20000208 	.word	0x20000208

08006720 <ssd1306_DrawPixel>:

//    Draw one pixel in the screenbuffer
//    X => X Coordinate
//    Y => Y Coordinate
//    color => Pixel color
void ssd1306_DrawPixel(uint8_t x, uint8_t y, SSD1306_COLOR color) {
 8006720:	b480      	push	{r7}
 8006722:	b083      	sub	sp, #12
 8006724:	af00      	add	r7, sp, #0
 8006726:	4603      	mov	r3, r0
 8006728:	71fb      	strb	r3, [r7, #7]
 800672a:	460b      	mov	r3, r1
 800672c:	71bb      	strb	r3, [r7, #6]
 800672e:	4613      	mov	r3, r2
 8006730:	717b      	strb	r3, [r7, #5]
    if(x >= SSD1306_WIDTH || y >= SSD1306_HEIGHT) {
 8006732:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8006736:	2b00      	cmp	r3, #0
 8006738:	db48      	blt.n	80067cc <ssd1306_DrawPixel+0xac>
 800673a:	79bb      	ldrb	r3, [r7, #6]
 800673c:	2b1f      	cmp	r3, #31
 800673e:	d845      	bhi.n	80067cc <ssd1306_DrawPixel+0xac>
        // Don't write outside the buffer
        return;
    }
    
    // Check if pixel should be inverted
    if(SSD1306.Inverted) {
 8006740:	4b25      	ldr	r3, [pc, #148]	; (80067d8 <ssd1306_DrawPixel+0xb8>)
 8006742:	791b      	ldrb	r3, [r3, #4]
 8006744:	2b00      	cmp	r3, #0
 8006746:	d006      	beq.n	8006756 <ssd1306_DrawPixel+0x36>
        color = (SSD1306_COLOR)!color;
 8006748:	797b      	ldrb	r3, [r7, #5]
 800674a:	2b00      	cmp	r3, #0
 800674c:	bf0c      	ite	eq
 800674e:	2301      	moveq	r3, #1
 8006750:	2300      	movne	r3, #0
 8006752:	b2db      	uxtb	r3, r3
 8006754:	717b      	strb	r3, [r7, #5]
    }
    
    // Draw in the right color
    if(color == White) {
 8006756:	797b      	ldrb	r3, [r7, #5]
 8006758:	2b01      	cmp	r3, #1
 800675a:	d11a      	bne.n	8006792 <ssd1306_DrawPixel+0x72>
        SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] |= 1 << (y % 8);
 800675c:	79fa      	ldrb	r2, [r7, #7]
 800675e:	79bb      	ldrb	r3, [r7, #6]
 8006760:	08db      	lsrs	r3, r3, #3
 8006762:	b2d8      	uxtb	r0, r3
 8006764:	4603      	mov	r3, r0
 8006766:	01db      	lsls	r3, r3, #7
 8006768:	4413      	add	r3, r2
 800676a:	4a1c      	ldr	r2, [pc, #112]	; (80067dc <ssd1306_DrawPixel+0xbc>)
 800676c:	5cd3      	ldrb	r3, [r2, r3]
 800676e:	b25a      	sxtb	r2, r3
 8006770:	79bb      	ldrb	r3, [r7, #6]
 8006772:	f003 0307 	and.w	r3, r3, #7
 8006776:	2101      	movs	r1, #1
 8006778:	fa01 f303 	lsl.w	r3, r1, r3
 800677c:	b25b      	sxtb	r3, r3
 800677e:	4313      	orrs	r3, r2
 8006780:	b259      	sxtb	r1, r3
 8006782:	79fa      	ldrb	r2, [r7, #7]
 8006784:	4603      	mov	r3, r0
 8006786:	01db      	lsls	r3, r3, #7
 8006788:	4413      	add	r3, r2
 800678a:	b2c9      	uxtb	r1, r1
 800678c:	4a13      	ldr	r2, [pc, #76]	; (80067dc <ssd1306_DrawPixel+0xbc>)
 800678e:	54d1      	strb	r1, [r2, r3]
 8006790:	e01d      	b.n	80067ce <ssd1306_DrawPixel+0xae>
    } else { 
        SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] &= ~(1 << (y % 8));
 8006792:	79fa      	ldrb	r2, [r7, #7]
 8006794:	79bb      	ldrb	r3, [r7, #6]
 8006796:	08db      	lsrs	r3, r3, #3
 8006798:	b2d8      	uxtb	r0, r3
 800679a:	4603      	mov	r3, r0
 800679c:	01db      	lsls	r3, r3, #7
 800679e:	4413      	add	r3, r2
 80067a0:	4a0e      	ldr	r2, [pc, #56]	; (80067dc <ssd1306_DrawPixel+0xbc>)
 80067a2:	5cd3      	ldrb	r3, [r2, r3]
 80067a4:	b25a      	sxtb	r2, r3
 80067a6:	79bb      	ldrb	r3, [r7, #6]
 80067a8:	f003 0307 	and.w	r3, r3, #7
 80067ac:	2101      	movs	r1, #1
 80067ae:	fa01 f303 	lsl.w	r3, r1, r3
 80067b2:	b25b      	sxtb	r3, r3
 80067b4:	43db      	mvns	r3, r3
 80067b6:	b25b      	sxtb	r3, r3
 80067b8:	4013      	ands	r3, r2
 80067ba:	b259      	sxtb	r1, r3
 80067bc:	79fa      	ldrb	r2, [r7, #7]
 80067be:	4603      	mov	r3, r0
 80067c0:	01db      	lsls	r3, r3, #7
 80067c2:	4413      	add	r3, r2
 80067c4:	b2c9      	uxtb	r1, r1
 80067c6:	4a05      	ldr	r2, [pc, #20]	; (80067dc <ssd1306_DrawPixel+0xbc>)
 80067c8:	54d1      	strb	r1, [r2, r3]
 80067ca:	e000      	b.n	80067ce <ssd1306_DrawPixel+0xae>
        return;
 80067cc:	bf00      	nop
    }
}
 80067ce:	370c      	adds	r7, #12
 80067d0:	46bd      	mov	sp, r7
 80067d2:	bc80      	pop	{r7}
 80067d4:	4770      	bx	lr
 80067d6:	bf00      	nop
 80067d8:	20000408 	.word	0x20000408
 80067dc:	20000208 	.word	0x20000208

080067e0 <ssd1306_WriteChar>:

// Draw 1 char to the screen buffer
// ch       => char om weg te schrijven
// Font     => Font waarmee we gaan schrijven
// color    => Black or White
char ssd1306_WriteChar(char ch, FontDef Font, SSD1306_COLOR color) {
 80067e0:	b590      	push	{r4, r7, lr}
 80067e2:	b089      	sub	sp, #36	; 0x24
 80067e4:	af00      	add	r7, sp, #0
 80067e6:	4604      	mov	r4, r0
 80067e8:	1d38      	adds	r0, r7, #4
 80067ea:	e880 0006 	stmia.w	r0, {r1, r2}
 80067ee:	461a      	mov	r2, r3
 80067f0:	4623      	mov	r3, r4
 80067f2:	73fb      	strb	r3, [r7, #15]
 80067f4:	4613      	mov	r3, r2
 80067f6:	73bb      	strb	r3, [r7, #14]
    uint32_t i, b, j;
    
    // Check if character is valid
    if (ch < 32 || ch > 126)
 80067f8:	7bfb      	ldrb	r3, [r7, #15]
 80067fa:	2b1f      	cmp	r3, #31
 80067fc:	d902      	bls.n	8006804 <ssd1306_WriteChar+0x24>
 80067fe:	7bfb      	ldrb	r3, [r7, #15]
 8006800:	2b7e      	cmp	r3, #126	; 0x7e
 8006802:	d901      	bls.n	8006808 <ssd1306_WriteChar+0x28>
        return 0;
 8006804:	2300      	movs	r3, #0
 8006806:	e06d      	b.n	80068e4 <ssd1306_WriteChar+0x104>
    
    // Check remaining space on current line
    if (SSD1306_WIDTH < (SSD1306.CurrentX + Font.FontWidth) ||
 8006808:	4b38      	ldr	r3, [pc, #224]	; (80068ec <ssd1306_WriteChar+0x10c>)
 800680a:	881b      	ldrh	r3, [r3, #0]
 800680c:	461a      	mov	r2, r3
 800680e:	793b      	ldrb	r3, [r7, #4]
 8006810:	4413      	add	r3, r2
 8006812:	2b80      	cmp	r3, #128	; 0x80
 8006814:	dc06      	bgt.n	8006824 <ssd1306_WriteChar+0x44>
        SSD1306_HEIGHT < (SSD1306.CurrentY + Font.FontHeight))
 8006816:	4b35      	ldr	r3, [pc, #212]	; (80068ec <ssd1306_WriteChar+0x10c>)
 8006818:	885b      	ldrh	r3, [r3, #2]
 800681a:	461a      	mov	r2, r3
 800681c:	797b      	ldrb	r3, [r7, #5]
 800681e:	4413      	add	r3, r2
    if (SSD1306_WIDTH < (SSD1306.CurrentX + Font.FontWidth) ||
 8006820:	2b20      	cmp	r3, #32
 8006822:	dd01      	ble.n	8006828 <ssd1306_WriteChar+0x48>
    {
        // Not enough space on current line
        return 0;
 8006824:	2300      	movs	r3, #0
 8006826:	e05d      	b.n	80068e4 <ssd1306_WriteChar+0x104>
    }
    
    // Use the font to write
    for(i = 0; i < Font.FontHeight; i++) {
 8006828:	2300      	movs	r3, #0
 800682a:	61fb      	str	r3, [r7, #28]
 800682c:	e04c      	b.n	80068c8 <ssd1306_WriteChar+0xe8>
        b = Font.data[(ch - 32) * Font.FontHeight + i];
 800682e:	68ba      	ldr	r2, [r7, #8]
 8006830:	7bfb      	ldrb	r3, [r7, #15]
 8006832:	3b20      	subs	r3, #32
 8006834:	7979      	ldrb	r1, [r7, #5]
 8006836:	fb01 f303 	mul.w	r3, r1, r3
 800683a:	4619      	mov	r1, r3
 800683c:	69fb      	ldr	r3, [r7, #28]
 800683e:	440b      	add	r3, r1
 8006840:	005b      	lsls	r3, r3, #1
 8006842:	4413      	add	r3, r2
 8006844:	881b      	ldrh	r3, [r3, #0]
 8006846:	617b      	str	r3, [r7, #20]
        for(j = 0; j < Font.FontWidth; j++) {
 8006848:	2300      	movs	r3, #0
 800684a:	61bb      	str	r3, [r7, #24]
 800684c:	e034      	b.n	80068b8 <ssd1306_WriteChar+0xd8>
            if((b << j) & 0x8000)  {
 800684e:	697a      	ldr	r2, [r7, #20]
 8006850:	69bb      	ldr	r3, [r7, #24]
 8006852:	fa02 f303 	lsl.w	r3, r2, r3
 8006856:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
 800685a:	2b00      	cmp	r3, #0
 800685c:	d012      	beq.n	8006884 <ssd1306_WriteChar+0xa4>
                ssd1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR) color);
 800685e:	4b23      	ldr	r3, [pc, #140]	; (80068ec <ssd1306_WriteChar+0x10c>)
 8006860:	881b      	ldrh	r3, [r3, #0]
 8006862:	b2da      	uxtb	r2, r3
 8006864:	69bb      	ldr	r3, [r7, #24]
 8006866:	b2db      	uxtb	r3, r3
 8006868:	4413      	add	r3, r2
 800686a:	b2d8      	uxtb	r0, r3
 800686c:	4b1f      	ldr	r3, [pc, #124]	; (80068ec <ssd1306_WriteChar+0x10c>)
 800686e:	885b      	ldrh	r3, [r3, #2]
 8006870:	b2da      	uxtb	r2, r3
 8006872:	69fb      	ldr	r3, [r7, #28]
 8006874:	b2db      	uxtb	r3, r3
 8006876:	4413      	add	r3, r2
 8006878:	b2db      	uxtb	r3, r3
 800687a:	7bba      	ldrb	r2, [r7, #14]
 800687c:	4619      	mov	r1, r3
 800687e:	f7ff ff4f 	bl	8006720 <ssd1306_DrawPixel>
 8006882:	e016      	b.n	80068b2 <ssd1306_WriteChar+0xd2>
            } else {
                ssd1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR)!color);
 8006884:	4b19      	ldr	r3, [pc, #100]	; (80068ec <ssd1306_WriteChar+0x10c>)
 8006886:	881b      	ldrh	r3, [r3, #0]
 8006888:	b2da      	uxtb	r2, r3
 800688a:	69bb      	ldr	r3, [r7, #24]
 800688c:	b2db      	uxtb	r3, r3
 800688e:	4413      	add	r3, r2
 8006890:	b2d8      	uxtb	r0, r3
 8006892:	4b16      	ldr	r3, [pc, #88]	; (80068ec <ssd1306_WriteChar+0x10c>)
 8006894:	885b      	ldrh	r3, [r3, #2]
 8006896:	b2da      	uxtb	r2, r3
 8006898:	69fb      	ldr	r3, [r7, #28]
 800689a:	b2db      	uxtb	r3, r3
 800689c:	4413      	add	r3, r2
 800689e:	b2d9      	uxtb	r1, r3
 80068a0:	7bbb      	ldrb	r3, [r7, #14]
 80068a2:	2b00      	cmp	r3, #0
 80068a4:	bf0c      	ite	eq
 80068a6:	2301      	moveq	r3, #1
 80068a8:	2300      	movne	r3, #0
 80068aa:	b2db      	uxtb	r3, r3
 80068ac:	461a      	mov	r2, r3
 80068ae:	f7ff ff37 	bl	8006720 <ssd1306_DrawPixel>
        for(j = 0; j < Font.FontWidth; j++) {
 80068b2:	69bb      	ldr	r3, [r7, #24]
 80068b4:	3301      	adds	r3, #1
 80068b6:	61bb      	str	r3, [r7, #24]
 80068b8:	793b      	ldrb	r3, [r7, #4]
 80068ba:	461a      	mov	r2, r3
 80068bc:	69bb      	ldr	r3, [r7, #24]
 80068be:	4293      	cmp	r3, r2
 80068c0:	d3c5      	bcc.n	800684e <ssd1306_WriteChar+0x6e>
    for(i = 0; i < Font.FontHeight; i++) {
 80068c2:	69fb      	ldr	r3, [r7, #28]
 80068c4:	3301      	adds	r3, #1
 80068c6:	61fb      	str	r3, [r7, #28]
 80068c8:	797b      	ldrb	r3, [r7, #5]
 80068ca:	461a      	mov	r2, r3
 80068cc:	69fb      	ldr	r3, [r7, #28]
 80068ce:	4293      	cmp	r3, r2
 80068d0:	d3ad      	bcc.n	800682e <ssd1306_WriteChar+0x4e>
            }
        }
    }
    
    // The current space is now taken
    SSD1306.CurrentX += Font.FontWidth;
 80068d2:	4b06      	ldr	r3, [pc, #24]	; (80068ec <ssd1306_WriteChar+0x10c>)
 80068d4:	881a      	ldrh	r2, [r3, #0]
 80068d6:	793b      	ldrb	r3, [r7, #4]
 80068d8:	b29b      	uxth	r3, r3
 80068da:	4413      	add	r3, r2
 80068dc:	b29a      	uxth	r2, r3
 80068de:	4b03      	ldr	r3, [pc, #12]	; (80068ec <ssd1306_WriteChar+0x10c>)
 80068e0:	801a      	strh	r2, [r3, #0]
    
    // Return written char for validation
    return ch;
 80068e2:	7bfb      	ldrb	r3, [r7, #15]
}
 80068e4:	4618      	mov	r0, r3
 80068e6:	3724      	adds	r7, #36	; 0x24
 80068e8:	46bd      	mov	sp, r7
 80068ea:	bd90      	pop	{r4, r7, pc}
 80068ec:	20000408 	.word	0x20000408

080068f0 <ssd1306_WriteString>:

// Write full string to screenbuffer
char ssd1306_WriteString(char* str, FontDef Font, SSD1306_COLOR color) {
 80068f0:	b580      	push	{r7, lr}
 80068f2:	b084      	sub	sp, #16
 80068f4:	af00      	add	r7, sp, #0
 80068f6:	60f8      	str	r0, [r7, #12]
 80068f8:	1d38      	adds	r0, r7, #4
 80068fa:	e880 0006 	stmia.w	r0, {r1, r2}
 80068fe:	70fb      	strb	r3, [r7, #3]
    // Write until null-byte
    while (*str) {
 8006900:	e012      	b.n	8006928 <ssd1306_WriteString+0x38>
        if (ssd1306_WriteChar(*str, Font, color) != *str) {
 8006902:	68fb      	ldr	r3, [r7, #12]
 8006904:	7818      	ldrb	r0, [r3, #0]
 8006906:	78fb      	ldrb	r3, [r7, #3]
 8006908:	1d3a      	adds	r2, r7, #4
 800690a:	ca06      	ldmia	r2, {r1, r2}
 800690c:	f7ff ff68 	bl	80067e0 <ssd1306_WriteChar>
 8006910:	4603      	mov	r3, r0
 8006912:	461a      	mov	r2, r3
 8006914:	68fb      	ldr	r3, [r7, #12]
 8006916:	781b      	ldrb	r3, [r3, #0]
 8006918:	429a      	cmp	r2, r3
 800691a:	d002      	beq.n	8006922 <ssd1306_WriteString+0x32>
            // Char could not be written
            return *str;
 800691c:	68fb      	ldr	r3, [r7, #12]
 800691e:	781b      	ldrb	r3, [r3, #0]
 8006920:	e008      	b.n	8006934 <ssd1306_WriteString+0x44>
        }
        
        // Next char
        str++;
 8006922:	68fb      	ldr	r3, [r7, #12]
 8006924:	3301      	adds	r3, #1
 8006926:	60fb      	str	r3, [r7, #12]
    while (*str) {
 8006928:	68fb      	ldr	r3, [r7, #12]
 800692a:	781b      	ldrb	r3, [r3, #0]
 800692c:	2b00      	cmp	r3, #0
 800692e:	d1e8      	bne.n	8006902 <ssd1306_WriteString+0x12>
    }
    
    // Everything ok
    return *str;
 8006930:	68fb      	ldr	r3, [r7, #12]
 8006932:	781b      	ldrb	r3, [r3, #0]
}
 8006934:	4618      	mov	r0, r3
 8006936:	3710      	adds	r7, #16
 8006938:	46bd      	mov	sp, r7
 800693a:	bd80      	pop	{r7, pc}

0800693c <ssd1306_SetCursor>:

// Position the cursor
void ssd1306_SetCursor(uint8_t x, uint8_t y) {
 800693c:	b480      	push	{r7}
 800693e:	b083      	sub	sp, #12
 8006940:	af00      	add	r7, sp, #0
 8006942:	4603      	mov	r3, r0
 8006944:	460a      	mov	r2, r1
 8006946:	71fb      	strb	r3, [r7, #7]
 8006948:	4613      	mov	r3, r2
 800694a:	71bb      	strb	r3, [r7, #6]
    SSD1306.CurrentX = x;
 800694c:	79fb      	ldrb	r3, [r7, #7]
 800694e:	b29a      	uxth	r2, r3
 8006950:	4b05      	ldr	r3, [pc, #20]	; (8006968 <ssd1306_SetCursor+0x2c>)
 8006952:	801a      	strh	r2, [r3, #0]
    SSD1306.CurrentY = y;
 8006954:	79bb      	ldrb	r3, [r7, #6]
 8006956:	b29a      	uxth	r2, r3
 8006958:	4b03      	ldr	r3, [pc, #12]	; (8006968 <ssd1306_SetCursor+0x2c>)
 800695a:	805a      	strh	r2, [r3, #2]
}
 800695c:	bf00      	nop
 800695e:	370c      	adds	r7, #12
 8006960:	46bd      	mov	sp, r7
 8006962:	bc80      	pop	{r7}
 8006964:	4770      	bx	lr
 8006966:	bf00      	nop
 8006968:	20000408 	.word	0x20000408

0800696c <ssd1306_Line>:

// Draw line by Bresenhem's algorithm
void ssd1306_Line(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) {
 800696c:	b590      	push	{r4, r7, lr}
 800696e:	b089      	sub	sp, #36	; 0x24
 8006970:	af00      	add	r7, sp, #0
 8006972:	4604      	mov	r4, r0
 8006974:	4608      	mov	r0, r1
 8006976:	4611      	mov	r1, r2
 8006978:	461a      	mov	r2, r3
 800697a:	4623      	mov	r3, r4
 800697c:	71fb      	strb	r3, [r7, #7]
 800697e:	4603      	mov	r3, r0
 8006980:	71bb      	strb	r3, [r7, #6]
 8006982:	460b      	mov	r3, r1
 8006984:	717b      	strb	r3, [r7, #5]
 8006986:	4613      	mov	r3, r2
 8006988:	713b      	strb	r3, [r7, #4]
  int32_t deltaX = abs(x2 - x1);
 800698a:	797a      	ldrb	r2, [r7, #5]
 800698c:	79fb      	ldrb	r3, [r7, #7]
 800698e:	1ad3      	subs	r3, r2, r3
 8006990:	2b00      	cmp	r3, #0
 8006992:	bfb8      	it	lt
 8006994:	425b      	neglt	r3, r3
 8006996:	61bb      	str	r3, [r7, #24]
  int32_t deltaY = abs(y2 - y1);
 8006998:	793a      	ldrb	r2, [r7, #4]
 800699a:	79bb      	ldrb	r3, [r7, #6]
 800699c:	1ad3      	subs	r3, r2, r3
 800699e:	2b00      	cmp	r3, #0
 80069a0:	bfb8      	it	lt
 80069a2:	425b      	neglt	r3, r3
 80069a4:	617b      	str	r3, [r7, #20]
  int32_t signX = ((x1 < x2) ? 1 : -1);
 80069a6:	79fa      	ldrb	r2, [r7, #7]
 80069a8:	797b      	ldrb	r3, [r7, #5]
 80069aa:	429a      	cmp	r2, r3
 80069ac:	d201      	bcs.n	80069b2 <ssd1306_Line+0x46>
 80069ae:	2301      	movs	r3, #1
 80069b0:	e001      	b.n	80069b6 <ssd1306_Line+0x4a>
 80069b2:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
 80069b6:	613b      	str	r3, [r7, #16]
  int32_t signY = ((y1 < y2) ? 1 : -1);
 80069b8:	79ba      	ldrb	r2, [r7, #6]
 80069ba:	793b      	ldrb	r3, [r7, #4]
 80069bc:	429a      	cmp	r2, r3
 80069be:	d201      	bcs.n	80069c4 <ssd1306_Line+0x58>
 80069c0:	2301      	movs	r3, #1
 80069c2:	e001      	b.n	80069c8 <ssd1306_Line+0x5c>
 80069c4:	f04f 33ff 	mov.w	r3, #4294967295	; 0xffffffff
 80069c8:	60fb      	str	r3, [r7, #12]
  int32_t error = deltaX - deltaY;
 80069ca:	69ba      	ldr	r2, [r7, #24]
 80069cc:	697b      	ldr	r3, [r7, #20]
 80069ce:	1ad3      	subs	r3, r2, r3
 80069d0:	61fb      	str	r3, [r7, #28]
  int32_t error2;
    
  ssd1306_DrawPixel(x2, y2, color);
 80069d2:	f897 2030 	ldrb.w	r2, [r7, #48]	; 0x30
 80069d6:	7939      	ldrb	r1, [r7, #4]
 80069d8:	797b      	ldrb	r3, [r7, #5]
 80069da:	4618      	mov	r0, r3
 80069dc:	f7ff fea0 	bl	8006720 <ssd1306_DrawPixel>
    while((x1 != x2) || (y1 != y2))
 80069e0:	e024      	b.n	8006a2c <ssd1306_Line+0xc0>
    {
    ssd1306_DrawPixel(x1, y1, color);
 80069e2:	f897 2030 	ldrb.w	r2, [r7, #48]	; 0x30
 80069e6:	79b9      	ldrb	r1, [r7, #6]
 80069e8:	79fb      	ldrb	r3, [r7, #7]
 80069ea:	4618      	mov	r0, r3
 80069ec:	f7ff fe98 	bl	8006720 <ssd1306_DrawPixel>
    error2 = error * 2;
 80069f0:	69fb      	ldr	r3, [r7, #28]
 80069f2:	005b      	lsls	r3, r3, #1
 80069f4:	60bb      	str	r3, [r7, #8]
    if(error2 > -deltaY)
 80069f6:	697b      	ldr	r3, [r7, #20]
 80069f8:	425b      	negs	r3, r3
 80069fa:	68ba      	ldr	r2, [r7, #8]
 80069fc:	429a      	cmp	r2, r3
 80069fe:	dd08      	ble.n	8006a12 <ssd1306_Line+0xa6>
    {
      error -= deltaY;
 8006a00:	69fa      	ldr	r2, [r7, #28]
 8006a02:	697b      	ldr	r3, [r7, #20]
 8006a04:	1ad3      	subs	r3, r2, r3
 8006a06:	61fb      	str	r3, [r7, #28]
      x1 += signX;
 8006a08:	693b      	ldr	r3, [r7, #16]
 8006a0a:	b2da      	uxtb	r2, r3
 8006a0c:	79fb      	ldrb	r3, [r7, #7]
 8006a0e:	4413      	add	r3, r2
 8006a10:	71fb      	strb	r3, [r7, #7]
    else
    {
    /*nothing to do*/
    }
        
    if(error2 < deltaX)
 8006a12:	68ba      	ldr	r2, [r7, #8]
 8006a14:	69bb      	ldr	r3, [r7, #24]
 8006a16:	429a      	cmp	r2, r3
 8006a18:	da08      	bge.n	8006a2c <ssd1306_Line+0xc0>
    {
      error += deltaX;
 8006a1a:	69fa      	ldr	r2, [r7, #28]
 8006a1c:	69bb      	ldr	r3, [r7, #24]
 8006a1e:	4413      	add	r3, r2
 8006a20:	61fb      	str	r3, [r7, #28]
      y1 += signY;
 8006a22:	68fb      	ldr	r3, [r7, #12]
 8006a24:	b2da      	uxtb	r2, r3
 8006a26:	79bb      	ldrb	r3, [r7, #6]
 8006a28:	4413      	add	r3, r2
 8006a2a:	71bb      	strb	r3, [r7, #6]
    while((x1 != x2) || (y1 != y2))
 8006a2c:	79fa      	ldrb	r2, [r7, #7]
 8006a2e:	797b      	ldrb	r3, [r7, #5]
 8006a30:	429a      	cmp	r2, r3
 8006a32:	d1d6      	bne.n	80069e2 <ssd1306_Line+0x76>
 8006a34:	79ba      	ldrb	r2, [r7, #6]
 8006a36:	793b      	ldrb	r3, [r7, #4]
 8006a38:	429a      	cmp	r2, r3
 8006a3a:	d1d2      	bne.n	80069e2 <ssd1306_Line+0x76>
    else
    {
    /*nothing to do*/
    }
  }
  return;
 8006a3c:	bf00      	nop
}
 8006a3e:	3724      	adds	r7, #36	; 0x24
 8006a40:	46bd      	mov	sp, r7
 8006a42:	bd90      	pop	{r4, r7, pc}

08006a44 <ssd1306_DrawRectangle>:

    return;
}

//Draw rectangle
void ssd1306_DrawRectangle(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) {
 8006a44:	b590      	push	{r4, r7, lr}
 8006a46:	b085      	sub	sp, #20
 8006a48:	af02      	add	r7, sp, #8
 8006a4a:	4604      	mov	r4, r0
 8006a4c:	4608      	mov	r0, r1
 8006a4e:	4611      	mov	r1, r2
 8006a50:	461a      	mov	r2, r3
 8006a52:	4623      	mov	r3, r4
 8006a54:	71fb      	strb	r3, [r7, #7]
 8006a56:	4603      	mov	r3, r0
 8006a58:	71bb      	strb	r3, [r7, #6]
 8006a5a:	460b      	mov	r3, r1
 8006a5c:	717b      	strb	r3, [r7, #5]
 8006a5e:	4613      	mov	r3, r2
 8006a60:	713b      	strb	r3, [r7, #4]
  ssd1306_Line(x1,y1,x2,y1,color);
 8006a62:	79bc      	ldrb	r4, [r7, #6]
 8006a64:	797a      	ldrb	r2, [r7, #5]
 8006a66:	79b9      	ldrb	r1, [r7, #6]
 8006a68:	79f8      	ldrb	r0, [r7, #7]
 8006a6a:	7e3b      	ldrb	r3, [r7, #24]
 8006a6c:	9300      	str	r3, [sp, #0]
 8006a6e:	4623      	mov	r3, r4
 8006a70:	f7ff ff7c 	bl	800696c <ssd1306_Line>
  ssd1306_Line(x2,y1,x2,y2,color);
 8006a74:	793c      	ldrb	r4, [r7, #4]
 8006a76:	797a      	ldrb	r2, [r7, #5]
 8006a78:	79b9      	ldrb	r1, [r7, #6]
 8006a7a:	7978      	ldrb	r0, [r7, #5]
 8006a7c:	7e3b      	ldrb	r3, [r7, #24]
 8006a7e:	9300      	str	r3, [sp, #0]
 8006a80:	4623      	mov	r3, r4
 8006a82:	f7ff ff73 	bl	800696c <ssd1306_Line>
  ssd1306_Line(x2,y2,x1,y2,color);
 8006a86:	793c      	ldrb	r4, [r7, #4]
 8006a88:	79fa      	ldrb	r2, [r7, #7]
 8006a8a:	7939      	ldrb	r1, [r7, #4]
 8006a8c:	7978      	ldrb	r0, [r7, #5]
 8006a8e:	7e3b      	ldrb	r3, [r7, #24]
 8006a90:	9300      	str	r3, [sp, #0]
 8006a92:	4623      	mov	r3, r4
 8006a94:	f7ff ff6a 	bl	800696c <ssd1306_Line>
  ssd1306_Line(x1,y2,x1,y1,color);
 8006a98:	79bc      	ldrb	r4, [r7, #6]
 8006a9a:	79fa      	ldrb	r2, [r7, #7]
 8006a9c:	7939      	ldrb	r1, [r7, #4]
 8006a9e:	79f8      	ldrb	r0, [r7, #7]
 8006aa0:	7e3b      	ldrb	r3, [r7, #24]
 8006aa2:	9300      	str	r3, [sp, #0]
 8006aa4:	4623      	mov	r3, r4
 8006aa6:	f7ff ff61 	bl	800696c <ssd1306_Line>

  return;
 8006aaa:	bf00      	nop
}
 8006aac:	370c      	adds	r7, #12
 8006aae:	46bd      	mov	sp, r7
 8006ab0:	bd90      	pop	{r4, r7, pc}

08006ab2 <ssd1306_SetContrast>:

void ssd1306_SetContrast(const uint8_t value) {
 8006ab2:	b580      	push	{r7, lr}
 8006ab4:	b084      	sub	sp, #16
 8006ab6:	af00      	add	r7, sp, #0
 8006ab8:	4603      	mov	r3, r0
 8006aba:	71fb      	strb	r3, [r7, #7]
    const uint8_t kSetContrastControlRegister = 0x81;
 8006abc:	2381      	movs	r3, #129	; 0x81
 8006abe:	73fb      	strb	r3, [r7, #15]
    ssd1306_WriteCommand(kSetContrastControlRegister);
 8006ac0:	7bfb      	ldrb	r3, [r7, #15]
 8006ac2:	4618      	mov	r0, r3
 8006ac4:	f7ff fd46 	bl	8006554 <ssd1306_WriteCommand>
    ssd1306_WriteCommand(value);
 8006ac8:	79fb      	ldrb	r3, [r7, #7]
 8006aca:	4618      	mov	r0, r3
 8006acc:	f7ff fd42 	bl	8006554 <ssd1306_WriteCommand>
}
 8006ad0:	bf00      	nop
 8006ad2:	3710      	adds	r7, #16
 8006ad4:	46bd      	mov	sp, r7
 8006ad6:	bd80      	pop	{r7, pc}

08006ad8 <ssd1306_SetDisplayOn>:

void ssd1306_SetDisplayOn(const uint8_t on) {
 8006ad8:	b580      	push	{r7, lr}
 8006ada:	b084      	sub	sp, #16
 8006adc:	af00      	add	r7, sp, #0
 8006ade:	4603      	mov	r3, r0
 8006ae0:	71fb      	strb	r3, [r7, #7]
    uint8_t value;
    if (on) {
 8006ae2:	79fb      	ldrb	r3, [r7, #7]
 8006ae4:	2b00      	cmp	r3, #0
 8006ae6:	d005      	beq.n	8006af4 <ssd1306_SetDisplayOn+0x1c>
        value = 0xAF;   // Display on
 8006ae8:	23af      	movs	r3, #175	; 0xaf
 8006aea:	73fb      	strb	r3, [r7, #15]
        SSD1306.DisplayOn = 1;
 8006aec:	4b08      	ldr	r3, [pc, #32]	; (8006b10 <ssd1306_SetDisplayOn+0x38>)
 8006aee:	2201      	movs	r2, #1
 8006af0:	719a      	strb	r2, [r3, #6]
 8006af2:	e004      	b.n	8006afe <ssd1306_SetDisplayOn+0x26>
    } else {
        value = 0xAE;   // Display off
 8006af4:	23ae      	movs	r3, #174	; 0xae
 8006af6:	73fb      	strb	r3, [r7, #15]
        SSD1306.DisplayOn = 0;
 8006af8:	4b05      	ldr	r3, [pc, #20]	; (8006b10 <ssd1306_SetDisplayOn+0x38>)
 8006afa:	2200      	movs	r2, #0
 8006afc:	719a      	strb	r2, [r3, #6]
    }
    ssd1306_WriteCommand(value);
 8006afe:	7bfb      	ldrb	r3, [r7, #15]
 8006b00:	4618      	mov	r0, r3
 8006b02:	f7ff fd27 	bl	8006554 <ssd1306_WriteCommand>
}
 8006b06:	bf00      	nop
 8006b08:	3710      	adds	r7, #16
 8006b0a:	46bd      	mov	sp, r7
 8006b0c:	bd80      	pop	{r7, pc}
 8006b0e:	bf00      	nop
 8006b10:	20000408 	.word	0x20000408

08006b14 <__errno>:
 8006b14:	4b01      	ldr	r3, [pc, #4]	; (8006b1c <__errno+0x8>)
 8006b16:	6818      	ldr	r0, [r3, #0]
 8006b18:	4770      	bx	lr
 8006b1a:	bf00      	nop
 8006b1c:	20000014 	.word	0x20000014

08006b20 <__libc_init_array>:
 8006b20:	b570      	push	{r4, r5, r6, lr}
 8006b22:	2600      	movs	r6, #0
 8006b24:	4d0c      	ldr	r5, [pc, #48]	; (8006b58 <__libc_init_array+0x38>)
 8006b26:	4c0d      	ldr	r4, [pc, #52]	; (8006b5c <__libc_init_array+0x3c>)
 8006b28:	1b64      	subs	r4, r4, r5
 8006b2a:	10a4      	asrs	r4, r4, #2
 8006b2c:	42a6      	cmp	r6, r4
 8006b2e:	d109      	bne.n	8006b44 <__libc_init_array+0x24>
 8006b30:	f002 febc 	bl	80098ac <_init>
 8006b34:	2600      	movs	r6, #0
 8006b36:	4d0a      	ldr	r5, [pc, #40]	; (8006b60 <__libc_init_array+0x40>)
 8006b38:	4c0a      	ldr	r4, [pc, #40]	; (8006b64 <__libc_init_array+0x44>)
 8006b3a:	1b64      	subs	r4, r4, r5
 8006b3c:	10a4      	asrs	r4, r4, #2
 8006b3e:	42a6      	cmp	r6, r4
 8006b40:	d105      	bne.n	8006b4e <__libc_init_array+0x2e>
 8006b42:	bd70      	pop	{r4, r5, r6, pc}
 8006b44:	f855 3b04 	ldr.w	r3, [r5], #4
 8006b48:	4798      	blx	r3
 8006b4a:	3601      	adds	r6, #1
 8006b4c:	e7ee      	b.n	8006b2c <__libc_init_array+0xc>
 8006b4e:	f855 3b04 	ldr.w	r3, [r5], #4
 8006b52:	4798      	blx	r3
 8006b54:	3601      	adds	r6, #1
 8006b56:	e7f2      	b.n	8006b3e <__libc_init_array+0x1e>
 8006b58:	0800aa3c 	.word	0x0800aa3c
 8006b5c:	0800aa3c 	.word	0x0800aa3c
 8006b60:	0800aa3c 	.word	0x0800aa3c
 8006b64:	0800aa40 	.word	0x0800aa40

08006b68 <memcpy>:
 8006b68:	440a      	add	r2, r1
 8006b6a:	4291      	cmp	r1, r2
 8006b6c:	f100 33ff 	add.w	r3, r0, #4294967295	; 0xffffffff
 8006b70:	d100      	bne.n	8006b74 <memcpy+0xc>
 8006b72:	4770      	bx	lr
 8006b74:	b510      	push	{r4, lr}
 8006b76:	f811 4b01 	ldrb.w	r4, [r1], #1
 8006b7a:	4291      	cmp	r1, r2
 8006b7c:	f803 4f01 	strb.w	r4, [r3, #1]!
 8006b80:	d1f9      	bne.n	8006b76 <memcpy+0xe>
 8006b82:	bd10      	pop	{r4, pc}

08006b84 <memmove>:
 8006b84:	4288      	cmp	r0, r1
 8006b86:	b510      	push	{r4, lr}
 8006b88:	eb01 0402 	add.w	r4, r1, r2
 8006b8c:	d902      	bls.n	8006b94 <memmove+0x10>
 8006b8e:	4284      	cmp	r4, r0
 8006b90:	4623      	mov	r3, r4
 8006b92:	d807      	bhi.n	8006ba4 <memmove+0x20>
 8006b94:	1e43      	subs	r3, r0, #1
 8006b96:	42a1      	cmp	r1, r4
 8006b98:	d008      	beq.n	8006bac <memmove+0x28>
 8006b9a:	f811 2b01 	ldrb.w	r2, [r1], #1
 8006b9e:	f803 2f01 	strb.w	r2, [r3, #1]!
 8006ba2:	e7f8      	b.n	8006b96 <memmove+0x12>
 8006ba4:	4601      	mov	r1, r0
 8006ba6:	4402      	add	r2, r0
 8006ba8:	428a      	cmp	r2, r1
 8006baa:	d100      	bne.n	8006bae <memmove+0x2a>
 8006bac:	bd10      	pop	{r4, pc}
 8006bae:	f813 4d01 	ldrb.w	r4, [r3, #-1]!
 8006bb2:	f802 4d01 	strb.w	r4, [r2, #-1]!
 8006bb6:	e7f7      	b.n	8006ba8 <memmove+0x24>

08006bb8 <memset>:
 8006bb8:	4603      	mov	r3, r0
 8006bba:	4402      	add	r2, r0
 8006bbc:	4293      	cmp	r3, r2
 8006bbe:	d100      	bne.n	8006bc2 <memset+0xa>
 8006bc0:	4770      	bx	lr
 8006bc2:	f803 1b01 	strb.w	r1, [r3], #1
 8006bc6:	e7f9      	b.n	8006bbc <memset+0x4>

08006bc8 <__cvt>:
 8006bc8:	2b00      	cmp	r3, #0
 8006bca:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8006bce:	461f      	mov	r7, r3
 8006bd0:	bfbb      	ittet	lt
 8006bd2:	f103 4300 	addlt.w	r3, r3, #2147483648	; 0x80000000
 8006bd6:	461f      	movlt	r7, r3
 8006bd8:	2300      	movge	r3, #0
 8006bda:	232d      	movlt	r3, #45	; 0x2d
 8006bdc:	b088      	sub	sp, #32
 8006bde:	4614      	mov	r4, r2
 8006be0:	9a12      	ldr	r2, [sp, #72]	; 0x48
 8006be2:	9d10      	ldr	r5, [sp, #64]	; 0x40
 8006be4:	7013      	strb	r3, [r2, #0]
 8006be6:	9b14      	ldr	r3, [sp, #80]	; 0x50
 8006be8:	f8dd a04c 	ldr.w	sl, [sp, #76]	; 0x4c
 8006bec:	f023 0820 	bic.w	r8, r3, #32
 8006bf0:	f1b8 0f46 	cmp.w	r8, #70	; 0x46
 8006bf4:	d005      	beq.n	8006c02 <__cvt+0x3a>
 8006bf6:	f1b8 0f45 	cmp.w	r8, #69	; 0x45
 8006bfa:	d100      	bne.n	8006bfe <__cvt+0x36>
 8006bfc:	3501      	adds	r5, #1
 8006bfe:	2302      	movs	r3, #2
 8006c00:	e000      	b.n	8006c04 <__cvt+0x3c>
 8006c02:	2303      	movs	r3, #3
 8006c04:	aa07      	add	r2, sp, #28
 8006c06:	9204      	str	r2, [sp, #16]
 8006c08:	aa06      	add	r2, sp, #24
 8006c0a:	e9cd a202 	strd	sl, r2, [sp, #8]
 8006c0e:	e9cd 3500 	strd	r3, r5, [sp]
 8006c12:	4622      	mov	r2, r4
 8006c14:	463b      	mov	r3, r7
 8006c16:	f000 fce7 	bl	80075e8 <_dtoa_r>
 8006c1a:	f1b8 0f47 	cmp.w	r8, #71	; 0x47
 8006c1e:	4606      	mov	r6, r0
 8006c20:	d102      	bne.n	8006c28 <__cvt+0x60>
 8006c22:	9b11      	ldr	r3, [sp, #68]	; 0x44
 8006c24:	07db      	lsls	r3, r3, #31
 8006c26:	d522      	bpl.n	8006c6e <__cvt+0xa6>
 8006c28:	f1b8 0f46 	cmp.w	r8, #70	; 0x46
 8006c2c:	eb06 0905 	add.w	r9, r6, r5
 8006c30:	d110      	bne.n	8006c54 <__cvt+0x8c>
 8006c32:	7833      	ldrb	r3, [r6, #0]
 8006c34:	2b30      	cmp	r3, #48	; 0x30
 8006c36:	d10a      	bne.n	8006c4e <__cvt+0x86>
 8006c38:	2200      	movs	r2, #0
 8006c3a:	2300      	movs	r3, #0
 8006c3c:	4620      	mov	r0, r4
 8006c3e:	4639      	mov	r1, r7
 8006c40:	f7f9 feca 	bl	80009d8 <__aeabi_dcmpeq>
 8006c44:	b918      	cbnz	r0, 8006c4e <__cvt+0x86>
 8006c46:	f1c5 0501 	rsb	r5, r5, #1
 8006c4a:	f8ca 5000 	str.w	r5, [sl]
 8006c4e:	f8da 3000 	ldr.w	r3, [sl]
 8006c52:	4499      	add	r9, r3
 8006c54:	2200      	movs	r2, #0
 8006c56:	2300      	movs	r3, #0
 8006c58:	4620      	mov	r0, r4
 8006c5a:	4639      	mov	r1, r7
 8006c5c:	f7f9 febc 	bl	80009d8 <__aeabi_dcmpeq>
 8006c60:	b108      	cbz	r0, 8006c66 <__cvt+0x9e>
 8006c62:	f8cd 901c 	str.w	r9, [sp, #28]
 8006c66:	2230      	movs	r2, #48	; 0x30
 8006c68:	9b07      	ldr	r3, [sp, #28]
 8006c6a:	454b      	cmp	r3, r9
 8006c6c:	d307      	bcc.n	8006c7e <__cvt+0xb6>
 8006c6e:	4630      	mov	r0, r6
 8006c70:	9b07      	ldr	r3, [sp, #28]
 8006c72:	9a15      	ldr	r2, [sp, #84]	; 0x54
 8006c74:	1b9b      	subs	r3, r3, r6
 8006c76:	6013      	str	r3, [r2, #0]
 8006c78:	b008      	add	sp, #32
 8006c7a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8006c7e:	1c59      	adds	r1, r3, #1
 8006c80:	9107      	str	r1, [sp, #28]
 8006c82:	701a      	strb	r2, [r3, #0]
 8006c84:	e7f0      	b.n	8006c68 <__cvt+0xa0>

08006c86 <__exponent>:
 8006c86:	4603      	mov	r3, r0
 8006c88:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
 8006c8a:	2900      	cmp	r1, #0
 8006c8c:	f803 2b02 	strb.w	r2, [r3], #2
 8006c90:	bfb6      	itet	lt
 8006c92:	222d      	movlt	r2, #45	; 0x2d
 8006c94:	222b      	movge	r2, #43	; 0x2b
 8006c96:	4249      	neglt	r1, r1
 8006c98:	2909      	cmp	r1, #9
 8006c9a:	7042      	strb	r2, [r0, #1]
 8006c9c:	dd2b      	ble.n	8006cf6 <__exponent+0x70>
 8006c9e:	f10d 0407 	add.w	r4, sp, #7
 8006ca2:	46a4      	mov	ip, r4
 8006ca4:	270a      	movs	r7, #10
 8006ca6:	fb91 f6f7 	sdiv	r6, r1, r7
 8006caa:	460a      	mov	r2, r1
 8006cac:	46a6      	mov	lr, r4
 8006cae:	fb07 1516 	mls	r5, r7, r6, r1
 8006cb2:	2a63      	cmp	r2, #99	; 0x63
 8006cb4:	f105 0530 	add.w	r5, r5, #48	; 0x30
 8006cb8:	4631      	mov	r1, r6
 8006cba:	f104 34ff 	add.w	r4, r4, #4294967295	; 0xffffffff
 8006cbe:	f80e 5c01 	strb.w	r5, [lr, #-1]
 8006cc2:	dcf0      	bgt.n	8006ca6 <__exponent+0x20>
 8006cc4:	3130      	adds	r1, #48	; 0x30
 8006cc6:	f1ae 0502 	sub.w	r5, lr, #2
 8006cca:	f804 1c01 	strb.w	r1, [r4, #-1]
 8006cce:	4629      	mov	r1, r5
 8006cd0:	1c44      	adds	r4, r0, #1
 8006cd2:	4561      	cmp	r1, ip
 8006cd4:	d30a      	bcc.n	8006cec <__exponent+0x66>
 8006cd6:	f10d 0209 	add.w	r2, sp, #9
 8006cda:	eba2 020e 	sub.w	r2, r2, lr
 8006cde:	4565      	cmp	r5, ip
 8006ce0:	bf88      	it	hi
 8006ce2:	2200      	movhi	r2, #0
 8006ce4:	4413      	add	r3, r2
 8006ce6:	1a18      	subs	r0, r3, r0
 8006ce8:	b003      	add	sp, #12
 8006cea:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8006cec:	f811 2b01 	ldrb.w	r2, [r1], #1
 8006cf0:	f804 2f01 	strb.w	r2, [r4, #1]!
 8006cf4:	e7ed      	b.n	8006cd2 <__exponent+0x4c>
 8006cf6:	2330      	movs	r3, #48	; 0x30
 8006cf8:	3130      	adds	r1, #48	; 0x30
 8006cfa:	7083      	strb	r3, [r0, #2]
 8006cfc:	70c1      	strb	r1, [r0, #3]
 8006cfe:	1d03      	adds	r3, r0, #4
 8006d00:	e7f1      	b.n	8006ce6 <__exponent+0x60>
	...

08006d04 <_printf_float>:
 8006d04:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8006d08:	b091      	sub	sp, #68	; 0x44
 8006d0a:	460c      	mov	r4, r1
 8006d0c:	f8dd 8068 	ldr.w	r8, [sp, #104]	; 0x68
 8006d10:	4616      	mov	r6, r2
 8006d12:	461f      	mov	r7, r3
 8006d14:	4605      	mov	r5, r0
 8006d16:	f001 fa55 	bl	80081c4 <_localeconv_r>
 8006d1a:	6803      	ldr	r3, [r0, #0]
 8006d1c:	4618      	mov	r0, r3
 8006d1e:	9309      	str	r3, [sp, #36]	; 0x24
 8006d20:	f7f9 fa2e 	bl	8000180 <strlen>
 8006d24:	2300      	movs	r3, #0
 8006d26:	930e      	str	r3, [sp, #56]	; 0x38
 8006d28:	f8d8 3000 	ldr.w	r3, [r8]
 8006d2c:	900a      	str	r0, [sp, #40]	; 0x28
 8006d2e:	3307      	adds	r3, #7
 8006d30:	f023 0307 	bic.w	r3, r3, #7
 8006d34:	f103 0208 	add.w	r2, r3, #8
 8006d38:	f894 9018 	ldrb.w	r9, [r4, #24]
 8006d3c:	f8d4 b000 	ldr.w	fp, [r4]
 8006d40:	f8c8 2000 	str.w	r2, [r8]
 8006d44:	e9d3 2300 	ldrd	r2, r3, [r3]
 8006d48:	e9c4 2312 	strd	r2, r3, [r4, #72]	; 0x48
 8006d4c:	e9d4 8a12 	ldrd	r8, sl, [r4, #72]	; 0x48
 8006d50:	f02a 4300 	bic.w	r3, sl, #2147483648	; 0x80000000
 8006d54:	930b      	str	r3, [sp, #44]	; 0x2c
 8006d56:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8006d5a:	4640      	mov	r0, r8
 8006d5c:	4b9c      	ldr	r3, [pc, #624]	; (8006fd0 <_printf_float+0x2cc>)
 8006d5e:	990b      	ldr	r1, [sp, #44]	; 0x2c
 8006d60:	f7f9 fe6c 	bl	8000a3c <__aeabi_dcmpun>
 8006d64:	bb70      	cbnz	r0, 8006dc4 <_printf_float+0xc0>
 8006d66:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8006d6a:	4640      	mov	r0, r8
 8006d6c:	4b98      	ldr	r3, [pc, #608]	; (8006fd0 <_printf_float+0x2cc>)
 8006d6e:	990b      	ldr	r1, [sp, #44]	; 0x2c
 8006d70:	f7f9 fe46 	bl	8000a00 <__aeabi_dcmple>
 8006d74:	bb30      	cbnz	r0, 8006dc4 <_printf_float+0xc0>
 8006d76:	2200      	movs	r2, #0
 8006d78:	2300      	movs	r3, #0
 8006d7a:	4640      	mov	r0, r8
 8006d7c:	4651      	mov	r1, sl
 8006d7e:	f7f9 fe35 	bl	80009ec <__aeabi_dcmplt>
 8006d82:	b110      	cbz	r0, 8006d8a <_printf_float+0x86>
 8006d84:	232d      	movs	r3, #45	; 0x2d
 8006d86:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 8006d8a:	4b92      	ldr	r3, [pc, #584]	; (8006fd4 <_printf_float+0x2d0>)
 8006d8c:	4892      	ldr	r0, [pc, #584]	; (8006fd8 <_printf_float+0x2d4>)
 8006d8e:	f1b9 0f47 	cmp.w	r9, #71	; 0x47
 8006d92:	bf94      	ite	ls
 8006d94:	4698      	movls	r8, r3
 8006d96:	4680      	movhi	r8, r0
 8006d98:	2303      	movs	r3, #3
 8006d9a:	f04f 0a00 	mov.w	sl, #0
 8006d9e:	6123      	str	r3, [r4, #16]
 8006da0:	f02b 0304 	bic.w	r3, fp, #4
 8006da4:	6023      	str	r3, [r4, #0]
 8006da6:	4633      	mov	r3, r6
 8006da8:	4621      	mov	r1, r4
 8006daa:	4628      	mov	r0, r5
 8006dac:	9700      	str	r7, [sp, #0]
 8006dae:	aa0f      	add	r2, sp, #60	; 0x3c
 8006db0:	f000 f9d4 	bl	800715c <_printf_common>
 8006db4:	3001      	adds	r0, #1
 8006db6:	f040 8090 	bne.w	8006eda <_printf_float+0x1d6>
 8006dba:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8006dbe:	b011      	add	sp, #68	; 0x44
 8006dc0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8006dc4:	4642      	mov	r2, r8
 8006dc6:	4653      	mov	r3, sl
 8006dc8:	4640      	mov	r0, r8
 8006dca:	4651      	mov	r1, sl
 8006dcc:	f7f9 fe36 	bl	8000a3c <__aeabi_dcmpun>
 8006dd0:	b148      	cbz	r0, 8006de6 <_printf_float+0xe2>
 8006dd2:	f1ba 0f00 	cmp.w	sl, #0
 8006dd6:	bfb8      	it	lt
 8006dd8:	232d      	movlt	r3, #45	; 0x2d
 8006dda:	4880      	ldr	r0, [pc, #512]	; (8006fdc <_printf_float+0x2d8>)
 8006ddc:	bfb8      	it	lt
 8006dde:	f884 3043 	strblt.w	r3, [r4, #67]	; 0x43
 8006de2:	4b7f      	ldr	r3, [pc, #508]	; (8006fe0 <_printf_float+0x2dc>)
 8006de4:	e7d3      	b.n	8006d8e <_printf_float+0x8a>
 8006de6:	6863      	ldr	r3, [r4, #4]
 8006de8:	f009 01df 	and.w	r1, r9, #223	; 0xdf
 8006dec:	1c5a      	adds	r2, r3, #1
 8006dee:	d142      	bne.n	8006e76 <_printf_float+0x172>
 8006df0:	2306      	movs	r3, #6
 8006df2:	6063      	str	r3, [r4, #4]
 8006df4:	2200      	movs	r2, #0
 8006df6:	9206      	str	r2, [sp, #24]
 8006df8:	aa0e      	add	r2, sp, #56	; 0x38
 8006dfa:	e9cd 9204 	strd	r9, r2, [sp, #16]
 8006dfe:	aa0d      	add	r2, sp, #52	; 0x34
 8006e00:	f44b 6380 	orr.w	r3, fp, #1024	; 0x400
 8006e04:	9203      	str	r2, [sp, #12]
 8006e06:	f10d 0233 	add.w	r2, sp, #51	; 0x33
 8006e0a:	e9cd 3201 	strd	r3, r2, [sp, #4]
 8006e0e:	6023      	str	r3, [r4, #0]
 8006e10:	6863      	ldr	r3, [r4, #4]
 8006e12:	4642      	mov	r2, r8
 8006e14:	9300      	str	r3, [sp, #0]
 8006e16:	4628      	mov	r0, r5
 8006e18:	4653      	mov	r3, sl
 8006e1a:	910b      	str	r1, [sp, #44]	; 0x2c
 8006e1c:	f7ff fed4 	bl	8006bc8 <__cvt>
 8006e20:	990b      	ldr	r1, [sp, #44]	; 0x2c
 8006e22:	4680      	mov	r8, r0
 8006e24:	2947      	cmp	r1, #71	; 0x47
 8006e26:	990d      	ldr	r1, [sp, #52]	; 0x34
 8006e28:	d108      	bne.n	8006e3c <_printf_float+0x138>
 8006e2a:	1cc8      	adds	r0, r1, #3
 8006e2c:	db02      	blt.n	8006e34 <_printf_float+0x130>
 8006e2e:	6863      	ldr	r3, [r4, #4]
 8006e30:	4299      	cmp	r1, r3
 8006e32:	dd40      	ble.n	8006eb6 <_printf_float+0x1b2>
 8006e34:	f1a9 0902 	sub.w	r9, r9, #2
 8006e38:	fa5f f989 	uxtb.w	r9, r9
 8006e3c:	f1b9 0f65 	cmp.w	r9, #101	; 0x65
 8006e40:	d81f      	bhi.n	8006e82 <_printf_float+0x17e>
 8006e42:	464a      	mov	r2, r9
 8006e44:	3901      	subs	r1, #1
 8006e46:	f104 0050 	add.w	r0, r4, #80	; 0x50
 8006e4a:	910d      	str	r1, [sp, #52]	; 0x34
 8006e4c:	f7ff ff1b 	bl	8006c86 <__exponent>
 8006e50:	9a0e      	ldr	r2, [sp, #56]	; 0x38
 8006e52:	4682      	mov	sl, r0
 8006e54:	1813      	adds	r3, r2, r0
 8006e56:	2a01      	cmp	r2, #1
 8006e58:	6123      	str	r3, [r4, #16]
 8006e5a:	dc02      	bgt.n	8006e62 <_printf_float+0x15e>
 8006e5c:	6822      	ldr	r2, [r4, #0]
 8006e5e:	07d2      	lsls	r2, r2, #31
 8006e60:	d501      	bpl.n	8006e66 <_printf_float+0x162>
 8006e62:	3301      	adds	r3, #1
 8006e64:	6123      	str	r3, [r4, #16]
 8006e66:	f89d 3033 	ldrb.w	r3, [sp, #51]	; 0x33
 8006e6a:	2b00      	cmp	r3, #0
 8006e6c:	d09b      	beq.n	8006da6 <_printf_float+0xa2>
 8006e6e:	232d      	movs	r3, #45	; 0x2d
 8006e70:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 8006e74:	e797      	b.n	8006da6 <_printf_float+0xa2>
 8006e76:	2947      	cmp	r1, #71	; 0x47
 8006e78:	d1bc      	bne.n	8006df4 <_printf_float+0xf0>
 8006e7a:	2b00      	cmp	r3, #0
 8006e7c:	d1ba      	bne.n	8006df4 <_printf_float+0xf0>
 8006e7e:	2301      	movs	r3, #1
 8006e80:	e7b7      	b.n	8006df2 <_printf_float+0xee>
 8006e82:	f1b9 0f66 	cmp.w	r9, #102	; 0x66
 8006e86:	d118      	bne.n	8006eba <_printf_float+0x1b6>
 8006e88:	2900      	cmp	r1, #0
 8006e8a:	6863      	ldr	r3, [r4, #4]
 8006e8c:	dd0b      	ble.n	8006ea6 <_printf_float+0x1a2>
 8006e8e:	6121      	str	r1, [r4, #16]
 8006e90:	b913      	cbnz	r3, 8006e98 <_printf_float+0x194>
 8006e92:	6822      	ldr	r2, [r4, #0]
 8006e94:	07d0      	lsls	r0, r2, #31
 8006e96:	d502      	bpl.n	8006e9e <_printf_float+0x19a>
 8006e98:	3301      	adds	r3, #1
 8006e9a:	440b      	add	r3, r1
 8006e9c:	6123      	str	r3, [r4, #16]
 8006e9e:	f04f 0a00 	mov.w	sl, #0
 8006ea2:	65a1      	str	r1, [r4, #88]	; 0x58
 8006ea4:	e7df      	b.n	8006e66 <_printf_float+0x162>
 8006ea6:	b913      	cbnz	r3, 8006eae <_printf_float+0x1aa>
 8006ea8:	6822      	ldr	r2, [r4, #0]
 8006eaa:	07d2      	lsls	r2, r2, #31
 8006eac:	d501      	bpl.n	8006eb2 <_printf_float+0x1ae>
 8006eae:	3302      	adds	r3, #2
 8006eb0:	e7f4      	b.n	8006e9c <_printf_float+0x198>
 8006eb2:	2301      	movs	r3, #1
 8006eb4:	e7f2      	b.n	8006e9c <_printf_float+0x198>
 8006eb6:	f04f 0967 	mov.w	r9, #103	; 0x67
 8006eba:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8006ebc:	4299      	cmp	r1, r3
 8006ebe:	db05      	blt.n	8006ecc <_printf_float+0x1c8>
 8006ec0:	6823      	ldr	r3, [r4, #0]
 8006ec2:	6121      	str	r1, [r4, #16]
 8006ec4:	07d8      	lsls	r0, r3, #31
 8006ec6:	d5ea      	bpl.n	8006e9e <_printf_float+0x19a>
 8006ec8:	1c4b      	adds	r3, r1, #1
 8006eca:	e7e7      	b.n	8006e9c <_printf_float+0x198>
 8006ecc:	2900      	cmp	r1, #0
 8006ece:	bfcc      	ite	gt
 8006ed0:	2201      	movgt	r2, #1
 8006ed2:	f1c1 0202 	rsble	r2, r1, #2
 8006ed6:	4413      	add	r3, r2
 8006ed8:	e7e0      	b.n	8006e9c <_printf_float+0x198>
 8006eda:	6823      	ldr	r3, [r4, #0]
 8006edc:	055a      	lsls	r2, r3, #21
 8006ede:	d407      	bmi.n	8006ef0 <_printf_float+0x1ec>
 8006ee0:	6923      	ldr	r3, [r4, #16]
 8006ee2:	4642      	mov	r2, r8
 8006ee4:	4631      	mov	r1, r6
 8006ee6:	4628      	mov	r0, r5
 8006ee8:	47b8      	blx	r7
 8006eea:	3001      	adds	r0, #1
 8006eec:	d12b      	bne.n	8006f46 <_printf_float+0x242>
 8006eee:	e764      	b.n	8006dba <_printf_float+0xb6>
 8006ef0:	f1b9 0f65 	cmp.w	r9, #101	; 0x65
 8006ef4:	f240 80dd 	bls.w	80070b2 <_printf_float+0x3ae>
 8006ef8:	e9d4 0112 	ldrd	r0, r1, [r4, #72]	; 0x48
 8006efc:	2200      	movs	r2, #0
 8006efe:	2300      	movs	r3, #0
 8006f00:	f7f9 fd6a 	bl	80009d8 <__aeabi_dcmpeq>
 8006f04:	2800      	cmp	r0, #0
 8006f06:	d033      	beq.n	8006f70 <_printf_float+0x26c>
 8006f08:	2301      	movs	r3, #1
 8006f0a:	4631      	mov	r1, r6
 8006f0c:	4628      	mov	r0, r5
 8006f0e:	4a35      	ldr	r2, [pc, #212]	; (8006fe4 <_printf_float+0x2e0>)
 8006f10:	47b8      	blx	r7
 8006f12:	3001      	adds	r0, #1
 8006f14:	f43f af51 	beq.w	8006dba <_printf_float+0xb6>
 8006f18:	e9dd 230d 	ldrd	r2, r3, [sp, #52]	; 0x34
 8006f1c:	429a      	cmp	r2, r3
 8006f1e:	db02      	blt.n	8006f26 <_printf_float+0x222>
 8006f20:	6823      	ldr	r3, [r4, #0]
 8006f22:	07d8      	lsls	r0, r3, #31
 8006f24:	d50f      	bpl.n	8006f46 <_printf_float+0x242>
 8006f26:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 8006f2a:	4631      	mov	r1, r6
 8006f2c:	4628      	mov	r0, r5
 8006f2e:	47b8      	blx	r7
 8006f30:	3001      	adds	r0, #1
 8006f32:	f43f af42 	beq.w	8006dba <_printf_float+0xb6>
 8006f36:	f04f 0800 	mov.w	r8, #0
 8006f3a:	f104 091a 	add.w	r9, r4, #26
 8006f3e:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8006f40:	3b01      	subs	r3, #1
 8006f42:	4543      	cmp	r3, r8
 8006f44:	dc09      	bgt.n	8006f5a <_printf_float+0x256>
 8006f46:	6823      	ldr	r3, [r4, #0]
 8006f48:	079b      	lsls	r3, r3, #30
 8006f4a:	f100 8102 	bmi.w	8007152 <_printf_float+0x44e>
 8006f4e:	68e0      	ldr	r0, [r4, #12]
 8006f50:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
 8006f52:	4298      	cmp	r0, r3
 8006f54:	bfb8      	it	lt
 8006f56:	4618      	movlt	r0, r3
 8006f58:	e731      	b.n	8006dbe <_printf_float+0xba>
 8006f5a:	2301      	movs	r3, #1
 8006f5c:	464a      	mov	r2, r9
 8006f5e:	4631      	mov	r1, r6
 8006f60:	4628      	mov	r0, r5
 8006f62:	47b8      	blx	r7
 8006f64:	3001      	adds	r0, #1
 8006f66:	f43f af28 	beq.w	8006dba <_printf_float+0xb6>
 8006f6a:	f108 0801 	add.w	r8, r8, #1
 8006f6e:	e7e6      	b.n	8006f3e <_printf_float+0x23a>
 8006f70:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8006f72:	2b00      	cmp	r3, #0
 8006f74:	dc38      	bgt.n	8006fe8 <_printf_float+0x2e4>
 8006f76:	2301      	movs	r3, #1
 8006f78:	4631      	mov	r1, r6
 8006f7a:	4628      	mov	r0, r5
 8006f7c:	4a19      	ldr	r2, [pc, #100]	; (8006fe4 <_printf_float+0x2e0>)
 8006f7e:	47b8      	blx	r7
 8006f80:	3001      	adds	r0, #1
 8006f82:	f43f af1a 	beq.w	8006dba <_printf_float+0xb6>
 8006f86:	e9dd 230d 	ldrd	r2, r3, [sp, #52]	; 0x34
 8006f8a:	4313      	orrs	r3, r2
 8006f8c:	d102      	bne.n	8006f94 <_printf_float+0x290>
 8006f8e:	6823      	ldr	r3, [r4, #0]
 8006f90:	07d9      	lsls	r1, r3, #31
 8006f92:	d5d8      	bpl.n	8006f46 <_printf_float+0x242>
 8006f94:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 8006f98:	4631      	mov	r1, r6
 8006f9a:	4628      	mov	r0, r5
 8006f9c:	47b8      	blx	r7
 8006f9e:	3001      	adds	r0, #1
 8006fa0:	f43f af0b 	beq.w	8006dba <_printf_float+0xb6>
 8006fa4:	f04f 0900 	mov.w	r9, #0
 8006fa8:	f104 0a1a 	add.w	sl, r4, #26
 8006fac:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8006fae:	425b      	negs	r3, r3
 8006fb0:	454b      	cmp	r3, r9
 8006fb2:	dc01      	bgt.n	8006fb8 <_printf_float+0x2b4>
 8006fb4:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8006fb6:	e794      	b.n	8006ee2 <_printf_float+0x1de>
 8006fb8:	2301      	movs	r3, #1
 8006fba:	4652      	mov	r2, sl
 8006fbc:	4631      	mov	r1, r6
 8006fbe:	4628      	mov	r0, r5
 8006fc0:	47b8      	blx	r7
 8006fc2:	3001      	adds	r0, #1
 8006fc4:	f43f aef9 	beq.w	8006dba <_printf_float+0xb6>
 8006fc8:	f109 0901 	add.w	r9, r9, #1
 8006fcc:	e7ee      	b.n	8006fac <_printf_float+0x2a8>
 8006fce:	bf00      	nop
 8006fd0:	7fefffff 	.word	0x7fefffff
 8006fd4:	0800a658 	.word	0x0800a658
 8006fd8:	0800a65c 	.word	0x0800a65c
 8006fdc:	0800a664 	.word	0x0800a664
 8006fe0:	0800a660 	.word	0x0800a660
 8006fe4:	0800a668 	.word	0x0800a668
 8006fe8:	9a0e      	ldr	r2, [sp, #56]	; 0x38
 8006fea:	6da3      	ldr	r3, [r4, #88]	; 0x58
 8006fec:	429a      	cmp	r2, r3
 8006fee:	bfa8      	it	ge
 8006ff0:	461a      	movge	r2, r3
 8006ff2:	2a00      	cmp	r2, #0
 8006ff4:	4691      	mov	r9, r2
 8006ff6:	dc37      	bgt.n	8007068 <_printf_float+0x364>
 8006ff8:	f04f 0b00 	mov.w	fp, #0
 8006ffc:	ea29 79e9 	bic.w	r9, r9, r9, asr #31
 8007000:	f104 021a 	add.w	r2, r4, #26
 8007004:	f8d4 a058 	ldr.w	sl, [r4, #88]	; 0x58
 8007008:	ebaa 0309 	sub.w	r3, sl, r9
 800700c:	455b      	cmp	r3, fp
 800700e:	dc33      	bgt.n	8007078 <_printf_float+0x374>
 8007010:	e9dd 230d 	ldrd	r2, r3, [sp, #52]	; 0x34
 8007014:	429a      	cmp	r2, r3
 8007016:	db3b      	blt.n	8007090 <_printf_float+0x38c>
 8007018:	6823      	ldr	r3, [r4, #0]
 800701a:	07da      	lsls	r2, r3, #31
 800701c:	d438      	bmi.n	8007090 <_printf_float+0x38c>
 800701e:	9a0e      	ldr	r2, [sp, #56]	; 0x38
 8007020:	990d      	ldr	r1, [sp, #52]	; 0x34
 8007022:	eba2 030a 	sub.w	r3, r2, sl
 8007026:	eba2 0901 	sub.w	r9, r2, r1
 800702a:	4599      	cmp	r9, r3
 800702c:	bfa8      	it	ge
 800702e:	4699      	movge	r9, r3
 8007030:	f1b9 0f00 	cmp.w	r9, #0
 8007034:	dc34      	bgt.n	80070a0 <_printf_float+0x39c>
 8007036:	f04f 0800 	mov.w	r8, #0
 800703a:	ea29 79e9 	bic.w	r9, r9, r9, asr #31
 800703e:	f104 0a1a 	add.w	sl, r4, #26
 8007042:	e9dd 230d 	ldrd	r2, r3, [sp, #52]	; 0x34
 8007046:	1a9b      	subs	r3, r3, r2
 8007048:	eba3 0309 	sub.w	r3, r3, r9
 800704c:	4543      	cmp	r3, r8
 800704e:	f77f af7a 	ble.w	8006f46 <_printf_float+0x242>
 8007052:	2301      	movs	r3, #1
 8007054:	4652      	mov	r2, sl
 8007056:	4631      	mov	r1, r6
 8007058:	4628      	mov	r0, r5
 800705a:	47b8      	blx	r7
 800705c:	3001      	adds	r0, #1
 800705e:	f43f aeac 	beq.w	8006dba <_printf_float+0xb6>
 8007062:	f108 0801 	add.w	r8, r8, #1
 8007066:	e7ec      	b.n	8007042 <_printf_float+0x33e>
 8007068:	4613      	mov	r3, r2
 800706a:	4631      	mov	r1, r6
 800706c:	4642      	mov	r2, r8
 800706e:	4628      	mov	r0, r5
 8007070:	47b8      	blx	r7
 8007072:	3001      	adds	r0, #1
 8007074:	d1c0      	bne.n	8006ff8 <_printf_float+0x2f4>
 8007076:	e6a0      	b.n	8006dba <_printf_float+0xb6>
 8007078:	2301      	movs	r3, #1
 800707a:	4631      	mov	r1, r6
 800707c:	4628      	mov	r0, r5
 800707e:	920b      	str	r2, [sp, #44]	; 0x2c
 8007080:	47b8      	blx	r7
 8007082:	3001      	adds	r0, #1
 8007084:	f43f ae99 	beq.w	8006dba <_printf_float+0xb6>
 8007088:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
 800708a:	f10b 0b01 	add.w	fp, fp, #1
 800708e:	e7b9      	b.n	8007004 <_printf_float+0x300>
 8007090:	4631      	mov	r1, r6
 8007092:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 8007096:	4628      	mov	r0, r5
 8007098:	47b8      	blx	r7
 800709a:	3001      	adds	r0, #1
 800709c:	d1bf      	bne.n	800701e <_printf_float+0x31a>
 800709e:	e68c      	b.n	8006dba <_printf_float+0xb6>
 80070a0:	464b      	mov	r3, r9
 80070a2:	4631      	mov	r1, r6
 80070a4:	4628      	mov	r0, r5
 80070a6:	eb08 020a 	add.w	r2, r8, sl
 80070aa:	47b8      	blx	r7
 80070ac:	3001      	adds	r0, #1
 80070ae:	d1c2      	bne.n	8007036 <_printf_float+0x332>
 80070b0:	e683      	b.n	8006dba <_printf_float+0xb6>
 80070b2:	9a0e      	ldr	r2, [sp, #56]	; 0x38
 80070b4:	2a01      	cmp	r2, #1
 80070b6:	dc01      	bgt.n	80070bc <_printf_float+0x3b8>
 80070b8:	07db      	lsls	r3, r3, #31
 80070ba:	d537      	bpl.n	800712c <_printf_float+0x428>
 80070bc:	2301      	movs	r3, #1
 80070be:	4642      	mov	r2, r8
 80070c0:	4631      	mov	r1, r6
 80070c2:	4628      	mov	r0, r5
 80070c4:	47b8      	blx	r7
 80070c6:	3001      	adds	r0, #1
 80070c8:	f43f ae77 	beq.w	8006dba <_printf_float+0xb6>
 80070cc:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 80070d0:	4631      	mov	r1, r6
 80070d2:	4628      	mov	r0, r5
 80070d4:	47b8      	blx	r7
 80070d6:	3001      	adds	r0, #1
 80070d8:	f43f ae6f 	beq.w	8006dba <_printf_float+0xb6>
 80070dc:	e9d4 0112 	ldrd	r0, r1, [r4, #72]	; 0x48
 80070e0:	2200      	movs	r2, #0
 80070e2:	2300      	movs	r3, #0
 80070e4:	f7f9 fc78 	bl	80009d8 <__aeabi_dcmpeq>
 80070e8:	b9d8      	cbnz	r0, 8007122 <_printf_float+0x41e>
 80070ea:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 80070ec:	f108 0201 	add.w	r2, r8, #1
 80070f0:	3b01      	subs	r3, #1
 80070f2:	4631      	mov	r1, r6
 80070f4:	4628      	mov	r0, r5
 80070f6:	47b8      	blx	r7
 80070f8:	3001      	adds	r0, #1
 80070fa:	d10e      	bne.n	800711a <_printf_float+0x416>
 80070fc:	e65d      	b.n	8006dba <_printf_float+0xb6>
 80070fe:	2301      	movs	r3, #1
 8007100:	464a      	mov	r2, r9
 8007102:	4631      	mov	r1, r6
 8007104:	4628      	mov	r0, r5
 8007106:	47b8      	blx	r7
 8007108:	3001      	adds	r0, #1
 800710a:	f43f ae56 	beq.w	8006dba <_printf_float+0xb6>
 800710e:	f108 0801 	add.w	r8, r8, #1
 8007112:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8007114:	3b01      	subs	r3, #1
 8007116:	4543      	cmp	r3, r8
 8007118:	dcf1      	bgt.n	80070fe <_printf_float+0x3fa>
 800711a:	4653      	mov	r3, sl
 800711c:	f104 0250 	add.w	r2, r4, #80	; 0x50
 8007120:	e6e0      	b.n	8006ee4 <_printf_float+0x1e0>
 8007122:	f04f 0800 	mov.w	r8, #0
 8007126:	f104 091a 	add.w	r9, r4, #26
 800712a:	e7f2      	b.n	8007112 <_printf_float+0x40e>
 800712c:	2301      	movs	r3, #1
 800712e:	4642      	mov	r2, r8
 8007130:	e7df      	b.n	80070f2 <_printf_float+0x3ee>
 8007132:	2301      	movs	r3, #1
 8007134:	464a      	mov	r2, r9
 8007136:	4631      	mov	r1, r6
 8007138:	4628      	mov	r0, r5
 800713a:	47b8      	blx	r7
 800713c:	3001      	adds	r0, #1
 800713e:	f43f ae3c 	beq.w	8006dba <_printf_float+0xb6>
 8007142:	f108 0801 	add.w	r8, r8, #1
 8007146:	68e3      	ldr	r3, [r4, #12]
 8007148:	990f      	ldr	r1, [sp, #60]	; 0x3c
 800714a:	1a5b      	subs	r3, r3, r1
 800714c:	4543      	cmp	r3, r8
 800714e:	dcf0      	bgt.n	8007132 <_printf_float+0x42e>
 8007150:	e6fd      	b.n	8006f4e <_printf_float+0x24a>
 8007152:	f04f 0800 	mov.w	r8, #0
 8007156:	f104 0919 	add.w	r9, r4, #25
 800715a:	e7f4      	b.n	8007146 <_printf_float+0x442>

0800715c <_printf_common>:
 800715c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8007160:	4616      	mov	r6, r2
 8007162:	4699      	mov	r9, r3
 8007164:	688a      	ldr	r2, [r1, #8]
 8007166:	690b      	ldr	r3, [r1, #16]
 8007168:	4607      	mov	r7, r0
 800716a:	4293      	cmp	r3, r2
 800716c:	bfb8      	it	lt
 800716e:	4613      	movlt	r3, r2
 8007170:	6033      	str	r3, [r6, #0]
 8007172:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
 8007176:	460c      	mov	r4, r1
 8007178:	f8dd 8020 	ldr.w	r8, [sp, #32]
 800717c:	b10a      	cbz	r2, 8007182 <_printf_common+0x26>
 800717e:	3301      	adds	r3, #1
 8007180:	6033      	str	r3, [r6, #0]
 8007182:	6823      	ldr	r3, [r4, #0]
 8007184:	0699      	lsls	r1, r3, #26
 8007186:	bf42      	ittt	mi
 8007188:	6833      	ldrmi	r3, [r6, #0]
 800718a:	3302      	addmi	r3, #2
 800718c:	6033      	strmi	r3, [r6, #0]
 800718e:	6825      	ldr	r5, [r4, #0]
 8007190:	f015 0506 	ands.w	r5, r5, #6
 8007194:	d106      	bne.n	80071a4 <_printf_common+0x48>
 8007196:	f104 0a19 	add.w	sl, r4, #25
 800719a:	68e3      	ldr	r3, [r4, #12]
 800719c:	6832      	ldr	r2, [r6, #0]
 800719e:	1a9b      	subs	r3, r3, r2
 80071a0:	42ab      	cmp	r3, r5
 80071a2:	dc28      	bgt.n	80071f6 <_printf_common+0x9a>
 80071a4:	f894 2043 	ldrb.w	r2, [r4, #67]	; 0x43
 80071a8:	1e13      	subs	r3, r2, #0
 80071aa:	6822      	ldr	r2, [r4, #0]
 80071ac:	bf18      	it	ne
 80071ae:	2301      	movne	r3, #1
 80071b0:	0692      	lsls	r2, r2, #26
 80071b2:	d42d      	bmi.n	8007210 <_printf_common+0xb4>
 80071b4:	4649      	mov	r1, r9
 80071b6:	4638      	mov	r0, r7
 80071b8:	f104 0243 	add.w	r2, r4, #67	; 0x43
 80071bc:	47c0      	blx	r8
 80071be:	3001      	adds	r0, #1
 80071c0:	d020      	beq.n	8007204 <_printf_common+0xa8>
 80071c2:	6823      	ldr	r3, [r4, #0]
 80071c4:	68e5      	ldr	r5, [r4, #12]
 80071c6:	f003 0306 	and.w	r3, r3, #6
 80071ca:	2b04      	cmp	r3, #4
 80071cc:	bf18      	it	ne
 80071ce:	2500      	movne	r5, #0
 80071d0:	6832      	ldr	r2, [r6, #0]
 80071d2:	f04f 0600 	mov.w	r6, #0
 80071d6:	68a3      	ldr	r3, [r4, #8]
 80071d8:	bf08      	it	eq
 80071da:	1aad      	subeq	r5, r5, r2
 80071dc:	6922      	ldr	r2, [r4, #16]
 80071de:	bf08      	it	eq
 80071e0:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 80071e4:	4293      	cmp	r3, r2
 80071e6:	bfc4      	itt	gt
 80071e8:	1a9b      	subgt	r3, r3, r2
 80071ea:	18ed      	addgt	r5, r5, r3
 80071ec:	341a      	adds	r4, #26
 80071ee:	42b5      	cmp	r5, r6
 80071f0:	d11a      	bne.n	8007228 <_printf_common+0xcc>
 80071f2:	2000      	movs	r0, #0
 80071f4:	e008      	b.n	8007208 <_printf_common+0xac>
 80071f6:	2301      	movs	r3, #1
 80071f8:	4652      	mov	r2, sl
 80071fa:	4649      	mov	r1, r9
 80071fc:	4638      	mov	r0, r7
 80071fe:	47c0      	blx	r8
 8007200:	3001      	adds	r0, #1
 8007202:	d103      	bne.n	800720c <_printf_common+0xb0>
 8007204:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8007208:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800720c:	3501      	adds	r5, #1
 800720e:	e7c4      	b.n	800719a <_printf_common+0x3e>
 8007210:	2030      	movs	r0, #48	; 0x30
 8007212:	18e1      	adds	r1, r4, r3
 8007214:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
 8007218:	1c5a      	adds	r2, r3, #1
 800721a:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
 800721e:	4422      	add	r2, r4
 8007220:	3302      	adds	r3, #2
 8007222:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
 8007226:	e7c5      	b.n	80071b4 <_printf_common+0x58>
 8007228:	2301      	movs	r3, #1
 800722a:	4622      	mov	r2, r4
 800722c:	4649      	mov	r1, r9
 800722e:	4638      	mov	r0, r7
 8007230:	47c0      	blx	r8
 8007232:	3001      	adds	r0, #1
 8007234:	d0e6      	beq.n	8007204 <_printf_common+0xa8>
 8007236:	3601      	adds	r6, #1
 8007238:	e7d9      	b.n	80071ee <_printf_common+0x92>
	...

0800723c <_printf_i>:
 800723c:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
 8007240:	460c      	mov	r4, r1
 8007242:	7e27      	ldrb	r7, [r4, #24]
 8007244:	4691      	mov	r9, r2
 8007246:	2f78      	cmp	r7, #120	; 0x78
 8007248:	4680      	mov	r8, r0
 800724a:	469a      	mov	sl, r3
 800724c:	990c      	ldr	r1, [sp, #48]	; 0x30
 800724e:	f104 0243 	add.w	r2, r4, #67	; 0x43
 8007252:	d807      	bhi.n	8007264 <_printf_i+0x28>
 8007254:	2f62      	cmp	r7, #98	; 0x62
 8007256:	d80a      	bhi.n	800726e <_printf_i+0x32>
 8007258:	2f00      	cmp	r7, #0
 800725a:	f000 80d9 	beq.w	8007410 <_printf_i+0x1d4>
 800725e:	2f58      	cmp	r7, #88	; 0x58
 8007260:	f000 80a4 	beq.w	80073ac <_printf_i+0x170>
 8007264:	f104 0642 	add.w	r6, r4, #66	; 0x42
 8007268:	f884 7042 	strb.w	r7, [r4, #66]	; 0x42
 800726c:	e03a      	b.n	80072e4 <_printf_i+0xa8>
 800726e:	f1a7 0363 	sub.w	r3, r7, #99	; 0x63
 8007272:	2b15      	cmp	r3, #21
 8007274:	d8f6      	bhi.n	8007264 <_printf_i+0x28>
 8007276:	a001      	add	r0, pc, #4	; (adr r0, 800727c <_printf_i+0x40>)
 8007278:	f850 f023 	ldr.w	pc, [r0, r3, lsl #2]
 800727c:	080072d5 	.word	0x080072d5
 8007280:	080072e9 	.word	0x080072e9
 8007284:	08007265 	.word	0x08007265
 8007288:	08007265 	.word	0x08007265
 800728c:	08007265 	.word	0x08007265
 8007290:	08007265 	.word	0x08007265
 8007294:	080072e9 	.word	0x080072e9
 8007298:	08007265 	.word	0x08007265
 800729c:	08007265 	.word	0x08007265
 80072a0:	08007265 	.word	0x08007265
 80072a4:	08007265 	.word	0x08007265
 80072a8:	080073f7 	.word	0x080073f7
 80072ac:	08007319 	.word	0x08007319
 80072b0:	080073d9 	.word	0x080073d9
 80072b4:	08007265 	.word	0x08007265
 80072b8:	08007265 	.word	0x08007265
 80072bc:	08007419 	.word	0x08007419
 80072c0:	08007265 	.word	0x08007265
 80072c4:	08007319 	.word	0x08007319
 80072c8:	08007265 	.word	0x08007265
 80072cc:	08007265 	.word	0x08007265
 80072d0:	080073e1 	.word	0x080073e1
 80072d4:	680b      	ldr	r3, [r1, #0]
 80072d6:	f104 0642 	add.w	r6, r4, #66	; 0x42
 80072da:	1d1a      	adds	r2, r3, #4
 80072dc:	681b      	ldr	r3, [r3, #0]
 80072de:	600a      	str	r2, [r1, #0]
 80072e0:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 80072e4:	2301      	movs	r3, #1
 80072e6:	e0a4      	b.n	8007432 <_printf_i+0x1f6>
 80072e8:	6825      	ldr	r5, [r4, #0]
 80072ea:	6808      	ldr	r0, [r1, #0]
 80072ec:	062e      	lsls	r6, r5, #24
 80072ee:	f100 0304 	add.w	r3, r0, #4
 80072f2:	d50a      	bpl.n	800730a <_printf_i+0xce>
 80072f4:	6805      	ldr	r5, [r0, #0]
 80072f6:	600b      	str	r3, [r1, #0]
 80072f8:	2d00      	cmp	r5, #0
 80072fa:	da03      	bge.n	8007304 <_printf_i+0xc8>
 80072fc:	232d      	movs	r3, #45	; 0x2d
 80072fe:	426d      	negs	r5, r5
 8007300:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 8007304:	230a      	movs	r3, #10
 8007306:	485e      	ldr	r0, [pc, #376]	; (8007480 <_printf_i+0x244>)
 8007308:	e019      	b.n	800733e <_printf_i+0x102>
 800730a:	f015 0f40 	tst.w	r5, #64	; 0x40
 800730e:	6805      	ldr	r5, [r0, #0]
 8007310:	600b      	str	r3, [r1, #0]
 8007312:	bf18      	it	ne
 8007314:	b22d      	sxthne	r5, r5
 8007316:	e7ef      	b.n	80072f8 <_printf_i+0xbc>
 8007318:	680b      	ldr	r3, [r1, #0]
 800731a:	6825      	ldr	r5, [r4, #0]
 800731c:	1d18      	adds	r0, r3, #4
 800731e:	6008      	str	r0, [r1, #0]
 8007320:	0628      	lsls	r0, r5, #24
 8007322:	d501      	bpl.n	8007328 <_printf_i+0xec>
 8007324:	681d      	ldr	r5, [r3, #0]
 8007326:	e002      	b.n	800732e <_printf_i+0xf2>
 8007328:	0669      	lsls	r1, r5, #25
 800732a:	d5fb      	bpl.n	8007324 <_printf_i+0xe8>
 800732c:	881d      	ldrh	r5, [r3, #0]
 800732e:	2f6f      	cmp	r7, #111	; 0x6f
 8007330:	bf0c      	ite	eq
 8007332:	2308      	moveq	r3, #8
 8007334:	230a      	movne	r3, #10
 8007336:	4852      	ldr	r0, [pc, #328]	; (8007480 <_printf_i+0x244>)
 8007338:	2100      	movs	r1, #0
 800733a:	f884 1043 	strb.w	r1, [r4, #67]	; 0x43
 800733e:	6866      	ldr	r6, [r4, #4]
 8007340:	2e00      	cmp	r6, #0
 8007342:	bfa8      	it	ge
 8007344:	6821      	ldrge	r1, [r4, #0]
 8007346:	60a6      	str	r6, [r4, #8]
 8007348:	bfa4      	itt	ge
 800734a:	f021 0104 	bicge.w	r1, r1, #4
 800734e:	6021      	strge	r1, [r4, #0]
 8007350:	b90d      	cbnz	r5, 8007356 <_printf_i+0x11a>
 8007352:	2e00      	cmp	r6, #0
 8007354:	d04d      	beq.n	80073f2 <_printf_i+0x1b6>
 8007356:	4616      	mov	r6, r2
 8007358:	fbb5 f1f3 	udiv	r1, r5, r3
 800735c:	fb03 5711 	mls	r7, r3, r1, r5
 8007360:	5dc7      	ldrb	r7, [r0, r7]
 8007362:	f806 7d01 	strb.w	r7, [r6, #-1]!
 8007366:	462f      	mov	r7, r5
 8007368:	42bb      	cmp	r3, r7
 800736a:	460d      	mov	r5, r1
 800736c:	d9f4      	bls.n	8007358 <_printf_i+0x11c>
 800736e:	2b08      	cmp	r3, #8
 8007370:	d10b      	bne.n	800738a <_printf_i+0x14e>
 8007372:	6823      	ldr	r3, [r4, #0]
 8007374:	07df      	lsls	r7, r3, #31
 8007376:	d508      	bpl.n	800738a <_printf_i+0x14e>
 8007378:	6923      	ldr	r3, [r4, #16]
 800737a:	6861      	ldr	r1, [r4, #4]
 800737c:	4299      	cmp	r1, r3
 800737e:	bfde      	ittt	le
 8007380:	2330      	movle	r3, #48	; 0x30
 8007382:	f806 3c01 	strble.w	r3, [r6, #-1]
 8007386:	f106 36ff 	addle.w	r6, r6, #4294967295	; 0xffffffff
 800738a:	1b92      	subs	r2, r2, r6
 800738c:	6122      	str	r2, [r4, #16]
 800738e:	464b      	mov	r3, r9
 8007390:	4621      	mov	r1, r4
 8007392:	4640      	mov	r0, r8
 8007394:	f8cd a000 	str.w	sl, [sp]
 8007398:	aa03      	add	r2, sp, #12
 800739a:	f7ff fedf 	bl	800715c <_printf_common>
 800739e:	3001      	adds	r0, #1
 80073a0:	d14c      	bne.n	800743c <_printf_i+0x200>
 80073a2:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 80073a6:	b004      	add	sp, #16
 80073a8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80073ac:	4834      	ldr	r0, [pc, #208]	; (8007480 <_printf_i+0x244>)
 80073ae:	f884 7045 	strb.w	r7, [r4, #69]	; 0x45
 80073b2:	680e      	ldr	r6, [r1, #0]
 80073b4:	6823      	ldr	r3, [r4, #0]
 80073b6:	f856 5b04 	ldr.w	r5, [r6], #4
 80073ba:	061f      	lsls	r7, r3, #24
 80073bc:	600e      	str	r6, [r1, #0]
 80073be:	d514      	bpl.n	80073ea <_printf_i+0x1ae>
 80073c0:	07d9      	lsls	r1, r3, #31
 80073c2:	bf44      	itt	mi
 80073c4:	f043 0320 	orrmi.w	r3, r3, #32
 80073c8:	6023      	strmi	r3, [r4, #0]
 80073ca:	b91d      	cbnz	r5, 80073d4 <_printf_i+0x198>
 80073cc:	6823      	ldr	r3, [r4, #0]
 80073ce:	f023 0320 	bic.w	r3, r3, #32
 80073d2:	6023      	str	r3, [r4, #0]
 80073d4:	2310      	movs	r3, #16
 80073d6:	e7af      	b.n	8007338 <_printf_i+0xfc>
 80073d8:	6823      	ldr	r3, [r4, #0]
 80073da:	f043 0320 	orr.w	r3, r3, #32
 80073de:	6023      	str	r3, [r4, #0]
 80073e0:	2378      	movs	r3, #120	; 0x78
 80073e2:	4828      	ldr	r0, [pc, #160]	; (8007484 <_printf_i+0x248>)
 80073e4:	f884 3045 	strb.w	r3, [r4, #69]	; 0x45
 80073e8:	e7e3      	b.n	80073b2 <_printf_i+0x176>
 80073ea:	065e      	lsls	r6, r3, #25
 80073ec:	bf48      	it	mi
 80073ee:	b2ad      	uxthmi	r5, r5
 80073f0:	e7e6      	b.n	80073c0 <_printf_i+0x184>
 80073f2:	4616      	mov	r6, r2
 80073f4:	e7bb      	b.n	800736e <_printf_i+0x132>
 80073f6:	680b      	ldr	r3, [r1, #0]
 80073f8:	6826      	ldr	r6, [r4, #0]
 80073fa:	1d1d      	adds	r5, r3, #4
 80073fc:	6960      	ldr	r0, [r4, #20]
 80073fe:	600d      	str	r5, [r1, #0]
 8007400:	0635      	lsls	r5, r6, #24
 8007402:	681b      	ldr	r3, [r3, #0]
 8007404:	d501      	bpl.n	800740a <_printf_i+0x1ce>
 8007406:	6018      	str	r0, [r3, #0]
 8007408:	e002      	b.n	8007410 <_printf_i+0x1d4>
 800740a:	0671      	lsls	r1, r6, #25
 800740c:	d5fb      	bpl.n	8007406 <_printf_i+0x1ca>
 800740e:	8018      	strh	r0, [r3, #0]
 8007410:	2300      	movs	r3, #0
 8007412:	4616      	mov	r6, r2
 8007414:	6123      	str	r3, [r4, #16]
 8007416:	e7ba      	b.n	800738e <_printf_i+0x152>
 8007418:	680b      	ldr	r3, [r1, #0]
 800741a:	1d1a      	adds	r2, r3, #4
 800741c:	600a      	str	r2, [r1, #0]
 800741e:	681e      	ldr	r6, [r3, #0]
 8007420:	2100      	movs	r1, #0
 8007422:	4630      	mov	r0, r6
 8007424:	6862      	ldr	r2, [r4, #4]
 8007426:	f000 fed9 	bl	80081dc <memchr>
 800742a:	b108      	cbz	r0, 8007430 <_printf_i+0x1f4>
 800742c:	1b80      	subs	r0, r0, r6
 800742e:	6060      	str	r0, [r4, #4]
 8007430:	6863      	ldr	r3, [r4, #4]
 8007432:	6123      	str	r3, [r4, #16]
 8007434:	2300      	movs	r3, #0
 8007436:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 800743a:	e7a8      	b.n	800738e <_printf_i+0x152>
 800743c:	4632      	mov	r2, r6
 800743e:	4649      	mov	r1, r9
 8007440:	4640      	mov	r0, r8
 8007442:	6923      	ldr	r3, [r4, #16]
 8007444:	47d0      	blx	sl
 8007446:	3001      	adds	r0, #1
 8007448:	d0ab      	beq.n	80073a2 <_printf_i+0x166>
 800744a:	6823      	ldr	r3, [r4, #0]
 800744c:	079b      	lsls	r3, r3, #30
 800744e:	d413      	bmi.n	8007478 <_printf_i+0x23c>
 8007450:	68e0      	ldr	r0, [r4, #12]
 8007452:	9b03      	ldr	r3, [sp, #12]
 8007454:	4298      	cmp	r0, r3
 8007456:	bfb8      	it	lt
 8007458:	4618      	movlt	r0, r3
 800745a:	e7a4      	b.n	80073a6 <_printf_i+0x16a>
 800745c:	2301      	movs	r3, #1
 800745e:	4632      	mov	r2, r6
 8007460:	4649      	mov	r1, r9
 8007462:	4640      	mov	r0, r8
 8007464:	47d0      	blx	sl
 8007466:	3001      	adds	r0, #1
 8007468:	d09b      	beq.n	80073a2 <_printf_i+0x166>
 800746a:	3501      	adds	r5, #1
 800746c:	68e3      	ldr	r3, [r4, #12]
 800746e:	9903      	ldr	r1, [sp, #12]
 8007470:	1a5b      	subs	r3, r3, r1
 8007472:	42ab      	cmp	r3, r5
 8007474:	dcf2      	bgt.n	800745c <_printf_i+0x220>
 8007476:	e7eb      	b.n	8007450 <_printf_i+0x214>
 8007478:	2500      	movs	r5, #0
 800747a:	f104 0619 	add.w	r6, r4, #25
 800747e:	e7f5      	b.n	800746c <_printf_i+0x230>
 8007480:	0800a66a 	.word	0x0800a66a
 8007484:	0800a67b 	.word	0x0800a67b

08007488 <siprintf>:
 8007488:	b40e      	push	{r1, r2, r3}
 800748a:	f06f 4100 	mvn.w	r1, #2147483648	; 0x80000000
 800748e:	b500      	push	{lr}
 8007490:	b09c      	sub	sp, #112	; 0x70
 8007492:	ab1d      	add	r3, sp, #116	; 0x74
 8007494:	9002      	str	r0, [sp, #8]
 8007496:	9006      	str	r0, [sp, #24]
 8007498:	9107      	str	r1, [sp, #28]
 800749a:	9104      	str	r1, [sp, #16]
 800749c:	4808      	ldr	r0, [pc, #32]	; (80074c0 <siprintf+0x38>)
 800749e:	4909      	ldr	r1, [pc, #36]	; (80074c4 <siprintf+0x3c>)
 80074a0:	f853 2b04 	ldr.w	r2, [r3], #4
 80074a4:	9105      	str	r1, [sp, #20]
 80074a6:	6800      	ldr	r0, [r0, #0]
 80074a8:	a902      	add	r1, sp, #8
 80074aa:	9301      	str	r3, [sp, #4]
 80074ac:	f001 fb36 	bl	8008b1c <_svfiprintf_r>
 80074b0:	2200      	movs	r2, #0
 80074b2:	9b02      	ldr	r3, [sp, #8]
 80074b4:	701a      	strb	r2, [r3, #0]
 80074b6:	b01c      	add	sp, #112	; 0x70
 80074b8:	f85d eb04 	ldr.w	lr, [sp], #4
 80074bc:	b003      	add	sp, #12
 80074be:	4770      	bx	lr
 80074c0:	20000014 	.word	0x20000014
 80074c4:	ffff0208 	.word	0xffff0208

080074c8 <quorem>:
 80074c8:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80074cc:	6903      	ldr	r3, [r0, #16]
 80074ce:	690c      	ldr	r4, [r1, #16]
 80074d0:	4607      	mov	r7, r0
 80074d2:	42a3      	cmp	r3, r4
 80074d4:	f2c0 8083 	blt.w	80075de <quorem+0x116>
 80074d8:	3c01      	subs	r4, #1
 80074da:	f100 0514 	add.w	r5, r0, #20
 80074de:	f101 0814 	add.w	r8, r1, #20
 80074e2:	eb05 0384 	add.w	r3, r5, r4, lsl #2
 80074e6:	9301      	str	r3, [sp, #4]
 80074e8:	f858 3024 	ldr.w	r3, [r8, r4, lsl #2]
 80074ec:	f855 2024 	ldr.w	r2, [r5, r4, lsl #2]
 80074f0:	3301      	adds	r3, #1
 80074f2:	429a      	cmp	r2, r3
 80074f4:	fbb2 f6f3 	udiv	r6, r2, r3
 80074f8:	ea4f 0b84 	mov.w	fp, r4, lsl #2
 80074fc:	eb08 0984 	add.w	r9, r8, r4, lsl #2
 8007500:	d332      	bcc.n	8007568 <quorem+0xa0>
 8007502:	f04f 0e00 	mov.w	lr, #0
 8007506:	4640      	mov	r0, r8
 8007508:	46ac      	mov	ip, r5
 800750a:	46f2      	mov	sl, lr
 800750c:	f850 2b04 	ldr.w	r2, [r0], #4
 8007510:	b293      	uxth	r3, r2
 8007512:	fb06 e303 	mla	r3, r6, r3, lr
 8007516:	0c12      	lsrs	r2, r2, #16
 8007518:	ea4f 4e13 	mov.w	lr, r3, lsr #16
 800751c:	fb06 e202 	mla	r2, r6, r2, lr
 8007520:	b29b      	uxth	r3, r3
 8007522:	ebaa 0303 	sub.w	r3, sl, r3
 8007526:	f8dc a000 	ldr.w	sl, [ip]
 800752a:	ea4f 4e12 	mov.w	lr, r2, lsr #16
 800752e:	fa1f fa8a 	uxth.w	sl, sl
 8007532:	4453      	add	r3, sl
 8007534:	fa1f fa82 	uxth.w	sl, r2
 8007538:	f8dc 2000 	ldr.w	r2, [ip]
 800753c:	4581      	cmp	r9, r0
 800753e:	ebca 4212 	rsb	r2, sl, r2, lsr #16
 8007542:	eb02 4223 	add.w	r2, r2, r3, asr #16
 8007546:	b29b      	uxth	r3, r3
 8007548:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 800754c:	ea4f 4a22 	mov.w	sl, r2, asr #16
 8007550:	f84c 3b04 	str.w	r3, [ip], #4
 8007554:	d2da      	bcs.n	800750c <quorem+0x44>
 8007556:	f855 300b 	ldr.w	r3, [r5, fp]
 800755a:	b92b      	cbnz	r3, 8007568 <quorem+0xa0>
 800755c:	9b01      	ldr	r3, [sp, #4]
 800755e:	3b04      	subs	r3, #4
 8007560:	429d      	cmp	r5, r3
 8007562:	461a      	mov	r2, r3
 8007564:	d32f      	bcc.n	80075c6 <quorem+0xfe>
 8007566:	613c      	str	r4, [r7, #16]
 8007568:	4638      	mov	r0, r7
 800756a:	f001 f8bf 	bl	80086ec <__mcmp>
 800756e:	2800      	cmp	r0, #0
 8007570:	db25      	blt.n	80075be <quorem+0xf6>
 8007572:	4628      	mov	r0, r5
 8007574:	f04f 0c00 	mov.w	ip, #0
 8007578:	3601      	adds	r6, #1
 800757a:	f858 1b04 	ldr.w	r1, [r8], #4
 800757e:	f8d0 e000 	ldr.w	lr, [r0]
 8007582:	b28b      	uxth	r3, r1
 8007584:	ebac 0303 	sub.w	r3, ip, r3
 8007588:	fa1f f28e 	uxth.w	r2, lr
 800758c:	4413      	add	r3, r2
 800758e:	0c0a      	lsrs	r2, r1, #16
 8007590:	ebc2 421e 	rsb	r2, r2, lr, lsr #16
 8007594:	eb02 4223 	add.w	r2, r2, r3, asr #16
 8007598:	b29b      	uxth	r3, r3
 800759a:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 800759e:	45c1      	cmp	r9, r8
 80075a0:	ea4f 4c22 	mov.w	ip, r2, asr #16
 80075a4:	f840 3b04 	str.w	r3, [r0], #4
 80075a8:	d2e7      	bcs.n	800757a <quorem+0xb2>
 80075aa:	f855 2024 	ldr.w	r2, [r5, r4, lsl #2]
 80075ae:	eb05 0384 	add.w	r3, r5, r4, lsl #2
 80075b2:	b922      	cbnz	r2, 80075be <quorem+0xf6>
 80075b4:	3b04      	subs	r3, #4
 80075b6:	429d      	cmp	r5, r3
 80075b8:	461a      	mov	r2, r3
 80075ba:	d30a      	bcc.n	80075d2 <quorem+0x10a>
 80075bc:	613c      	str	r4, [r7, #16]
 80075be:	4630      	mov	r0, r6
 80075c0:	b003      	add	sp, #12
 80075c2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 80075c6:	6812      	ldr	r2, [r2, #0]
 80075c8:	3b04      	subs	r3, #4
 80075ca:	2a00      	cmp	r2, #0
 80075cc:	d1cb      	bne.n	8007566 <quorem+0x9e>
 80075ce:	3c01      	subs	r4, #1
 80075d0:	e7c6      	b.n	8007560 <quorem+0x98>
 80075d2:	6812      	ldr	r2, [r2, #0]
 80075d4:	3b04      	subs	r3, #4
 80075d6:	2a00      	cmp	r2, #0
 80075d8:	d1f0      	bne.n	80075bc <quorem+0xf4>
 80075da:	3c01      	subs	r4, #1
 80075dc:	e7eb      	b.n	80075b6 <quorem+0xee>
 80075de:	2000      	movs	r0, #0
 80075e0:	e7ee      	b.n	80075c0 <quorem+0xf8>
 80075e2:	0000      	movs	r0, r0
 80075e4:	0000      	movs	r0, r0
	...

080075e8 <_dtoa_r>:
 80075e8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80075ec:	4616      	mov	r6, r2
 80075ee:	461f      	mov	r7, r3
 80075f0:	6a44      	ldr	r4, [r0, #36]	; 0x24
 80075f2:	b099      	sub	sp, #100	; 0x64
 80075f4:	4605      	mov	r5, r0
 80075f6:	e9cd 6704 	strd	r6, r7, [sp, #16]
 80075fa:	f8dd 8094 	ldr.w	r8, [sp, #148]	; 0x94
 80075fe:	b974      	cbnz	r4, 800761e <_dtoa_r+0x36>
 8007600:	2010      	movs	r0, #16
 8007602:	f000 fde3 	bl	80081cc <malloc>
 8007606:	4602      	mov	r2, r0
 8007608:	6268      	str	r0, [r5, #36]	; 0x24
 800760a:	b920      	cbnz	r0, 8007616 <_dtoa_r+0x2e>
 800760c:	21ea      	movs	r1, #234	; 0xea
 800760e:	4bae      	ldr	r3, [pc, #696]	; (80078c8 <_dtoa_r+0x2e0>)
 8007610:	48ae      	ldr	r0, [pc, #696]	; (80078cc <_dtoa_r+0x2e4>)
 8007612:	f001 fb93 	bl	8008d3c <__assert_func>
 8007616:	e9c0 4401 	strd	r4, r4, [r0, #4]
 800761a:	6004      	str	r4, [r0, #0]
 800761c:	60c4      	str	r4, [r0, #12]
 800761e:	6a6b      	ldr	r3, [r5, #36]	; 0x24
 8007620:	6819      	ldr	r1, [r3, #0]
 8007622:	b151      	cbz	r1, 800763a <_dtoa_r+0x52>
 8007624:	685a      	ldr	r2, [r3, #4]
 8007626:	2301      	movs	r3, #1
 8007628:	4093      	lsls	r3, r2
 800762a:	604a      	str	r2, [r1, #4]
 800762c:	608b      	str	r3, [r1, #8]
 800762e:	4628      	mov	r0, r5
 8007630:	f000 fe22 	bl	8008278 <_Bfree>
 8007634:	2200      	movs	r2, #0
 8007636:	6a6b      	ldr	r3, [r5, #36]	; 0x24
 8007638:	601a      	str	r2, [r3, #0]
 800763a:	1e3b      	subs	r3, r7, #0
 800763c:	bfaf      	iteee	ge
 800763e:	2300      	movge	r3, #0
 8007640:	2201      	movlt	r2, #1
 8007642:	f023 4300 	biclt.w	r3, r3, #2147483648	; 0x80000000
 8007646:	9305      	strlt	r3, [sp, #20]
 8007648:	bfa8      	it	ge
 800764a:	f8c8 3000 	strge.w	r3, [r8]
 800764e:	f8dd 9014 	ldr.w	r9, [sp, #20]
 8007652:	4b9f      	ldr	r3, [pc, #636]	; (80078d0 <_dtoa_r+0x2e8>)
 8007654:	bfb8      	it	lt
 8007656:	f8c8 2000 	strlt.w	r2, [r8]
 800765a:	ea33 0309 	bics.w	r3, r3, r9
 800765e:	d119      	bne.n	8007694 <_dtoa_r+0xac>
 8007660:	f242 730f 	movw	r3, #9999	; 0x270f
 8007664:	9a24      	ldr	r2, [sp, #144]	; 0x90
 8007666:	6013      	str	r3, [r2, #0]
 8007668:	f3c9 0313 	ubfx	r3, r9, #0, #20
 800766c:	4333      	orrs	r3, r6
 800766e:	f000 8580 	beq.w	8008172 <_dtoa_r+0xb8a>
 8007672:	9b26      	ldr	r3, [sp, #152]	; 0x98
 8007674:	b953      	cbnz	r3, 800768c <_dtoa_r+0xa4>
 8007676:	4b97      	ldr	r3, [pc, #604]	; (80078d4 <_dtoa_r+0x2ec>)
 8007678:	e022      	b.n	80076c0 <_dtoa_r+0xd8>
 800767a:	4b97      	ldr	r3, [pc, #604]	; (80078d8 <_dtoa_r+0x2f0>)
 800767c:	9308      	str	r3, [sp, #32]
 800767e:	3308      	adds	r3, #8
 8007680:	9a26      	ldr	r2, [sp, #152]	; 0x98
 8007682:	6013      	str	r3, [r2, #0]
 8007684:	9808      	ldr	r0, [sp, #32]
 8007686:	b019      	add	sp, #100	; 0x64
 8007688:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 800768c:	4b91      	ldr	r3, [pc, #580]	; (80078d4 <_dtoa_r+0x2ec>)
 800768e:	9308      	str	r3, [sp, #32]
 8007690:	3303      	adds	r3, #3
 8007692:	e7f5      	b.n	8007680 <_dtoa_r+0x98>
 8007694:	e9dd 3404 	ldrd	r3, r4, [sp, #16]
 8007698:	e9cd 340c 	strd	r3, r4, [sp, #48]	; 0x30
 800769c:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
 80076a0:	2200      	movs	r2, #0
 80076a2:	2300      	movs	r3, #0
 80076a4:	f7f9 f998 	bl	80009d8 <__aeabi_dcmpeq>
 80076a8:	4680      	mov	r8, r0
 80076aa:	b158      	cbz	r0, 80076c4 <_dtoa_r+0xdc>
 80076ac:	2301      	movs	r3, #1
 80076ae:	9a24      	ldr	r2, [sp, #144]	; 0x90
 80076b0:	6013      	str	r3, [r2, #0]
 80076b2:	9b26      	ldr	r3, [sp, #152]	; 0x98
 80076b4:	2b00      	cmp	r3, #0
 80076b6:	f000 8559 	beq.w	800816c <_dtoa_r+0xb84>
 80076ba:	4888      	ldr	r0, [pc, #544]	; (80078dc <_dtoa_r+0x2f4>)
 80076bc:	6018      	str	r0, [r3, #0]
 80076be:	1e43      	subs	r3, r0, #1
 80076c0:	9308      	str	r3, [sp, #32]
 80076c2:	e7df      	b.n	8007684 <_dtoa_r+0x9c>
 80076c4:	ab16      	add	r3, sp, #88	; 0x58
 80076c6:	9301      	str	r3, [sp, #4]
 80076c8:	ab17      	add	r3, sp, #92	; 0x5c
 80076ca:	9300      	str	r3, [sp, #0]
 80076cc:	4628      	mov	r0, r5
 80076ce:	e9dd 230c 	ldrd	r2, r3, [sp, #48]	; 0x30
 80076d2:	f001 f8b7 	bl	8008844 <__d2b>
 80076d6:	f3c9 540a 	ubfx	r4, r9, #20, #11
 80076da:	4682      	mov	sl, r0
 80076dc:	2c00      	cmp	r4, #0
 80076de:	d07e      	beq.n	80077de <_dtoa_r+0x1f6>
 80076e0:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
 80076e4:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 80076e6:	f2a4 34ff 	subw	r4, r4, #1023	; 0x3ff
 80076ea:	f3c3 0313 	ubfx	r3, r3, #0, #20
 80076ee:	f043 517f 	orr.w	r1, r3, #1069547520	; 0x3fc00000
 80076f2:	f441 1140 	orr.w	r1, r1, #3145728	; 0x300000
 80076f6:	f8cd 804c 	str.w	r8, [sp, #76]	; 0x4c
 80076fa:	2200      	movs	r2, #0
 80076fc:	4b78      	ldr	r3, [pc, #480]	; (80078e0 <_dtoa_r+0x2f8>)
 80076fe:	f7f8 fd4b 	bl	8000198 <__aeabi_dsub>
 8007702:	a36b      	add	r3, pc, #428	; (adr r3, 80078b0 <_dtoa_r+0x2c8>)
 8007704:	e9d3 2300 	ldrd	r2, r3, [r3]
 8007708:	f7f8 fefe 	bl	8000508 <__aeabi_dmul>
 800770c:	a36a      	add	r3, pc, #424	; (adr r3, 80078b8 <_dtoa_r+0x2d0>)
 800770e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8007712:	f7f8 fd43 	bl	800019c <__adddf3>
 8007716:	4606      	mov	r6, r0
 8007718:	4620      	mov	r0, r4
 800771a:	460f      	mov	r7, r1
 800771c:	f7f8 fe8a 	bl	8000434 <__aeabi_i2d>
 8007720:	a367      	add	r3, pc, #412	; (adr r3, 80078c0 <_dtoa_r+0x2d8>)
 8007722:	e9d3 2300 	ldrd	r2, r3, [r3]
 8007726:	f7f8 feef 	bl	8000508 <__aeabi_dmul>
 800772a:	4602      	mov	r2, r0
 800772c:	460b      	mov	r3, r1
 800772e:	4630      	mov	r0, r6
 8007730:	4639      	mov	r1, r7
 8007732:	f7f8 fd33 	bl	800019c <__adddf3>
 8007736:	4606      	mov	r6, r0
 8007738:	460f      	mov	r7, r1
 800773a:	f7f9 f995 	bl	8000a68 <__aeabi_d2iz>
 800773e:	2200      	movs	r2, #0
 8007740:	4681      	mov	r9, r0
 8007742:	2300      	movs	r3, #0
 8007744:	4630      	mov	r0, r6
 8007746:	4639      	mov	r1, r7
 8007748:	f7f9 f950 	bl	80009ec <__aeabi_dcmplt>
 800774c:	b148      	cbz	r0, 8007762 <_dtoa_r+0x17a>
 800774e:	4648      	mov	r0, r9
 8007750:	f7f8 fe70 	bl	8000434 <__aeabi_i2d>
 8007754:	4632      	mov	r2, r6
 8007756:	463b      	mov	r3, r7
 8007758:	f7f9 f93e 	bl	80009d8 <__aeabi_dcmpeq>
 800775c:	b908      	cbnz	r0, 8007762 <_dtoa_r+0x17a>
 800775e:	f109 39ff 	add.w	r9, r9, #4294967295	; 0xffffffff
 8007762:	f1b9 0f16 	cmp.w	r9, #22
 8007766:	d857      	bhi.n	8007818 <_dtoa_r+0x230>
 8007768:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
 800776c:	4b5d      	ldr	r3, [pc, #372]	; (80078e4 <_dtoa_r+0x2fc>)
 800776e:	eb03 03c9 	add.w	r3, r3, r9, lsl #3
 8007772:	e9d3 2300 	ldrd	r2, r3, [r3]
 8007776:	f7f9 f939 	bl	80009ec <__aeabi_dcmplt>
 800777a:	2800      	cmp	r0, #0
 800777c:	d04e      	beq.n	800781c <_dtoa_r+0x234>
 800777e:	2300      	movs	r3, #0
 8007780:	f109 39ff 	add.w	r9, r9, #4294967295	; 0xffffffff
 8007784:	930f      	str	r3, [sp, #60]	; 0x3c
 8007786:	9b16      	ldr	r3, [sp, #88]	; 0x58
 8007788:	1b1c      	subs	r4, r3, r4
 800778a:	1e63      	subs	r3, r4, #1
 800778c:	9309      	str	r3, [sp, #36]	; 0x24
 800778e:	bf49      	itett	mi
 8007790:	f1c4 0301 	rsbmi	r3, r4, #1
 8007794:	2300      	movpl	r3, #0
 8007796:	9306      	strmi	r3, [sp, #24]
 8007798:	2300      	movmi	r3, #0
 800779a:	bf54      	ite	pl
 800779c:	9306      	strpl	r3, [sp, #24]
 800779e:	9309      	strmi	r3, [sp, #36]	; 0x24
 80077a0:	f1b9 0f00 	cmp.w	r9, #0
 80077a4:	db3c      	blt.n	8007820 <_dtoa_r+0x238>
 80077a6:	9b09      	ldr	r3, [sp, #36]	; 0x24
 80077a8:	f8cd 9038 	str.w	r9, [sp, #56]	; 0x38
 80077ac:	444b      	add	r3, r9
 80077ae:	9309      	str	r3, [sp, #36]	; 0x24
 80077b0:	2300      	movs	r3, #0
 80077b2:	930a      	str	r3, [sp, #40]	; 0x28
 80077b4:	9b22      	ldr	r3, [sp, #136]	; 0x88
 80077b6:	2b09      	cmp	r3, #9
 80077b8:	d86c      	bhi.n	8007894 <_dtoa_r+0x2ac>
 80077ba:	2b05      	cmp	r3, #5
 80077bc:	bfc4      	itt	gt
 80077be:	3b04      	subgt	r3, #4
 80077c0:	9322      	strgt	r3, [sp, #136]	; 0x88
 80077c2:	9b22      	ldr	r3, [sp, #136]	; 0x88
 80077c4:	bfc8      	it	gt
 80077c6:	2400      	movgt	r4, #0
 80077c8:	f1a3 0302 	sub.w	r3, r3, #2
 80077cc:	bfd8      	it	le
 80077ce:	2401      	movle	r4, #1
 80077d0:	2b03      	cmp	r3, #3
 80077d2:	f200 808b 	bhi.w	80078ec <_dtoa_r+0x304>
 80077d6:	e8df f003 	tbb	[pc, r3]
 80077da:	4f2d      	.short	0x4f2d
 80077dc:	5b4d      	.short	0x5b4d
 80077de:	e9dd 4316 	ldrd	r4, r3, [sp, #88]	; 0x58
 80077e2:	441c      	add	r4, r3
 80077e4:	f204 4332 	addw	r3, r4, #1074	; 0x432
 80077e8:	2b20      	cmp	r3, #32
 80077ea:	bfc3      	ittte	gt
 80077ec:	f1c3 0340 	rsbgt	r3, r3, #64	; 0x40
 80077f0:	f204 4012 	addwgt	r0, r4, #1042	; 0x412
 80077f4:	fa09 f303 	lslgt.w	r3, r9, r3
 80077f8:	f1c3 0320 	rsble	r3, r3, #32
 80077fc:	bfc6      	itte	gt
 80077fe:	fa26 f000 	lsrgt.w	r0, r6, r0
 8007802:	4318      	orrgt	r0, r3
 8007804:	fa06 f003 	lslle.w	r0, r6, r3
 8007808:	f7f8 fe04 	bl	8000414 <__aeabi_ui2d>
 800780c:	2301      	movs	r3, #1
 800780e:	f1a1 71f8 	sub.w	r1, r1, #32505856	; 0x1f00000
 8007812:	3c01      	subs	r4, #1
 8007814:	9313      	str	r3, [sp, #76]	; 0x4c
 8007816:	e770      	b.n	80076fa <_dtoa_r+0x112>
 8007818:	2301      	movs	r3, #1
 800781a:	e7b3      	b.n	8007784 <_dtoa_r+0x19c>
 800781c:	900f      	str	r0, [sp, #60]	; 0x3c
 800781e:	e7b2      	b.n	8007786 <_dtoa_r+0x19e>
 8007820:	9b06      	ldr	r3, [sp, #24]
 8007822:	eba3 0309 	sub.w	r3, r3, r9
 8007826:	9306      	str	r3, [sp, #24]
 8007828:	f1c9 0300 	rsb	r3, r9, #0
 800782c:	930a      	str	r3, [sp, #40]	; 0x28
 800782e:	2300      	movs	r3, #0
 8007830:	930e      	str	r3, [sp, #56]	; 0x38
 8007832:	e7bf      	b.n	80077b4 <_dtoa_r+0x1cc>
 8007834:	2300      	movs	r3, #0
 8007836:	930b      	str	r3, [sp, #44]	; 0x2c
 8007838:	9b23      	ldr	r3, [sp, #140]	; 0x8c
 800783a:	2b00      	cmp	r3, #0
 800783c:	dc59      	bgt.n	80078f2 <_dtoa_r+0x30a>
 800783e:	f04f 0b01 	mov.w	fp, #1
 8007842:	465b      	mov	r3, fp
 8007844:	f8cd b008 	str.w	fp, [sp, #8]
 8007848:	f8cd b08c 	str.w	fp, [sp, #140]	; 0x8c
 800784c:	2200      	movs	r2, #0
 800784e:	6a68      	ldr	r0, [r5, #36]	; 0x24
 8007850:	6042      	str	r2, [r0, #4]
 8007852:	2204      	movs	r2, #4
 8007854:	f102 0614 	add.w	r6, r2, #20
 8007858:	429e      	cmp	r6, r3
 800785a:	6841      	ldr	r1, [r0, #4]
 800785c:	d94f      	bls.n	80078fe <_dtoa_r+0x316>
 800785e:	4628      	mov	r0, r5
 8007860:	f000 fcca 	bl	80081f8 <_Balloc>
 8007864:	9008      	str	r0, [sp, #32]
 8007866:	2800      	cmp	r0, #0
 8007868:	d14d      	bne.n	8007906 <_dtoa_r+0x31e>
 800786a:	4602      	mov	r2, r0
 800786c:	f44f 71d5 	mov.w	r1, #426	; 0x1aa
 8007870:	4b1d      	ldr	r3, [pc, #116]	; (80078e8 <_dtoa_r+0x300>)
 8007872:	e6cd      	b.n	8007610 <_dtoa_r+0x28>
 8007874:	2301      	movs	r3, #1
 8007876:	e7de      	b.n	8007836 <_dtoa_r+0x24e>
 8007878:	2300      	movs	r3, #0
 800787a:	930b      	str	r3, [sp, #44]	; 0x2c
 800787c:	9b23      	ldr	r3, [sp, #140]	; 0x8c
 800787e:	eb09 0b03 	add.w	fp, r9, r3
 8007882:	f10b 0301 	add.w	r3, fp, #1
 8007886:	2b01      	cmp	r3, #1
 8007888:	9302      	str	r3, [sp, #8]
 800788a:	bfb8      	it	lt
 800788c:	2301      	movlt	r3, #1
 800788e:	e7dd      	b.n	800784c <_dtoa_r+0x264>
 8007890:	2301      	movs	r3, #1
 8007892:	e7f2      	b.n	800787a <_dtoa_r+0x292>
 8007894:	2401      	movs	r4, #1
 8007896:	2300      	movs	r3, #0
 8007898:	940b      	str	r4, [sp, #44]	; 0x2c
 800789a:	9322      	str	r3, [sp, #136]	; 0x88
 800789c:	f04f 3bff 	mov.w	fp, #4294967295	; 0xffffffff
 80078a0:	2200      	movs	r2, #0
 80078a2:	2312      	movs	r3, #18
 80078a4:	f8cd b008 	str.w	fp, [sp, #8]
 80078a8:	9223      	str	r2, [sp, #140]	; 0x8c
 80078aa:	e7cf      	b.n	800784c <_dtoa_r+0x264>
 80078ac:	f3af 8000 	nop.w
 80078b0:	636f4361 	.word	0x636f4361
 80078b4:	3fd287a7 	.word	0x3fd287a7
 80078b8:	8b60c8b3 	.word	0x8b60c8b3
 80078bc:	3fc68a28 	.word	0x3fc68a28
 80078c0:	509f79fb 	.word	0x509f79fb
 80078c4:	3fd34413 	.word	0x3fd34413
 80078c8:	0800a699 	.word	0x0800a699
 80078cc:	0800a6b0 	.word	0x0800a6b0
 80078d0:	7ff00000 	.word	0x7ff00000
 80078d4:	0800a695 	.word	0x0800a695
 80078d8:	0800a68c 	.word	0x0800a68c
 80078dc:	0800a669 	.word	0x0800a669
 80078e0:	3ff80000 	.word	0x3ff80000
 80078e4:	0800a7a8 	.word	0x0800a7a8
 80078e8:	0800a70f 	.word	0x0800a70f
 80078ec:	2301      	movs	r3, #1
 80078ee:	930b      	str	r3, [sp, #44]	; 0x2c
 80078f0:	e7d4      	b.n	800789c <_dtoa_r+0x2b4>
 80078f2:	f8dd b08c 	ldr.w	fp, [sp, #140]	; 0x8c
 80078f6:	465b      	mov	r3, fp
 80078f8:	f8cd b008 	str.w	fp, [sp, #8]
 80078fc:	e7a6      	b.n	800784c <_dtoa_r+0x264>
 80078fe:	3101      	adds	r1, #1
 8007900:	6041      	str	r1, [r0, #4]
 8007902:	0052      	lsls	r2, r2, #1
 8007904:	e7a6      	b.n	8007854 <_dtoa_r+0x26c>
 8007906:	6a6b      	ldr	r3, [r5, #36]	; 0x24
 8007908:	9a08      	ldr	r2, [sp, #32]
 800790a:	601a      	str	r2, [r3, #0]
 800790c:	9b02      	ldr	r3, [sp, #8]
 800790e:	2b0e      	cmp	r3, #14
 8007910:	f200 80a8 	bhi.w	8007a64 <_dtoa_r+0x47c>
 8007914:	2c00      	cmp	r4, #0
 8007916:	f000 80a5 	beq.w	8007a64 <_dtoa_r+0x47c>
 800791a:	f1b9 0f00 	cmp.w	r9, #0
 800791e:	dd34      	ble.n	800798a <_dtoa_r+0x3a2>
 8007920:	4a9a      	ldr	r2, [pc, #616]	; (8007b8c <_dtoa_r+0x5a4>)
 8007922:	f009 030f 	and.w	r3, r9, #15
 8007926:	eb02 03c3 	add.w	r3, r2, r3, lsl #3
 800792a:	f419 7f80 	tst.w	r9, #256	; 0x100
 800792e:	e9d3 3400 	ldrd	r3, r4, [r3]
 8007932:	e9cd 3410 	strd	r3, r4, [sp, #64]	; 0x40
 8007936:	ea4f 1429 	mov.w	r4, r9, asr #4
 800793a:	d016      	beq.n	800796a <_dtoa_r+0x382>
 800793c:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
 8007940:	4b93      	ldr	r3, [pc, #588]	; (8007b90 <_dtoa_r+0x5a8>)
 8007942:	2703      	movs	r7, #3
 8007944:	e9d3 2308 	ldrd	r2, r3, [r3, #32]
 8007948:	f7f8 ff08 	bl	800075c <__aeabi_ddiv>
 800794c:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8007950:	f004 040f 	and.w	r4, r4, #15
 8007954:	4e8e      	ldr	r6, [pc, #568]	; (8007b90 <_dtoa_r+0x5a8>)
 8007956:	b954      	cbnz	r4, 800796e <_dtoa_r+0x386>
 8007958:	e9dd 2310 	ldrd	r2, r3, [sp, #64]	; 0x40
 800795c:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007960:	f7f8 fefc 	bl	800075c <__aeabi_ddiv>
 8007964:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8007968:	e029      	b.n	80079be <_dtoa_r+0x3d6>
 800796a:	2702      	movs	r7, #2
 800796c:	e7f2      	b.n	8007954 <_dtoa_r+0x36c>
 800796e:	07e1      	lsls	r1, r4, #31
 8007970:	d508      	bpl.n	8007984 <_dtoa_r+0x39c>
 8007972:	e9dd 0110 	ldrd	r0, r1, [sp, #64]	; 0x40
 8007976:	e9d6 2300 	ldrd	r2, r3, [r6]
 800797a:	f7f8 fdc5 	bl	8000508 <__aeabi_dmul>
 800797e:	e9cd 0110 	strd	r0, r1, [sp, #64]	; 0x40
 8007982:	3701      	adds	r7, #1
 8007984:	1064      	asrs	r4, r4, #1
 8007986:	3608      	adds	r6, #8
 8007988:	e7e5      	b.n	8007956 <_dtoa_r+0x36e>
 800798a:	f000 80a5 	beq.w	8007ad8 <_dtoa_r+0x4f0>
 800798e:	e9dd 010c 	ldrd	r0, r1, [sp, #48]	; 0x30
 8007992:	f1c9 0400 	rsb	r4, r9, #0
 8007996:	4b7d      	ldr	r3, [pc, #500]	; (8007b8c <_dtoa_r+0x5a4>)
 8007998:	f004 020f 	and.w	r2, r4, #15
 800799c:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
 80079a0:	e9d3 2300 	ldrd	r2, r3, [r3]
 80079a4:	f7f8 fdb0 	bl	8000508 <__aeabi_dmul>
 80079a8:	2702      	movs	r7, #2
 80079aa:	2300      	movs	r3, #0
 80079ac:	e9cd 0104 	strd	r0, r1, [sp, #16]
 80079b0:	4e77      	ldr	r6, [pc, #476]	; (8007b90 <_dtoa_r+0x5a8>)
 80079b2:	1124      	asrs	r4, r4, #4
 80079b4:	2c00      	cmp	r4, #0
 80079b6:	f040 8084 	bne.w	8007ac2 <_dtoa_r+0x4da>
 80079ba:	2b00      	cmp	r3, #0
 80079bc:	d1d2      	bne.n	8007964 <_dtoa_r+0x37c>
 80079be:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
 80079c0:	2b00      	cmp	r3, #0
 80079c2:	f000 808b 	beq.w	8007adc <_dtoa_r+0x4f4>
 80079c6:	e9dd 3404 	ldrd	r3, r4, [sp, #16]
 80079ca:	e9cd 3410 	strd	r3, r4, [sp, #64]	; 0x40
 80079ce:	e9dd 0110 	ldrd	r0, r1, [sp, #64]	; 0x40
 80079d2:	2200      	movs	r2, #0
 80079d4:	4b6f      	ldr	r3, [pc, #444]	; (8007b94 <_dtoa_r+0x5ac>)
 80079d6:	f7f9 f809 	bl	80009ec <__aeabi_dcmplt>
 80079da:	2800      	cmp	r0, #0
 80079dc:	d07e      	beq.n	8007adc <_dtoa_r+0x4f4>
 80079de:	9b02      	ldr	r3, [sp, #8]
 80079e0:	2b00      	cmp	r3, #0
 80079e2:	d07b      	beq.n	8007adc <_dtoa_r+0x4f4>
 80079e4:	f1bb 0f00 	cmp.w	fp, #0
 80079e8:	dd38      	ble.n	8007a5c <_dtoa_r+0x474>
 80079ea:	e9dd 0110 	ldrd	r0, r1, [sp, #64]	; 0x40
 80079ee:	2200      	movs	r2, #0
 80079f0:	4b69      	ldr	r3, [pc, #420]	; (8007b98 <_dtoa_r+0x5b0>)
 80079f2:	f7f8 fd89 	bl	8000508 <__aeabi_dmul>
 80079f6:	465c      	mov	r4, fp
 80079f8:	e9cd 0104 	strd	r0, r1, [sp, #16]
 80079fc:	f109 38ff 	add.w	r8, r9, #4294967295	; 0xffffffff
 8007a00:	3701      	adds	r7, #1
 8007a02:	4638      	mov	r0, r7
 8007a04:	f7f8 fd16 	bl	8000434 <__aeabi_i2d>
 8007a08:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8007a0c:	f7f8 fd7c 	bl	8000508 <__aeabi_dmul>
 8007a10:	2200      	movs	r2, #0
 8007a12:	4b62      	ldr	r3, [pc, #392]	; (8007b9c <_dtoa_r+0x5b4>)
 8007a14:	f7f8 fbc2 	bl	800019c <__adddf3>
 8007a18:	f1a1 7650 	sub.w	r6, r1, #54525952	; 0x3400000
 8007a1c:	e9cd 0110 	strd	r0, r1, [sp, #64]	; 0x40
 8007a20:	9611      	str	r6, [sp, #68]	; 0x44
 8007a22:	2c00      	cmp	r4, #0
 8007a24:	d15d      	bne.n	8007ae2 <_dtoa_r+0x4fa>
 8007a26:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007a2a:	2200      	movs	r2, #0
 8007a2c:	4b5c      	ldr	r3, [pc, #368]	; (8007ba0 <_dtoa_r+0x5b8>)
 8007a2e:	f7f8 fbb3 	bl	8000198 <__aeabi_dsub>
 8007a32:	4602      	mov	r2, r0
 8007a34:	460b      	mov	r3, r1
 8007a36:	e9cd 2304 	strd	r2, r3, [sp, #16]
 8007a3a:	4633      	mov	r3, r6
 8007a3c:	9a10      	ldr	r2, [sp, #64]	; 0x40
 8007a3e:	f7f8 fff3 	bl	8000a28 <__aeabi_dcmpgt>
 8007a42:	2800      	cmp	r0, #0
 8007a44:	f040 829e 	bne.w	8007f84 <_dtoa_r+0x99c>
 8007a48:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007a4c:	9a10      	ldr	r2, [sp, #64]	; 0x40
 8007a4e:	f106 4300 	add.w	r3, r6, #2147483648	; 0x80000000
 8007a52:	f7f8 ffcb 	bl	80009ec <__aeabi_dcmplt>
 8007a56:	2800      	cmp	r0, #0
 8007a58:	f040 8292 	bne.w	8007f80 <_dtoa_r+0x998>
 8007a5c:	e9dd 340c 	ldrd	r3, r4, [sp, #48]	; 0x30
 8007a60:	e9cd 3404 	strd	r3, r4, [sp, #16]
 8007a64:	9b17      	ldr	r3, [sp, #92]	; 0x5c
 8007a66:	2b00      	cmp	r3, #0
 8007a68:	f2c0 8153 	blt.w	8007d12 <_dtoa_r+0x72a>
 8007a6c:	f1b9 0f0e 	cmp.w	r9, #14
 8007a70:	f300 814f 	bgt.w	8007d12 <_dtoa_r+0x72a>
 8007a74:	4b45      	ldr	r3, [pc, #276]	; (8007b8c <_dtoa_r+0x5a4>)
 8007a76:	eb03 03c9 	add.w	r3, r3, r9, lsl #3
 8007a7a:	e9d3 3400 	ldrd	r3, r4, [r3]
 8007a7e:	e9cd 3406 	strd	r3, r4, [sp, #24]
 8007a82:	9b23      	ldr	r3, [sp, #140]	; 0x8c
 8007a84:	2b00      	cmp	r3, #0
 8007a86:	f280 80db 	bge.w	8007c40 <_dtoa_r+0x658>
 8007a8a:	9b02      	ldr	r3, [sp, #8]
 8007a8c:	2b00      	cmp	r3, #0
 8007a8e:	f300 80d7 	bgt.w	8007c40 <_dtoa_r+0x658>
 8007a92:	f040 8274 	bne.w	8007f7e <_dtoa_r+0x996>
 8007a96:	e9dd 0106 	ldrd	r0, r1, [sp, #24]
 8007a9a:	2200      	movs	r2, #0
 8007a9c:	4b40      	ldr	r3, [pc, #256]	; (8007ba0 <_dtoa_r+0x5b8>)
 8007a9e:	f7f8 fd33 	bl	8000508 <__aeabi_dmul>
 8007aa2:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8007aa6:	f7f8 ffb5 	bl	8000a14 <__aeabi_dcmpge>
 8007aaa:	9c02      	ldr	r4, [sp, #8]
 8007aac:	4626      	mov	r6, r4
 8007aae:	2800      	cmp	r0, #0
 8007ab0:	f040 824a 	bne.w	8007f48 <_dtoa_r+0x960>
 8007ab4:	2331      	movs	r3, #49	; 0x31
 8007ab6:	9f08      	ldr	r7, [sp, #32]
 8007ab8:	f109 0901 	add.w	r9, r9, #1
 8007abc:	f807 3b01 	strb.w	r3, [r7], #1
 8007ac0:	e246      	b.n	8007f50 <_dtoa_r+0x968>
 8007ac2:	07e2      	lsls	r2, r4, #31
 8007ac4:	d505      	bpl.n	8007ad2 <_dtoa_r+0x4ea>
 8007ac6:	e9d6 2300 	ldrd	r2, r3, [r6]
 8007aca:	f7f8 fd1d 	bl	8000508 <__aeabi_dmul>
 8007ace:	2301      	movs	r3, #1
 8007ad0:	3701      	adds	r7, #1
 8007ad2:	1064      	asrs	r4, r4, #1
 8007ad4:	3608      	adds	r6, #8
 8007ad6:	e76d      	b.n	80079b4 <_dtoa_r+0x3cc>
 8007ad8:	2702      	movs	r7, #2
 8007ada:	e770      	b.n	80079be <_dtoa_r+0x3d6>
 8007adc:	46c8      	mov	r8, r9
 8007ade:	9c02      	ldr	r4, [sp, #8]
 8007ae0:	e78f      	b.n	8007a02 <_dtoa_r+0x41a>
 8007ae2:	9908      	ldr	r1, [sp, #32]
 8007ae4:	4b29      	ldr	r3, [pc, #164]	; (8007b8c <_dtoa_r+0x5a4>)
 8007ae6:	4421      	add	r1, r4
 8007ae8:	9112      	str	r1, [sp, #72]	; 0x48
 8007aea:	990b      	ldr	r1, [sp, #44]	; 0x2c
 8007aec:	eb03 03c4 	add.w	r3, r3, r4, lsl #3
 8007af0:	e9dd 6710 	ldrd	r6, r7, [sp, #64]	; 0x40
 8007af4:	e953 2302 	ldrd	r2, r3, [r3, #-8]
 8007af8:	2900      	cmp	r1, #0
 8007afa:	d055      	beq.n	8007ba8 <_dtoa_r+0x5c0>
 8007afc:	2000      	movs	r0, #0
 8007afe:	4929      	ldr	r1, [pc, #164]	; (8007ba4 <_dtoa_r+0x5bc>)
 8007b00:	f7f8 fe2c 	bl	800075c <__aeabi_ddiv>
 8007b04:	463b      	mov	r3, r7
 8007b06:	4632      	mov	r2, r6
 8007b08:	f7f8 fb46 	bl	8000198 <__aeabi_dsub>
 8007b0c:	e9cd 0110 	strd	r0, r1, [sp, #64]	; 0x40
 8007b10:	9f08      	ldr	r7, [sp, #32]
 8007b12:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007b16:	f7f8 ffa7 	bl	8000a68 <__aeabi_d2iz>
 8007b1a:	4604      	mov	r4, r0
 8007b1c:	f7f8 fc8a 	bl	8000434 <__aeabi_i2d>
 8007b20:	4602      	mov	r2, r0
 8007b22:	460b      	mov	r3, r1
 8007b24:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007b28:	f7f8 fb36 	bl	8000198 <__aeabi_dsub>
 8007b2c:	4602      	mov	r2, r0
 8007b2e:	460b      	mov	r3, r1
 8007b30:	3430      	adds	r4, #48	; 0x30
 8007b32:	e9cd 2304 	strd	r2, r3, [sp, #16]
 8007b36:	e9dd 2310 	ldrd	r2, r3, [sp, #64]	; 0x40
 8007b3a:	f807 4b01 	strb.w	r4, [r7], #1
 8007b3e:	f7f8 ff55 	bl	80009ec <__aeabi_dcmplt>
 8007b42:	2800      	cmp	r0, #0
 8007b44:	d174      	bne.n	8007c30 <_dtoa_r+0x648>
 8007b46:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8007b4a:	2000      	movs	r0, #0
 8007b4c:	4911      	ldr	r1, [pc, #68]	; (8007b94 <_dtoa_r+0x5ac>)
 8007b4e:	f7f8 fb23 	bl	8000198 <__aeabi_dsub>
 8007b52:	e9dd 2310 	ldrd	r2, r3, [sp, #64]	; 0x40
 8007b56:	f7f8 ff49 	bl	80009ec <__aeabi_dcmplt>
 8007b5a:	2800      	cmp	r0, #0
 8007b5c:	f040 80b6 	bne.w	8007ccc <_dtoa_r+0x6e4>
 8007b60:	9b12      	ldr	r3, [sp, #72]	; 0x48
 8007b62:	429f      	cmp	r7, r3
 8007b64:	f43f af7a 	beq.w	8007a5c <_dtoa_r+0x474>
 8007b68:	e9dd 0110 	ldrd	r0, r1, [sp, #64]	; 0x40
 8007b6c:	2200      	movs	r2, #0
 8007b6e:	4b0a      	ldr	r3, [pc, #40]	; (8007b98 <_dtoa_r+0x5b0>)
 8007b70:	f7f8 fcca 	bl	8000508 <__aeabi_dmul>
 8007b74:	2200      	movs	r2, #0
 8007b76:	e9cd 0110 	strd	r0, r1, [sp, #64]	; 0x40
 8007b7a:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007b7e:	4b06      	ldr	r3, [pc, #24]	; (8007b98 <_dtoa_r+0x5b0>)
 8007b80:	f7f8 fcc2 	bl	8000508 <__aeabi_dmul>
 8007b84:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8007b88:	e7c3      	b.n	8007b12 <_dtoa_r+0x52a>
 8007b8a:	bf00      	nop
 8007b8c:	0800a7a8 	.word	0x0800a7a8
 8007b90:	0800a780 	.word	0x0800a780
 8007b94:	3ff00000 	.word	0x3ff00000
 8007b98:	40240000 	.word	0x40240000
 8007b9c:	401c0000 	.word	0x401c0000
 8007ba0:	40140000 	.word	0x40140000
 8007ba4:	3fe00000 	.word	0x3fe00000
 8007ba8:	4630      	mov	r0, r6
 8007baa:	4639      	mov	r1, r7
 8007bac:	f7f8 fcac 	bl	8000508 <__aeabi_dmul>
 8007bb0:	9b12      	ldr	r3, [sp, #72]	; 0x48
 8007bb2:	e9cd 0110 	strd	r0, r1, [sp, #64]	; 0x40
 8007bb6:	9c08      	ldr	r4, [sp, #32]
 8007bb8:	9314      	str	r3, [sp, #80]	; 0x50
 8007bba:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007bbe:	f7f8 ff53 	bl	8000a68 <__aeabi_d2iz>
 8007bc2:	9015      	str	r0, [sp, #84]	; 0x54
 8007bc4:	f7f8 fc36 	bl	8000434 <__aeabi_i2d>
 8007bc8:	4602      	mov	r2, r0
 8007bca:	460b      	mov	r3, r1
 8007bcc:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007bd0:	f7f8 fae2 	bl	8000198 <__aeabi_dsub>
 8007bd4:	9b15      	ldr	r3, [sp, #84]	; 0x54
 8007bd6:	4606      	mov	r6, r0
 8007bd8:	3330      	adds	r3, #48	; 0x30
 8007bda:	f804 3b01 	strb.w	r3, [r4], #1
 8007bde:	9b12      	ldr	r3, [sp, #72]	; 0x48
 8007be0:	460f      	mov	r7, r1
 8007be2:	429c      	cmp	r4, r3
 8007be4:	f04f 0200 	mov.w	r2, #0
 8007be8:	d124      	bne.n	8007c34 <_dtoa_r+0x64c>
 8007bea:	e9dd 0110 	ldrd	r0, r1, [sp, #64]	; 0x40
 8007bee:	4bb3      	ldr	r3, [pc, #716]	; (8007ebc <_dtoa_r+0x8d4>)
 8007bf0:	f7f8 fad4 	bl	800019c <__adddf3>
 8007bf4:	4602      	mov	r2, r0
 8007bf6:	460b      	mov	r3, r1
 8007bf8:	4630      	mov	r0, r6
 8007bfa:	4639      	mov	r1, r7
 8007bfc:	f7f8 ff14 	bl	8000a28 <__aeabi_dcmpgt>
 8007c00:	2800      	cmp	r0, #0
 8007c02:	d162      	bne.n	8007cca <_dtoa_r+0x6e2>
 8007c04:	e9dd 2310 	ldrd	r2, r3, [sp, #64]	; 0x40
 8007c08:	2000      	movs	r0, #0
 8007c0a:	49ac      	ldr	r1, [pc, #688]	; (8007ebc <_dtoa_r+0x8d4>)
 8007c0c:	f7f8 fac4 	bl	8000198 <__aeabi_dsub>
 8007c10:	4602      	mov	r2, r0
 8007c12:	460b      	mov	r3, r1
 8007c14:	4630      	mov	r0, r6
 8007c16:	4639      	mov	r1, r7
 8007c18:	f7f8 fee8 	bl	80009ec <__aeabi_dcmplt>
 8007c1c:	2800      	cmp	r0, #0
 8007c1e:	f43f af1d 	beq.w	8007a5c <_dtoa_r+0x474>
 8007c22:	9f14      	ldr	r7, [sp, #80]	; 0x50
 8007c24:	1e7b      	subs	r3, r7, #1
 8007c26:	9314      	str	r3, [sp, #80]	; 0x50
 8007c28:	f817 3c01 	ldrb.w	r3, [r7, #-1]
 8007c2c:	2b30      	cmp	r3, #48	; 0x30
 8007c2e:	d0f8      	beq.n	8007c22 <_dtoa_r+0x63a>
 8007c30:	46c1      	mov	r9, r8
 8007c32:	e03a      	b.n	8007caa <_dtoa_r+0x6c2>
 8007c34:	4ba2      	ldr	r3, [pc, #648]	; (8007ec0 <_dtoa_r+0x8d8>)
 8007c36:	f7f8 fc67 	bl	8000508 <__aeabi_dmul>
 8007c3a:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8007c3e:	e7bc      	b.n	8007bba <_dtoa_r+0x5d2>
 8007c40:	9f08      	ldr	r7, [sp, #32]
 8007c42:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
 8007c46:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007c4a:	f7f8 fd87 	bl	800075c <__aeabi_ddiv>
 8007c4e:	f7f8 ff0b 	bl	8000a68 <__aeabi_d2iz>
 8007c52:	4604      	mov	r4, r0
 8007c54:	f7f8 fbee 	bl	8000434 <__aeabi_i2d>
 8007c58:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
 8007c5c:	f7f8 fc54 	bl	8000508 <__aeabi_dmul>
 8007c60:	f104 0630 	add.w	r6, r4, #48	; 0x30
 8007c64:	460b      	mov	r3, r1
 8007c66:	4602      	mov	r2, r0
 8007c68:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8007c6c:	f7f8 fa94 	bl	8000198 <__aeabi_dsub>
 8007c70:	f807 6b01 	strb.w	r6, [r7], #1
 8007c74:	9e08      	ldr	r6, [sp, #32]
 8007c76:	9b02      	ldr	r3, [sp, #8]
 8007c78:	1bbe      	subs	r6, r7, r6
 8007c7a:	42b3      	cmp	r3, r6
 8007c7c:	d13a      	bne.n	8007cf4 <_dtoa_r+0x70c>
 8007c7e:	4602      	mov	r2, r0
 8007c80:	460b      	mov	r3, r1
 8007c82:	f7f8 fa8b 	bl	800019c <__adddf3>
 8007c86:	4602      	mov	r2, r0
 8007c88:	460b      	mov	r3, r1
 8007c8a:	e9cd 2302 	strd	r2, r3, [sp, #8]
 8007c8e:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
 8007c92:	f7f8 fec9 	bl	8000a28 <__aeabi_dcmpgt>
 8007c96:	bb58      	cbnz	r0, 8007cf0 <_dtoa_r+0x708>
 8007c98:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
 8007c9c:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8007ca0:	f7f8 fe9a 	bl	80009d8 <__aeabi_dcmpeq>
 8007ca4:	b108      	cbz	r0, 8007caa <_dtoa_r+0x6c2>
 8007ca6:	07e1      	lsls	r1, r4, #31
 8007ca8:	d422      	bmi.n	8007cf0 <_dtoa_r+0x708>
 8007caa:	4628      	mov	r0, r5
 8007cac:	4651      	mov	r1, sl
 8007cae:	f000 fae3 	bl	8008278 <_Bfree>
 8007cb2:	2300      	movs	r3, #0
 8007cb4:	703b      	strb	r3, [r7, #0]
 8007cb6:	9b24      	ldr	r3, [sp, #144]	; 0x90
 8007cb8:	f109 0001 	add.w	r0, r9, #1
 8007cbc:	6018      	str	r0, [r3, #0]
 8007cbe:	9b26      	ldr	r3, [sp, #152]	; 0x98
 8007cc0:	2b00      	cmp	r3, #0
 8007cc2:	f43f acdf 	beq.w	8007684 <_dtoa_r+0x9c>
 8007cc6:	601f      	str	r7, [r3, #0]
 8007cc8:	e4dc      	b.n	8007684 <_dtoa_r+0x9c>
 8007cca:	4627      	mov	r7, r4
 8007ccc:	463b      	mov	r3, r7
 8007cce:	461f      	mov	r7, r3
 8007cd0:	f813 2d01 	ldrb.w	r2, [r3, #-1]!
 8007cd4:	2a39      	cmp	r2, #57	; 0x39
 8007cd6:	d107      	bne.n	8007ce8 <_dtoa_r+0x700>
 8007cd8:	9a08      	ldr	r2, [sp, #32]
 8007cda:	429a      	cmp	r2, r3
 8007cdc:	d1f7      	bne.n	8007cce <_dtoa_r+0x6e6>
 8007cde:	2230      	movs	r2, #48	; 0x30
 8007ce0:	9908      	ldr	r1, [sp, #32]
 8007ce2:	f108 0801 	add.w	r8, r8, #1
 8007ce6:	700a      	strb	r2, [r1, #0]
 8007ce8:	781a      	ldrb	r2, [r3, #0]
 8007cea:	3201      	adds	r2, #1
 8007cec:	701a      	strb	r2, [r3, #0]
 8007cee:	e79f      	b.n	8007c30 <_dtoa_r+0x648>
 8007cf0:	46c8      	mov	r8, r9
 8007cf2:	e7eb      	b.n	8007ccc <_dtoa_r+0x6e4>
 8007cf4:	2200      	movs	r2, #0
 8007cf6:	4b72      	ldr	r3, [pc, #456]	; (8007ec0 <_dtoa_r+0x8d8>)
 8007cf8:	f7f8 fc06 	bl	8000508 <__aeabi_dmul>
 8007cfc:	4602      	mov	r2, r0
 8007cfe:	460b      	mov	r3, r1
 8007d00:	e9cd 2304 	strd	r2, r3, [sp, #16]
 8007d04:	2200      	movs	r2, #0
 8007d06:	2300      	movs	r3, #0
 8007d08:	f7f8 fe66 	bl	80009d8 <__aeabi_dcmpeq>
 8007d0c:	2800      	cmp	r0, #0
 8007d0e:	d098      	beq.n	8007c42 <_dtoa_r+0x65a>
 8007d10:	e7cb      	b.n	8007caa <_dtoa_r+0x6c2>
 8007d12:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
 8007d14:	2a00      	cmp	r2, #0
 8007d16:	f000 80cd 	beq.w	8007eb4 <_dtoa_r+0x8cc>
 8007d1a:	9a22      	ldr	r2, [sp, #136]	; 0x88
 8007d1c:	2a01      	cmp	r2, #1
 8007d1e:	f300 80af 	bgt.w	8007e80 <_dtoa_r+0x898>
 8007d22:	9a13      	ldr	r2, [sp, #76]	; 0x4c
 8007d24:	2a00      	cmp	r2, #0
 8007d26:	f000 80a7 	beq.w	8007e78 <_dtoa_r+0x890>
 8007d2a:	f203 4333 	addw	r3, r3, #1075	; 0x433
 8007d2e:	9c0a      	ldr	r4, [sp, #40]	; 0x28
 8007d30:	9f06      	ldr	r7, [sp, #24]
 8007d32:	9a06      	ldr	r2, [sp, #24]
 8007d34:	2101      	movs	r1, #1
 8007d36:	441a      	add	r2, r3
 8007d38:	9206      	str	r2, [sp, #24]
 8007d3a:	9a09      	ldr	r2, [sp, #36]	; 0x24
 8007d3c:	4628      	mov	r0, r5
 8007d3e:	441a      	add	r2, r3
 8007d40:	9209      	str	r2, [sp, #36]	; 0x24
 8007d42:	f000 fb53 	bl	80083ec <__i2b>
 8007d46:	4606      	mov	r6, r0
 8007d48:	2f00      	cmp	r7, #0
 8007d4a:	dd0c      	ble.n	8007d66 <_dtoa_r+0x77e>
 8007d4c:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007d4e:	2b00      	cmp	r3, #0
 8007d50:	dd09      	ble.n	8007d66 <_dtoa_r+0x77e>
 8007d52:	42bb      	cmp	r3, r7
 8007d54:	bfa8      	it	ge
 8007d56:	463b      	movge	r3, r7
 8007d58:	9a06      	ldr	r2, [sp, #24]
 8007d5a:	1aff      	subs	r7, r7, r3
 8007d5c:	1ad2      	subs	r2, r2, r3
 8007d5e:	9206      	str	r2, [sp, #24]
 8007d60:	9a09      	ldr	r2, [sp, #36]	; 0x24
 8007d62:	1ad3      	subs	r3, r2, r3
 8007d64:	9309      	str	r3, [sp, #36]	; 0x24
 8007d66:	9b0a      	ldr	r3, [sp, #40]	; 0x28
 8007d68:	b1f3      	cbz	r3, 8007da8 <_dtoa_r+0x7c0>
 8007d6a:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
 8007d6c:	2b00      	cmp	r3, #0
 8007d6e:	f000 80a9 	beq.w	8007ec4 <_dtoa_r+0x8dc>
 8007d72:	2c00      	cmp	r4, #0
 8007d74:	dd10      	ble.n	8007d98 <_dtoa_r+0x7b0>
 8007d76:	4631      	mov	r1, r6
 8007d78:	4622      	mov	r2, r4
 8007d7a:	4628      	mov	r0, r5
 8007d7c:	f000 fbf0 	bl	8008560 <__pow5mult>
 8007d80:	4652      	mov	r2, sl
 8007d82:	4601      	mov	r1, r0
 8007d84:	4606      	mov	r6, r0
 8007d86:	4628      	mov	r0, r5
 8007d88:	f000 fb46 	bl	8008418 <__multiply>
 8007d8c:	4680      	mov	r8, r0
 8007d8e:	4651      	mov	r1, sl
 8007d90:	4628      	mov	r0, r5
 8007d92:	f000 fa71 	bl	8008278 <_Bfree>
 8007d96:	46c2      	mov	sl, r8
 8007d98:	9b0a      	ldr	r3, [sp, #40]	; 0x28
 8007d9a:	1b1a      	subs	r2, r3, r4
 8007d9c:	d004      	beq.n	8007da8 <_dtoa_r+0x7c0>
 8007d9e:	4651      	mov	r1, sl
 8007da0:	4628      	mov	r0, r5
 8007da2:	f000 fbdd 	bl	8008560 <__pow5mult>
 8007da6:	4682      	mov	sl, r0
 8007da8:	2101      	movs	r1, #1
 8007daa:	4628      	mov	r0, r5
 8007dac:	f000 fb1e 	bl	80083ec <__i2b>
 8007db0:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8007db2:	4604      	mov	r4, r0
 8007db4:	2b00      	cmp	r3, #0
 8007db6:	f340 8087 	ble.w	8007ec8 <_dtoa_r+0x8e0>
 8007dba:	461a      	mov	r2, r3
 8007dbc:	4601      	mov	r1, r0
 8007dbe:	4628      	mov	r0, r5
 8007dc0:	f000 fbce 	bl	8008560 <__pow5mult>
 8007dc4:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8007dc6:	4604      	mov	r4, r0
 8007dc8:	2b01      	cmp	r3, #1
 8007dca:	f340 8080 	ble.w	8007ece <_dtoa_r+0x8e6>
 8007dce:	f04f 0800 	mov.w	r8, #0
 8007dd2:	6923      	ldr	r3, [r4, #16]
 8007dd4:	eb04 0383 	add.w	r3, r4, r3, lsl #2
 8007dd8:	6918      	ldr	r0, [r3, #16]
 8007dda:	f000 fab9 	bl	8008350 <__hi0bits>
 8007dde:	f1c0 0020 	rsb	r0, r0, #32
 8007de2:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007de4:	4418      	add	r0, r3
 8007de6:	f010 001f 	ands.w	r0, r0, #31
 8007dea:	f000 8092 	beq.w	8007f12 <_dtoa_r+0x92a>
 8007dee:	f1c0 0320 	rsb	r3, r0, #32
 8007df2:	2b04      	cmp	r3, #4
 8007df4:	f340 808a 	ble.w	8007f0c <_dtoa_r+0x924>
 8007df8:	f1c0 001c 	rsb	r0, r0, #28
 8007dfc:	9b06      	ldr	r3, [sp, #24]
 8007dfe:	4407      	add	r7, r0
 8007e00:	4403      	add	r3, r0
 8007e02:	9306      	str	r3, [sp, #24]
 8007e04:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007e06:	4403      	add	r3, r0
 8007e08:	9309      	str	r3, [sp, #36]	; 0x24
 8007e0a:	9b06      	ldr	r3, [sp, #24]
 8007e0c:	2b00      	cmp	r3, #0
 8007e0e:	dd05      	ble.n	8007e1c <_dtoa_r+0x834>
 8007e10:	4651      	mov	r1, sl
 8007e12:	461a      	mov	r2, r3
 8007e14:	4628      	mov	r0, r5
 8007e16:	f000 fbfd 	bl	8008614 <__lshift>
 8007e1a:	4682      	mov	sl, r0
 8007e1c:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007e1e:	2b00      	cmp	r3, #0
 8007e20:	dd05      	ble.n	8007e2e <_dtoa_r+0x846>
 8007e22:	4621      	mov	r1, r4
 8007e24:	461a      	mov	r2, r3
 8007e26:	4628      	mov	r0, r5
 8007e28:	f000 fbf4 	bl	8008614 <__lshift>
 8007e2c:	4604      	mov	r4, r0
 8007e2e:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
 8007e30:	2b00      	cmp	r3, #0
 8007e32:	d070      	beq.n	8007f16 <_dtoa_r+0x92e>
 8007e34:	4621      	mov	r1, r4
 8007e36:	4650      	mov	r0, sl
 8007e38:	f000 fc58 	bl	80086ec <__mcmp>
 8007e3c:	2800      	cmp	r0, #0
 8007e3e:	da6a      	bge.n	8007f16 <_dtoa_r+0x92e>
 8007e40:	2300      	movs	r3, #0
 8007e42:	4651      	mov	r1, sl
 8007e44:	220a      	movs	r2, #10
 8007e46:	4628      	mov	r0, r5
 8007e48:	f000 fa38 	bl	80082bc <__multadd>
 8007e4c:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
 8007e4e:	4682      	mov	sl, r0
 8007e50:	f109 39ff 	add.w	r9, r9, #4294967295	; 0xffffffff
 8007e54:	2b00      	cmp	r3, #0
 8007e56:	f000 8193 	beq.w	8008180 <_dtoa_r+0xb98>
 8007e5a:	4631      	mov	r1, r6
 8007e5c:	2300      	movs	r3, #0
 8007e5e:	220a      	movs	r2, #10
 8007e60:	4628      	mov	r0, r5
 8007e62:	f000 fa2b 	bl	80082bc <__multadd>
 8007e66:	f1bb 0f00 	cmp.w	fp, #0
 8007e6a:	4606      	mov	r6, r0
 8007e6c:	f300 8093 	bgt.w	8007f96 <_dtoa_r+0x9ae>
 8007e70:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8007e72:	2b02      	cmp	r3, #2
 8007e74:	dc57      	bgt.n	8007f26 <_dtoa_r+0x93e>
 8007e76:	e08e      	b.n	8007f96 <_dtoa_r+0x9ae>
 8007e78:	9b16      	ldr	r3, [sp, #88]	; 0x58
 8007e7a:	f1c3 0336 	rsb	r3, r3, #54	; 0x36
 8007e7e:	e756      	b.n	8007d2e <_dtoa_r+0x746>
 8007e80:	9b02      	ldr	r3, [sp, #8]
 8007e82:	1e5c      	subs	r4, r3, #1
 8007e84:	9b0a      	ldr	r3, [sp, #40]	; 0x28
 8007e86:	42a3      	cmp	r3, r4
 8007e88:	bfb7      	itett	lt
 8007e8a:	9b0a      	ldrlt	r3, [sp, #40]	; 0x28
 8007e8c:	1b1c      	subge	r4, r3, r4
 8007e8e:	1ae2      	sublt	r2, r4, r3
 8007e90:	9b0e      	ldrlt	r3, [sp, #56]	; 0x38
 8007e92:	bfbe      	ittt	lt
 8007e94:	940a      	strlt	r4, [sp, #40]	; 0x28
 8007e96:	189b      	addlt	r3, r3, r2
 8007e98:	930e      	strlt	r3, [sp, #56]	; 0x38
 8007e9a:	9b02      	ldr	r3, [sp, #8]
 8007e9c:	bfb8      	it	lt
 8007e9e:	2400      	movlt	r4, #0
 8007ea0:	2b00      	cmp	r3, #0
 8007ea2:	bfbb      	ittet	lt
 8007ea4:	9b06      	ldrlt	r3, [sp, #24]
 8007ea6:	9a02      	ldrlt	r2, [sp, #8]
 8007ea8:	9f06      	ldrge	r7, [sp, #24]
 8007eaa:	1a9f      	sublt	r7, r3, r2
 8007eac:	bfac      	ite	ge
 8007eae:	9b02      	ldrge	r3, [sp, #8]
 8007eb0:	2300      	movlt	r3, #0
 8007eb2:	e73e      	b.n	8007d32 <_dtoa_r+0x74a>
 8007eb4:	9c0a      	ldr	r4, [sp, #40]	; 0x28
 8007eb6:	9f06      	ldr	r7, [sp, #24]
 8007eb8:	9e0b      	ldr	r6, [sp, #44]	; 0x2c
 8007eba:	e745      	b.n	8007d48 <_dtoa_r+0x760>
 8007ebc:	3fe00000 	.word	0x3fe00000
 8007ec0:	40240000 	.word	0x40240000
 8007ec4:	9a0a      	ldr	r2, [sp, #40]	; 0x28
 8007ec6:	e76a      	b.n	8007d9e <_dtoa_r+0x7b6>
 8007ec8:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8007eca:	2b01      	cmp	r3, #1
 8007ecc:	dc19      	bgt.n	8007f02 <_dtoa_r+0x91a>
 8007ece:	9b04      	ldr	r3, [sp, #16]
 8007ed0:	b9bb      	cbnz	r3, 8007f02 <_dtoa_r+0x91a>
 8007ed2:	9b05      	ldr	r3, [sp, #20]
 8007ed4:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8007ed8:	b99b      	cbnz	r3, 8007f02 <_dtoa_r+0x91a>
 8007eda:	9b05      	ldr	r3, [sp, #20]
 8007edc:	f023 4300 	bic.w	r3, r3, #2147483648	; 0x80000000
 8007ee0:	0d1b      	lsrs	r3, r3, #20
 8007ee2:	051b      	lsls	r3, r3, #20
 8007ee4:	b183      	cbz	r3, 8007f08 <_dtoa_r+0x920>
 8007ee6:	f04f 0801 	mov.w	r8, #1
 8007eea:	9b06      	ldr	r3, [sp, #24]
 8007eec:	3301      	adds	r3, #1
 8007eee:	9306      	str	r3, [sp, #24]
 8007ef0:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007ef2:	3301      	adds	r3, #1
 8007ef4:	9309      	str	r3, [sp, #36]	; 0x24
 8007ef6:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8007ef8:	2b00      	cmp	r3, #0
 8007efa:	f47f af6a 	bne.w	8007dd2 <_dtoa_r+0x7ea>
 8007efe:	2001      	movs	r0, #1
 8007f00:	e76f      	b.n	8007de2 <_dtoa_r+0x7fa>
 8007f02:	f04f 0800 	mov.w	r8, #0
 8007f06:	e7f6      	b.n	8007ef6 <_dtoa_r+0x90e>
 8007f08:	4698      	mov	r8, r3
 8007f0a:	e7f4      	b.n	8007ef6 <_dtoa_r+0x90e>
 8007f0c:	f43f af7d 	beq.w	8007e0a <_dtoa_r+0x822>
 8007f10:	4618      	mov	r0, r3
 8007f12:	301c      	adds	r0, #28
 8007f14:	e772      	b.n	8007dfc <_dtoa_r+0x814>
 8007f16:	9b02      	ldr	r3, [sp, #8]
 8007f18:	2b00      	cmp	r3, #0
 8007f1a:	dc36      	bgt.n	8007f8a <_dtoa_r+0x9a2>
 8007f1c:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8007f1e:	2b02      	cmp	r3, #2
 8007f20:	dd33      	ble.n	8007f8a <_dtoa_r+0x9a2>
 8007f22:	f8dd b008 	ldr.w	fp, [sp, #8]
 8007f26:	f1bb 0f00 	cmp.w	fp, #0
 8007f2a:	d10d      	bne.n	8007f48 <_dtoa_r+0x960>
 8007f2c:	4621      	mov	r1, r4
 8007f2e:	465b      	mov	r3, fp
 8007f30:	2205      	movs	r2, #5
 8007f32:	4628      	mov	r0, r5
 8007f34:	f000 f9c2 	bl	80082bc <__multadd>
 8007f38:	4601      	mov	r1, r0
 8007f3a:	4604      	mov	r4, r0
 8007f3c:	4650      	mov	r0, sl
 8007f3e:	f000 fbd5 	bl	80086ec <__mcmp>
 8007f42:	2800      	cmp	r0, #0
 8007f44:	f73f adb6 	bgt.w	8007ab4 <_dtoa_r+0x4cc>
 8007f48:	9b23      	ldr	r3, [sp, #140]	; 0x8c
 8007f4a:	9f08      	ldr	r7, [sp, #32]
 8007f4c:	ea6f 0903 	mvn.w	r9, r3
 8007f50:	f04f 0800 	mov.w	r8, #0
 8007f54:	4621      	mov	r1, r4
 8007f56:	4628      	mov	r0, r5
 8007f58:	f000 f98e 	bl	8008278 <_Bfree>
 8007f5c:	2e00      	cmp	r6, #0
 8007f5e:	f43f aea4 	beq.w	8007caa <_dtoa_r+0x6c2>
 8007f62:	f1b8 0f00 	cmp.w	r8, #0
 8007f66:	d005      	beq.n	8007f74 <_dtoa_r+0x98c>
 8007f68:	45b0      	cmp	r8, r6
 8007f6a:	d003      	beq.n	8007f74 <_dtoa_r+0x98c>
 8007f6c:	4641      	mov	r1, r8
 8007f6e:	4628      	mov	r0, r5
 8007f70:	f000 f982 	bl	8008278 <_Bfree>
 8007f74:	4631      	mov	r1, r6
 8007f76:	4628      	mov	r0, r5
 8007f78:	f000 f97e 	bl	8008278 <_Bfree>
 8007f7c:	e695      	b.n	8007caa <_dtoa_r+0x6c2>
 8007f7e:	2400      	movs	r4, #0
 8007f80:	4626      	mov	r6, r4
 8007f82:	e7e1      	b.n	8007f48 <_dtoa_r+0x960>
 8007f84:	46c1      	mov	r9, r8
 8007f86:	4626      	mov	r6, r4
 8007f88:	e594      	b.n	8007ab4 <_dtoa_r+0x4cc>
 8007f8a:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
 8007f8c:	f8dd b008 	ldr.w	fp, [sp, #8]
 8007f90:	2b00      	cmp	r3, #0
 8007f92:	f000 80fc 	beq.w	800818e <_dtoa_r+0xba6>
 8007f96:	2f00      	cmp	r7, #0
 8007f98:	dd05      	ble.n	8007fa6 <_dtoa_r+0x9be>
 8007f9a:	4631      	mov	r1, r6
 8007f9c:	463a      	mov	r2, r7
 8007f9e:	4628      	mov	r0, r5
 8007fa0:	f000 fb38 	bl	8008614 <__lshift>
 8007fa4:	4606      	mov	r6, r0
 8007fa6:	f1b8 0f00 	cmp.w	r8, #0
 8007faa:	d05c      	beq.n	8008066 <_dtoa_r+0xa7e>
 8007fac:	4628      	mov	r0, r5
 8007fae:	6871      	ldr	r1, [r6, #4]
 8007fb0:	f000 f922 	bl	80081f8 <_Balloc>
 8007fb4:	4607      	mov	r7, r0
 8007fb6:	b928      	cbnz	r0, 8007fc4 <_dtoa_r+0x9dc>
 8007fb8:	4602      	mov	r2, r0
 8007fba:	f240 21ea 	movw	r1, #746	; 0x2ea
 8007fbe:	4b7e      	ldr	r3, [pc, #504]	; (80081b8 <_dtoa_r+0xbd0>)
 8007fc0:	f7ff bb26 	b.w	8007610 <_dtoa_r+0x28>
 8007fc4:	6932      	ldr	r2, [r6, #16]
 8007fc6:	f106 010c 	add.w	r1, r6, #12
 8007fca:	3202      	adds	r2, #2
 8007fcc:	0092      	lsls	r2, r2, #2
 8007fce:	300c      	adds	r0, #12
 8007fd0:	f7fe fdca 	bl	8006b68 <memcpy>
 8007fd4:	2201      	movs	r2, #1
 8007fd6:	4639      	mov	r1, r7
 8007fd8:	4628      	mov	r0, r5
 8007fda:	f000 fb1b 	bl	8008614 <__lshift>
 8007fde:	46b0      	mov	r8, r6
 8007fe0:	4606      	mov	r6, r0
 8007fe2:	9b08      	ldr	r3, [sp, #32]
 8007fe4:	3301      	adds	r3, #1
 8007fe6:	9302      	str	r3, [sp, #8]
 8007fe8:	9b08      	ldr	r3, [sp, #32]
 8007fea:	445b      	add	r3, fp
 8007fec:	930a      	str	r3, [sp, #40]	; 0x28
 8007fee:	9b04      	ldr	r3, [sp, #16]
 8007ff0:	f003 0301 	and.w	r3, r3, #1
 8007ff4:	9309      	str	r3, [sp, #36]	; 0x24
 8007ff6:	9b02      	ldr	r3, [sp, #8]
 8007ff8:	4621      	mov	r1, r4
 8007ffa:	4650      	mov	r0, sl
 8007ffc:	f103 3bff 	add.w	fp, r3, #4294967295	; 0xffffffff
 8008000:	f7ff fa62 	bl	80074c8 <quorem>
 8008004:	4603      	mov	r3, r0
 8008006:	4641      	mov	r1, r8
 8008008:	3330      	adds	r3, #48	; 0x30
 800800a:	9004      	str	r0, [sp, #16]
 800800c:	4650      	mov	r0, sl
 800800e:	930b      	str	r3, [sp, #44]	; 0x2c
 8008010:	f000 fb6c 	bl	80086ec <__mcmp>
 8008014:	4632      	mov	r2, r6
 8008016:	9006      	str	r0, [sp, #24]
 8008018:	4621      	mov	r1, r4
 800801a:	4628      	mov	r0, r5
 800801c:	f000 fb82 	bl	8008724 <__mdiff>
 8008020:	68c2      	ldr	r2, [r0, #12]
 8008022:	4607      	mov	r7, r0
 8008024:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
 8008026:	bb02      	cbnz	r2, 800806a <_dtoa_r+0xa82>
 8008028:	4601      	mov	r1, r0
 800802a:	4650      	mov	r0, sl
 800802c:	f000 fb5e 	bl	80086ec <__mcmp>
 8008030:	4602      	mov	r2, r0
 8008032:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
 8008034:	4639      	mov	r1, r7
 8008036:	4628      	mov	r0, r5
 8008038:	e9cd 320b 	strd	r3, r2, [sp, #44]	; 0x2c
 800803c:	f000 f91c 	bl	8008278 <_Bfree>
 8008040:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8008042:	9a0c      	ldr	r2, [sp, #48]	; 0x30
 8008044:	9f02      	ldr	r7, [sp, #8]
 8008046:	ea43 0102 	orr.w	r1, r3, r2
 800804a:	9b09      	ldr	r3, [sp, #36]	; 0x24
 800804c:	430b      	orrs	r3, r1
 800804e:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
 8008050:	d10d      	bne.n	800806e <_dtoa_r+0xa86>
 8008052:	2b39      	cmp	r3, #57	; 0x39
 8008054:	d027      	beq.n	80080a6 <_dtoa_r+0xabe>
 8008056:	9a06      	ldr	r2, [sp, #24]
 8008058:	2a00      	cmp	r2, #0
 800805a:	dd01      	ble.n	8008060 <_dtoa_r+0xa78>
 800805c:	9b04      	ldr	r3, [sp, #16]
 800805e:	3331      	adds	r3, #49	; 0x31
 8008060:	f88b 3000 	strb.w	r3, [fp]
 8008064:	e776      	b.n	8007f54 <_dtoa_r+0x96c>
 8008066:	4630      	mov	r0, r6
 8008068:	e7b9      	b.n	8007fde <_dtoa_r+0x9f6>
 800806a:	2201      	movs	r2, #1
 800806c:	e7e2      	b.n	8008034 <_dtoa_r+0xa4c>
 800806e:	9906      	ldr	r1, [sp, #24]
 8008070:	2900      	cmp	r1, #0
 8008072:	db04      	blt.n	800807e <_dtoa_r+0xa96>
 8008074:	9822      	ldr	r0, [sp, #136]	; 0x88
 8008076:	4301      	orrs	r1, r0
 8008078:	9809      	ldr	r0, [sp, #36]	; 0x24
 800807a:	4301      	orrs	r1, r0
 800807c:	d120      	bne.n	80080c0 <_dtoa_r+0xad8>
 800807e:	2a00      	cmp	r2, #0
 8008080:	ddee      	ble.n	8008060 <_dtoa_r+0xa78>
 8008082:	4651      	mov	r1, sl
 8008084:	2201      	movs	r2, #1
 8008086:	4628      	mov	r0, r5
 8008088:	9302      	str	r3, [sp, #8]
 800808a:	f000 fac3 	bl	8008614 <__lshift>
 800808e:	4621      	mov	r1, r4
 8008090:	4682      	mov	sl, r0
 8008092:	f000 fb2b 	bl	80086ec <__mcmp>
 8008096:	2800      	cmp	r0, #0
 8008098:	9b02      	ldr	r3, [sp, #8]
 800809a:	dc02      	bgt.n	80080a2 <_dtoa_r+0xaba>
 800809c:	d1e0      	bne.n	8008060 <_dtoa_r+0xa78>
 800809e:	07da      	lsls	r2, r3, #31
 80080a0:	d5de      	bpl.n	8008060 <_dtoa_r+0xa78>
 80080a2:	2b39      	cmp	r3, #57	; 0x39
 80080a4:	d1da      	bne.n	800805c <_dtoa_r+0xa74>
 80080a6:	2339      	movs	r3, #57	; 0x39
 80080a8:	f88b 3000 	strb.w	r3, [fp]
 80080ac:	463b      	mov	r3, r7
 80080ae:	461f      	mov	r7, r3
 80080b0:	f817 2c01 	ldrb.w	r2, [r7, #-1]
 80080b4:	3b01      	subs	r3, #1
 80080b6:	2a39      	cmp	r2, #57	; 0x39
 80080b8:	d050      	beq.n	800815c <_dtoa_r+0xb74>
 80080ba:	3201      	adds	r2, #1
 80080bc:	701a      	strb	r2, [r3, #0]
 80080be:	e749      	b.n	8007f54 <_dtoa_r+0x96c>
 80080c0:	2a00      	cmp	r2, #0
 80080c2:	dd03      	ble.n	80080cc <_dtoa_r+0xae4>
 80080c4:	2b39      	cmp	r3, #57	; 0x39
 80080c6:	d0ee      	beq.n	80080a6 <_dtoa_r+0xabe>
 80080c8:	3301      	adds	r3, #1
 80080ca:	e7c9      	b.n	8008060 <_dtoa_r+0xa78>
 80080cc:	9a02      	ldr	r2, [sp, #8]
 80080ce:	990a      	ldr	r1, [sp, #40]	; 0x28
 80080d0:	f802 3c01 	strb.w	r3, [r2, #-1]
 80080d4:	428a      	cmp	r2, r1
 80080d6:	d02a      	beq.n	800812e <_dtoa_r+0xb46>
 80080d8:	4651      	mov	r1, sl
 80080da:	2300      	movs	r3, #0
 80080dc:	220a      	movs	r2, #10
 80080de:	4628      	mov	r0, r5
 80080e0:	f000 f8ec 	bl	80082bc <__multadd>
 80080e4:	45b0      	cmp	r8, r6
 80080e6:	4682      	mov	sl, r0
 80080e8:	f04f 0300 	mov.w	r3, #0
 80080ec:	f04f 020a 	mov.w	r2, #10
 80080f0:	4641      	mov	r1, r8
 80080f2:	4628      	mov	r0, r5
 80080f4:	d107      	bne.n	8008106 <_dtoa_r+0xb1e>
 80080f6:	f000 f8e1 	bl	80082bc <__multadd>
 80080fa:	4680      	mov	r8, r0
 80080fc:	4606      	mov	r6, r0
 80080fe:	9b02      	ldr	r3, [sp, #8]
 8008100:	3301      	adds	r3, #1
 8008102:	9302      	str	r3, [sp, #8]
 8008104:	e777      	b.n	8007ff6 <_dtoa_r+0xa0e>
 8008106:	f000 f8d9 	bl	80082bc <__multadd>
 800810a:	4631      	mov	r1, r6
 800810c:	4680      	mov	r8, r0
 800810e:	2300      	movs	r3, #0
 8008110:	220a      	movs	r2, #10
 8008112:	4628      	mov	r0, r5
 8008114:	f000 f8d2 	bl	80082bc <__multadd>
 8008118:	4606      	mov	r6, r0
 800811a:	e7f0      	b.n	80080fe <_dtoa_r+0xb16>
 800811c:	f1bb 0f00 	cmp.w	fp, #0
 8008120:	bfcc      	ite	gt
 8008122:	465f      	movgt	r7, fp
 8008124:	2701      	movle	r7, #1
 8008126:	f04f 0800 	mov.w	r8, #0
 800812a:	9a08      	ldr	r2, [sp, #32]
 800812c:	4417      	add	r7, r2
 800812e:	4651      	mov	r1, sl
 8008130:	2201      	movs	r2, #1
 8008132:	4628      	mov	r0, r5
 8008134:	9302      	str	r3, [sp, #8]
 8008136:	f000 fa6d 	bl	8008614 <__lshift>
 800813a:	4621      	mov	r1, r4
 800813c:	4682      	mov	sl, r0
 800813e:	f000 fad5 	bl	80086ec <__mcmp>
 8008142:	2800      	cmp	r0, #0
 8008144:	dcb2      	bgt.n	80080ac <_dtoa_r+0xac4>
 8008146:	d102      	bne.n	800814e <_dtoa_r+0xb66>
 8008148:	9b02      	ldr	r3, [sp, #8]
 800814a:	07db      	lsls	r3, r3, #31
 800814c:	d4ae      	bmi.n	80080ac <_dtoa_r+0xac4>
 800814e:	463b      	mov	r3, r7
 8008150:	461f      	mov	r7, r3
 8008152:	f813 2d01 	ldrb.w	r2, [r3, #-1]!
 8008156:	2a30      	cmp	r2, #48	; 0x30
 8008158:	d0fa      	beq.n	8008150 <_dtoa_r+0xb68>
 800815a:	e6fb      	b.n	8007f54 <_dtoa_r+0x96c>
 800815c:	9a08      	ldr	r2, [sp, #32]
 800815e:	429a      	cmp	r2, r3
 8008160:	d1a5      	bne.n	80080ae <_dtoa_r+0xac6>
 8008162:	2331      	movs	r3, #49	; 0x31
 8008164:	f109 0901 	add.w	r9, r9, #1
 8008168:	7013      	strb	r3, [r2, #0]
 800816a:	e6f3      	b.n	8007f54 <_dtoa_r+0x96c>
 800816c:	4b13      	ldr	r3, [pc, #76]	; (80081bc <_dtoa_r+0xbd4>)
 800816e:	f7ff baa7 	b.w	80076c0 <_dtoa_r+0xd8>
 8008172:	9b26      	ldr	r3, [sp, #152]	; 0x98
 8008174:	2b00      	cmp	r3, #0
 8008176:	f47f aa80 	bne.w	800767a <_dtoa_r+0x92>
 800817a:	4b11      	ldr	r3, [pc, #68]	; (80081c0 <_dtoa_r+0xbd8>)
 800817c:	f7ff baa0 	b.w	80076c0 <_dtoa_r+0xd8>
 8008180:	f1bb 0f00 	cmp.w	fp, #0
 8008184:	dc03      	bgt.n	800818e <_dtoa_r+0xba6>
 8008186:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8008188:	2b02      	cmp	r3, #2
 800818a:	f73f aecc 	bgt.w	8007f26 <_dtoa_r+0x93e>
 800818e:	9f08      	ldr	r7, [sp, #32]
 8008190:	4621      	mov	r1, r4
 8008192:	4650      	mov	r0, sl
 8008194:	f7ff f998 	bl	80074c8 <quorem>
 8008198:	9a08      	ldr	r2, [sp, #32]
 800819a:	f100 0330 	add.w	r3, r0, #48	; 0x30
 800819e:	f807 3b01 	strb.w	r3, [r7], #1
 80081a2:	1aba      	subs	r2, r7, r2
 80081a4:	4593      	cmp	fp, r2
 80081a6:	ddb9      	ble.n	800811c <_dtoa_r+0xb34>
 80081a8:	4651      	mov	r1, sl
 80081aa:	2300      	movs	r3, #0
 80081ac:	220a      	movs	r2, #10
 80081ae:	4628      	mov	r0, r5
 80081b0:	f000 f884 	bl	80082bc <__multadd>
 80081b4:	4682      	mov	sl, r0
 80081b6:	e7eb      	b.n	8008190 <_dtoa_r+0xba8>
 80081b8:	0800a70f 	.word	0x0800a70f
 80081bc:	0800a668 	.word	0x0800a668
 80081c0:	0800a68c 	.word	0x0800a68c

080081c4 <_localeconv_r>:
 80081c4:	4800      	ldr	r0, [pc, #0]	; (80081c8 <_localeconv_r+0x4>)
 80081c6:	4770      	bx	lr
 80081c8:	20000168 	.word	0x20000168

080081cc <malloc>:
 80081cc:	4b02      	ldr	r3, [pc, #8]	; (80081d8 <malloc+0xc>)
 80081ce:	4601      	mov	r1, r0
 80081d0:	6818      	ldr	r0, [r3, #0]
 80081d2:	f000 bbed 	b.w	80089b0 <_malloc_r>
 80081d6:	bf00      	nop
 80081d8:	20000014 	.word	0x20000014

080081dc <memchr>:
 80081dc:	4603      	mov	r3, r0
 80081de:	b510      	push	{r4, lr}
 80081e0:	b2c9      	uxtb	r1, r1
 80081e2:	4402      	add	r2, r0
 80081e4:	4293      	cmp	r3, r2
 80081e6:	4618      	mov	r0, r3
 80081e8:	d101      	bne.n	80081ee <memchr+0x12>
 80081ea:	2000      	movs	r0, #0
 80081ec:	e003      	b.n	80081f6 <memchr+0x1a>
 80081ee:	7804      	ldrb	r4, [r0, #0]
 80081f0:	3301      	adds	r3, #1
 80081f2:	428c      	cmp	r4, r1
 80081f4:	d1f6      	bne.n	80081e4 <memchr+0x8>
 80081f6:	bd10      	pop	{r4, pc}

080081f8 <_Balloc>:
 80081f8:	b570      	push	{r4, r5, r6, lr}
 80081fa:	6a46      	ldr	r6, [r0, #36]	; 0x24
 80081fc:	4604      	mov	r4, r0
 80081fe:	460d      	mov	r5, r1
 8008200:	b976      	cbnz	r6, 8008220 <_Balloc+0x28>
 8008202:	2010      	movs	r0, #16
 8008204:	f7ff ffe2 	bl	80081cc <malloc>
 8008208:	4602      	mov	r2, r0
 800820a:	6260      	str	r0, [r4, #36]	; 0x24
 800820c:	b920      	cbnz	r0, 8008218 <_Balloc+0x20>
 800820e:	2166      	movs	r1, #102	; 0x66
 8008210:	4b17      	ldr	r3, [pc, #92]	; (8008270 <_Balloc+0x78>)
 8008212:	4818      	ldr	r0, [pc, #96]	; (8008274 <_Balloc+0x7c>)
 8008214:	f000 fd92 	bl	8008d3c <__assert_func>
 8008218:	e9c0 6601 	strd	r6, r6, [r0, #4]
 800821c:	6006      	str	r6, [r0, #0]
 800821e:	60c6      	str	r6, [r0, #12]
 8008220:	6a66      	ldr	r6, [r4, #36]	; 0x24
 8008222:	68f3      	ldr	r3, [r6, #12]
 8008224:	b183      	cbz	r3, 8008248 <_Balloc+0x50>
 8008226:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8008228:	68db      	ldr	r3, [r3, #12]
 800822a:	f853 0025 	ldr.w	r0, [r3, r5, lsl #2]
 800822e:	b9b8      	cbnz	r0, 8008260 <_Balloc+0x68>
 8008230:	2101      	movs	r1, #1
 8008232:	fa01 f605 	lsl.w	r6, r1, r5
 8008236:	1d72      	adds	r2, r6, #5
 8008238:	4620      	mov	r0, r4
 800823a:	0092      	lsls	r2, r2, #2
 800823c:	f000 fb5e 	bl	80088fc <_calloc_r>
 8008240:	b160      	cbz	r0, 800825c <_Balloc+0x64>
 8008242:	e9c0 5601 	strd	r5, r6, [r0, #4]
 8008246:	e00e      	b.n	8008266 <_Balloc+0x6e>
 8008248:	2221      	movs	r2, #33	; 0x21
 800824a:	2104      	movs	r1, #4
 800824c:	4620      	mov	r0, r4
 800824e:	f000 fb55 	bl	80088fc <_calloc_r>
 8008252:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8008254:	60f0      	str	r0, [r6, #12]
 8008256:	68db      	ldr	r3, [r3, #12]
 8008258:	2b00      	cmp	r3, #0
 800825a:	d1e4      	bne.n	8008226 <_Balloc+0x2e>
 800825c:	2000      	movs	r0, #0
 800825e:	bd70      	pop	{r4, r5, r6, pc}
 8008260:	6802      	ldr	r2, [r0, #0]
 8008262:	f843 2025 	str.w	r2, [r3, r5, lsl #2]
 8008266:	2300      	movs	r3, #0
 8008268:	e9c0 3303 	strd	r3, r3, [r0, #12]
 800826c:	e7f7      	b.n	800825e <_Balloc+0x66>
 800826e:	bf00      	nop
 8008270:	0800a699 	.word	0x0800a699
 8008274:	0800a720 	.word	0x0800a720

08008278 <_Bfree>:
 8008278:	b570      	push	{r4, r5, r6, lr}
 800827a:	6a46      	ldr	r6, [r0, #36]	; 0x24
 800827c:	4605      	mov	r5, r0
 800827e:	460c      	mov	r4, r1
 8008280:	b976      	cbnz	r6, 80082a0 <_Bfree+0x28>
 8008282:	2010      	movs	r0, #16
 8008284:	f7ff ffa2 	bl	80081cc <malloc>
 8008288:	4602      	mov	r2, r0
 800828a:	6268      	str	r0, [r5, #36]	; 0x24
 800828c:	b920      	cbnz	r0, 8008298 <_Bfree+0x20>
 800828e:	218a      	movs	r1, #138	; 0x8a
 8008290:	4b08      	ldr	r3, [pc, #32]	; (80082b4 <_Bfree+0x3c>)
 8008292:	4809      	ldr	r0, [pc, #36]	; (80082b8 <_Bfree+0x40>)
 8008294:	f000 fd52 	bl	8008d3c <__assert_func>
 8008298:	e9c0 6601 	strd	r6, r6, [r0, #4]
 800829c:	6006      	str	r6, [r0, #0]
 800829e:	60c6      	str	r6, [r0, #12]
 80082a0:	b13c      	cbz	r4, 80082b2 <_Bfree+0x3a>
 80082a2:	6a6b      	ldr	r3, [r5, #36]	; 0x24
 80082a4:	6862      	ldr	r2, [r4, #4]
 80082a6:	68db      	ldr	r3, [r3, #12]
 80082a8:	f853 1022 	ldr.w	r1, [r3, r2, lsl #2]
 80082ac:	6021      	str	r1, [r4, #0]
 80082ae:	f843 4022 	str.w	r4, [r3, r2, lsl #2]
 80082b2:	bd70      	pop	{r4, r5, r6, pc}
 80082b4:	0800a699 	.word	0x0800a699
 80082b8:	0800a720 	.word	0x0800a720

080082bc <__multadd>:
 80082bc:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 80082c0:	4698      	mov	r8, r3
 80082c2:	460c      	mov	r4, r1
 80082c4:	2300      	movs	r3, #0
 80082c6:	690e      	ldr	r6, [r1, #16]
 80082c8:	4607      	mov	r7, r0
 80082ca:	f101 0014 	add.w	r0, r1, #20
 80082ce:	6805      	ldr	r5, [r0, #0]
 80082d0:	3301      	adds	r3, #1
 80082d2:	b2a9      	uxth	r1, r5
 80082d4:	fb02 8101 	mla	r1, r2, r1, r8
 80082d8:	0c2d      	lsrs	r5, r5, #16
 80082da:	ea4f 4c11 	mov.w	ip, r1, lsr #16
 80082de:	fb02 c505 	mla	r5, r2, r5, ip
 80082e2:	b289      	uxth	r1, r1
 80082e4:	eb01 4105 	add.w	r1, r1, r5, lsl #16
 80082e8:	429e      	cmp	r6, r3
 80082ea:	ea4f 4815 	mov.w	r8, r5, lsr #16
 80082ee:	f840 1b04 	str.w	r1, [r0], #4
 80082f2:	dcec      	bgt.n	80082ce <__multadd+0x12>
 80082f4:	f1b8 0f00 	cmp.w	r8, #0
 80082f8:	d022      	beq.n	8008340 <__multadd+0x84>
 80082fa:	68a3      	ldr	r3, [r4, #8]
 80082fc:	42b3      	cmp	r3, r6
 80082fe:	dc19      	bgt.n	8008334 <__multadd+0x78>
 8008300:	6861      	ldr	r1, [r4, #4]
 8008302:	4638      	mov	r0, r7
 8008304:	3101      	adds	r1, #1
 8008306:	f7ff ff77 	bl	80081f8 <_Balloc>
 800830a:	4605      	mov	r5, r0
 800830c:	b928      	cbnz	r0, 800831a <__multadd+0x5e>
 800830e:	4602      	mov	r2, r0
 8008310:	21b5      	movs	r1, #181	; 0xb5
 8008312:	4b0d      	ldr	r3, [pc, #52]	; (8008348 <__multadd+0x8c>)
 8008314:	480d      	ldr	r0, [pc, #52]	; (800834c <__multadd+0x90>)
 8008316:	f000 fd11 	bl	8008d3c <__assert_func>
 800831a:	6922      	ldr	r2, [r4, #16]
 800831c:	f104 010c 	add.w	r1, r4, #12
 8008320:	3202      	adds	r2, #2
 8008322:	0092      	lsls	r2, r2, #2
 8008324:	300c      	adds	r0, #12
 8008326:	f7fe fc1f 	bl	8006b68 <memcpy>
 800832a:	4621      	mov	r1, r4
 800832c:	4638      	mov	r0, r7
 800832e:	f7ff ffa3 	bl	8008278 <_Bfree>
 8008332:	462c      	mov	r4, r5
 8008334:	eb04 0386 	add.w	r3, r4, r6, lsl #2
 8008338:	3601      	adds	r6, #1
 800833a:	f8c3 8014 	str.w	r8, [r3, #20]
 800833e:	6126      	str	r6, [r4, #16]
 8008340:	4620      	mov	r0, r4
 8008342:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8008346:	bf00      	nop
 8008348:	0800a70f 	.word	0x0800a70f
 800834c:	0800a720 	.word	0x0800a720

08008350 <__hi0bits>:
 8008350:	0c02      	lsrs	r2, r0, #16
 8008352:	0412      	lsls	r2, r2, #16
 8008354:	4603      	mov	r3, r0
 8008356:	b9ca      	cbnz	r2, 800838c <__hi0bits+0x3c>
 8008358:	0403      	lsls	r3, r0, #16
 800835a:	2010      	movs	r0, #16
 800835c:	f013 4f7f 	tst.w	r3, #4278190080	; 0xff000000
 8008360:	bf04      	itt	eq
 8008362:	021b      	lsleq	r3, r3, #8
 8008364:	3008      	addeq	r0, #8
 8008366:	f013 4f70 	tst.w	r3, #4026531840	; 0xf0000000
 800836a:	bf04      	itt	eq
 800836c:	011b      	lsleq	r3, r3, #4
 800836e:	3004      	addeq	r0, #4
 8008370:	f013 4f40 	tst.w	r3, #3221225472	; 0xc0000000
 8008374:	bf04      	itt	eq
 8008376:	009b      	lsleq	r3, r3, #2
 8008378:	3002      	addeq	r0, #2
 800837a:	2b00      	cmp	r3, #0
 800837c:	db05      	blt.n	800838a <__hi0bits+0x3a>
 800837e:	f013 4f80 	tst.w	r3, #1073741824	; 0x40000000
 8008382:	f100 0001 	add.w	r0, r0, #1
 8008386:	bf08      	it	eq
 8008388:	2020      	moveq	r0, #32
 800838a:	4770      	bx	lr
 800838c:	2000      	movs	r0, #0
 800838e:	e7e5      	b.n	800835c <__hi0bits+0xc>

08008390 <__lo0bits>:
 8008390:	6803      	ldr	r3, [r0, #0]
 8008392:	4602      	mov	r2, r0
 8008394:	f013 0007 	ands.w	r0, r3, #7
 8008398:	d00b      	beq.n	80083b2 <__lo0bits+0x22>
 800839a:	07d9      	lsls	r1, r3, #31
 800839c:	d422      	bmi.n	80083e4 <__lo0bits+0x54>
 800839e:	0798      	lsls	r0, r3, #30
 80083a0:	bf49      	itett	mi
 80083a2:	085b      	lsrmi	r3, r3, #1
 80083a4:	089b      	lsrpl	r3, r3, #2
 80083a6:	2001      	movmi	r0, #1
 80083a8:	6013      	strmi	r3, [r2, #0]
 80083aa:	bf5c      	itt	pl
 80083ac:	2002      	movpl	r0, #2
 80083ae:	6013      	strpl	r3, [r2, #0]
 80083b0:	4770      	bx	lr
 80083b2:	b299      	uxth	r1, r3
 80083b4:	b909      	cbnz	r1, 80083ba <__lo0bits+0x2a>
 80083b6:	2010      	movs	r0, #16
 80083b8:	0c1b      	lsrs	r3, r3, #16
 80083ba:	f013 0fff 	tst.w	r3, #255	; 0xff
 80083be:	bf04      	itt	eq
 80083c0:	0a1b      	lsreq	r3, r3, #8
 80083c2:	3008      	addeq	r0, #8
 80083c4:	0719      	lsls	r1, r3, #28
 80083c6:	bf04      	itt	eq
 80083c8:	091b      	lsreq	r3, r3, #4
 80083ca:	3004      	addeq	r0, #4
 80083cc:	0799      	lsls	r1, r3, #30
 80083ce:	bf04      	itt	eq
 80083d0:	089b      	lsreq	r3, r3, #2
 80083d2:	3002      	addeq	r0, #2
 80083d4:	07d9      	lsls	r1, r3, #31
 80083d6:	d403      	bmi.n	80083e0 <__lo0bits+0x50>
 80083d8:	085b      	lsrs	r3, r3, #1
 80083da:	f100 0001 	add.w	r0, r0, #1
 80083de:	d003      	beq.n	80083e8 <__lo0bits+0x58>
 80083e0:	6013      	str	r3, [r2, #0]
 80083e2:	4770      	bx	lr
 80083e4:	2000      	movs	r0, #0
 80083e6:	4770      	bx	lr
 80083e8:	2020      	movs	r0, #32
 80083ea:	4770      	bx	lr

080083ec <__i2b>:
 80083ec:	b510      	push	{r4, lr}
 80083ee:	460c      	mov	r4, r1
 80083f0:	2101      	movs	r1, #1
 80083f2:	f7ff ff01 	bl	80081f8 <_Balloc>
 80083f6:	4602      	mov	r2, r0
 80083f8:	b928      	cbnz	r0, 8008406 <__i2b+0x1a>
 80083fa:	f44f 71a0 	mov.w	r1, #320	; 0x140
 80083fe:	4b04      	ldr	r3, [pc, #16]	; (8008410 <__i2b+0x24>)
 8008400:	4804      	ldr	r0, [pc, #16]	; (8008414 <__i2b+0x28>)
 8008402:	f000 fc9b 	bl	8008d3c <__assert_func>
 8008406:	2301      	movs	r3, #1
 8008408:	6144      	str	r4, [r0, #20]
 800840a:	6103      	str	r3, [r0, #16]
 800840c:	bd10      	pop	{r4, pc}
 800840e:	bf00      	nop
 8008410:	0800a70f 	.word	0x0800a70f
 8008414:	0800a720 	.word	0x0800a720

08008418 <__multiply>:
 8008418:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 800841c:	4614      	mov	r4, r2
 800841e:	690a      	ldr	r2, [r1, #16]
 8008420:	6923      	ldr	r3, [r4, #16]
 8008422:	460d      	mov	r5, r1
 8008424:	429a      	cmp	r2, r3
 8008426:	bfbe      	ittt	lt
 8008428:	460b      	movlt	r3, r1
 800842a:	4625      	movlt	r5, r4
 800842c:	461c      	movlt	r4, r3
 800842e:	f8d5 a010 	ldr.w	sl, [r5, #16]
 8008432:	f8d4 9010 	ldr.w	r9, [r4, #16]
 8008436:	68ab      	ldr	r3, [r5, #8]
 8008438:	6869      	ldr	r1, [r5, #4]
 800843a:	eb0a 0709 	add.w	r7, sl, r9
 800843e:	42bb      	cmp	r3, r7
 8008440:	b085      	sub	sp, #20
 8008442:	bfb8      	it	lt
 8008444:	3101      	addlt	r1, #1
 8008446:	f7ff fed7 	bl	80081f8 <_Balloc>
 800844a:	b930      	cbnz	r0, 800845a <__multiply+0x42>
 800844c:	4602      	mov	r2, r0
 800844e:	f240 115d 	movw	r1, #349	; 0x15d
 8008452:	4b41      	ldr	r3, [pc, #260]	; (8008558 <__multiply+0x140>)
 8008454:	4841      	ldr	r0, [pc, #260]	; (800855c <__multiply+0x144>)
 8008456:	f000 fc71 	bl	8008d3c <__assert_func>
 800845a:	f100 0614 	add.w	r6, r0, #20
 800845e:	4633      	mov	r3, r6
 8008460:	2200      	movs	r2, #0
 8008462:	eb06 0887 	add.w	r8, r6, r7, lsl #2
 8008466:	4543      	cmp	r3, r8
 8008468:	d31e      	bcc.n	80084a8 <__multiply+0x90>
 800846a:	f105 0c14 	add.w	ip, r5, #20
 800846e:	f104 0314 	add.w	r3, r4, #20
 8008472:	eb0c 0c8a 	add.w	ip, ip, sl, lsl #2
 8008476:	eb03 0289 	add.w	r2, r3, r9, lsl #2
 800847a:	9202      	str	r2, [sp, #8]
 800847c:	ebac 0205 	sub.w	r2, ip, r5
 8008480:	3a15      	subs	r2, #21
 8008482:	f022 0203 	bic.w	r2, r2, #3
 8008486:	3204      	adds	r2, #4
 8008488:	f105 0115 	add.w	r1, r5, #21
 800848c:	458c      	cmp	ip, r1
 800848e:	bf38      	it	cc
 8008490:	2204      	movcc	r2, #4
 8008492:	9201      	str	r2, [sp, #4]
 8008494:	9a02      	ldr	r2, [sp, #8]
 8008496:	9303      	str	r3, [sp, #12]
 8008498:	429a      	cmp	r2, r3
 800849a:	d808      	bhi.n	80084ae <__multiply+0x96>
 800849c:	2f00      	cmp	r7, #0
 800849e:	dc55      	bgt.n	800854c <__multiply+0x134>
 80084a0:	6107      	str	r7, [r0, #16]
 80084a2:	b005      	add	sp, #20
 80084a4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 80084a8:	f843 2b04 	str.w	r2, [r3], #4
 80084ac:	e7db      	b.n	8008466 <__multiply+0x4e>
 80084ae:	f8b3 a000 	ldrh.w	sl, [r3]
 80084b2:	f1ba 0f00 	cmp.w	sl, #0
 80084b6:	d020      	beq.n	80084fa <__multiply+0xe2>
 80084b8:	46b1      	mov	r9, r6
 80084ba:	2200      	movs	r2, #0
 80084bc:	f105 0e14 	add.w	lr, r5, #20
 80084c0:	f85e 4b04 	ldr.w	r4, [lr], #4
 80084c4:	f8d9 b000 	ldr.w	fp, [r9]
 80084c8:	b2a1      	uxth	r1, r4
 80084ca:	fa1f fb8b 	uxth.w	fp, fp
 80084ce:	fb0a b101 	mla	r1, sl, r1, fp
 80084d2:	4411      	add	r1, r2
 80084d4:	f8d9 2000 	ldr.w	r2, [r9]
 80084d8:	0c24      	lsrs	r4, r4, #16
 80084da:	0c12      	lsrs	r2, r2, #16
 80084dc:	fb0a 2404 	mla	r4, sl, r4, r2
 80084e0:	eb04 4411 	add.w	r4, r4, r1, lsr #16
 80084e4:	b289      	uxth	r1, r1
 80084e6:	ea41 4104 	orr.w	r1, r1, r4, lsl #16
 80084ea:	45f4      	cmp	ip, lr
 80084ec:	ea4f 4214 	mov.w	r2, r4, lsr #16
 80084f0:	f849 1b04 	str.w	r1, [r9], #4
 80084f4:	d8e4      	bhi.n	80084c0 <__multiply+0xa8>
 80084f6:	9901      	ldr	r1, [sp, #4]
 80084f8:	5072      	str	r2, [r6, r1]
 80084fa:	9a03      	ldr	r2, [sp, #12]
 80084fc:	3304      	adds	r3, #4
 80084fe:	f8b2 9002 	ldrh.w	r9, [r2, #2]
 8008502:	f1b9 0f00 	cmp.w	r9, #0
 8008506:	d01f      	beq.n	8008548 <__multiply+0x130>
 8008508:	46b6      	mov	lr, r6
 800850a:	f04f 0a00 	mov.w	sl, #0
 800850e:	6834      	ldr	r4, [r6, #0]
 8008510:	f105 0114 	add.w	r1, r5, #20
 8008514:	880a      	ldrh	r2, [r1, #0]
 8008516:	f8be b002 	ldrh.w	fp, [lr, #2]
 800851a:	b2a4      	uxth	r4, r4
 800851c:	fb09 b202 	mla	r2, r9, r2, fp
 8008520:	4492      	add	sl, r2
 8008522:	ea44 440a 	orr.w	r4, r4, sl, lsl #16
 8008526:	f84e 4b04 	str.w	r4, [lr], #4
 800852a:	f851 4b04 	ldr.w	r4, [r1], #4
 800852e:	f8be 2000 	ldrh.w	r2, [lr]
 8008532:	0c24      	lsrs	r4, r4, #16
 8008534:	fb09 2404 	mla	r4, r9, r4, r2
 8008538:	458c      	cmp	ip, r1
 800853a:	eb04 441a 	add.w	r4, r4, sl, lsr #16
 800853e:	ea4f 4a14 	mov.w	sl, r4, lsr #16
 8008542:	d8e7      	bhi.n	8008514 <__multiply+0xfc>
 8008544:	9a01      	ldr	r2, [sp, #4]
 8008546:	50b4      	str	r4, [r6, r2]
 8008548:	3604      	adds	r6, #4
 800854a:	e7a3      	b.n	8008494 <__multiply+0x7c>
 800854c:	f858 3d04 	ldr.w	r3, [r8, #-4]!
 8008550:	2b00      	cmp	r3, #0
 8008552:	d1a5      	bne.n	80084a0 <__multiply+0x88>
 8008554:	3f01      	subs	r7, #1
 8008556:	e7a1      	b.n	800849c <__multiply+0x84>
 8008558:	0800a70f 	.word	0x0800a70f
 800855c:	0800a720 	.word	0x0800a720

08008560 <__pow5mult>:
 8008560:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8008564:	4615      	mov	r5, r2
 8008566:	f012 0203 	ands.w	r2, r2, #3
 800856a:	4606      	mov	r6, r0
 800856c:	460f      	mov	r7, r1
 800856e:	d007      	beq.n	8008580 <__pow5mult+0x20>
 8008570:	4c25      	ldr	r4, [pc, #148]	; (8008608 <__pow5mult+0xa8>)
 8008572:	3a01      	subs	r2, #1
 8008574:	2300      	movs	r3, #0
 8008576:	f854 2022 	ldr.w	r2, [r4, r2, lsl #2]
 800857a:	f7ff fe9f 	bl	80082bc <__multadd>
 800857e:	4607      	mov	r7, r0
 8008580:	10ad      	asrs	r5, r5, #2
 8008582:	d03d      	beq.n	8008600 <__pow5mult+0xa0>
 8008584:	6a74      	ldr	r4, [r6, #36]	; 0x24
 8008586:	b97c      	cbnz	r4, 80085a8 <__pow5mult+0x48>
 8008588:	2010      	movs	r0, #16
 800858a:	f7ff fe1f 	bl	80081cc <malloc>
 800858e:	4602      	mov	r2, r0
 8008590:	6270      	str	r0, [r6, #36]	; 0x24
 8008592:	b928      	cbnz	r0, 80085a0 <__pow5mult+0x40>
 8008594:	f44f 71d7 	mov.w	r1, #430	; 0x1ae
 8008598:	4b1c      	ldr	r3, [pc, #112]	; (800860c <__pow5mult+0xac>)
 800859a:	481d      	ldr	r0, [pc, #116]	; (8008610 <__pow5mult+0xb0>)
 800859c:	f000 fbce 	bl	8008d3c <__assert_func>
 80085a0:	e9c0 4401 	strd	r4, r4, [r0, #4]
 80085a4:	6004      	str	r4, [r0, #0]
 80085a6:	60c4      	str	r4, [r0, #12]
 80085a8:	f8d6 8024 	ldr.w	r8, [r6, #36]	; 0x24
 80085ac:	f8d8 4008 	ldr.w	r4, [r8, #8]
 80085b0:	b94c      	cbnz	r4, 80085c6 <__pow5mult+0x66>
 80085b2:	f240 2171 	movw	r1, #625	; 0x271
 80085b6:	4630      	mov	r0, r6
 80085b8:	f7ff ff18 	bl	80083ec <__i2b>
 80085bc:	2300      	movs	r3, #0
 80085be:	4604      	mov	r4, r0
 80085c0:	f8c8 0008 	str.w	r0, [r8, #8]
 80085c4:	6003      	str	r3, [r0, #0]
 80085c6:	f04f 0900 	mov.w	r9, #0
 80085ca:	07eb      	lsls	r3, r5, #31
 80085cc:	d50a      	bpl.n	80085e4 <__pow5mult+0x84>
 80085ce:	4639      	mov	r1, r7
 80085d0:	4622      	mov	r2, r4
 80085d2:	4630      	mov	r0, r6
 80085d4:	f7ff ff20 	bl	8008418 <__multiply>
 80085d8:	4680      	mov	r8, r0
 80085da:	4639      	mov	r1, r7
 80085dc:	4630      	mov	r0, r6
 80085de:	f7ff fe4b 	bl	8008278 <_Bfree>
 80085e2:	4647      	mov	r7, r8
 80085e4:	106d      	asrs	r5, r5, #1
 80085e6:	d00b      	beq.n	8008600 <__pow5mult+0xa0>
 80085e8:	6820      	ldr	r0, [r4, #0]
 80085ea:	b938      	cbnz	r0, 80085fc <__pow5mult+0x9c>
 80085ec:	4622      	mov	r2, r4
 80085ee:	4621      	mov	r1, r4
 80085f0:	4630      	mov	r0, r6
 80085f2:	f7ff ff11 	bl	8008418 <__multiply>
 80085f6:	6020      	str	r0, [r4, #0]
 80085f8:	f8c0 9000 	str.w	r9, [r0]
 80085fc:	4604      	mov	r4, r0
 80085fe:	e7e4      	b.n	80085ca <__pow5mult+0x6a>
 8008600:	4638      	mov	r0, r7
 8008602:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8008606:	bf00      	nop
 8008608:	0800a870 	.word	0x0800a870
 800860c:	0800a699 	.word	0x0800a699
 8008610:	0800a720 	.word	0x0800a720

08008614 <__lshift>:
 8008614:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8008618:	460c      	mov	r4, r1
 800861a:	4607      	mov	r7, r0
 800861c:	4691      	mov	r9, r2
 800861e:	6923      	ldr	r3, [r4, #16]
 8008620:	6849      	ldr	r1, [r1, #4]
 8008622:	eb03 1862 	add.w	r8, r3, r2, asr #5
 8008626:	68a3      	ldr	r3, [r4, #8]
 8008628:	ea4f 1a62 	mov.w	sl, r2, asr #5
 800862c:	f108 0601 	add.w	r6, r8, #1
 8008630:	42b3      	cmp	r3, r6
 8008632:	db0b      	blt.n	800864c <__lshift+0x38>
 8008634:	4638      	mov	r0, r7
 8008636:	f7ff fddf 	bl	80081f8 <_Balloc>
 800863a:	4605      	mov	r5, r0
 800863c:	b948      	cbnz	r0, 8008652 <__lshift+0x3e>
 800863e:	4602      	mov	r2, r0
 8008640:	f240 11d9 	movw	r1, #473	; 0x1d9
 8008644:	4b27      	ldr	r3, [pc, #156]	; (80086e4 <__lshift+0xd0>)
 8008646:	4828      	ldr	r0, [pc, #160]	; (80086e8 <__lshift+0xd4>)
 8008648:	f000 fb78 	bl	8008d3c <__assert_func>
 800864c:	3101      	adds	r1, #1
 800864e:	005b      	lsls	r3, r3, #1
 8008650:	e7ee      	b.n	8008630 <__lshift+0x1c>
 8008652:	2300      	movs	r3, #0
 8008654:	f100 0114 	add.w	r1, r0, #20
 8008658:	f100 0210 	add.w	r2, r0, #16
 800865c:	4618      	mov	r0, r3
 800865e:	4553      	cmp	r3, sl
 8008660:	db33      	blt.n	80086ca <__lshift+0xb6>
 8008662:	6920      	ldr	r0, [r4, #16]
 8008664:	ea2a 7aea 	bic.w	sl, sl, sl, asr #31
 8008668:	f104 0314 	add.w	r3, r4, #20
 800866c:	f019 091f 	ands.w	r9, r9, #31
 8008670:	eb01 018a 	add.w	r1, r1, sl, lsl #2
 8008674:	eb03 0c80 	add.w	ip, r3, r0, lsl #2
 8008678:	d02b      	beq.n	80086d2 <__lshift+0xbe>
 800867a:	468a      	mov	sl, r1
 800867c:	2200      	movs	r2, #0
 800867e:	f1c9 0e20 	rsb	lr, r9, #32
 8008682:	6818      	ldr	r0, [r3, #0]
 8008684:	fa00 f009 	lsl.w	r0, r0, r9
 8008688:	4302      	orrs	r2, r0
 800868a:	f84a 2b04 	str.w	r2, [sl], #4
 800868e:	f853 2b04 	ldr.w	r2, [r3], #4
 8008692:	459c      	cmp	ip, r3
 8008694:	fa22 f20e 	lsr.w	r2, r2, lr
 8008698:	d8f3      	bhi.n	8008682 <__lshift+0x6e>
 800869a:	ebac 0304 	sub.w	r3, ip, r4
 800869e:	3b15      	subs	r3, #21
 80086a0:	f023 0303 	bic.w	r3, r3, #3
 80086a4:	3304      	adds	r3, #4
 80086a6:	f104 0015 	add.w	r0, r4, #21
 80086aa:	4584      	cmp	ip, r0
 80086ac:	bf38      	it	cc
 80086ae:	2304      	movcc	r3, #4
 80086b0:	50ca      	str	r2, [r1, r3]
 80086b2:	b10a      	cbz	r2, 80086b8 <__lshift+0xa4>
 80086b4:	f108 0602 	add.w	r6, r8, #2
 80086b8:	3e01      	subs	r6, #1
 80086ba:	4638      	mov	r0, r7
 80086bc:	4621      	mov	r1, r4
 80086be:	612e      	str	r6, [r5, #16]
 80086c0:	f7ff fdda 	bl	8008278 <_Bfree>
 80086c4:	4628      	mov	r0, r5
 80086c6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80086ca:	f842 0f04 	str.w	r0, [r2, #4]!
 80086ce:	3301      	adds	r3, #1
 80086d0:	e7c5      	b.n	800865e <__lshift+0x4a>
 80086d2:	3904      	subs	r1, #4
 80086d4:	f853 2b04 	ldr.w	r2, [r3], #4
 80086d8:	459c      	cmp	ip, r3
 80086da:	f841 2f04 	str.w	r2, [r1, #4]!
 80086de:	d8f9      	bhi.n	80086d4 <__lshift+0xc0>
 80086e0:	e7ea      	b.n	80086b8 <__lshift+0xa4>
 80086e2:	bf00      	nop
 80086e4:	0800a70f 	.word	0x0800a70f
 80086e8:	0800a720 	.word	0x0800a720

080086ec <__mcmp>:
 80086ec:	4603      	mov	r3, r0
 80086ee:	690a      	ldr	r2, [r1, #16]
 80086f0:	6900      	ldr	r0, [r0, #16]
 80086f2:	b530      	push	{r4, r5, lr}
 80086f4:	1a80      	subs	r0, r0, r2
 80086f6:	d10d      	bne.n	8008714 <__mcmp+0x28>
 80086f8:	3314      	adds	r3, #20
 80086fa:	3114      	adds	r1, #20
 80086fc:	eb03 0482 	add.w	r4, r3, r2, lsl #2
 8008700:	eb01 0182 	add.w	r1, r1, r2, lsl #2
 8008704:	f854 5d04 	ldr.w	r5, [r4, #-4]!
 8008708:	f851 2d04 	ldr.w	r2, [r1, #-4]!
 800870c:	4295      	cmp	r5, r2
 800870e:	d002      	beq.n	8008716 <__mcmp+0x2a>
 8008710:	d304      	bcc.n	800871c <__mcmp+0x30>
 8008712:	2001      	movs	r0, #1
 8008714:	bd30      	pop	{r4, r5, pc}
 8008716:	42a3      	cmp	r3, r4
 8008718:	d3f4      	bcc.n	8008704 <__mcmp+0x18>
 800871a:	e7fb      	b.n	8008714 <__mcmp+0x28>
 800871c:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8008720:	e7f8      	b.n	8008714 <__mcmp+0x28>
	...

08008724 <__mdiff>:
 8008724:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008728:	460c      	mov	r4, r1
 800872a:	4606      	mov	r6, r0
 800872c:	4611      	mov	r1, r2
 800872e:	4620      	mov	r0, r4
 8008730:	4692      	mov	sl, r2
 8008732:	f7ff ffdb 	bl	80086ec <__mcmp>
 8008736:	1e05      	subs	r5, r0, #0
 8008738:	d111      	bne.n	800875e <__mdiff+0x3a>
 800873a:	4629      	mov	r1, r5
 800873c:	4630      	mov	r0, r6
 800873e:	f7ff fd5b 	bl	80081f8 <_Balloc>
 8008742:	4602      	mov	r2, r0
 8008744:	b928      	cbnz	r0, 8008752 <__mdiff+0x2e>
 8008746:	f240 2132 	movw	r1, #562	; 0x232
 800874a:	4b3c      	ldr	r3, [pc, #240]	; (800883c <__mdiff+0x118>)
 800874c:	483c      	ldr	r0, [pc, #240]	; (8008840 <__mdiff+0x11c>)
 800874e:	f000 faf5 	bl	8008d3c <__assert_func>
 8008752:	2301      	movs	r3, #1
 8008754:	e9c0 3504 	strd	r3, r5, [r0, #16]
 8008758:	4610      	mov	r0, r2
 800875a:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
 800875e:	bfa4      	itt	ge
 8008760:	4653      	movge	r3, sl
 8008762:	46a2      	movge	sl, r4
 8008764:	4630      	mov	r0, r6
 8008766:	f8da 1004 	ldr.w	r1, [sl, #4]
 800876a:	bfa6      	itte	ge
 800876c:	461c      	movge	r4, r3
 800876e:	2500      	movge	r5, #0
 8008770:	2501      	movlt	r5, #1
 8008772:	f7ff fd41 	bl	80081f8 <_Balloc>
 8008776:	4602      	mov	r2, r0
 8008778:	b918      	cbnz	r0, 8008782 <__mdiff+0x5e>
 800877a:	f44f 7110 	mov.w	r1, #576	; 0x240
 800877e:	4b2f      	ldr	r3, [pc, #188]	; (800883c <__mdiff+0x118>)
 8008780:	e7e4      	b.n	800874c <__mdiff+0x28>
 8008782:	f100 0814 	add.w	r8, r0, #20
 8008786:	f8da 7010 	ldr.w	r7, [sl, #16]
 800878a:	60c5      	str	r5, [r0, #12]
 800878c:	f04f 0c00 	mov.w	ip, #0
 8008790:	f10a 0514 	add.w	r5, sl, #20
 8008794:	f10a 0010 	add.w	r0, sl, #16
 8008798:	46c2      	mov	sl, r8
 800879a:	6926      	ldr	r6, [r4, #16]
 800879c:	f104 0914 	add.w	r9, r4, #20
 80087a0:	eb05 0e87 	add.w	lr, r5, r7, lsl #2
 80087a4:	eb09 0686 	add.w	r6, r9, r6, lsl #2
 80087a8:	f850 bf04 	ldr.w	fp, [r0, #4]!
 80087ac:	f859 3b04 	ldr.w	r3, [r9], #4
 80087b0:	fa1f f18b 	uxth.w	r1, fp
 80087b4:	4461      	add	r1, ip
 80087b6:	fa1f fc83 	uxth.w	ip, r3
 80087ba:	0c1b      	lsrs	r3, r3, #16
 80087bc:	eba1 010c 	sub.w	r1, r1, ip
 80087c0:	ebc3 431b 	rsb	r3, r3, fp, lsr #16
 80087c4:	eb03 4321 	add.w	r3, r3, r1, asr #16
 80087c8:	b289      	uxth	r1, r1
 80087ca:	ea4f 4c23 	mov.w	ip, r3, asr #16
 80087ce:	454e      	cmp	r6, r9
 80087d0:	ea41 4303 	orr.w	r3, r1, r3, lsl #16
 80087d4:	f84a 3b04 	str.w	r3, [sl], #4
 80087d8:	d8e6      	bhi.n	80087a8 <__mdiff+0x84>
 80087da:	1b33      	subs	r3, r6, r4
 80087dc:	3b15      	subs	r3, #21
 80087de:	f023 0303 	bic.w	r3, r3, #3
 80087e2:	3415      	adds	r4, #21
 80087e4:	3304      	adds	r3, #4
 80087e6:	42a6      	cmp	r6, r4
 80087e8:	bf38      	it	cc
 80087ea:	2304      	movcc	r3, #4
 80087ec:	441d      	add	r5, r3
 80087ee:	4443      	add	r3, r8
 80087f0:	461e      	mov	r6, r3
 80087f2:	462c      	mov	r4, r5
 80087f4:	4574      	cmp	r4, lr
 80087f6:	d30e      	bcc.n	8008816 <__mdiff+0xf2>
 80087f8:	f10e 0103 	add.w	r1, lr, #3
 80087fc:	1b49      	subs	r1, r1, r5
 80087fe:	f021 0103 	bic.w	r1, r1, #3
 8008802:	3d03      	subs	r5, #3
 8008804:	45ae      	cmp	lr, r5
 8008806:	bf38      	it	cc
 8008808:	2100      	movcc	r1, #0
 800880a:	4419      	add	r1, r3
 800880c:	f851 3d04 	ldr.w	r3, [r1, #-4]!
 8008810:	b18b      	cbz	r3, 8008836 <__mdiff+0x112>
 8008812:	6117      	str	r7, [r2, #16]
 8008814:	e7a0      	b.n	8008758 <__mdiff+0x34>
 8008816:	f854 8b04 	ldr.w	r8, [r4], #4
 800881a:	fa1f f188 	uxth.w	r1, r8
 800881e:	4461      	add	r1, ip
 8008820:	1408      	asrs	r0, r1, #16
 8008822:	eb00 4018 	add.w	r0, r0, r8, lsr #16
 8008826:	b289      	uxth	r1, r1
 8008828:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
 800882c:	ea4f 4c20 	mov.w	ip, r0, asr #16
 8008830:	f846 1b04 	str.w	r1, [r6], #4
 8008834:	e7de      	b.n	80087f4 <__mdiff+0xd0>
 8008836:	3f01      	subs	r7, #1
 8008838:	e7e8      	b.n	800880c <__mdiff+0xe8>
 800883a:	bf00      	nop
 800883c:	0800a70f 	.word	0x0800a70f
 8008840:	0800a720 	.word	0x0800a720

08008844 <__d2b>:
 8008844:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
 8008848:	2101      	movs	r1, #1
 800884a:	e9dd 7608 	ldrd	r7, r6, [sp, #32]
 800884e:	4690      	mov	r8, r2
 8008850:	461d      	mov	r5, r3
 8008852:	f7ff fcd1 	bl	80081f8 <_Balloc>
 8008856:	4604      	mov	r4, r0
 8008858:	b930      	cbnz	r0, 8008868 <__d2b+0x24>
 800885a:	4602      	mov	r2, r0
 800885c:	f240 310a 	movw	r1, #778	; 0x30a
 8008860:	4b24      	ldr	r3, [pc, #144]	; (80088f4 <__d2b+0xb0>)
 8008862:	4825      	ldr	r0, [pc, #148]	; (80088f8 <__d2b+0xb4>)
 8008864:	f000 fa6a 	bl	8008d3c <__assert_func>
 8008868:	f3c5 0313 	ubfx	r3, r5, #0, #20
 800886c:	f3c5 550a 	ubfx	r5, r5, #20, #11
 8008870:	bb2d      	cbnz	r5, 80088be <__d2b+0x7a>
 8008872:	9301      	str	r3, [sp, #4]
 8008874:	f1b8 0300 	subs.w	r3, r8, #0
 8008878:	d026      	beq.n	80088c8 <__d2b+0x84>
 800887a:	4668      	mov	r0, sp
 800887c:	9300      	str	r3, [sp, #0]
 800887e:	f7ff fd87 	bl	8008390 <__lo0bits>
 8008882:	9900      	ldr	r1, [sp, #0]
 8008884:	b1f0      	cbz	r0, 80088c4 <__d2b+0x80>
 8008886:	9a01      	ldr	r2, [sp, #4]
 8008888:	f1c0 0320 	rsb	r3, r0, #32
 800888c:	fa02 f303 	lsl.w	r3, r2, r3
 8008890:	430b      	orrs	r3, r1
 8008892:	40c2      	lsrs	r2, r0
 8008894:	6163      	str	r3, [r4, #20]
 8008896:	9201      	str	r2, [sp, #4]
 8008898:	9b01      	ldr	r3, [sp, #4]
 800889a:	2b00      	cmp	r3, #0
 800889c:	bf14      	ite	ne
 800889e:	2102      	movne	r1, #2
 80088a0:	2101      	moveq	r1, #1
 80088a2:	61a3      	str	r3, [r4, #24]
 80088a4:	6121      	str	r1, [r4, #16]
 80088a6:	b1c5      	cbz	r5, 80088da <__d2b+0x96>
 80088a8:	f2a5 4533 	subw	r5, r5, #1075	; 0x433
 80088ac:	4405      	add	r5, r0
 80088ae:	f1c0 0035 	rsb	r0, r0, #53	; 0x35
 80088b2:	603d      	str	r5, [r7, #0]
 80088b4:	6030      	str	r0, [r6, #0]
 80088b6:	4620      	mov	r0, r4
 80088b8:	b002      	add	sp, #8
 80088ba:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 80088be:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 80088c2:	e7d6      	b.n	8008872 <__d2b+0x2e>
 80088c4:	6161      	str	r1, [r4, #20]
 80088c6:	e7e7      	b.n	8008898 <__d2b+0x54>
 80088c8:	a801      	add	r0, sp, #4
 80088ca:	f7ff fd61 	bl	8008390 <__lo0bits>
 80088ce:	2101      	movs	r1, #1
 80088d0:	9b01      	ldr	r3, [sp, #4]
 80088d2:	6121      	str	r1, [r4, #16]
 80088d4:	6163      	str	r3, [r4, #20]
 80088d6:	3020      	adds	r0, #32
 80088d8:	e7e5      	b.n	80088a6 <__d2b+0x62>
 80088da:	eb04 0381 	add.w	r3, r4, r1, lsl #2
 80088de:	f2a0 4032 	subw	r0, r0, #1074	; 0x432
 80088e2:	6038      	str	r0, [r7, #0]
 80088e4:	6918      	ldr	r0, [r3, #16]
 80088e6:	f7ff fd33 	bl	8008350 <__hi0bits>
 80088ea:	ebc0 1141 	rsb	r1, r0, r1, lsl #5
 80088ee:	6031      	str	r1, [r6, #0]
 80088f0:	e7e1      	b.n	80088b6 <__d2b+0x72>
 80088f2:	bf00      	nop
 80088f4:	0800a70f 	.word	0x0800a70f
 80088f8:	0800a720 	.word	0x0800a720

080088fc <_calloc_r>:
 80088fc:	b538      	push	{r3, r4, r5, lr}
 80088fe:	fb02 f501 	mul.w	r5, r2, r1
 8008902:	4629      	mov	r1, r5
 8008904:	f000 f854 	bl	80089b0 <_malloc_r>
 8008908:	4604      	mov	r4, r0
 800890a:	b118      	cbz	r0, 8008914 <_calloc_r+0x18>
 800890c:	462a      	mov	r2, r5
 800890e:	2100      	movs	r1, #0
 8008910:	f7fe f952 	bl	8006bb8 <memset>
 8008914:	4620      	mov	r0, r4
 8008916:	bd38      	pop	{r3, r4, r5, pc}

08008918 <_free_r>:
 8008918:	b538      	push	{r3, r4, r5, lr}
 800891a:	4605      	mov	r5, r0
 800891c:	2900      	cmp	r1, #0
 800891e:	d043      	beq.n	80089a8 <_free_r+0x90>
 8008920:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8008924:	1f0c      	subs	r4, r1, #4
 8008926:	2b00      	cmp	r3, #0
 8008928:	bfb8      	it	lt
 800892a:	18e4      	addlt	r4, r4, r3
 800892c:	f000 fa48 	bl	8008dc0 <__malloc_lock>
 8008930:	4a1e      	ldr	r2, [pc, #120]	; (80089ac <_free_r+0x94>)
 8008932:	6813      	ldr	r3, [r2, #0]
 8008934:	4610      	mov	r0, r2
 8008936:	b933      	cbnz	r3, 8008946 <_free_r+0x2e>
 8008938:	6063      	str	r3, [r4, #4]
 800893a:	6014      	str	r4, [r2, #0]
 800893c:	4628      	mov	r0, r5
 800893e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8008942:	f000 ba43 	b.w	8008dcc <__malloc_unlock>
 8008946:	42a3      	cmp	r3, r4
 8008948:	d90a      	bls.n	8008960 <_free_r+0x48>
 800894a:	6821      	ldr	r1, [r4, #0]
 800894c:	1862      	adds	r2, r4, r1
 800894e:	4293      	cmp	r3, r2
 8008950:	bf01      	itttt	eq
 8008952:	681a      	ldreq	r2, [r3, #0]
 8008954:	685b      	ldreq	r3, [r3, #4]
 8008956:	1852      	addeq	r2, r2, r1
 8008958:	6022      	streq	r2, [r4, #0]
 800895a:	6063      	str	r3, [r4, #4]
 800895c:	6004      	str	r4, [r0, #0]
 800895e:	e7ed      	b.n	800893c <_free_r+0x24>
 8008960:	461a      	mov	r2, r3
 8008962:	685b      	ldr	r3, [r3, #4]
 8008964:	b10b      	cbz	r3, 800896a <_free_r+0x52>
 8008966:	42a3      	cmp	r3, r4
 8008968:	d9fa      	bls.n	8008960 <_free_r+0x48>
 800896a:	6811      	ldr	r1, [r2, #0]
 800896c:	1850      	adds	r0, r2, r1
 800896e:	42a0      	cmp	r0, r4
 8008970:	d10b      	bne.n	800898a <_free_r+0x72>
 8008972:	6820      	ldr	r0, [r4, #0]
 8008974:	4401      	add	r1, r0
 8008976:	1850      	adds	r0, r2, r1
 8008978:	4283      	cmp	r3, r0
 800897a:	6011      	str	r1, [r2, #0]
 800897c:	d1de      	bne.n	800893c <_free_r+0x24>
 800897e:	6818      	ldr	r0, [r3, #0]
 8008980:	685b      	ldr	r3, [r3, #4]
 8008982:	4401      	add	r1, r0
 8008984:	6011      	str	r1, [r2, #0]
 8008986:	6053      	str	r3, [r2, #4]
 8008988:	e7d8      	b.n	800893c <_free_r+0x24>
 800898a:	d902      	bls.n	8008992 <_free_r+0x7a>
 800898c:	230c      	movs	r3, #12
 800898e:	602b      	str	r3, [r5, #0]
 8008990:	e7d4      	b.n	800893c <_free_r+0x24>
 8008992:	6820      	ldr	r0, [r4, #0]
 8008994:	1821      	adds	r1, r4, r0
 8008996:	428b      	cmp	r3, r1
 8008998:	bf01      	itttt	eq
 800899a:	6819      	ldreq	r1, [r3, #0]
 800899c:	685b      	ldreq	r3, [r3, #4]
 800899e:	1809      	addeq	r1, r1, r0
 80089a0:	6021      	streq	r1, [r4, #0]
 80089a2:	6063      	str	r3, [r4, #4]
 80089a4:	6054      	str	r4, [r2, #4]
 80089a6:	e7c9      	b.n	800893c <_free_r+0x24>
 80089a8:	bd38      	pop	{r3, r4, r5, pc}
 80089aa:	bf00      	nop
 80089ac:	20000410 	.word	0x20000410

080089b0 <_malloc_r>:
 80089b0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80089b2:	1ccd      	adds	r5, r1, #3
 80089b4:	f025 0503 	bic.w	r5, r5, #3
 80089b8:	3508      	adds	r5, #8
 80089ba:	2d0c      	cmp	r5, #12
 80089bc:	bf38      	it	cc
 80089be:	250c      	movcc	r5, #12
 80089c0:	2d00      	cmp	r5, #0
 80089c2:	4606      	mov	r6, r0
 80089c4:	db01      	blt.n	80089ca <_malloc_r+0x1a>
 80089c6:	42a9      	cmp	r1, r5
 80089c8:	d903      	bls.n	80089d2 <_malloc_r+0x22>
 80089ca:	230c      	movs	r3, #12
 80089cc:	6033      	str	r3, [r6, #0]
 80089ce:	2000      	movs	r0, #0
 80089d0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 80089d2:	f000 f9f5 	bl	8008dc0 <__malloc_lock>
 80089d6:	4921      	ldr	r1, [pc, #132]	; (8008a5c <_malloc_r+0xac>)
 80089d8:	680a      	ldr	r2, [r1, #0]
 80089da:	4614      	mov	r4, r2
 80089dc:	b99c      	cbnz	r4, 8008a06 <_malloc_r+0x56>
 80089de:	4f20      	ldr	r7, [pc, #128]	; (8008a60 <_malloc_r+0xb0>)
 80089e0:	683b      	ldr	r3, [r7, #0]
 80089e2:	b923      	cbnz	r3, 80089ee <_malloc_r+0x3e>
 80089e4:	4621      	mov	r1, r4
 80089e6:	4630      	mov	r0, r6
 80089e8:	f000 f998 	bl	8008d1c <_sbrk_r>
 80089ec:	6038      	str	r0, [r7, #0]
 80089ee:	4629      	mov	r1, r5
 80089f0:	4630      	mov	r0, r6
 80089f2:	f000 f993 	bl	8008d1c <_sbrk_r>
 80089f6:	1c43      	adds	r3, r0, #1
 80089f8:	d123      	bne.n	8008a42 <_malloc_r+0x92>
 80089fa:	230c      	movs	r3, #12
 80089fc:	4630      	mov	r0, r6
 80089fe:	6033      	str	r3, [r6, #0]
 8008a00:	f000 f9e4 	bl	8008dcc <__malloc_unlock>
 8008a04:	e7e3      	b.n	80089ce <_malloc_r+0x1e>
 8008a06:	6823      	ldr	r3, [r4, #0]
 8008a08:	1b5b      	subs	r3, r3, r5
 8008a0a:	d417      	bmi.n	8008a3c <_malloc_r+0x8c>
 8008a0c:	2b0b      	cmp	r3, #11
 8008a0e:	d903      	bls.n	8008a18 <_malloc_r+0x68>
 8008a10:	6023      	str	r3, [r4, #0]
 8008a12:	441c      	add	r4, r3
 8008a14:	6025      	str	r5, [r4, #0]
 8008a16:	e004      	b.n	8008a22 <_malloc_r+0x72>
 8008a18:	6863      	ldr	r3, [r4, #4]
 8008a1a:	42a2      	cmp	r2, r4
 8008a1c:	bf0c      	ite	eq
 8008a1e:	600b      	streq	r3, [r1, #0]
 8008a20:	6053      	strne	r3, [r2, #4]
 8008a22:	4630      	mov	r0, r6
 8008a24:	f000 f9d2 	bl	8008dcc <__malloc_unlock>
 8008a28:	f104 000b 	add.w	r0, r4, #11
 8008a2c:	1d23      	adds	r3, r4, #4
 8008a2e:	f020 0007 	bic.w	r0, r0, #7
 8008a32:	1ac2      	subs	r2, r0, r3
 8008a34:	d0cc      	beq.n	80089d0 <_malloc_r+0x20>
 8008a36:	1a1b      	subs	r3, r3, r0
 8008a38:	50a3      	str	r3, [r4, r2]
 8008a3a:	e7c9      	b.n	80089d0 <_malloc_r+0x20>
 8008a3c:	4622      	mov	r2, r4
 8008a3e:	6864      	ldr	r4, [r4, #4]
 8008a40:	e7cc      	b.n	80089dc <_malloc_r+0x2c>
 8008a42:	1cc4      	adds	r4, r0, #3
 8008a44:	f024 0403 	bic.w	r4, r4, #3
 8008a48:	42a0      	cmp	r0, r4
 8008a4a:	d0e3      	beq.n	8008a14 <_malloc_r+0x64>
 8008a4c:	1a21      	subs	r1, r4, r0
 8008a4e:	4630      	mov	r0, r6
 8008a50:	f000 f964 	bl	8008d1c <_sbrk_r>
 8008a54:	3001      	adds	r0, #1
 8008a56:	d1dd      	bne.n	8008a14 <_malloc_r+0x64>
 8008a58:	e7cf      	b.n	80089fa <_malloc_r+0x4a>
 8008a5a:	bf00      	nop
 8008a5c:	20000410 	.word	0x20000410
 8008a60:	20000414 	.word	0x20000414

08008a64 <__ssputs_r>:
 8008a64:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8008a68:	688e      	ldr	r6, [r1, #8]
 8008a6a:	4682      	mov	sl, r0
 8008a6c:	429e      	cmp	r6, r3
 8008a6e:	460c      	mov	r4, r1
 8008a70:	4690      	mov	r8, r2
 8008a72:	461f      	mov	r7, r3
 8008a74:	d838      	bhi.n	8008ae8 <__ssputs_r+0x84>
 8008a76:	898a      	ldrh	r2, [r1, #12]
 8008a78:	f412 6f90 	tst.w	r2, #1152	; 0x480
 8008a7c:	d032      	beq.n	8008ae4 <__ssputs_r+0x80>
 8008a7e:	6825      	ldr	r5, [r4, #0]
 8008a80:	6909      	ldr	r1, [r1, #16]
 8008a82:	3301      	adds	r3, #1
 8008a84:	eba5 0901 	sub.w	r9, r5, r1
 8008a88:	6965      	ldr	r5, [r4, #20]
 8008a8a:	444b      	add	r3, r9
 8008a8c:	eb05 0545 	add.w	r5, r5, r5, lsl #1
 8008a90:	eb05 75d5 	add.w	r5, r5, r5, lsr #31
 8008a94:	106d      	asrs	r5, r5, #1
 8008a96:	429d      	cmp	r5, r3
 8008a98:	bf38      	it	cc
 8008a9a:	461d      	movcc	r5, r3
 8008a9c:	0553      	lsls	r3, r2, #21
 8008a9e:	d531      	bpl.n	8008b04 <__ssputs_r+0xa0>
 8008aa0:	4629      	mov	r1, r5
 8008aa2:	f7ff ff85 	bl	80089b0 <_malloc_r>
 8008aa6:	4606      	mov	r6, r0
 8008aa8:	b950      	cbnz	r0, 8008ac0 <__ssputs_r+0x5c>
 8008aaa:	230c      	movs	r3, #12
 8008aac:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8008ab0:	f8ca 3000 	str.w	r3, [sl]
 8008ab4:	89a3      	ldrh	r3, [r4, #12]
 8008ab6:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8008aba:	81a3      	strh	r3, [r4, #12]
 8008abc:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8008ac0:	464a      	mov	r2, r9
 8008ac2:	6921      	ldr	r1, [r4, #16]
 8008ac4:	f7fe f850 	bl	8006b68 <memcpy>
 8008ac8:	89a3      	ldrh	r3, [r4, #12]
 8008aca:	f423 6390 	bic.w	r3, r3, #1152	; 0x480
 8008ace:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8008ad2:	81a3      	strh	r3, [r4, #12]
 8008ad4:	6126      	str	r6, [r4, #16]
 8008ad6:	444e      	add	r6, r9
 8008ad8:	6026      	str	r6, [r4, #0]
 8008ada:	463e      	mov	r6, r7
 8008adc:	6165      	str	r5, [r4, #20]
 8008ade:	eba5 0509 	sub.w	r5, r5, r9
 8008ae2:	60a5      	str	r5, [r4, #8]
 8008ae4:	42be      	cmp	r6, r7
 8008ae6:	d900      	bls.n	8008aea <__ssputs_r+0x86>
 8008ae8:	463e      	mov	r6, r7
 8008aea:	4632      	mov	r2, r6
 8008aec:	4641      	mov	r1, r8
 8008aee:	6820      	ldr	r0, [r4, #0]
 8008af0:	f7fe f848 	bl	8006b84 <memmove>
 8008af4:	68a3      	ldr	r3, [r4, #8]
 8008af6:	6822      	ldr	r2, [r4, #0]
 8008af8:	1b9b      	subs	r3, r3, r6
 8008afa:	4432      	add	r2, r6
 8008afc:	2000      	movs	r0, #0
 8008afe:	60a3      	str	r3, [r4, #8]
 8008b00:	6022      	str	r2, [r4, #0]
 8008b02:	e7db      	b.n	8008abc <__ssputs_r+0x58>
 8008b04:	462a      	mov	r2, r5
 8008b06:	f000 f967 	bl	8008dd8 <_realloc_r>
 8008b0a:	4606      	mov	r6, r0
 8008b0c:	2800      	cmp	r0, #0
 8008b0e:	d1e1      	bne.n	8008ad4 <__ssputs_r+0x70>
 8008b10:	4650      	mov	r0, sl
 8008b12:	6921      	ldr	r1, [r4, #16]
 8008b14:	f7ff ff00 	bl	8008918 <_free_r>
 8008b18:	e7c7      	b.n	8008aaa <__ssputs_r+0x46>
	...

08008b1c <_svfiprintf_r>:
 8008b1c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008b20:	4698      	mov	r8, r3
 8008b22:	898b      	ldrh	r3, [r1, #12]
 8008b24:	4607      	mov	r7, r0
 8008b26:	061b      	lsls	r3, r3, #24
 8008b28:	460d      	mov	r5, r1
 8008b2a:	4614      	mov	r4, r2
 8008b2c:	b09d      	sub	sp, #116	; 0x74
 8008b2e:	d50e      	bpl.n	8008b4e <_svfiprintf_r+0x32>
 8008b30:	690b      	ldr	r3, [r1, #16]
 8008b32:	b963      	cbnz	r3, 8008b4e <_svfiprintf_r+0x32>
 8008b34:	2140      	movs	r1, #64	; 0x40
 8008b36:	f7ff ff3b 	bl	80089b0 <_malloc_r>
 8008b3a:	6028      	str	r0, [r5, #0]
 8008b3c:	6128      	str	r0, [r5, #16]
 8008b3e:	b920      	cbnz	r0, 8008b4a <_svfiprintf_r+0x2e>
 8008b40:	230c      	movs	r3, #12
 8008b42:	603b      	str	r3, [r7, #0]
 8008b44:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8008b48:	e0d1      	b.n	8008cee <_svfiprintf_r+0x1d2>
 8008b4a:	2340      	movs	r3, #64	; 0x40
 8008b4c:	616b      	str	r3, [r5, #20]
 8008b4e:	2300      	movs	r3, #0
 8008b50:	9309      	str	r3, [sp, #36]	; 0x24
 8008b52:	2320      	movs	r3, #32
 8008b54:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
 8008b58:	2330      	movs	r3, #48	; 0x30
 8008b5a:	f04f 0901 	mov.w	r9, #1
 8008b5e:	f8cd 800c 	str.w	r8, [sp, #12]
 8008b62:	f8df 81a4 	ldr.w	r8, [pc, #420]	; 8008d08 <_svfiprintf_r+0x1ec>
 8008b66:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
 8008b6a:	4623      	mov	r3, r4
 8008b6c:	469a      	mov	sl, r3
 8008b6e:	f813 2b01 	ldrb.w	r2, [r3], #1
 8008b72:	b10a      	cbz	r2, 8008b78 <_svfiprintf_r+0x5c>
 8008b74:	2a25      	cmp	r2, #37	; 0x25
 8008b76:	d1f9      	bne.n	8008b6c <_svfiprintf_r+0x50>
 8008b78:	ebba 0b04 	subs.w	fp, sl, r4
 8008b7c:	d00b      	beq.n	8008b96 <_svfiprintf_r+0x7a>
 8008b7e:	465b      	mov	r3, fp
 8008b80:	4622      	mov	r2, r4
 8008b82:	4629      	mov	r1, r5
 8008b84:	4638      	mov	r0, r7
 8008b86:	f7ff ff6d 	bl	8008a64 <__ssputs_r>
 8008b8a:	3001      	adds	r0, #1
 8008b8c:	f000 80aa 	beq.w	8008ce4 <_svfiprintf_r+0x1c8>
 8008b90:	9a09      	ldr	r2, [sp, #36]	; 0x24
 8008b92:	445a      	add	r2, fp
 8008b94:	9209      	str	r2, [sp, #36]	; 0x24
 8008b96:	f89a 3000 	ldrb.w	r3, [sl]
 8008b9a:	2b00      	cmp	r3, #0
 8008b9c:	f000 80a2 	beq.w	8008ce4 <_svfiprintf_r+0x1c8>
 8008ba0:	2300      	movs	r3, #0
 8008ba2:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8008ba6:	e9cd 2305 	strd	r2, r3, [sp, #20]
 8008baa:	f10a 0a01 	add.w	sl, sl, #1
 8008bae:	9304      	str	r3, [sp, #16]
 8008bb0:	9307      	str	r3, [sp, #28]
 8008bb2:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
 8008bb6:	931a      	str	r3, [sp, #104]	; 0x68
 8008bb8:	4654      	mov	r4, sl
 8008bba:	2205      	movs	r2, #5
 8008bbc:	f814 1b01 	ldrb.w	r1, [r4], #1
 8008bc0:	4851      	ldr	r0, [pc, #324]	; (8008d08 <_svfiprintf_r+0x1ec>)
 8008bc2:	f7ff fb0b 	bl	80081dc <memchr>
 8008bc6:	9a04      	ldr	r2, [sp, #16]
 8008bc8:	b9d8      	cbnz	r0, 8008c02 <_svfiprintf_r+0xe6>
 8008bca:	06d0      	lsls	r0, r2, #27
 8008bcc:	bf44      	itt	mi
 8008bce:	2320      	movmi	r3, #32
 8008bd0:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
 8008bd4:	0711      	lsls	r1, r2, #28
 8008bd6:	bf44      	itt	mi
 8008bd8:	232b      	movmi	r3, #43	; 0x2b
 8008bda:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
 8008bde:	f89a 3000 	ldrb.w	r3, [sl]
 8008be2:	2b2a      	cmp	r3, #42	; 0x2a
 8008be4:	d015      	beq.n	8008c12 <_svfiprintf_r+0xf6>
 8008be6:	4654      	mov	r4, sl
 8008be8:	2000      	movs	r0, #0
 8008bea:	f04f 0c0a 	mov.w	ip, #10
 8008bee:	9a07      	ldr	r2, [sp, #28]
 8008bf0:	4621      	mov	r1, r4
 8008bf2:	f811 3b01 	ldrb.w	r3, [r1], #1
 8008bf6:	3b30      	subs	r3, #48	; 0x30
 8008bf8:	2b09      	cmp	r3, #9
 8008bfa:	d94e      	bls.n	8008c9a <_svfiprintf_r+0x17e>
 8008bfc:	b1b0      	cbz	r0, 8008c2c <_svfiprintf_r+0x110>
 8008bfe:	9207      	str	r2, [sp, #28]
 8008c00:	e014      	b.n	8008c2c <_svfiprintf_r+0x110>
 8008c02:	eba0 0308 	sub.w	r3, r0, r8
 8008c06:	fa09 f303 	lsl.w	r3, r9, r3
 8008c0a:	4313      	orrs	r3, r2
 8008c0c:	46a2      	mov	sl, r4
 8008c0e:	9304      	str	r3, [sp, #16]
 8008c10:	e7d2      	b.n	8008bb8 <_svfiprintf_r+0x9c>
 8008c12:	9b03      	ldr	r3, [sp, #12]
 8008c14:	1d19      	adds	r1, r3, #4
 8008c16:	681b      	ldr	r3, [r3, #0]
 8008c18:	9103      	str	r1, [sp, #12]
 8008c1a:	2b00      	cmp	r3, #0
 8008c1c:	bfbb      	ittet	lt
 8008c1e:	425b      	neglt	r3, r3
 8008c20:	f042 0202 	orrlt.w	r2, r2, #2
 8008c24:	9307      	strge	r3, [sp, #28]
 8008c26:	9307      	strlt	r3, [sp, #28]
 8008c28:	bfb8      	it	lt
 8008c2a:	9204      	strlt	r2, [sp, #16]
 8008c2c:	7823      	ldrb	r3, [r4, #0]
 8008c2e:	2b2e      	cmp	r3, #46	; 0x2e
 8008c30:	d10c      	bne.n	8008c4c <_svfiprintf_r+0x130>
 8008c32:	7863      	ldrb	r3, [r4, #1]
 8008c34:	2b2a      	cmp	r3, #42	; 0x2a
 8008c36:	d135      	bne.n	8008ca4 <_svfiprintf_r+0x188>
 8008c38:	9b03      	ldr	r3, [sp, #12]
 8008c3a:	3402      	adds	r4, #2
 8008c3c:	1d1a      	adds	r2, r3, #4
 8008c3e:	681b      	ldr	r3, [r3, #0]
 8008c40:	9203      	str	r2, [sp, #12]
 8008c42:	2b00      	cmp	r3, #0
 8008c44:	bfb8      	it	lt
 8008c46:	f04f 33ff 	movlt.w	r3, #4294967295	; 0xffffffff
 8008c4a:	9305      	str	r3, [sp, #20]
 8008c4c:	f8df a0c8 	ldr.w	sl, [pc, #200]	; 8008d18 <_svfiprintf_r+0x1fc>
 8008c50:	2203      	movs	r2, #3
 8008c52:	4650      	mov	r0, sl
 8008c54:	7821      	ldrb	r1, [r4, #0]
 8008c56:	f7ff fac1 	bl	80081dc <memchr>
 8008c5a:	b140      	cbz	r0, 8008c6e <_svfiprintf_r+0x152>
 8008c5c:	2340      	movs	r3, #64	; 0x40
 8008c5e:	eba0 000a 	sub.w	r0, r0, sl
 8008c62:	fa03 f000 	lsl.w	r0, r3, r0
 8008c66:	9b04      	ldr	r3, [sp, #16]
 8008c68:	3401      	adds	r4, #1
 8008c6a:	4303      	orrs	r3, r0
 8008c6c:	9304      	str	r3, [sp, #16]
 8008c6e:	f814 1b01 	ldrb.w	r1, [r4], #1
 8008c72:	2206      	movs	r2, #6
 8008c74:	4825      	ldr	r0, [pc, #148]	; (8008d0c <_svfiprintf_r+0x1f0>)
 8008c76:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
 8008c7a:	f7ff faaf 	bl	80081dc <memchr>
 8008c7e:	2800      	cmp	r0, #0
 8008c80:	d038      	beq.n	8008cf4 <_svfiprintf_r+0x1d8>
 8008c82:	4b23      	ldr	r3, [pc, #140]	; (8008d10 <_svfiprintf_r+0x1f4>)
 8008c84:	bb1b      	cbnz	r3, 8008cce <_svfiprintf_r+0x1b2>
 8008c86:	9b03      	ldr	r3, [sp, #12]
 8008c88:	3307      	adds	r3, #7
 8008c8a:	f023 0307 	bic.w	r3, r3, #7
 8008c8e:	3308      	adds	r3, #8
 8008c90:	9303      	str	r3, [sp, #12]
 8008c92:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8008c94:	4433      	add	r3, r6
 8008c96:	9309      	str	r3, [sp, #36]	; 0x24
 8008c98:	e767      	b.n	8008b6a <_svfiprintf_r+0x4e>
 8008c9a:	460c      	mov	r4, r1
 8008c9c:	2001      	movs	r0, #1
 8008c9e:	fb0c 3202 	mla	r2, ip, r2, r3
 8008ca2:	e7a5      	b.n	8008bf0 <_svfiprintf_r+0xd4>
 8008ca4:	2300      	movs	r3, #0
 8008ca6:	f04f 0c0a 	mov.w	ip, #10
 8008caa:	4619      	mov	r1, r3
 8008cac:	3401      	adds	r4, #1
 8008cae:	9305      	str	r3, [sp, #20]
 8008cb0:	4620      	mov	r0, r4
 8008cb2:	f810 2b01 	ldrb.w	r2, [r0], #1
 8008cb6:	3a30      	subs	r2, #48	; 0x30
 8008cb8:	2a09      	cmp	r2, #9
 8008cba:	d903      	bls.n	8008cc4 <_svfiprintf_r+0x1a8>
 8008cbc:	2b00      	cmp	r3, #0
 8008cbe:	d0c5      	beq.n	8008c4c <_svfiprintf_r+0x130>
 8008cc0:	9105      	str	r1, [sp, #20]
 8008cc2:	e7c3      	b.n	8008c4c <_svfiprintf_r+0x130>
 8008cc4:	4604      	mov	r4, r0
 8008cc6:	2301      	movs	r3, #1
 8008cc8:	fb0c 2101 	mla	r1, ip, r1, r2
 8008ccc:	e7f0      	b.n	8008cb0 <_svfiprintf_r+0x194>
 8008cce:	ab03      	add	r3, sp, #12
 8008cd0:	9300      	str	r3, [sp, #0]
 8008cd2:	462a      	mov	r2, r5
 8008cd4:	4638      	mov	r0, r7
 8008cd6:	4b0f      	ldr	r3, [pc, #60]	; (8008d14 <_svfiprintf_r+0x1f8>)
 8008cd8:	a904      	add	r1, sp, #16
 8008cda:	f7fe f813 	bl	8006d04 <_printf_float>
 8008cde:	1c42      	adds	r2, r0, #1
 8008ce0:	4606      	mov	r6, r0
 8008ce2:	d1d6      	bne.n	8008c92 <_svfiprintf_r+0x176>
 8008ce4:	89ab      	ldrh	r3, [r5, #12]
 8008ce6:	065b      	lsls	r3, r3, #25
 8008ce8:	f53f af2c 	bmi.w	8008b44 <_svfiprintf_r+0x28>
 8008cec:	9809      	ldr	r0, [sp, #36]	; 0x24
 8008cee:	b01d      	add	sp, #116	; 0x74
 8008cf0:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8008cf4:	ab03      	add	r3, sp, #12
 8008cf6:	9300      	str	r3, [sp, #0]
 8008cf8:	462a      	mov	r2, r5
 8008cfa:	4638      	mov	r0, r7
 8008cfc:	4b05      	ldr	r3, [pc, #20]	; (8008d14 <_svfiprintf_r+0x1f8>)
 8008cfe:	a904      	add	r1, sp, #16
 8008d00:	f7fe fa9c 	bl	800723c <_printf_i>
 8008d04:	e7eb      	b.n	8008cde <_svfiprintf_r+0x1c2>
 8008d06:	bf00      	nop
 8008d08:	0800a87c 	.word	0x0800a87c
 8008d0c:	0800a886 	.word	0x0800a886
 8008d10:	08006d05 	.word	0x08006d05
 8008d14:	08008a65 	.word	0x08008a65
 8008d18:	0800a882 	.word	0x0800a882

08008d1c <_sbrk_r>:
 8008d1c:	b538      	push	{r3, r4, r5, lr}
 8008d1e:	2300      	movs	r3, #0
 8008d20:	4d05      	ldr	r5, [pc, #20]	; (8008d38 <_sbrk_r+0x1c>)
 8008d22:	4604      	mov	r4, r0
 8008d24:	4608      	mov	r0, r1
 8008d26:	602b      	str	r3, [r5, #0]
 8008d28:	f7f9 fac8 	bl	80022bc <_sbrk>
 8008d2c:	1c43      	adds	r3, r0, #1
 8008d2e:	d102      	bne.n	8008d36 <_sbrk_r+0x1a>
 8008d30:	682b      	ldr	r3, [r5, #0]
 8008d32:	b103      	cbz	r3, 8008d36 <_sbrk_r+0x1a>
 8008d34:	6023      	str	r3, [r4, #0]
 8008d36:	bd38      	pop	{r3, r4, r5, pc}
 8008d38:	200006f4 	.word	0x200006f4

08008d3c <__assert_func>:
 8008d3c:	b51f      	push	{r0, r1, r2, r3, r4, lr}
 8008d3e:	4614      	mov	r4, r2
 8008d40:	461a      	mov	r2, r3
 8008d42:	4b09      	ldr	r3, [pc, #36]	; (8008d68 <__assert_func+0x2c>)
 8008d44:	4605      	mov	r5, r0
 8008d46:	681b      	ldr	r3, [r3, #0]
 8008d48:	68d8      	ldr	r0, [r3, #12]
 8008d4a:	b14c      	cbz	r4, 8008d60 <__assert_func+0x24>
 8008d4c:	4b07      	ldr	r3, [pc, #28]	; (8008d6c <__assert_func+0x30>)
 8008d4e:	e9cd 3401 	strd	r3, r4, [sp, #4]
 8008d52:	9100      	str	r1, [sp, #0]
 8008d54:	462b      	mov	r3, r5
 8008d56:	4906      	ldr	r1, [pc, #24]	; (8008d70 <__assert_func+0x34>)
 8008d58:	f000 f80e 	bl	8008d78 <fiprintf>
 8008d5c:	f000 fa88 	bl	8009270 <abort>
 8008d60:	4b04      	ldr	r3, [pc, #16]	; (8008d74 <__assert_func+0x38>)
 8008d62:	461c      	mov	r4, r3
 8008d64:	e7f3      	b.n	8008d4e <__assert_func+0x12>
 8008d66:	bf00      	nop
 8008d68:	20000014 	.word	0x20000014
 8008d6c:	0800a88d 	.word	0x0800a88d
 8008d70:	0800a89a 	.word	0x0800a89a
 8008d74:	0800a8c8 	.word	0x0800a8c8

08008d78 <fiprintf>:
 8008d78:	b40e      	push	{r1, r2, r3}
 8008d7a:	b503      	push	{r0, r1, lr}
 8008d7c:	4601      	mov	r1, r0
 8008d7e:	ab03      	add	r3, sp, #12
 8008d80:	4805      	ldr	r0, [pc, #20]	; (8008d98 <fiprintf+0x20>)
 8008d82:	f853 2b04 	ldr.w	r2, [r3], #4
 8008d86:	6800      	ldr	r0, [r0, #0]
 8008d88:	9301      	str	r3, [sp, #4]
 8008d8a:	f000 f873 	bl	8008e74 <_vfiprintf_r>
 8008d8e:	b002      	add	sp, #8
 8008d90:	f85d eb04 	ldr.w	lr, [sp], #4
 8008d94:	b003      	add	sp, #12
 8008d96:	4770      	bx	lr
 8008d98:	20000014 	.word	0x20000014

08008d9c <__ascii_mbtowc>:
 8008d9c:	b082      	sub	sp, #8
 8008d9e:	b901      	cbnz	r1, 8008da2 <__ascii_mbtowc+0x6>
 8008da0:	a901      	add	r1, sp, #4
 8008da2:	b142      	cbz	r2, 8008db6 <__ascii_mbtowc+0x1a>
 8008da4:	b14b      	cbz	r3, 8008dba <__ascii_mbtowc+0x1e>
 8008da6:	7813      	ldrb	r3, [r2, #0]
 8008da8:	600b      	str	r3, [r1, #0]
 8008daa:	7812      	ldrb	r2, [r2, #0]
 8008dac:	1e10      	subs	r0, r2, #0
 8008dae:	bf18      	it	ne
 8008db0:	2001      	movne	r0, #1
 8008db2:	b002      	add	sp, #8
 8008db4:	4770      	bx	lr
 8008db6:	4610      	mov	r0, r2
 8008db8:	e7fb      	b.n	8008db2 <__ascii_mbtowc+0x16>
 8008dba:	f06f 0001 	mvn.w	r0, #1
 8008dbe:	e7f8      	b.n	8008db2 <__ascii_mbtowc+0x16>

08008dc0 <__malloc_lock>:
 8008dc0:	4801      	ldr	r0, [pc, #4]	; (8008dc8 <__malloc_lock+0x8>)
 8008dc2:	f000 bc15 	b.w	80095f0 <__retarget_lock_acquire_recursive>
 8008dc6:	bf00      	nop
 8008dc8:	200006fc 	.word	0x200006fc

08008dcc <__malloc_unlock>:
 8008dcc:	4801      	ldr	r0, [pc, #4]	; (8008dd4 <__malloc_unlock+0x8>)
 8008dce:	f000 bc10 	b.w	80095f2 <__retarget_lock_release_recursive>
 8008dd2:	bf00      	nop
 8008dd4:	200006fc 	.word	0x200006fc

08008dd8 <_realloc_r>:
 8008dd8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8008dda:	4607      	mov	r7, r0
 8008ddc:	4614      	mov	r4, r2
 8008dde:	460e      	mov	r6, r1
 8008de0:	b921      	cbnz	r1, 8008dec <_realloc_r+0x14>
 8008de2:	4611      	mov	r1, r2
 8008de4:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
 8008de8:	f7ff bde2 	b.w	80089b0 <_malloc_r>
 8008dec:	b922      	cbnz	r2, 8008df8 <_realloc_r+0x20>
 8008dee:	f7ff fd93 	bl	8008918 <_free_r>
 8008df2:	4625      	mov	r5, r4
 8008df4:	4628      	mov	r0, r5
 8008df6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8008df8:	f000 fc60 	bl	80096bc <_malloc_usable_size_r>
 8008dfc:	42a0      	cmp	r0, r4
 8008dfe:	d20f      	bcs.n	8008e20 <_realloc_r+0x48>
 8008e00:	4621      	mov	r1, r4
 8008e02:	4638      	mov	r0, r7
 8008e04:	f7ff fdd4 	bl	80089b0 <_malloc_r>
 8008e08:	4605      	mov	r5, r0
 8008e0a:	2800      	cmp	r0, #0
 8008e0c:	d0f2      	beq.n	8008df4 <_realloc_r+0x1c>
 8008e0e:	4631      	mov	r1, r6
 8008e10:	4622      	mov	r2, r4
 8008e12:	f7fd fea9 	bl	8006b68 <memcpy>
 8008e16:	4631      	mov	r1, r6
 8008e18:	4638      	mov	r0, r7
 8008e1a:	f7ff fd7d 	bl	8008918 <_free_r>
 8008e1e:	e7e9      	b.n	8008df4 <_realloc_r+0x1c>
 8008e20:	4635      	mov	r5, r6
 8008e22:	e7e7      	b.n	8008df4 <_realloc_r+0x1c>

08008e24 <__sfputc_r>:
 8008e24:	6893      	ldr	r3, [r2, #8]
 8008e26:	b410      	push	{r4}
 8008e28:	3b01      	subs	r3, #1
 8008e2a:	2b00      	cmp	r3, #0
 8008e2c:	6093      	str	r3, [r2, #8]
 8008e2e:	da07      	bge.n	8008e40 <__sfputc_r+0x1c>
 8008e30:	6994      	ldr	r4, [r2, #24]
 8008e32:	42a3      	cmp	r3, r4
 8008e34:	db01      	blt.n	8008e3a <__sfputc_r+0x16>
 8008e36:	290a      	cmp	r1, #10
 8008e38:	d102      	bne.n	8008e40 <__sfputc_r+0x1c>
 8008e3a:	bc10      	pop	{r4}
 8008e3c:	f000 b94a 	b.w	80090d4 <__swbuf_r>
 8008e40:	6813      	ldr	r3, [r2, #0]
 8008e42:	1c58      	adds	r0, r3, #1
 8008e44:	6010      	str	r0, [r2, #0]
 8008e46:	7019      	strb	r1, [r3, #0]
 8008e48:	4608      	mov	r0, r1
 8008e4a:	bc10      	pop	{r4}
 8008e4c:	4770      	bx	lr

08008e4e <__sfputs_r>:
 8008e4e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8008e50:	4606      	mov	r6, r0
 8008e52:	460f      	mov	r7, r1
 8008e54:	4614      	mov	r4, r2
 8008e56:	18d5      	adds	r5, r2, r3
 8008e58:	42ac      	cmp	r4, r5
 8008e5a:	d101      	bne.n	8008e60 <__sfputs_r+0x12>
 8008e5c:	2000      	movs	r0, #0
 8008e5e:	e007      	b.n	8008e70 <__sfputs_r+0x22>
 8008e60:	463a      	mov	r2, r7
 8008e62:	4630      	mov	r0, r6
 8008e64:	f814 1b01 	ldrb.w	r1, [r4], #1
 8008e68:	f7ff ffdc 	bl	8008e24 <__sfputc_r>
 8008e6c:	1c43      	adds	r3, r0, #1
 8008e6e:	d1f3      	bne.n	8008e58 <__sfputs_r+0xa>
 8008e70:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	...

08008e74 <_vfiprintf_r>:
 8008e74:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008e78:	460d      	mov	r5, r1
 8008e7a:	4614      	mov	r4, r2
 8008e7c:	4698      	mov	r8, r3
 8008e7e:	4606      	mov	r6, r0
 8008e80:	b09d      	sub	sp, #116	; 0x74
 8008e82:	b118      	cbz	r0, 8008e8c <_vfiprintf_r+0x18>
 8008e84:	6983      	ldr	r3, [r0, #24]
 8008e86:	b90b      	cbnz	r3, 8008e8c <_vfiprintf_r+0x18>
 8008e88:	f000 fb14 	bl	80094b4 <__sinit>
 8008e8c:	4b89      	ldr	r3, [pc, #548]	; (80090b4 <_vfiprintf_r+0x240>)
 8008e8e:	429d      	cmp	r5, r3
 8008e90:	d11b      	bne.n	8008eca <_vfiprintf_r+0x56>
 8008e92:	6875      	ldr	r5, [r6, #4]
 8008e94:	6e6b      	ldr	r3, [r5, #100]	; 0x64
 8008e96:	07d9      	lsls	r1, r3, #31
 8008e98:	d405      	bmi.n	8008ea6 <_vfiprintf_r+0x32>
 8008e9a:	89ab      	ldrh	r3, [r5, #12]
 8008e9c:	059a      	lsls	r2, r3, #22
 8008e9e:	d402      	bmi.n	8008ea6 <_vfiprintf_r+0x32>
 8008ea0:	6da8      	ldr	r0, [r5, #88]	; 0x58
 8008ea2:	f000 fba5 	bl	80095f0 <__retarget_lock_acquire_recursive>
 8008ea6:	89ab      	ldrh	r3, [r5, #12]
 8008ea8:	071b      	lsls	r3, r3, #28
 8008eaa:	d501      	bpl.n	8008eb0 <_vfiprintf_r+0x3c>
 8008eac:	692b      	ldr	r3, [r5, #16]
 8008eae:	b9eb      	cbnz	r3, 8008eec <_vfiprintf_r+0x78>
 8008eb0:	4629      	mov	r1, r5
 8008eb2:	4630      	mov	r0, r6
 8008eb4:	f000 f96e 	bl	8009194 <__swsetup_r>
 8008eb8:	b1c0      	cbz	r0, 8008eec <_vfiprintf_r+0x78>
 8008eba:	6e6b      	ldr	r3, [r5, #100]	; 0x64
 8008ebc:	07dc      	lsls	r4, r3, #31
 8008ebe:	d50e      	bpl.n	8008ede <_vfiprintf_r+0x6a>
 8008ec0:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8008ec4:	b01d      	add	sp, #116	; 0x74
 8008ec6:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8008eca:	4b7b      	ldr	r3, [pc, #492]	; (80090b8 <_vfiprintf_r+0x244>)
 8008ecc:	429d      	cmp	r5, r3
 8008ece:	d101      	bne.n	8008ed4 <_vfiprintf_r+0x60>
 8008ed0:	68b5      	ldr	r5, [r6, #8]
 8008ed2:	e7df      	b.n	8008e94 <_vfiprintf_r+0x20>
 8008ed4:	4b79      	ldr	r3, [pc, #484]	; (80090bc <_vfiprintf_r+0x248>)
 8008ed6:	429d      	cmp	r5, r3
 8008ed8:	bf08      	it	eq
 8008eda:	68f5      	ldreq	r5, [r6, #12]
 8008edc:	e7da      	b.n	8008e94 <_vfiprintf_r+0x20>
 8008ede:	89ab      	ldrh	r3, [r5, #12]
 8008ee0:	0598      	lsls	r0, r3, #22
 8008ee2:	d4ed      	bmi.n	8008ec0 <_vfiprintf_r+0x4c>
 8008ee4:	6da8      	ldr	r0, [r5, #88]	; 0x58
 8008ee6:	f000 fb84 	bl	80095f2 <__retarget_lock_release_recursive>
 8008eea:	e7e9      	b.n	8008ec0 <_vfiprintf_r+0x4c>
 8008eec:	2300      	movs	r3, #0
 8008eee:	9309      	str	r3, [sp, #36]	; 0x24
 8008ef0:	2320      	movs	r3, #32
 8008ef2:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
 8008ef6:	2330      	movs	r3, #48	; 0x30
 8008ef8:	f04f 0901 	mov.w	r9, #1
 8008efc:	f8cd 800c 	str.w	r8, [sp, #12]
 8008f00:	f8df 81bc 	ldr.w	r8, [pc, #444]	; 80090c0 <_vfiprintf_r+0x24c>
 8008f04:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
 8008f08:	4623      	mov	r3, r4
 8008f0a:	469a      	mov	sl, r3
 8008f0c:	f813 2b01 	ldrb.w	r2, [r3], #1
 8008f10:	b10a      	cbz	r2, 8008f16 <_vfiprintf_r+0xa2>
 8008f12:	2a25      	cmp	r2, #37	; 0x25
 8008f14:	d1f9      	bne.n	8008f0a <_vfiprintf_r+0x96>
 8008f16:	ebba 0b04 	subs.w	fp, sl, r4
 8008f1a:	d00b      	beq.n	8008f34 <_vfiprintf_r+0xc0>
 8008f1c:	465b      	mov	r3, fp
 8008f1e:	4622      	mov	r2, r4
 8008f20:	4629      	mov	r1, r5
 8008f22:	4630      	mov	r0, r6
 8008f24:	f7ff ff93 	bl	8008e4e <__sfputs_r>
 8008f28:	3001      	adds	r0, #1
 8008f2a:	f000 80aa 	beq.w	8009082 <_vfiprintf_r+0x20e>
 8008f2e:	9a09      	ldr	r2, [sp, #36]	; 0x24
 8008f30:	445a      	add	r2, fp
 8008f32:	9209      	str	r2, [sp, #36]	; 0x24
 8008f34:	f89a 3000 	ldrb.w	r3, [sl]
 8008f38:	2b00      	cmp	r3, #0
 8008f3a:	f000 80a2 	beq.w	8009082 <_vfiprintf_r+0x20e>
 8008f3e:	2300      	movs	r3, #0
 8008f40:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8008f44:	e9cd 2305 	strd	r2, r3, [sp, #20]
 8008f48:	f10a 0a01 	add.w	sl, sl, #1
 8008f4c:	9304      	str	r3, [sp, #16]
 8008f4e:	9307      	str	r3, [sp, #28]
 8008f50:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
 8008f54:	931a      	str	r3, [sp, #104]	; 0x68
 8008f56:	4654      	mov	r4, sl
 8008f58:	2205      	movs	r2, #5
 8008f5a:	f814 1b01 	ldrb.w	r1, [r4], #1
 8008f5e:	4858      	ldr	r0, [pc, #352]	; (80090c0 <_vfiprintf_r+0x24c>)
 8008f60:	f7ff f93c 	bl	80081dc <memchr>
 8008f64:	9a04      	ldr	r2, [sp, #16]
 8008f66:	b9d8      	cbnz	r0, 8008fa0 <_vfiprintf_r+0x12c>
 8008f68:	06d1      	lsls	r1, r2, #27
 8008f6a:	bf44      	itt	mi
 8008f6c:	2320      	movmi	r3, #32
 8008f6e:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
 8008f72:	0713      	lsls	r3, r2, #28
 8008f74:	bf44      	itt	mi
 8008f76:	232b      	movmi	r3, #43	; 0x2b
 8008f78:	f88d 3053 	strbmi.w	r3, [sp, #83]	; 0x53
 8008f7c:	f89a 3000 	ldrb.w	r3, [sl]
 8008f80:	2b2a      	cmp	r3, #42	; 0x2a
 8008f82:	d015      	beq.n	8008fb0 <_vfiprintf_r+0x13c>
 8008f84:	4654      	mov	r4, sl
 8008f86:	2000      	movs	r0, #0
 8008f88:	f04f 0c0a 	mov.w	ip, #10
 8008f8c:	9a07      	ldr	r2, [sp, #28]
 8008f8e:	4621      	mov	r1, r4
 8008f90:	f811 3b01 	ldrb.w	r3, [r1], #1
 8008f94:	3b30      	subs	r3, #48	; 0x30
 8008f96:	2b09      	cmp	r3, #9
 8008f98:	d94e      	bls.n	8009038 <_vfiprintf_r+0x1c4>
 8008f9a:	b1b0      	cbz	r0, 8008fca <_vfiprintf_r+0x156>
 8008f9c:	9207      	str	r2, [sp, #28]
 8008f9e:	e014      	b.n	8008fca <_vfiprintf_r+0x156>
 8008fa0:	eba0 0308 	sub.w	r3, r0, r8
 8008fa4:	fa09 f303 	lsl.w	r3, r9, r3
 8008fa8:	4313      	orrs	r3, r2
 8008faa:	46a2      	mov	sl, r4
 8008fac:	9304      	str	r3, [sp, #16]
 8008fae:	e7d2      	b.n	8008f56 <_vfiprintf_r+0xe2>
 8008fb0:	9b03      	ldr	r3, [sp, #12]
 8008fb2:	1d19      	adds	r1, r3, #4
 8008fb4:	681b      	ldr	r3, [r3, #0]
 8008fb6:	9103      	str	r1, [sp, #12]
 8008fb8:	2b00      	cmp	r3, #0
 8008fba:	bfbb      	ittet	lt
 8008fbc:	425b      	neglt	r3, r3
 8008fbe:	f042 0202 	orrlt.w	r2, r2, #2
 8008fc2:	9307      	strge	r3, [sp, #28]
 8008fc4:	9307      	strlt	r3, [sp, #28]
 8008fc6:	bfb8      	it	lt
 8008fc8:	9204      	strlt	r2, [sp, #16]
 8008fca:	7823      	ldrb	r3, [r4, #0]
 8008fcc:	2b2e      	cmp	r3, #46	; 0x2e
 8008fce:	d10c      	bne.n	8008fea <_vfiprintf_r+0x176>
 8008fd0:	7863      	ldrb	r3, [r4, #1]
 8008fd2:	2b2a      	cmp	r3, #42	; 0x2a
 8008fd4:	d135      	bne.n	8009042 <_vfiprintf_r+0x1ce>
 8008fd6:	9b03      	ldr	r3, [sp, #12]
 8008fd8:	3402      	adds	r4, #2
 8008fda:	1d1a      	adds	r2, r3, #4
 8008fdc:	681b      	ldr	r3, [r3, #0]
 8008fde:	9203      	str	r2, [sp, #12]
 8008fe0:	2b00      	cmp	r3, #0
 8008fe2:	bfb8      	it	lt
 8008fe4:	f04f 33ff 	movlt.w	r3, #4294967295	; 0xffffffff
 8008fe8:	9305      	str	r3, [sp, #20]
 8008fea:	f8df a0e4 	ldr.w	sl, [pc, #228]	; 80090d0 <_vfiprintf_r+0x25c>
 8008fee:	2203      	movs	r2, #3
 8008ff0:	4650      	mov	r0, sl
 8008ff2:	7821      	ldrb	r1, [r4, #0]
 8008ff4:	f7ff f8f2 	bl	80081dc <memchr>
 8008ff8:	b140      	cbz	r0, 800900c <_vfiprintf_r+0x198>
 8008ffa:	2340      	movs	r3, #64	; 0x40
 8008ffc:	eba0 000a 	sub.w	r0, r0, sl
 8009000:	fa03 f000 	lsl.w	r0, r3, r0
 8009004:	9b04      	ldr	r3, [sp, #16]
 8009006:	3401      	adds	r4, #1
 8009008:	4303      	orrs	r3, r0
 800900a:	9304      	str	r3, [sp, #16]
 800900c:	f814 1b01 	ldrb.w	r1, [r4], #1
 8009010:	2206      	movs	r2, #6
 8009012:	482c      	ldr	r0, [pc, #176]	; (80090c4 <_vfiprintf_r+0x250>)
 8009014:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
 8009018:	f7ff f8e0 	bl	80081dc <memchr>
 800901c:	2800      	cmp	r0, #0
 800901e:	d03f      	beq.n	80090a0 <_vfiprintf_r+0x22c>
 8009020:	4b29      	ldr	r3, [pc, #164]	; (80090c8 <_vfiprintf_r+0x254>)
 8009022:	bb1b      	cbnz	r3, 800906c <_vfiprintf_r+0x1f8>
 8009024:	9b03      	ldr	r3, [sp, #12]
 8009026:	3307      	adds	r3, #7
 8009028:	f023 0307 	bic.w	r3, r3, #7
 800902c:	3308      	adds	r3, #8
 800902e:	9303      	str	r3, [sp, #12]
 8009030:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8009032:	443b      	add	r3, r7
 8009034:	9309      	str	r3, [sp, #36]	; 0x24
 8009036:	e767      	b.n	8008f08 <_vfiprintf_r+0x94>
 8009038:	460c      	mov	r4, r1
 800903a:	2001      	movs	r0, #1
 800903c:	fb0c 3202 	mla	r2, ip, r2, r3
 8009040:	e7a5      	b.n	8008f8e <_vfiprintf_r+0x11a>
 8009042:	2300      	movs	r3, #0
 8009044:	f04f 0c0a 	mov.w	ip, #10
 8009048:	4619      	mov	r1, r3
 800904a:	3401      	adds	r4, #1
 800904c:	9305      	str	r3, [sp, #20]
 800904e:	4620      	mov	r0, r4
 8009050:	f810 2b01 	ldrb.w	r2, [r0], #1
 8009054:	3a30      	subs	r2, #48	; 0x30
 8009056:	2a09      	cmp	r2, #9
 8009058:	d903      	bls.n	8009062 <_vfiprintf_r+0x1ee>
 800905a:	2b00      	cmp	r3, #0
 800905c:	d0c5      	beq.n	8008fea <_vfiprintf_r+0x176>
 800905e:	9105      	str	r1, [sp, #20]
 8009060:	e7c3      	b.n	8008fea <_vfiprintf_r+0x176>
 8009062:	4604      	mov	r4, r0
 8009064:	2301      	movs	r3, #1
 8009066:	fb0c 2101 	mla	r1, ip, r1, r2
 800906a:	e7f0      	b.n	800904e <_vfiprintf_r+0x1da>
 800906c:	ab03      	add	r3, sp, #12
 800906e:	9300      	str	r3, [sp, #0]
 8009070:	462a      	mov	r2, r5
 8009072:	4630      	mov	r0, r6
 8009074:	4b15      	ldr	r3, [pc, #84]	; (80090cc <_vfiprintf_r+0x258>)
 8009076:	a904      	add	r1, sp, #16
 8009078:	f7fd fe44 	bl	8006d04 <_printf_float>
 800907c:	4607      	mov	r7, r0
 800907e:	1c78      	adds	r0, r7, #1
 8009080:	d1d6      	bne.n	8009030 <_vfiprintf_r+0x1bc>
 8009082:	6e6b      	ldr	r3, [r5, #100]	; 0x64
 8009084:	07d9      	lsls	r1, r3, #31
 8009086:	d405      	bmi.n	8009094 <_vfiprintf_r+0x220>
 8009088:	89ab      	ldrh	r3, [r5, #12]
 800908a:	059a      	lsls	r2, r3, #22
 800908c:	d402      	bmi.n	8009094 <_vfiprintf_r+0x220>
 800908e:	6da8      	ldr	r0, [r5, #88]	; 0x58
 8009090:	f000 faaf 	bl	80095f2 <__retarget_lock_release_recursive>
 8009094:	89ab      	ldrh	r3, [r5, #12]
 8009096:	065b      	lsls	r3, r3, #25
 8009098:	f53f af12 	bmi.w	8008ec0 <_vfiprintf_r+0x4c>
 800909c:	9809      	ldr	r0, [sp, #36]	; 0x24
 800909e:	e711      	b.n	8008ec4 <_vfiprintf_r+0x50>
 80090a0:	ab03      	add	r3, sp, #12
 80090a2:	9300      	str	r3, [sp, #0]
 80090a4:	462a      	mov	r2, r5
 80090a6:	4630      	mov	r0, r6
 80090a8:	4b08      	ldr	r3, [pc, #32]	; (80090cc <_vfiprintf_r+0x258>)
 80090aa:	a904      	add	r1, sp, #16
 80090ac:	f7fe f8c6 	bl	800723c <_printf_i>
 80090b0:	e7e4      	b.n	800907c <_vfiprintf_r+0x208>
 80090b2:	bf00      	nop
 80090b4:	0800a9f4 	.word	0x0800a9f4
 80090b8:	0800aa14 	.word	0x0800aa14
 80090bc:	0800a9d4 	.word	0x0800a9d4
 80090c0:	0800a87c 	.word	0x0800a87c
 80090c4:	0800a886 	.word	0x0800a886
 80090c8:	08006d05 	.word	0x08006d05
 80090cc:	08008e4f 	.word	0x08008e4f
 80090d0:	0800a882 	.word	0x0800a882

080090d4 <__swbuf_r>:
 80090d4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80090d6:	460e      	mov	r6, r1
 80090d8:	4614      	mov	r4, r2
 80090da:	4605      	mov	r5, r0
 80090dc:	b118      	cbz	r0, 80090e6 <__swbuf_r+0x12>
 80090de:	6983      	ldr	r3, [r0, #24]
 80090e0:	b90b      	cbnz	r3, 80090e6 <__swbuf_r+0x12>
 80090e2:	f000 f9e7 	bl	80094b4 <__sinit>
 80090e6:	4b21      	ldr	r3, [pc, #132]	; (800916c <__swbuf_r+0x98>)
 80090e8:	429c      	cmp	r4, r3
 80090ea:	d12b      	bne.n	8009144 <__swbuf_r+0x70>
 80090ec:	686c      	ldr	r4, [r5, #4]
 80090ee:	69a3      	ldr	r3, [r4, #24]
 80090f0:	60a3      	str	r3, [r4, #8]
 80090f2:	89a3      	ldrh	r3, [r4, #12]
 80090f4:	071a      	lsls	r2, r3, #28
 80090f6:	d52f      	bpl.n	8009158 <__swbuf_r+0x84>
 80090f8:	6923      	ldr	r3, [r4, #16]
 80090fa:	b36b      	cbz	r3, 8009158 <__swbuf_r+0x84>
 80090fc:	6923      	ldr	r3, [r4, #16]
 80090fe:	6820      	ldr	r0, [r4, #0]
 8009100:	b2f6      	uxtb	r6, r6
 8009102:	1ac0      	subs	r0, r0, r3
 8009104:	6963      	ldr	r3, [r4, #20]
 8009106:	4637      	mov	r7, r6
 8009108:	4283      	cmp	r3, r0
 800910a:	dc04      	bgt.n	8009116 <__swbuf_r+0x42>
 800910c:	4621      	mov	r1, r4
 800910e:	4628      	mov	r0, r5
 8009110:	f000 f93c 	bl	800938c <_fflush_r>
 8009114:	bb30      	cbnz	r0, 8009164 <__swbuf_r+0x90>
 8009116:	68a3      	ldr	r3, [r4, #8]
 8009118:	3001      	adds	r0, #1
 800911a:	3b01      	subs	r3, #1
 800911c:	60a3      	str	r3, [r4, #8]
 800911e:	6823      	ldr	r3, [r4, #0]
 8009120:	1c5a      	adds	r2, r3, #1
 8009122:	6022      	str	r2, [r4, #0]
 8009124:	701e      	strb	r6, [r3, #0]
 8009126:	6963      	ldr	r3, [r4, #20]
 8009128:	4283      	cmp	r3, r0
 800912a:	d004      	beq.n	8009136 <__swbuf_r+0x62>
 800912c:	89a3      	ldrh	r3, [r4, #12]
 800912e:	07db      	lsls	r3, r3, #31
 8009130:	d506      	bpl.n	8009140 <__swbuf_r+0x6c>
 8009132:	2e0a      	cmp	r6, #10
 8009134:	d104      	bne.n	8009140 <__swbuf_r+0x6c>
 8009136:	4621      	mov	r1, r4
 8009138:	4628      	mov	r0, r5
 800913a:	f000 f927 	bl	800938c <_fflush_r>
 800913e:	b988      	cbnz	r0, 8009164 <__swbuf_r+0x90>
 8009140:	4638      	mov	r0, r7
 8009142:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8009144:	4b0a      	ldr	r3, [pc, #40]	; (8009170 <__swbuf_r+0x9c>)
 8009146:	429c      	cmp	r4, r3
 8009148:	d101      	bne.n	800914e <__swbuf_r+0x7a>
 800914a:	68ac      	ldr	r4, [r5, #8]
 800914c:	e7cf      	b.n	80090ee <__swbuf_r+0x1a>
 800914e:	4b09      	ldr	r3, [pc, #36]	; (8009174 <__swbuf_r+0xa0>)
 8009150:	429c      	cmp	r4, r3
 8009152:	bf08      	it	eq
 8009154:	68ec      	ldreq	r4, [r5, #12]
 8009156:	e7ca      	b.n	80090ee <__swbuf_r+0x1a>
 8009158:	4621      	mov	r1, r4
 800915a:	4628      	mov	r0, r5
 800915c:	f000 f81a 	bl	8009194 <__swsetup_r>
 8009160:	2800      	cmp	r0, #0
 8009162:	d0cb      	beq.n	80090fc <__swbuf_r+0x28>
 8009164:	f04f 37ff 	mov.w	r7, #4294967295	; 0xffffffff
 8009168:	e7ea      	b.n	8009140 <__swbuf_r+0x6c>
 800916a:	bf00      	nop
 800916c:	0800a9f4 	.word	0x0800a9f4
 8009170:	0800aa14 	.word	0x0800aa14
 8009174:	0800a9d4 	.word	0x0800a9d4

08009178 <__ascii_wctomb>:
 8009178:	4603      	mov	r3, r0
 800917a:	4608      	mov	r0, r1
 800917c:	b141      	cbz	r1, 8009190 <__ascii_wctomb+0x18>
 800917e:	2aff      	cmp	r2, #255	; 0xff
 8009180:	d904      	bls.n	800918c <__ascii_wctomb+0x14>
 8009182:	228a      	movs	r2, #138	; 0x8a
 8009184:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8009188:	601a      	str	r2, [r3, #0]
 800918a:	4770      	bx	lr
 800918c:	2001      	movs	r0, #1
 800918e:	700a      	strb	r2, [r1, #0]
 8009190:	4770      	bx	lr
	...

08009194 <__swsetup_r>:
 8009194:	4b32      	ldr	r3, [pc, #200]	; (8009260 <__swsetup_r+0xcc>)
 8009196:	b570      	push	{r4, r5, r6, lr}
 8009198:	681d      	ldr	r5, [r3, #0]
 800919a:	4606      	mov	r6, r0
 800919c:	460c      	mov	r4, r1
 800919e:	b125      	cbz	r5, 80091aa <__swsetup_r+0x16>
 80091a0:	69ab      	ldr	r3, [r5, #24]
 80091a2:	b913      	cbnz	r3, 80091aa <__swsetup_r+0x16>
 80091a4:	4628      	mov	r0, r5
 80091a6:	f000 f985 	bl	80094b4 <__sinit>
 80091aa:	4b2e      	ldr	r3, [pc, #184]	; (8009264 <__swsetup_r+0xd0>)
 80091ac:	429c      	cmp	r4, r3
 80091ae:	d10f      	bne.n	80091d0 <__swsetup_r+0x3c>
 80091b0:	686c      	ldr	r4, [r5, #4]
 80091b2:	89a3      	ldrh	r3, [r4, #12]
 80091b4:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
 80091b8:	0719      	lsls	r1, r3, #28
 80091ba:	d42c      	bmi.n	8009216 <__swsetup_r+0x82>
 80091bc:	06dd      	lsls	r5, r3, #27
 80091be:	d411      	bmi.n	80091e4 <__swsetup_r+0x50>
 80091c0:	2309      	movs	r3, #9
 80091c2:	6033      	str	r3, [r6, #0]
 80091c4:	f042 0340 	orr.w	r3, r2, #64	; 0x40
 80091c8:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 80091cc:	81a3      	strh	r3, [r4, #12]
 80091ce:	e03e      	b.n	800924e <__swsetup_r+0xba>
 80091d0:	4b25      	ldr	r3, [pc, #148]	; (8009268 <__swsetup_r+0xd4>)
 80091d2:	429c      	cmp	r4, r3
 80091d4:	d101      	bne.n	80091da <__swsetup_r+0x46>
 80091d6:	68ac      	ldr	r4, [r5, #8]
 80091d8:	e7eb      	b.n	80091b2 <__swsetup_r+0x1e>
 80091da:	4b24      	ldr	r3, [pc, #144]	; (800926c <__swsetup_r+0xd8>)
 80091dc:	429c      	cmp	r4, r3
 80091de:	bf08      	it	eq
 80091e0:	68ec      	ldreq	r4, [r5, #12]
 80091e2:	e7e6      	b.n	80091b2 <__swsetup_r+0x1e>
 80091e4:	0758      	lsls	r0, r3, #29
 80091e6:	d512      	bpl.n	800920e <__swsetup_r+0x7a>
 80091e8:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80091ea:	b141      	cbz	r1, 80091fe <__swsetup_r+0x6a>
 80091ec:	f104 0344 	add.w	r3, r4, #68	; 0x44
 80091f0:	4299      	cmp	r1, r3
 80091f2:	d002      	beq.n	80091fa <__swsetup_r+0x66>
 80091f4:	4630      	mov	r0, r6
 80091f6:	f7ff fb8f 	bl	8008918 <_free_r>
 80091fa:	2300      	movs	r3, #0
 80091fc:	6363      	str	r3, [r4, #52]	; 0x34
 80091fe:	89a3      	ldrh	r3, [r4, #12]
 8009200:	f023 0324 	bic.w	r3, r3, #36	; 0x24
 8009204:	81a3      	strh	r3, [r4, #12]
 8009206:	2300      	movs	r3, #0
 8009208:	6063      	str	r3, [r4, #4]
 800920a:	6923      	ldr	r3, [r4, #16]
 800920c:	6023      	str	r3, [r4, #0]
 800920e:	89a3      	ldrh	r3, [r4, #12]
 8009210:	f043 0308 	orr.w	r3, r3, #8
 8009214:	81a3      	strh	r3, [r4, #12]
 8009216:	6923      	ldr	r3, [r4, #16]
 8009218:	b94b      	cbnz	r3, 800922e <__swsetup_r+0x9a>
 800921a:	89a3      	ldrh	r3, [r4, #12]
 800921c:	f403 7320 	and.w	r3, r3, #640	; 0x280
 8009220:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8009224:	d003      	beq.n	800922e <__swsetup_r+0x9a>
 8009226:	4621      	mov	r1, r4
 8009228:	4630      	mov	r0, r6
 800922a:	f000 fa07 	bl	800963c <__smakebuf_r>
 800922e:	89a0      	ldrh	r0, [r4, #12]
 8009230:	f9b4 200c 	ldrsh.w	r2, [r4, #12]
 8009234:	f010 0301 	ands.w	r3, r0, #1
 8009238:	d00a      	beq.n	8009250 <__swsetup_r+0xbc>
 800923a:	2300      	movs	r3, #0
 800923c:	60a3      	str	r3, [r4, #8]
 800923e:	6963      	ldr	r3, [r4, #20]
 8009240:	425b      	negs	r3, r3
 8009242:	61a3      	str	r3, [r4, #24]
 8009244:	6923      	ldr	r3, [r4, #16]
 8009246:	b943      	cbnz	r3, 800925a <__swsetup_r+0xc6>
 8009248:	f010 0080 	ands.w	r0, r0, #128	; 0x80
 800924c:	d1ba      	bne.n	80091c4 <__swsetup_r+0x30>
 800924e:	bd70      	pop	{r4, r5, r6, pc}
 8009250:	0781      	lsls	r1, r0, #30
 8009252:	bf58      	it	pl
 8009254:	6963      	ldrpl	r3, [r4, #20]
 8009256:	60a3      	str	r3, [r4, #8]
 8009258:	e7f4      	b.n	8009244 <__swsetup_r+0xb0>
 800925a:	2000      	movs	r0, #0
 800925c:	e7f7      	b.n	800924e <__swsetup_r+0xba>
 800925e:	bf00      	nop
 8009260:	20000014 	.word	0x20000014
 8009264:	0800a9f4 	.word	0x0800a9f4
 8009268:	0800aa14 	.word	0x0800aa14
 800926c:	0800a9d4 	.word	0x0800a9d4

08009270 <abort>:
 8009270:	2006      	movs	r0, #6
 8009272:	b508      	push	{r3, lr}
 8009274:	f000 fa52 	bl	800971c <raise>
 8009278:	2001      	movs	r0, #1
 800927a:	f7f8 ffac 	bl	80021d6 <_exit>
	...

08009280 <__sflush_r>:
 8009280:	898a      	ldrh	r2, [r1, #12]
 8009282:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8009286:	4605      	mov	r5, r0
 8009288:	0710      	lsls	r0, r2, #28
 800928a:	460c      	mov	r4, r1
 800928c:	d458      	bmi.n	8009340 <__sflush_r+0xc0>
 800928e:	684b      	ldr	r3, [r1, #4]
 8009290:	2b00      	cmp	r3, #0
 8009292:	dc05      	bgt.n	80092a0 <__sflush_r+0x20>
 8009294:	6c0b      	ldr	r3, [r1, #64]	; 0x40
 8009296:	2b00      	cmp	r3, #0
 8009298:	dc02      	bgt.n	80092a0 <__sflush_r+0x20>
 800929a:	2000      	movs	r0, #0
 800929c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 80092a0:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 80092a2:	2e00      	cmp	r6, #0
 80092a4:	d0f9      	beq.n	800929a <__sflush_r+0x1a>
 80092a6:	2300      	movs	r3, #0
 80092a8:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
 80092ac:	682f      	ldr	r7, [r5, #0]
 80092ae:	602b      	str	r3, [r5, #0]
 80092b0:	d032      	beq.n	8009318 <__sflush_r+0x98>
 80092b2:	6d60      	ldr	r0, [r4, #84]	; 0x54
 80092b4:	89a3      	ldrh	r3, [r4, #12]
 80092b6:	075a      	lsls	r2, r3, #29
 80092b8:	d505      	bpl.n	80092c6 <__sflush_r+0x46>
 80092ba:	6863      	ldr	r3, [r4, #4]
 80092bc:	1ac0      	subs	r0, r0, r3
 80092be:	6b63      	ldr	r3, [r4, #52]	; 0x34
 80092c0:	b10b      	cbz	r3, 80092c6 <__sflush_r+0x46>
 80092c2:	6c23      	ldr	r3, [r4, #64]	; 0x40
 80092c4:	1ac0      	subs	r0, r0, r3
 80092c6:	2300      	movs	r3, #0
 80092c8:	4602      	mov	r2, r0
 80092ca:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 80092cc:	4628      	mov	r0, r5
 80092ce:	6a21      	ldr	r1, [r4, #32]
 80092d0:	47b0      	blx	r6
 80092d2:	1c43      	adds	r3, r0, #1
 80092d4:	89a3      	ldrh	r3, [r4, #12]
 80092d6:	d106      	bne.n	80092e6 <__sflush_r+0x66>
 80092d8:	6829      	ldr	r1, [r5, #0]
 80092da:	291d      	cmp	r1, #29
 80092dc:	d82c      	bhi.n	8009338 <__sflush_r+0xb8>
 80092de:	4a2a      	ldr	r2, [pc, #168]	; (8009388 <__sflush_r+0x108>)
 80092e0:	40ca      	lsrs	r2, r1
 80092e2:	07d6      	lsls	r6, r2, #31
 80092e4:	d528      	bpl.n	8009338 <__sflush_r+0xb8>
 80092e6:	2200      	movs	r2, #0
 80092e8:	6062      	str	r2, [r4, #4]
 80092ea:	6922      	ldr	r2, [r4, #16]
 80092ec:	04d9      	lsls	r1, r3, #19
 80092ee:	6022      	str	r2, [r4, #0]
 80092f0:	d504      	bpl.n	80092fc <__sflush_r+0x7c>
 80092f2:	1c42      	adds	r2, r0, #1
 80092f4:	d101      	bne.n	80092fa <__sflush_r+0x7a>
 80092f6:	682b      	ldr	r3, [r5, #0]
 80092f8:	b903      	cbnz	r3, 80092fc <__sflush_r+0x7c>
 80092fa:	6560      	str	r0, [r4, #84]	; 0x54
 80092fc:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80092fe:	602f      	str	r7, [r5, #0]
 8009300:	2900      	cmp	r1, #0
 8009302:	d0ca      	beq.n	800929a <__sflush_r+0x1a>
 8009304:	f104 0344 	add.w	r3, r4, #68	; 0x44
 8009308:	4299      	cmp	r1, r3
 800930a:	d002      	beq.n	8009312 <__sflush_r+0x92>
 800930c:	4628      	mov	r0, r5
 800930e:	f7ff fb03 	bl	8008918 <_free_r>
 8009312:	2000      	movs	r0, #0
 8009314:	6360      	str	r0, [r4, #52]	; 0x34
 8009316:	e7c1      	b.n	800929c <__sflush_r+0x1c>
 8009318:	6a21      	ldr	r1, [r4, #32]
 800931a:	2301      	movs	r3, #1
 800931c:	4628      	mov	r0, r5
 800931e:	47b0      	blx	r6
 8009320:	1c41      	adds	r1, r0, #1
 8009322:	d1c7      	bne.n	80092b4 <__sflush_r+0x34>
 8009324:	682b      	ldr	r3, [r5, #0]
 8009326:	2b00      	cmp	r3, #0
 8009328:	d0c4      	beq.n	80092b4 <__sflush_r+0x34>
 800932a:	2b1d      	cmp	r3, #29
 800932c:	d001      	beq.n	8009332 <__sflush_r+0xb2>
 800932e:	2b16      	cmp	r3, #22
 8009330:	d101      	bne.n	8009336 <__sflush_r+0xb6>
 8009332:	602f      	str	r7, [r5, #0]
 8009334:	e7b1      	b.n	800929a <__sflush_r+0x1a>
 8009336:	89a3      	ldrh	r3, [r4, #12]
 8009338:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800933c:	81a3      	strh	r3, [r4, #12]
 800933e:	e7ad      	b.n	800929c <__sflush_r+0x1c>
 8009340:	690f      	ldr	r7, [r1, #16]
 8009342:	2f00      	cmp	r7, #0
 8009344:	d0a9      	beq.n	800929a <__sflush_r+0x1a>
 8009346:	0793      	lsls	r3, r2, #30
 8009348:	bf18      	it	ne
 800934a:	2300      	movne	r3, #0
 800934c:	680e      	ldr	r6, [r1, #0]
 800934e:	bf08      	it	eq
 8009350:	694b      	ldreq	r3, [r1, #20]
 8009352:	eba6 0807 	sub.w	r8, r6, r7
 8009356:	600f      	str	r7, [r1, #0]
 8009358:	608b      	str	r3, [r1, #8]
 800935a:	f1b8 0f00 	cmp.w	r8, #0
 800935e:	dd9c      	ble.n	800929a <__sflush_r+0x1a>
 8009360:	4643      	mov	r3, r8
 8009362:	463a      	mov	r2, r7
 8009364:	4628      	mov	r0, r5
 8009366:	6a21      	ldr	r1, [r4, #32]
 8009368:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 800936a:	47b0      	blx	r6
 800936c:	2800      	cmp	r0, #0
 800936e:	dc06      	bgt.n	800937e <__sflush_r+0xfe>
 8009370:	89a3      	ldrh	r3, [r4, #12]
 8009372:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8009376:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800937a:	81a3      	strh	r3, [r4, #12]
 800937c:	e78e      	b.n	800929c <__sflush_r+0x1c>
 800937e:	4407      	add	r7, r0
 8009380:	eba8 0800 	sub.w	r8, r8, r0
 8009384:	e7e9      	b.n	800935a <__sflush_r+0xda>
 8009386:	bf00      	nop
 8009388:	20400001 	.word	0x20400001

0800938c <_fflush_r>:
 800938c:	b538      	push	{r3, r4, r5, lr}
 800938e:	690b      	ldr	r3, [r1, #16]
 8009390:	4605      	mov	r5, r0
 8009392:	460c      	mov	r4, r1
 8009394:	b913      	cbnz	r3, 800939c <_fflush_r+0x10>
 8009396:	2500      	movs	r5, #0
 8009398:	4628      	mov	r0, r5
 800939a:	bd38      	pop	{r3, r4, r5, pc}
 800939c:	b118      	cbz	r0, 80093a6 <_fflush_r+0x1a>
 800939e:	6983      	ldr	r3, [r0, #24]
 80093a0:	b90b      	cbnz	r3, 80093a6 <_fflush_r+0x1a>
 80093a2:	f000 f887 	bl	80094b4 <__sinit>
 80093a6:	4b14      	ldr	r3, [pc, #80]	; (80093f8 <_fflush_r+0x6c>)
 80093a8:	429c      	cmp	r4, r3
 80093aa:	d11b      	bne.n	80093e4 <_fflush_r+0x58>
 80093ac:	686c      	ldr	r4, [r5, #4]
 80093ae:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80093b2:	2b00      	cmp	r3, #0
 80093b4:	d0ef      	beq.n	8009396 <_fflush_r+0xa>
 80093b6:	6e62      	ldr	r2, [r4, #100]	; 0x64
 80093b8:	07d0      	lsls	r0, r2, #31
 80093ba:	d404      	bmi.n	80093c6 <_fflush_r+0x3a>
 80093bc:	0599      	lsls	r1, r3, #22
 80093be:	d402      	bmi.n	80093c6 <_fflush_r+0x3a>
 80093c0:	6da0      	ldr	r0, [r4, #88]	; 0x58
 80093c2:	f000 f915 	bl	80095f0 <__retarget_lock_acquire_recursive>
 80093c6:	4628      	mov	r0, r5
 80093c8:	4621      	mov	r1, r4
 80093ca:	f7ff ff59 	bl	8009280 <__sflush_r>
 80093ce:	6e63      	ldr	r3, [r4, #100]	; 0x64
 80093d0:	4605      	mov	r5, r0
 80093d2:	07da      	lsls	r2, r3, #31
 80093d4:	d4e0      	bmi.n	8009398 <_fflush_r+0xc>
 80093d6:	89a3      	ldrh	r3, [r4, #12]
 80093d8:	059b      	lsls	r3, r3, #22
 80093da:	d4dd      	bmi.n	8009398 <_fflush_r+0xc>
 80093dc:	6da0      	ldr	r0, [r4, #88]	; 0x58
 80093de:	f000 f908 	bl	80095f2 <__retarget_lock_release_recursive>
 80093e2:	e7d9      	b.n	8009398 <_fflush_r+0xc>
 80093e4:	4b05      	ldr	r3, [pc, #20]	; (80093fc <_fflush_r+0x70>)
 80093e6:	429c      	cmp	r4, r3
 80093e8:	d101      	bne.n	80093ee <_fflush_r+0x62>
 80093ea:	68ac      	ldr	r4, [r5, #8]
 80093ec:	e7df      	b.n	80093ae <_fflush_r+0x22>
 80093ee:	4b04      	ldr	r3, [pc, #16]	; (8009400 <_fflush_r+0x74>)
 80093f0:	429c      	cmp	r4, r3
 80093f2:	bf08      	it	eq
 80093f4:	68ec      	ldreq	r4, [r5, #12]
 80093f6:	e7da      	b.n	80093ae <_fflush_r+0x22>
 80093f8:	0800a9f4 	.word	0x0800a9f4
 80093fc:	0800aa14 	.word	0x0800aa14
 8009400:	0800a9d4 	.word	0x0800a9d4

08009404 <std>:
 8009404:	2300      	movs	r3, #0
 8009406:	b510      	push	{r4, lr}
 8009408:	4604      	mov	r4, r0
 800940a:	e9c0 3300 	strd	r3, r3, [r0]
 800940e:	e9c0 3304 	strd	r3, r3, [r0, #16]
 8009412:	6083      	str	r3, [r0, #8]
 8009414:	8181      	strh	r1, [r0, #12]
 8009416:	6643      	str	r3, [r0, #100]	; 0x64
 8009418:	81c2      	strh	r2, [r0, #14]
 800941a:	6183      	str	r3, [r0, #24]
 800941c:	4619      	mov	r1, r3
 800941e:	2208      	movs	r2, #8
 8009420:	305c      	adds	r0, #92	; 0x5c
 8009422:	f7fd fbc9 	bl	8006bb8 <memset>
 8009426:	4b05      	ldr	r3, [pc, #20]	; (800943c <std+0x38>)
 8009428:	6224      	str	r4, [r4, #32]
 800942a:	6263      	str	r3, [r4, #36]	; 0x24
 800942c:	4b04      	ldr	r3, [pc, #16]	; (8009440 <std+0x3c>)
 800942e:	62a3      	str	r3, [r4, #40]	; 0x28
 8009430:	4b04      	ldr	r3, [pc, #16]	; (8009444 <std+0x40>)
 8009432:	62e3      	str	r3, [r4, #44]	; 0x2c
 8009434:	4b04      	ldr	r3, [pc, #16]	; (8009448 <std+0x44>)
 8009436:	6323      	str	r3, [r4, #48]	; 0x30
 8009438:	bd10      	pop	{r4, pc}
 800943a:	bf00      	nop
 800943c:	08009755 	.word	0x08009755
 8009440:	08009777 	.word	0x08009777
 8009444:	080097af 	.word	0x080097af
 8009448:	080097d3 	.word	0x080097d3

0800944c <_cleanup_r>:
 800944c:	4901      	ldr	r1, [pc, #4]	; (8009454 <_cleanup_r+0x8>)
 800944e:	f000 b8af 	b.w	80095b0 <_fwalk_reent>
 8009452:	bf00      	nop
 8009454:	0800938d 	.word	0x0800938d

08009458 <__sfmoreglue>:
 8009458:	b570      	push	{r4, r5, r6, lr}
 800945a:	2568      	movs	r5, #104	; 0x68
 800945c:	1e4a      	subs	r2, r1, #1
 800945e:	4355      	muls	r5, r2
 8009460:	460e      	mov	r6, r1
 8009462:	f105 0174 	add.w	r1, r5, #116	; 0x74
 8009466:	f7ff faa3 	bl	80089b0 <_malloc_r>
 800946a:	4604      	mov	r4, r0
 800946c:	b140      	cbz	r0, 8009480 <__sfmoreglue+0x28>
 800946e:	2100      	movs	r1, #0
 8009470:	e9c0 1600 	strd	r1, r6, [r0]
 8009474:	300c      	adds	r0, #12
 8009476:	60a0      	str	r0, [r4, #8]
 8009478:	f105 0268 	add.w	r2, r5, #104	; 0x68
 800947c:	f7fd fb9c 	bl	8006bb8 <memset>
 8009480:	4620      	mov	r0, r4
 8009482:	bd70      	pop	{r4, r5, r6, pc}

08009484 <__sfp_lock_acquire>:
 8009484:	4801      	ldr	r0, [pc, #4]	; (800948c <__sfp_lock_acquire+0x8>)
 8009486:	f000 b8b3 	b.w	80095f0 <__retarget_lock_acquire_recursive>
 800948a:	bf00      	nop
 800948c:	20000700 	.word	0x20000700

08009490 <__sfp_lock_release>:
 8009490:	4801      	ldr	r0, [pc, #4]	; (8009498 <__sfp_lock_release+0x8>)
 8009492:	f000 b8ae 	b.w	80095f2 <__retarget_lock_release_recursive>
 8009496:	bf00      	nop
 8009498:	20000700 	.word	0x20000700

0800949c <__sinit_lock_acquire>:
 800949c:	4801      	ldr	r0, [pc, #4]	; (80094a4 <__sinit_lock_acquire+0x8>)
 800949e:	f000 b8a7 	b.w	80095f0 <__retarget_lock_acquire_recursive>
 80094a2:	bf00      	nop
 80094a4:	200006fb 	.word	0x200006fb

080094a8 <__sinit_lock_release>:
 80094a8:	4801      	ldr	r0, [pc, #4]	; (80094b0 <__sinit_lock_release+0x8>)
 80094aa:	f000 b8a2 	b.w	80095f2 <__retarget_lock_release_recursive>
 80094ae:	bf00      	nop
 80094b0:	200006fb 	.word	0x200006fb

080094b4 <__sinit>:
 80094b4:	b510      	push	{r4, lr}
 80094b6:	4604      	mov	r4, r0
 80094b8:	f7ff fff0 	bl	800949c <__sinit_lock_acquire>
 80094bc:	69a3      	ldr	r3, [r4, #24]
 80094be:	b11b      	cbz	r3, 80094c8 <__sinit+0x14>
 80094c0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 80094c4:	f7ff bff0 	b.w	80094a8 <__sinit_lock_release>
 80094c8:	e9c4 3312 	strd	r3, r3, [r4, #72]	; 0x48
 80094cc:	6523      	str	r3, [r4, #80]	; 0x50
 80094ce:	4b13      	ldr	r3, [pc, #76]	; (800951c <__sinit+0x68>)
 80094d0:	4a13      	ldr	r2, [pc, #76]	; (8009520 <__sinit+0x6c>)
 80094d2:	681b      	ldr	r3, [r3, #0]
 80094d4:	62a2      	str	r2, [r4, #40]	; 0x28
 80094d6:	42a3      	cmp	r3, r4
 80094d8:	bf08      	it	eq
 80094da:	2301      	moveq	r3, #1
 80094dc:	4620      	mov	r0, r4
 80094de:	bf08      	it	eq
 80094e0:	61a3      	streq	r3, [r4, #24]
 80094e2:	f000 f81f 	bl	8009524 <__sfp>
 80094e6:	6060      	str	r0, [r4, #4]
 80094e8:	4620      	mov	r0, r4
 80094ea:	f000 f81b 	bl	8009524 <__sfp>
 80094ee:	60a0      	str	r0, [r4, #8]
 80094f0:	4620      	mov	r0, r4
 80094f2:	f000 f817 	bl	8009524 <__sfp>
 80094f6:	2200      	movs	r2, #0
 80094f8:	2104      	movs	r1, #4
 80094fa:	60e0      	str	r0, [r4, #12]
 80094fc:	6860      	ldr	r0, [r4, #4]
 80094fe:	f7ff ff81 	bl	8009404 <std>
 8009502:	2201      	movs	r2, #1
 8009504:	2109      	movs	r1, #9
 8009506:	68a0      	ldr	r0, [r4, #8]
 8009508:	f7ff ff7c 	bl	8009404 <std>
 800950c:	2202      	movs	r2, #2
 800950e:	2112      	movs	r1, #18
 8009510:	68e0      	ldr	r0, [r4, #12]
 8009512:	f7ff ff77 	bl	8009404 <std>
 8009516:	2301      	movs	r3, #1
 8009518:	61a3      	str	r3, [r4, #24]
 800951a:	e7d1      	b.n	80094c0 <__sinit+0xc>
 800951c:	0800a654 	.word	0x0800a654
 8009520:	0800944d 	.word	0x0800944d

08009524 <__sfp>:
 8009524:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8009526:	4607      	mov	r7, r0
 8009528:	f7ff ffac 	bl	8009484 <__sfp_lock_acquire>
 800952c:	4b1e      	ldr	r3, [pc, #120]	; (80095a8 <__sfp+0x84>)
 800952e:	681e      	ldr	r6, [r3, #0]
 8009530:	69b3      	ldr	r3, [r6, #24]
 8009532:	b913      	cbnz	r3, 800953a <__sfp+0x16>
 8009534:	4630      	mov	r0, r6
 8009536:	f7ff ffbd 	bl	80094b4 <__sinit>
 800953a:	3648      	adds	r6, #72	; 0x48
 800953c:	e9d6 3401 	ldrd	r3, r4, [r6, #4]
 8009540:	3b01      	subs	r3, #1
 8009542:	d503      	bpl.n	800954c <__sfp+0x28>
 8009544:	6833      	ldr	r3, [r6, #0]
 8009546:	b30b      	cbz	r3, 800958c <__sfp+0x68>
 8009548:	6836      	ldr	r6, [r6, #0]
 800954a:	e7f7      	b.n	800953c <__sfp+0x18>
 800954c:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
 8009550:	b9d5      	cbnz	r5, 8009588 <__sfp+0x64>
 8009552:	4b16      	ldr	r3, [pc, #88]	; (80095ac <__sfp+0x88>)
 8009554:	f104 0058 	add.w	r0, r4, #88	; 0x58
 8009558:	60e3      	str	r3, [r4, #12]
 800955a:	6665      	str	r5, [r4, #100]	; 0x64
 800955c:	f000 f847 	bl	80095ee <__retarget_lock_init_recursive>
 8009560:	f7ff ff96 	bl	8009490 <__sfp_lock_release>
 8009564:	2208      	movs	r2, #8
 8009566:	4629      	mov	r1, r5
 8009568:	e9c4 5501 	strd	r5, r5, [r4, #4]
 800956c:	e9c4 5504 	strd	r5, r5, [r4, #16]
 8009570:	6025      	str	r5, [r4, #0]
 8009572:	61a5      	str	r5, [r4, #24]
 8009574:	f104 005c 	add.w	r0, r4, #92	; 0x5c
 8009578:	f7fd fb1e 	bl	8006bb8 <memset>
 800957c:	e9c4 550d 	strd	r5, r5, [r4, #52]	; 0x34
 8009580:	e9c4 5512 	strd	r5, r5, [r4, #72]	; 0x48
 8009584:	4620      	mov	r0, r4
 8009586:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8009588:	3468      	adds	r4, #104	; 0x68
 800958a:	e7d9      	b.n	8009540 <__sfp+0x1c>
 800958c:	2104      	movs	r1, #4
 800958e:	4638      	mov	r0, r7
 8009590:	f7ff ff62 	bl	8009458 <__sfmoreglue>
 8009594:	4604      	mov	r4, r0
 8009596:	6030      	str	r0, [r6, #0]
 8009598:	2800      	cmp	r0, #0
 800959a:	d1d5      	bne.n	8009548 <__sfp+0x24>
 800959c:	f7ff ff78 	bl	8009490 <__sfp_lock_release>
 80095a0:	230c      	movs	r3, #12
 80095a2:	603b      	str	r3, [r7, #0]
 80095a4:	e7ee      	b.n	8009584 <__sfp+0x60>
 80095a6:	bf00      	nop
 80095a8:	0800a654 	.word	0x0800a654
 80095ac:	ffff0001 	.word	0xffff0001

080095b0 <_fwalk_reent>:
 80095b0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 80095b4:	4606      	mov	r6, r0
 80095b6:	4688      	mov	r8, r1
 80095b8:	2700      	movs	r7, #0
 80095ba:	f100 0448 	add.w	r4, r0, #72	; 0x48
 80095be:	e9d4 9501 	ldrd	r9, r5, [r4, #4]
 80095c2:	f1b9 0901 	subs.w	r9, r9, #1
 80095c6:	d505      	bpl.n	80095d4 <_fwalk_reent+0x24>
 80095c8:	6824      	ldr	r4, [r4, #0]
 80095ca:	2c00      	cmp	r4, #0
 80095cc:	d1f7      	bne.n	80095be <_fwalk_reent+0xe>
 80095ce:	4638      	mov	r0, r7
 80095d0:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 80095d4:	89ab      	ldrh	r3, [r5, #12]
 80095d6:	2b01      	cmp	r3, #1
 80095d8:	d907      	bls.n	80095ea <_fwalk_reent+0x3a>
 80095da:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 80095de:	3301      	adds	r3, #1
 80095e0:	d003      	beq.n	80095ea <_fwalk_reent+0x3a>
 80095e2:	4629      	mov	r1, r5
 80095e4:	4630      	mov	r0, r6
 80095e6:	47c0      	blx	r8
 80095e8:	4307      	orrs	r7, r0
 80095ea:	3568      	adds	r5, #104	; 0x68
 80095ec:	e7e9      	b.n	80095c2 <_fwalk_reent+0x12>

080095ee <__retarget_lock_init_recursive>:
 80095ee:	4770      	bx	lr

080095f0 <__retarget_lock_acquire_recursive>:
 80095f0:	4770      	bx	lr

080095f2 <__retarget_lock_release_recursive>:
 80095f2:	4770      	bx	lr

080095f4 <__swhatbuf_r>:
 80095f4:	b570      	push	{r4, r5, r6, lr}
 80095f6:	460e      	mov	r6, r1
 80095f8:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80095fc:	4614      	mov	r4, r2
 80095fe:	2900      	cmp	r1, #0
 8009600:	461d      	mov	r5, r3
 8009602:	b096      	sub	sp, #88	; 0x58
 8009604:	da07      	bge.n	8009616 <__swhatbuf_r+0x22>
 8009606:	2300      	movs	r3, #0
 8009608:	602b      	str	r3, [r5, #0]
 800960a:	89b3      	ldrh	r3, [r6, #12]
 800960c:	061a      	lsls	r2, r3, #24
 800960e:	d410      	bmi.n	8009632 <__swhatbuf_r+0x3e>
 8009610:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8009614:	e00e      	b.n	8009634 <__swhatbuf_r+0x40>
 8009616:	466a      	mov	r2, sp
 8009618:	f000 f902 	bl	8009820 <_fstat_r>
 800961c:	2800      	cmp	r0, #0
 800961e:	dbf2      	blt.n	8009606 <__swhatbuf_r+0x12>
 8009620:	9a01      	ldr	r2, [sp, #4]
 8009622:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
 8009626:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
 800962a:	425a      	negs	r2, r3
 800962c:	415a      	adcs	r2, r3
 800962e:	602a      	str	r2, [r5, #0]
 8009630:	e7ee      	b.n	8009610 <__swhatbuf_r+0x1c>
 8009632:	2340      	movs	r3, #64	; 0x40
 8009634:	2000      	movs	r0, #0
 8009636:	6023      	str	r3, [r4, #0]
 8009638:	b016      	add	sp, #88	; 0x58
 800963a:	bd70      	pop	{r4, r5, r6, pc}

0800963c <__smakebuf_r>:
 800963c:	898b      	ldrh	r3, [r1, #12]
 800963e:	b573      	push	{r0, r1, r4, r5, r6, lr}
 8009640:	079d      	lsls	r5, r3, #30
 8009642:	4606      	mov	r6, r0
 8009644:	460c      	mov	r4, r1
 8009646:	d507      	bpl.n	8009658 <__smakebuf_r+0x1c>
 8009648:	f104 0347 	add.w	r3, r4, #71	; 0x47
 800964c:	6023      	str	r3, [r4, #0]
 800964e:	6123      	str	r3, [r4, #16]
 8009650:	2301      	movs	r3, #1
 8009652:	6163      	str	r3, [r4, #20]
 8009654:	b002      	add	sp, #8
 8009656:	bd70      	pop	{r4, r5, r6, pc}
 8009658:	466a      	mov	r2, sp
 800965a:	ab01      	add	r3, sp, #4
 800965c:	f7ff ffca 	bl	80095f4 <__swhatbuf_r>
 8009660:	9900      	ldr	r1, [sp, #0]
 8009662:	4605      	mov	r5, r0
 8009664:	4630      	mov	r0, r6
 8009666:	f7ff f9a3 	bl	80089b0 <_malloc_r>
 800966a:	b948      	cbnz	r0, 8009680 <__smakebuf_r+0x44>
 800966c:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8009670:	059a      	lsls	r2, r3, #22
 8009672:	d4ef      	bmi.n	8009654 <__smakebuf_r+0x18>
 8009674:	f023 0303 	bic.w	r3, r3, #3
 8009678:	f043 0302 	orr.w	r3, r3, #2
 800967c:	81a3      	strh	r3, [r4, #12]
 800967e:	e7e3      	b.n	8009648 <__smakebuf_r+0xc>
 8009680:	4b0d      	ldr	r3, [pc, #52]	; (80096b8 <__smakebuf_r+0x7c>)
 8009682:	62b3      	str	r3, [r6, #40]	; 0x28
 8009684:	89a3      	ldrh	r3, [r4, #12]
 8009686:	6020      	str	r0, [r4, #0]
 8009688:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 800968c:	81a3      	strh	r3, [r4, #12]
 800968e:	9b00      	ldr	r3, [sp, #0]
 8009690:	6120      	str	r0, [r4, #16]
 8009692:	6163      	str	r3, [r4, #20]
 8009694:	9b01      	ldr	r3, [sp, #4]
 8009696:	b15b      	cbz	r3, 80096b0 <__smakebuf_r+0x74>
 8009698:	4630      	mov	r0, r6
 800969a:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 800969e:	f000 f8d1 	bl	8009844 <_isatty_r>
 80096a2:	b128      	cbz	r0, 80096b0 <__smakebuf_r+0x74>
 80096a4:	89a3      	ldrh	r3, [r4, #12]
 80096a6:	f023 0303 	bic.w	r3, r3, #3
 80096aa:	f043 0301 	orr.w	r3, r3, #1
 80096ae:	81a3      	strh	r3, [r4, #12]
 80096b0:	89a0      	ldrh	r0, [r4, #12]
 80096b2:	4305      	orrs	r5, r0
 80096b4:	81a5      	strh	r5, [r4, #12]
 80096b6:	e7cd      	b.n	8009654 <__smakebuf_r+0x18>
 80096b8:	0800944d 	.word	0x0800944d

080096bc <_malloc_usable_size_r>:
 80096bc:	f851 3c04 	ldr.w	r3, [r1, #-4]
 80096c0:	1f18      	subs	r0, r3, #4
 80096c2:	2b00      	cmp	r3, #0
 80096c4:	bfbc      	itt	lt
 80096c6:	580b      	ldrlt	r3, [r1, r0]
 80096c8:	18c0      	addlt	r0, r0, r3
 80096ca:	4770      	bx	lr

080096cc <_raise_r>:
 80096cc:	291f      	cmp	r1, #31
 80096ce:	b538      	push	{r3, r4, r5, lr}
 80096d0:	4604      	mov	r4, r0
 80096d2:	460d      	mov	r5, r1
 80096d4:	d904      	bls.n	80096e0 <_raise_r+0x14>
 80096d6:	2316      	movs	r3, #22
 80096d8:	6003      	str	r3, [r0, #0]
 80096da:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 80096de:	bd38      	pop	{r3, r4, r5, pc}
 80096e0:	6c42      	ldr	r2, [r0, #68]	; 0x44
 80096e2:	b112      	cbz	r2, 80096ea <_raise_r+0x1e>
 80096e4:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
 80096e8:	b94b      	cbnz	r3, 80096fe <_raise_r+0x32>
 80096ea:	4620      	mov	r0, r4
 80096ec:	f000 f830 	bl	8009750 <_getpid_r>
 80096f0:	462a      	mov	r2, r5
 80096f2:	4601      	mov	r1, r0
 80096f4:	4620      	mov	r0, r4
 80096f6:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 80096fa:	f000 b817 	b.w	800972c <_kill_r>
 80096fe:	2b01      	cmp	r3, #1
 8009700:	d00a      	beq.n	8009718 <_raise_r+0x4c>
 8009702:	1c59      	adds	r1, r3, #1
 8009704:	d103      	bne.n	800970e <_raise_r+0x42>
 8009706:	2316      	movs	r3, #22
 8009708:	6003      	str	r3, [r0, #0]
 800970a:	2001      	movs	r0, #1
 800970c:	e7e7      	b.n	80096de <_raise_r+0x12>
 800970e:	2400      	movs	r4, #0
 8009710:	4628      	mov	r0, r5
 8009712:	f842 4025 	str.w	r4, [r2, r5, lsl #2]
 8009716:	4798      	blx	r3
 8009718:	2000      	movs	r0, #0
 800971a:	e7e0      	b.n	80096de <_raise_r+0x12>

0800971c <raise>:
 800971c:	4b02      	ldr	r3, [pc, #8]	; (8009728 <raise+0xc>)
 800971e:	4601      	mov	r1, r0
 8009720:	6818      	ldr	r0, [r3, #0]
 8009722:	f7ff bfd3 	b.w	80096cc <_raise_r>
 8009726:	bf00      	nop
 8009728:	20000014 	.word	0x20000014

0800972c <_kill_r>:
 800972c:	b538      	push	{r3, r4, r5, lr}
 800972e:	2300      	movs	r3, #0
 8009730:	4d06      	ldr	r5, [pc, #24]	; (800974c <_kill_r+0x20>)
 8009732:	4604      	mov	r4, r0
 8009734:	4608      	mov	r0, r1
 8009736:	4611      	mov	r1, r2
 8009738:	602b      	str	r3, [r5, #0]
 800973a:	f7f8 fd3c 	bl	80021b6 <_kill>
 800973e:	1c43      	adds	r3, r0, #1
 8009740:	d102      	bne.n	8009748 <_kill_r+0x1c>
 8009742:	682b      	ldr	r3, [r5, #0]
 8009744:	b103      	cbz	r3, 8009748 <_kill_r+0x1c>
 8009746:	6023      	str	r3, [r4, #0]
 8009748:	bd38      	pop	{r3, r4, r5, pc}
 800974a:	bf00      	nop
 800974c:	200006f4 	.word	0x200006f4

08009750 <_getpid_r>:
 8009750:	f7f8 bd2a 	b.w	80021a8 <_getpid>

08009754 <__sread>:
 8009754:	b510      	push	{r4, lr}
 8009756:	460c      	mov	r4, r1
 8009758:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800975c:	f000 f894 	bl	8009888 <_read_r>
 8009760:	2800      	cmp	r0, #0
 8009762:	bfab      	itete	ge
 8009764:	6d63      	ldrge	r3, [r4, #84]	; 0x54
 8009766:	89a3      	ldrhlt	r3, [r4, #12]
 8009768:	181b      	addge	r3, r3, r0
 800976a:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
 800976e:	bfac      	ite	ge
 8009770:	6563      	strge	r3, [r4, #84]	; 0x54
 8009772:	81a3      	strhlt	r3, [r4, #12]
 8009774:	bd10      	pop	{r4, pc}

08009776 <__swrite>:
 8009776:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 800977a:	461f      	mov	r7, r3
 800977c:	898b      	ldrh	r3, [r1, #12]
 800977e:	4605      	mov	r5, r0
 8009780:	05db      	lsls	r3, r3, #23
 8009782:	460c      	mov	r4, r1
 8009784:	4616      	mov	r6, r2
 8009786:	d505      	bpl.n	8009794 <__swrite+0x1e>
 8009788:	2302      	movs	r3, #2
 800978a:	2200      	movs	r2, #0
 800978c:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8009790:	f000 f868 	bl	8009864 <_lseek_r>
 8009794:	89a3      	ldrh	r3, [r4, #12]
 8009796:	4632      	mov	r2, r6
 8009798:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 800979c:	81a3      	strh	r3, [r4, #12]
 800979e:	4628      	mov	r0, r5
 80097a0:	463b      	mov	r3, r7
 80097a2:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 80097a6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 80097aa:	f000 b817 	b.w	80097dc <_write_r>

080097ae <__sseek>:
 80097ae:	b510      	push	{r4, lr}
 80097b0:	460c      	mov	r4, r1
 80097b2:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80097b6:	f000 f855 	bl	8009864 <_lseek_r>
 80097ba:	1c43      	adds	r3, r0, #1
 80097bc:	89a3      	ldrh	r3, [r4, #12]
 80097be:	bf15      	itete	ne
 80097c0:	6560      	strne	r0, [r4, #84]	; 0x54
 80097c2:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
 80097c6:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
 80097ca:	81a3      	strheq	r3, [r4, #12]
 80097cc:	bf18      	it	ne
 80097ce:	81a3      	strhne	r3, [r4, #12]
 80097d0:	bd10      	pop	{r4, pc}

080097d2 <__sclose>:
 80097d2:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80097d6:	f000 b813 	b.w	8009800 <_close_r>
	...

080097dc <_write_r>:
 80097dc:	b538      	push	{r3, r4, r5, lr}
 80097de:	4604      	mov	r4, r0
 80097e0:	4608      	mov	r0, r1
 80097e2:	4611      	mov	r1, r2
 80097e4:	2200      	movs	r2, #0
 80097e6:	4d05      	ldr	r5, [pc, #20]	; (80097fc <_write_r+0x20>)
 80097e8:	602a      	str	r2, [r5, #0]
 80097ea:	461a      	mov	r2, r3
 80097ec:	f7f8 fd1a 	bl	8002224 <_write>
 80097f0:	1c43      	adds	r3, r0, #1
 80097f2:	d102      	bne.n	80097fa <_write_r+0x1e>
 80097f4:	682b      	ldr	r3, [r5, #0]
 80097f6:	b103      	cbz	r3, 80097fa <_write_r+0x1e>
 80097f8:	6023      	str	r3, [r4, #0]
 80097fa:	bd38      	pop	{r3, r4, r5, pc}
 80097fc:	200006f4 	.word	0x200006f4

08009800 <_close_r>:
 8009800:	b538      	push	{r3, r4, r5, lr}
 8009802:	2300      	movs	r3, #0
 8009804:	4d05      	ldr	r5, [pc, #20]	; (800981c <_close_r+0x1c>)
 8009806:	4604      	mov	r4, r0
 8009808:	4608      	mov	r0, r1
 800980a:	602b      	str	r3, [r5, #0]
 800980c:	f7f8 fd26 	bl	800225c <_close>
 8009810:	1c43      	adds	r3, r0, #1
 8009812:	d102      	bne.n	800981a <_close_r+0x1a>
 8009814:	682b      	ldr	r3, [r5, #0]
 8009816:	b103      	cbz	r3, 800981a <_close_r+0x1a>
 8009818:	6023      	str	r3, [r4, #0]
 800981a:	bd38      	pop	{r3, r4, r5, pc}
 800981c:	200006f4 	.word	0x200006f4

08009820 <_fstat_r>:
 8009820:	b538      	push	{r3, r4, r5, lr}
 8009822:	2300      	movs	r3, #0
 8009824:	4d06      	ldr	r5, [pc, #24]	; (8009840 <_fstat_r+0x20>)
 8009826:	4604      	mov	r4, r0
 8009828:	4608      	mov	r0, r1
 800982a:	4611      	mov	r1, r2
 800982c:	602b      	str	r3, [r5, #0]
 800982e:	f7f8 fd20 	bl	8002272 <_fstat>
 8009832:	1c43      	adds	r3, r0, #1
 8009834:	d102      	bne.n	800983c <_fstat_r+0x1c>
 8009836:	682b      	ldr	r3, [r5, #0]
 8009838:	b103      	cbz	r3, 800983c <_fstat_r+0x1c>
 800983a:	6023      	str	r3, [r4, #0]
 800983c:	bd38      	pop	{r3, r4, r5, pc}
 800983e:	bf00      	nop
 8009840:	200006f4 	.word	0x200006f4

08009844 <_isatty_r>:
 8009844:	b538      	push	{r3, r4, r5, lr}
 8009846:	2300      	movs	r3, #0
 8009848:	4d05      	ldr	r5, [pc, #20]	; (8009860 <_isatty_r+0x1c>)
 800984a:	4604      	mov	r4, r0
 800984c:	4608      	mov	r0, r1
 800984e:	602b      	str	r3, [r5, #0]
 8009850:	f7f8 fd1e 	bl	8002290 <_isatty>
 8009854:	1c43      	adds	r3, r0, #1
 8009856:	d102      	bne.n	800985e <_isatty_r+0x1a>
 8009858:	682b      	ldr	r3, [r5, #0]
 800985a:	b103      	cbz	r3, 800985e <_isatty_r+0x1a>
 800985c:	6023      	str	r3, [r4, #0]
 800985e:	bd38      	pop	{r3, r4, r5, pc}
 8009860:	200006f4 	.word	0x200006f4

08009864 <_lseek_r>:
 8009864:	b538      	push	{r3, r4, r5, lr}
 8009866:	4604      	mov	r4, r0
 8009868:	4608      	mov	r0, r1
 800986a:	4611      	mov	r1, r2
 800986c:	2200      	movs	r2, #0
 800986e:	4d05      	ldr	r5, [pc, #20]	; (8009884 <_lseek_r+0x20>)
 8009870:	602a      	str	r2, [r5, #0]
 8009872:	461a      	mov	r2, r3
 8009874:	f7f8 fd16 	bl	80022a4 <_lseek>
 8009878:	1c43      	adds	r3, r0, #1
 800987a:	d102      	bne.n	8009882 <_lseek_r+0x1e>
 800987c:	682b      	ldr	r3, [r5, #0]
 800987e:	b103      	cbz	r3, 8009882 <_lseek_r+0x1e>
 8009880:	6023      	str	r3, [r4, #0]
 8009882:	bd38      	pop	{r3, r4, r5, pc}
 8009884:	200006f4 	.word	0x200006f4

08009888 <_read_r>:
 8009888:	b538      	push	{r3, r4, r5, lr}
 800988a:	4604      	mov	r4, r0
 800988c:	4608      	mov	r0, r1
 800988e:	4611      	mov	r1, r2
 8009890:	2200      	movs	r2, #0
 8009892:	4d05      	ldr	r5, [pc, #20]	; (80098a8 <_read_r+0x20>)
 8009894:	602a      	str	r2, [r5, #0]
 8009896:	461a      	mov	r2, r3
 8009898:	f7f8 fca7 	bl	80021ea <_read>
 800989c:	1c43      	adds	r3, r0, #1
 800989e:	d102      	bne.n	80098a6 <_read_r+0x1e>
 80098a0:	682b      	ldr	r3, [r5, #0]
 80098a2:	b103      	cbz	r3, 80098a6 <_read_r+0x1e>
 80098a4:	6023      	str	r3, [r4, #0]
 80098a6:	bd38      	pop	{r3, r4, r5, pc}
 80098a8:	200006f4 	.word	0x200006f4

080098ac <_init>:
 80098ac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80098ae:	bf00      	nop
 80098b0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80098b2:	bc08      	pop	{r3}
 80098b4:	469e      	mov	lr, r3
 80098b6:	4770      	bx	lr

080098b8 <_fini>:
 80098b8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80098ba:	bf00      	nop
 80098bc:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80098be:	bc08      	pop	{r3}
 80098c0:	469e      	mov	lr, r3
 80098c2:	4770      	bx	lr