dosimeter-fw.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c4 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00008d9c 080001c4 080001c4 000101c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000060 08008f60 08008f60 00018f60 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08008fc0 08008fc0 00020190 2**0 CONTENTS 4 .ARM 00000008 08008fc0 08008fc0 00018fc0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08008fc8 08008fc8 00020190 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08008fc8 08008fc8 00018fc8 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08008fcc 08008fcc 00018fcc 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000190 20000000 08008fd0 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00001d6c 20000190 08009160 00020190 2**2 ALLOC 10 ._user_heap_stack 00000604 20001efc 08009160 00021efc 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00020190 2**0 CONTENTS, READONLY 12 .debug_info 00022c42 00000000 00000000 000201c0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 0000429c 00000000 00000000 00042e02 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001960 00000000 00000000 000470a0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 000017c8 00000000 00000000 00048a00 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00028414 00000000 00000000 0004a1c8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001f97f 00000000 00000000 000725dc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000ebf42 00000000 00000000 00091f5b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000053 00000000 00000000 0017de9d 2**0 CONTENTS, READONLY 20 .debug_frame 00006c2c 00000000 00000000 0017def0 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001c4 <__do_global_dtors_aux>: 80001c4: b510 push {r4, lr} 80001c6: 4c05 ldr r4, [pc, #20] ; (80001dc <__do_global_dtors_aux+0x18>) 80001c8: 7823 ldrb r3, [r4, #0] 80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16> 80001cc: 4b04 ldr r3, [pc, #16] ; (80001e0 <__do_global_dtors_aux+0x1c>) 80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12> 80001d0: 4804 ldr r0, [pc, #16] ; (80001e4 <__do_global_dtors_aux+0x20>) 80001d2: f3af 8000 nop.w 80001d6: 2301 movs r3, #1 80001d8: 7023 strb r3, [r4, #0] 80001da: bd10 pop {r4, pc} 80001dc: 20000190 .word 0x20000190 80001e0: 00000000 .word 0x00000000 80001e4: 08008f48 .word 0x08008f48 080001e8 : 80001e8: b508 push {r3, lr} 80001ea: 4b03 ldr r3, [pc, #12] ; (80001f8 ) 80001ec: b11b cbz r3, 80001f6 80001ee: 4903 ldr r1, [pc, #12] ; (80001fc ) 80001f0: 4803 ldr r0, [pc, #12] ; (8000200 ) 80001f2: f3af 8000 nop.w 80001f6: bd08 pop {r3, pc} 80001f8: 00000000 .word 0x00000000 80001fc: 20000194 .word 0x20000194 8000200: 08008f48 .word 0x08008f48 08000204 <__aeabi_uldivmod>: 8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18> 8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18> 8000208: 2900 cmp r1, #0 800020a: bf08 it eq 800020c: 2800 cmpeq r0, #0 800020e: bf1c itt ne 8000210: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff 8000214: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 8000218: f000 b96e b.w 80004f8 <__aeabi_idiv0> 800021c: f1ad 0c08 sub.w ip, sp, #8 8000220: e96d ce04 strd ip, lr, [sp, #-16]! 8000224: f000 f806 bl 8000234 <__udivmoddi4> 8000228: f8dd e004 ldr.w lr, [sp, #4] 800022c: e9dd 2302 ldrd r2, r3, [sp, #8] 8000230: b004 add sp, #16 8000232: 4770 bx lr 08000234 <__udivmoddi4>: 8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000238: 9d08 ldr r5, [sp, #32] 800023a: 4604 mov r4, r0 800023c: 468c mov ip, r1 800023e: 2b00 cmp r3, #0 8000240: f040 8083 bne.w 800034a <__udivmoddi4+0x116> 8000244: 428a cmp r2, r1 8000246: 4617 mov r7, r2 8000248: d947 bls.n 80002da <__udivmoddi4+0xa6> 800024a: fab2 f282 clz r2, r2 800024e: b142 cbz r2, 8000262 <__udivmoddi4+0x2e> 8000250: f1c2 0020 rsb r0, r2, #32 8000254: fa24 f000 lsr.w r0, r4, r0 8000258: 4091 lsls r1, r2 800025a: 4097 lsls r7, r2 800025c: ea40 0c01 orr.w ip, r0, r1 8000260: 4094 lsls r4, r2 8000262: ea4f 4817 mov.w r8, r7, lsr #16 8000266: 0c23 lsrs r3, r4, #16 8000268: fbbc f6f8 udiv r6, ip, r8 800026c: fa1f fe87 uxth.w lr, r7 8000270: fb08 c116 mls r1, r8, r6, ip 8000274: ea43 4301 orr.w r3, r3, r1, lsl #16 8000278: fb06 f10e mul.w r1, r6, lr 800027c: 4299 cmp r1, r3 800027e: d909 bls.n 8000294 <__udivmoddi4+0x60> 8000280: 18fb adds r3, r7, r3 8000282: f106 30ff add.w r0, r6, #4294967295 ; 0xffffffff 8000286: f080 8119 bcs.w 80004bc <__udivmoddi4+0x288> 800028a: 4299 cmp r1, r3 800028c: f240 8116 bls.w 80004bc <__udivmoddi4+0x288> 8000290: 3e02 subs r6, #2 8000292: 443b add r3, r7 8000294: 1a5b subs r3, r3, r1 8000296: b2a4 uxth r4, r4 8000298: fbb3 f0f8 udiv r0, r3, r8 800029c: fb08 3310 mls r3, r8, r0, r3 80002a0: ea44 4403 orr.w r4, r4, r3, lsl #16 80002a4: fb00 fe0e mul.w lr, r0, lr 80002a8: 45a6 cmp lr, r4 80002aa: d909 bls.n 80002c0 <__udivmoddi4+0x8c> 80002ac: 193c adds r4, r7, r4 80002ae: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 80002b2: f080 8105 bcs.w 80004c0 <__udivmoddi4+0x28c> 80002b6: 45a6 cmp lr, r4 80002b8: f240 8102 bls.w 80004c0 <__udivmoddi4+0x28c> 80002bc: 3802 subs r0, #2 80002be: 443c add r4, r7 80002c0: ea40 4006 orr.w r0, r0, r6, lsl #16 80002c4: eba4 040e sub.w r4, r4, lr 80002c8: 2600 movs r6, #0 80002ca: b11d cbz r5, 80002d4 <__udivmoddi4+0xa0> 80002cc: 40d4 lsrs r4, r2 80002ce: 2300 movs r3, #0 80002d0: e9c5 4300 strd r4, r3, [r5] 80002d4: 4631 mov r1, r6 80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002da: b902 cbnz r2, 80002de <__udivmoddi4+0xaa> 80002dc: deff udf #255 ; 0xff 80002de: fab2 f282 clz r2, r2 80002e2: 2a00 cmp r2, #0 80002e4: d150 bne.n 8000388 <__udivmoddi4+0x154> 80002e6: 1bcb subs r3, r1, r7 80002e8: ea4f 4e17 mov.w lr, r7, lsr #16 80002ec: fa1f f887 uxth.w r8, r7 80002f0: 2601 movs r6, #1 80002f2: fbb3 fcfe udiv ip, r3, lr 80002f6: 0c21 lsrs r1, r4, #16 80002f8: fb0e 331c mls r3, lr, ip, r3 80002fc: ea41 4103 orr.w r1, r1, r3, lsl #16 8000300: fb08 f30c mul.w r3, r8, ip 8000304: 428b cmp r3, r1 8000306: d907 bls.n 8000318 <__udivmoddi4+0xe4> 8000308: 1879 adds r1, r7, r1 800030a: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff 800030e: d202 bcs.n 8000316 <__udivmoddi4+0xe2> 8000310: 428b cmp r3, r1 8000312: f200 80e9 bhi.w 80004e8 <__udivmoddi4+0x2b4> 8000316: 4684 mov ip, r0 8000318: 1ac9 subs r1, r1, r3 800031a: b2a3 uxth r3, r4 800031c: fbb1 f0fe udiv r0, r1, lr 8000320: fb0e 1110 mls r1, lr, r0, r1 8000324: ea43 4401 orr.w r4, r3, r1, lsl #16 8000328: fb08 f800 mul.w r8, r8, r0 800032c: 45a0 cmp r8, r4 800032e: d907 bls.n 8000340 <__udivmoddi4+0x10c> 8000330: 193c adds r4, r7, r4 8000332: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 8000336: d202 bcs.n 800033e <__udivmoddi4+0x10a> 8000338: 45a0 cmp r8, r4 800033a: f200 80d9 bhi.w 80004f0 <__udivmoddi4+0x2bc> 800033e: 4618 mov r0, r3 8000340: eba4 0408 sub.w r4, r4, r8 8000344: ea40 400c orr.w r0, r0, ip, lsl #16 8000348: e7bf b.n 80002ca <__udivmoddi4+0x96> 800034a: 428b cmp r3, r1 800034c: d909 bls.n 8000362 <__udivmoddi4+0x12e> 800034e: 2d00 cmp r5, #0 8000350: f000 80b1 beq.w 80004b6 <__udivmoddi4+0x282> 8000354: 2600 movs r6, #0 8000356: e9c5 0100 strd r0, r1, [r5] 800035a: 4630 mov r0, r6 800035c: 4631 mov r1, r6 800035e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000362: fab3 f683 clz r6, r3 8000366: 2e00 cmp r6, #0 8000368: d14a bne.n 8000400 <__udivmoddi4+0x1cc> 800036a: 428b cmp r3, r1 800036c: d302 bcc.n 8000374 <__udivmoddi4+0x140> 800036e: 4282 cmp r2, r0 8000370: f200 80b8 bhi.w 80004e4 <__udivmoddi4+0x2b0> 8000374: 1a84 subs r4, r0, r2 8000376: eb61 0103 sbc.w r1, r1, r3 800037a: 2001 movs r0, #1 800037c: 468c mov ip, r1 800037e: 2d00 cmp r5, #0 8000380: d0a8 beq.n 80002d4 <__udivmoddi4+0xa0> 8000382: e9c5 4c00 strd r4, ip, [r5] 8000386: e7a5 b.n 80002d4 <__udivmoddi4+0xa0> 8000388: f1c2 0320 rsb r3, r2, #32 800038c: fa20 f603 lsr.w r6, r0, r3 8000390: 4097 lsls r7, r2 8000392: fa01 f002 lsl.w r0, r1, r2 8000396: ea4f 4e17 mov.w lr, r7, lsr #16 800039a: 40d9 lsrs r1, r3 800039c: 4330 orrs r0, r6 800039e: 0c03 lsrs r3, r0, #16 80003a0: fbb1 f6fe udiv r6, r1, lr 80003a4: fa1f f887 uxth.w r8, r7 80003a8: fb0e 1116 mls r1, lr, r6, r1 80003ac: ea43 4301 orr.w r3, r3, r1, lsl #16 80003b0: fb06 f108 mul.w r1, r6, r8 80003b4: 4299 cmp r1, r3 80003b6: fa04 f402 lsl.w r4, r4, r2 80003ba: d909 bls.n 80003d0 <__udivmoddi4+0x19c> 80003bc: 18fb adds r3, r7, r3 80003be: f106 3cff add.w ip, r6, #4294967295 ; 0xffffffff 80003c2: f080 808d bcs.w 80004e0 <__udivmoddi4+0x2ac> 80003c6: 4299 cmp r1, r3 80003c8: f240 808a bls.w 80004e0 <__udivmoddi4+0x2ac> 80003cc: 3e02 subs r6, #2 80003ce: 443b add r3, r7 80003d0: 1a5b subs r3, r3, r1 80003d2: b281 uxth r1, r0 80003d4: fbb3 f0fe udiv r0, r3, lr 80003d8: fb0e 3310 mls r3, lr, r0, r3 80003dc: ea41 4103 orr.w r1, r1, r3, lsl #16 80003e0: fb00 f308 mul.w r3, r0, r8 80003e4: 428b cmp r3, r1 80003e6: d907 bls.n 80003f8 <__udivmoddi4+0x1c4> 80003e8: 1879 adds r1, r7, r1 80003ea: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff 80003ee: d273 bcs.n 80004d8 <__udivmoddi4+0x2a4> 80003f0: 428b cmp r3, r1 80003f2: d971 bls.n 80004d8 <__udivmoddi4+0x2a4> 80003f4: 3802 subs r0, #2 80003f6: 4439 add r1, r7 80003f8: 1acb subs r3, r1, r3 80003fa: ea40 4606 orr.w r6, r0, r6, lsl #16 80003fe: e778 b.n 80002f2 <__udivmoddi4+0xbe> 8000400: f1c6 0c20 rsb ip, r6, #32 8000404: fa03 f406 lsl.w r4, r3, r6 8000408: fa22 f30c lsr.w r3, r2, ip 800040c: 431c orrs r4, r3 800040e: fa20 f70c lsr.w r7, r0, ip 8000412: fa01 f306 lsl.w r3, r1, r6 8000416: ea4f 4e14 mov.w lr, r4, lsr #16 800041a: fa21 f10c lsr.w r1, r1, ip 800041e: 431f orrs r7, r3 8000420: 0c3b lsrs r3, r7, #16 8000422: fbb1 f9fe udiv r9, r1, lr 8000426: fa1f f884 uxth.w r8, r4 800042a: fb0e 1119 mls r1, lr, r9, r1 800042e: ea43 4101 orr.w r1, r3, r1, lsl #16 8000432: fb09 fa08 mul.w sl, r9, r8 8000436: 458a cmp sl, r1 8000438: fa02 f206 lsl.w r2, r2, r6 800043c: fa00 f306 lsl.w r3, r0, r6 8000440: d908 bls.n 8000454 <__udivmoddi4+0x220> 8000442: 1861 adds r1, r4, r1 8000444: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff 8000448: d248 bcs.n 80004dc <__udivmoddi4+0x2a8> 800044a: 458a cmp sl, r1 800044c: d946 bls.n 80004dc <__udivmoddi4+0x2a8> 800044e: f1a9 0902 sub.w r9, r9, #2 8000452: 4421 add r1, r4 8000454: eba1 010a sub.w r1, r1, sl 8000458: b2bf uxth r7, r7 800045a: fbb1 f0fe udiv r0, r1, lr 800045e: fb0e 1110 mls r1, lr, r0, r1 8000462: ea47 4701 orr.w r7, r7, r1, lsl #16 8000466: fb00 f808 mul.w r8, r0, r8 800046a: 45b8 cmp r8, r7 800046c: d907 bls.n 800047e <__udivmoddi4+0x24a> 800046e: 19e7 adds r7, r4, r7 8000470: f100 31ff add.w r1, r0, #4294967295 ; 0xffffffff 8000474: d22e bcs.n 80004d4 <__udivmoddi4+0x2a0> 8000476: 45b8 cmp r8, r7 8000478: d92c bls.n 80004d4 <__udivmoddi4+0x2a0> 800047a: 3802 subs r0, #2 800047c: 4427 add r7, r4 800047e: ea40 4009 orr.w r0, r0, r9, lsl #16 8000482: eba7 0708 sub.w r7, r7, r8 8000486: fba0 8902 umull r8, r9, r0, r2 800048a: 454f cmp r7, r9 800048c: 46c6 mov lr, r8 800048e: 4649 mov r1, r9 8000490: d31a bcc.n 80004c8 <__udivmoddi4+0x294> 8000492: d017 beq.n 80004c4 <__udivmoddi4+0x290> 8000494: b15d cbz r5, 80004ae <__udivmoddi4+0x27a> 8000496: ebb3 020e subs.w r2, r3, lr 800049a: eb67 0701 sbc.w r7, r7, r1 800049e: fa07 fc0c lsl.w ip, r7, ip 80004a2: 40f2 lsrs r2, r6 80004a4: ea4c 0202 orr.w r2, ip, r2 80004a8: 40f7 lsrs r7, r6 80004aa: e9c5 2700 strd r2, r7, [r5] 80004ae: 2600 movs r6, #0 80004b0: 4631 mov r1, r6 80004b2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80004b6: 462e mov r6, r5 80004b8: 4628 mov r0, r5 80004ba: e70b b.n 80002d4 <__udivmoddi4+0xa0> 80004bc: 4606 mov r6, r0 80004be: e6e9 b.n 8000294 <__udivmoddi4+0x60> 80004c0: 4618 mov r0, r3 80004c2: e6fd b.n 80002c0 <__udivmoddi4+0x8c> 80004c4: 4543 cmp r3, r8 80004c6: d2e5 bcs.n 8000494 <__udivmoddi4+0x260> 80004c8: ebb8 0e02 subs.w lr, r8, r2 80004cc: eb69 0104 sbc.w r1, r9, r4 80004d0: 3801 subs r0, #1 80004d2: e7df b.n 8000494 <__udivmoddi4+0x260> 80004d4: 4608 mov r0, r1 80004d6: e7d2 b.n 800047e <__udivmoddi4+0x24a> 80004d8: 4660 mov r0, ip 80004da: e78d b.n 80003f8 <__udivmoddi4+0x1c4> 80004dc: 4681 mov r9, r0 80004de: e7b9 b.n 8000454 <__udivmoddi4+0x220> 80004e0: 4666 mov r6, ip 80004e2: e775 b.n 80003d0 <__udivmoddi4+0x19c> 80004e4: 4630 mov r0, r6 80004e6: e74a b.n 800037e <__udivmoddi4+0x14a> 80004e8: f1ac 0c02 sub.w ip, ip, #2 80004ec: 4439 add r1, r7 80004ee: e713 b.n 8000318 <__udivmoddi4+0xe4> 80004f0: 3802 subs r0, #2 80004f2: 443c add r4, r7 80004f4: e724 b.n 8000340 <__udivmoddi4+0x10c> 80004f6: bf00 nop 080004f8 <__aeabi_idiv0>: 80004f8: 4770 bx lr 80004fa: bf00 nop 080004fc
: /** * @brief The application entry point. * @retval int */ int main(void) { 80004fc: b580 push {r7, lr} 80004fe: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000500: f000 fe66 bl 80011d0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000504: f000 f818 bl 8000538 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000508: f000 fad2 bl 8000ab0 MX_ADC1_Init(); 800050c: f000 f882 bl 8000614 MX_ADC2_Init(); 8000510: f000 f8d2 bl 80006b8 MX_DAC_Init(); 8000514: f000 f922 bl 800075c MX_I2C1_SMBUS_Init(); 8000518: f000 f954 bl 80007c4 MX_RTC_Init(); 800051c: f000 f984 bl 8000828 MX_SPI1_Init(); 8000520: f000 f9dc bl 80008dc MX_SPI2_Init(); 8000524: f000 fa10 bl 8000948 MX_USART1_UART_Init(); 8000528: f000 fa98 bl 8000a5c MX_USB_DEVICE_Init(); 800052c: f007 ff6a bl 8008404 MX_TIM2_Init(); 8000530: f000 fa40 bl 80009b4 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000534: e7fe b.n 8000534 ... 08000538 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000538: b580 push {r7, lr} 800053a: b094 sub sp, #80 ; 0x50 800053c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800053e: f107 031c add.w r3, r7, #28 8000542: 2234 movs r2, #52 ; 0x34 8000544: 2100 movs r1, #0 8000546: 4618 mov r0, r3 8000548: f008 fcf6 bl 8008f38 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800054c: f107 0308 add.w r3, r7, #8 8000550: 2200 movs r2, #0 8000552: 601a str r2, [r3, #0] 8000554: 605a str r2, [r3, #4] 8000556: 609a str r2, [r3, #8] 8000558: 60da str r2, [r3, #12] 800055a: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 800055c: 2300 movs r3, #0 800055e: 607b str r3, [r7, #4] 8000560: 4b2a ldr r3, [pc, #168] ; (800060c ) 8000562: 6c1b ldr r3, [r3, #64] ; 0x40 8000564: 4a29 ldr r2, [pc, #164] ; (800060c ) 8000566: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800056a: 6413 str r3, [r2, #64] ; 0x40 800056c: 4b27 ldr r3, [pc, #156] ; (800060c ) 800056e: 6c1b ldr r3, [r3, #64] ; 0x40 8000570: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000574: 607b str r3, [r7, #4] 8000576: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8000578: 2300 movs r3, #0 800057a: 603b str r3, [r7, #0] 800057c: 4b24 ldr r3, [pc, #144] ; (8000610 ) 800057e: 681b ldr r3, [r3, #0] 8000580: 4a23 ldr r2, [pc, #140] ; (8000610 ) 8000582: f443 4340 orr.w r3, r3, #49152 ; 0xc000 8000586: 6013 str r3, [r2, #0] 8000588: 4b21 ldr r3, [pc, #132] ; (8000610 ) 800058a: 681b ldr r3, [r3, #0] 800058c: f403 4340 and.w r3, r3, #49152 ; 0xc000 8000590: 603b str r3, [r7, #0] 8000592: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; 8000594: 2305 movs r3, #5 8000596: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000598: f44f 3380 mov.w r3, #65536 ; 0x10000 800059c: 623b str r3, [r7, #32] RCC_OscInitStruct.LSEState = RCC_LSE_ON; 800059e: 2301 movs r3, #1 80005a0: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80005a2: 2302 movs r3, #2 80005a4: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80005a6: f44f 0380 mov.w r3, #4194304 ; 0x400000 80005aa: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLM = 4; 80005ac: 2304 movs r3, #4 80005ae: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLN = 160; 80005b0: 23a0 movs r3, #160 ; 0xa0 80005b2: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80005b4: 2302 movs r3, #2 80005b6: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLQ = 2; 80005b8: 2302 movs r3, #2 80005ba: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 80005bc: 2302 movs r3, #2 80005be: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80005c0: f107 031c add.w r3, r7, #28 80005c4: 4618 mov r0, r3 80005c6: f003 fbff bl 8003dc8 80005ca: 4603 mov r3, r0 80005cc: 2b00 cmp r3, #0 80005ce: d001 beq.n 80005d4 { Error_Handler(); 80005d0: f000 fb46 bl 8000c60 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80005d4: 230f movs r3, #15 80005d6: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80005d8: 2302 movs r3, #2 80005da: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80005dc: 2300 movs r3, #0 80005de: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 80005e0: f44f 53a0 mov.w r3, #5120 ; 0x1400 80005e4: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 80005e6: f44f 5380 mov.w r3, #4096 ; 0x1000 80005ea: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) 80005ec: f107 0308 add.w r3, r7, #8 80005f0: 2105 movs r1, #5 80005f2: 4618 mov r0, r3 80005f4: f002 fdf2 bl 80031dc 80005f8: 4603 mov r3, r0 80005fa: 2b00 cmp r3, #0 80005fc: d001 beq.n 8000602 { Error_Handler(); 80005fe: f000 fb2f bl 8000c60 } } 8000602: bf00 nop 8000604: 3750 adds r7, #80 ; 0x50 8000606: 46bd mov sp, r7 8000608: bd80 pop {r7, pc} 800060a: bf00 nop 800060c: 40023800 .word 0x40023800 8000610: 40007000 .word 0x40007000 08000614 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000614: b580 push {r7, lr} 8000616: b084 sub sp, #16 8000618: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800061a: 463b mov r3, r7 800061c: 2200 movs r2, #0 800061e: 601a str r2, [r3, #0] 8000620: 605a str r2, [r3, #4] 8000622: 609a str r2, [r3, #8] 8000624: 60da str r2, [r3, #12] /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc1.Instance = ADC1; 8000626: 4b21 ldr r3, [pc, #132] ; (80006ac ) 8000628: 4a21 ldr r2, [pc, #132] ; (80006b0 ) 800062a: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 800062c: 4b1f ldr r3, [pc, #124] ; (80006ac ) 800062e: f44f 3280 mov.w r2, #65536 ; 0x10000 8000632: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_12B; 8000634: 4b1d ldr r3, [pc, #116] ; (80006ac ) 8000636: 2200 movs r2, #0 8000638: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = DISABLE; 800063a: 4b1c ldr r3, [pc, #112] ; (80006ac ) 800063c: 2200 movs r2, #0 800063e: 611a str r2, [r3, #16] hadc1.Init.ContinuousConvMode = DISABLE; 8000640: 4b1a ldr r3, [pc, #104] ; (80006ac ) 8000642: 2200 movs r2, #0 8000644: 761a strb r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000646: 4b19 ldr r3, [pc, #100] ; (80006ac ) 8000648: 2200 movs r2, #0 800064a: f883 2020 strb.w r2, [r3, #32] hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 800064e: 4b17 ldr r3, [pc, #92] ; (80006ac ) 8000650: 2200 movs r2, #0 8000652: 62da str r2, [r3, #44] ; 0x2c hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000654: 4b15 ldr r3, [pc, #84] ; (80006ac ) 8000656: 4a17 ldr r2, [pc, #92] ; (80006b4 ) 8000658: 629a str r2, [r3, #40] ; 0x28 hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 800065a: 4b14 ldr r3, [pc, #80] ; (80006ac ) 800065c: 2200 movs r2, #0 800065e: 60da str r2, [r3, #12] hadc1.Init.NbrOfConversion = 1; 8000660: 4b12 ldr r3, [pc, #72] ; (80006ac ) 8000662: 2201 movs r2, #1 8000664: 61da str r2, [r3, #28] hadc1.Init.DMAContinuousRequests = DISABLE; 8000666: 4b11 ldr r3, [pc, #68] ; (80006ac ) 8000668: 2200 movs r2, #0 800066a: f883 2030 strb.w r2, [r3, #48] ; 0x30 hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 800066e: 4b0f ldr r3, [pc, #60] ; (80006ac ) 8000670: 2201 movs r2, #1 8000672: 615a str r2, [r3, #20] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000674: 480d ldr r0, [pc, #52] ; (80006ac ) 8000676: f000 fe41 bl 80012fc 800067a: 4603 mov r3, r0 800067c: 2b00 cmp r3, #0 800067e: d001 beq.n 8000684 { Error_Handler(); 8000680: f000 faee bl 8000c60 } /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000684: 2311 movs r3, #17 8000686: 603b str r3, [r7, #0] sConfig.Rank = 1; 8000688: 2301 movs r3, #1 800068a: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 800068c: 2300 movs r3, #0 800068e: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000690: 463b mov r3, r7 8000692: 4619 mov r1, r3 8000694: 4805 ldr r0, [pc, #20] ; (80006ac ) 8000696: f000 fe75 bl 8001384 800069a: 4603 mov r3, r0 800069c: 2b00 cmp r3, #0 800069e: d001 beq.n 80006a4 { Error_Handler(); 80006a0: f000 fade bl 8000c60 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80006a4: bf00 nop 80006a6: 3710 adds r7, #16 80006a8: 46bd mov sp, r7 80006aa: bd80 pop {r7, pc} 80006ac: 20000470 .word 0x20000470 80006b0: 40012000 .word 0x40012000 80006b4: 0f000001 .word 0x0f000001 080006b8 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 80006b8: b580 push {r7, lr} 80006ba: b084 sub sp, #16 80006bc: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80006be: 463b mov r3, r7 80006c0: 2200 movs r2, #0 80006c2: 601a str r2, [r3, #0] 80006c4: 605a str r2, [r3, #4] 80006c6: 609a str r2, [r3, #8] 80006c8: 60da str r2, [r3, #12] /* USER CODE BEGIN ADC2_Init 1 */ /* USER CODE END ADC2_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc2.Instance = ADC2; 80006ca: 4b21 ldr r3, [pc, #132] ; (8000750 ) 80006cc: 4a21 ldr r2, [pc, #132] ; (8000754 ) 80006ce: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; 80006d0: 4b1f ldr r3, [pc, #124] ; (8000750 ) 80006d2: f44f 3280 mov.w r2, #65536 ; 0x10000 80006d6: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_12B; 80006d8: 4b1d ldr r3, [pc, #116] ; (8000750 ) 80006da: 2200 movs r2, #0 80006dc: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = DISABLE; 80006de: 4b1c ldr r3, [pc, #112] ; (8000750 ) 80006e0: 2200 movs r2, #0 80006e2: 611a str r2, [r3, #16] hadc2.Init.ContinuousConvMode = DISABLE; 80006e4: 4b1a ldr r3, [pc, #104] ; (8000750 ) 80006e6: 2200 movs r2, #0 80006e8: 761a strb r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 80006ea: 4b19 ldr r3, [pc, #100] ; (8000750 ) 80006ec: 2200 movs r2, #0 80006ee: f883 2020 strb.w r2, [r3, #32] hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 80006f2: 4b17 ldr r3, [pc, #92] ; (8000750 ) 80006f4: 2200 movs r2, #0 80006f6: 62da str r2, [r3, #44] ; 0x2c hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; 80006f8: 4b15 ldr r3, [pc, #84] ; (8000750 ) 80006fa: 4a17 ldr r2, [pc, #92] ; (8000758 ) 80006fc: 629a str r2, [r3, #40] ; 0x28 hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80006fe: 4b14 ldr r3, [pc, #80] ; (8000750 ) 8000700: 2200 movs r2, #0 8000702: 60da str r2, [r3, #12] hadc2.Init.NbrOfConversion = 1; 8000704: 4b12 ldr r3, [pc, #72] ; (8000750 ) 8000706: 2201 movs r2, #1 8000708: 61da str r2, [r3, #28] hadc2.Init.DMAContinuousRequests = DISABLE; 800070a: 4b11 ldr r3, [pc, #68] ; (8000750 ) 800070c: 2200 movs r2, #0 800070e: f883 2030 strb.w r2, [r3, #48] ; 0x30 hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8000712: 4b0f ldr r3, [pc, #60] ; (8000750 ) 8000714: 2201 movs r2, #1 8000716: 615a str r2, [r3, #20] if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000718: 480d ldr r0, [pc, #52] ; (8000750 ) 800071a: f000 fdef bl 80012fc 800071e: 4603 mov r3, r0 8000720: 2b00 cmp r3, #0 8000722: d001 beq.n 8000728 { Error_Handler(); 8000724: f000 fa9c bl 8000c60 } /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. */ sConfig.Channel = ADC_CHANNEL_14; 8000728: 230e movs r3, #14 800072a: 603b str r3, [r7, #0] sConfig.Rank = 1; 800072c: 2301 movs r3, #1 800072e: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; 8000730: 2300 movs r3, #0 8000732: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000734: 463b mov r3, r7 8000736: 4619 mov r1, r3 8000738: 4805 ldr r0, [pc, #20] ; (8000750 ) 800073a: f000 fe23 bl 8001384 800073e: 4603 mov r3, r0 8000740: 2b00 cmp r3, #0 8000742: d001 beq.n 8000748 { Error_Handler(); 8000744: f000 fa8c bl 8000c60 } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } 8000748: bf00 nop 800074a: 3710 adds r7, #16 800074c: 46bd mov sp, r7 800074e: bd80 pop {r7, pc} 8000750: 20000428 .word 0x20000428 8000754: 40012100 .word 0x40012100 8000758: 0f000001 .word 0x0f000001 0800075c : * @brief DAC Initialization Function * @param None * @retval None */ static void MX_DAC_Init(void) { 800075c: b580 push {r7, lr} 800075e: b082 sub sp, #8 8000760: af00 add r7, sp, #0 /* USER CODE BEGIN DAC_Init 0 */ /* USER CODE END DAC_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000762: 463b mov r3, r7 8000764: 2200 movs r2, #0 8000766: 601a str r2, [r3, #0] 8000768: 605a str r2, [r3, #4] /* USER CODE BEGIN DAC_Init 1 */ /* USER CODE END DAC_Init 1 */ /** DAC Initialization */ hdac.Instance = DAC; 800076a: 4b14 ldr r3, [pc, #80] ; (80007bc ) 800076c: 4a14 ldr r2, [pc, #80] ; (80007c0 ) 800076e: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac) != HAL_OK) 8000770: 4812 ldr r0, [pc, #72] ; (80007bc ) 8000772: f001 f946 bl 8001a02 8000776: 4603 mov r3, r0 8000778: 2b00 cmp r3, #0 800077a: d001 beq.n 8000780 { Error_Handler(); 800077c: f000 fa70 bl 8000c60 } /** DAC channel OUT1 config */ sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8000780: 2300 movs r3, #0 8000782: 603b str r3, [r7, #0] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8000784: 2300 movs r3, #0 8000786: 607b str r3, [r7, #4] if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000788: 463b mov r3, r7 800078a: 2200 movs r2, #0 800078c: 4619 mov r1, r3 800078e: 480b ldr r0, [pc, #44] ; (80007bc ) 8000790: f001 f959 bl 8001a46 8000794: 4603 mov r3, r0 8000796: 2b00 cmp r3, #0 8000798: d001 beq.n 800079e { Error_Handler(); 800079a: f000 fa61 bl 8000c60 } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_2) != HAL_OK) 800079e: 463b mov r3, r7 80007a0: 2210 movs r2, #16 80007a2: 4619 mov r1, r3 80007a4: 4805 ldr r0, [pc, #20] ; (80007bc ) 80007a6: f001 f94e bl 8001a46 80007aa: 4603 mov r3, r0 80007ac: 2b00 cmp r3, #0 80007ae: d001 beq.n 80007b4 { Error_Handler(); 80007b0: f000 fa56 bl 8000c60 } /* USER CODE BEGIN DAC_Init 2 */ /* USER CODE END DAC_Init 2 */ } 80007b4: bf00 nop 80007b6: 3708 adds r7, #8 80007b8: 46bd mov sp, r7 80007ba: bd80 pop {r7, pc} 80007bc: 200004fc .word 0x200004fc 80007c0: 40007400 .word 0x40007400 080007c4 : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_SMBUS_Init(void) { 80007c4: b580 push {r7, lr} 80007c6: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hsmbus1.Instance = I2C1; 80007c8: 4b14 ldr r3, [pc, #80] ; (800081c ) 80007ca: 4a15 ldr r2, [pc, #84] ; (8000820 ) 80007cc: 601a str r2, [r3, #0] hsmbus1.Init.ClockSpeed = 100000; 80007ce: 4b13 ldr r3, [pc, #76] ; (800081c ) 80007d0: 4a14 ldr r2, [pc, #80] ; (8000824 ) 80007d2: 605a str r2, [r3, #4] hsmbus1.Init.OwnAddress1 = 0; 80007d4: 4b11 ldr r3, [pc, #68] ; (800081c ) 80007d6: 2200 movs r2, #0 80007d8: 60da str r2, [r3, #12] hsmbus1.Init.AddressingMode = SMBUS_ADDRESSINGMODE_7BIT; 80007da: 4b10 ldr r3, [pc, #64] ; (800081c ) 80007dc: f44f 4280 mov.w r2, #16384 ; 0x4000 80007e0: 611a str r2, [r3, #16] hsmbus1.Init.DualAddressMode = SMBUS_DUALADDRESS_DISABLE; 80007e2: 4b0e ldr r3, [pc, #56] ; (800081c ) 80007e4: 2200 movs r2, #0 80007e6: 615a str r2, [r3, #20] hsmbus1.Init.OwnAddress2 = 0; 80007e8: 4b0c ldr r3, [pc, #48] ; (800081c ) 80007ea: 2200 movs r2, #0 80007ec: 619a str r2, [r3, #24] hsmbus1.Init.GeneralCallMode = SMBUS_GENERALCALL_DISABLE; 80007ee: 4b0b ldr r3, [pc, #44] ; (800081c ) 80007f0: 2200 movs r2, #0 80007f2: 61da str r2, [r3, #28] hsmbus1.Init.NoStretchMode = SMBUS_NOSTRETCH_DISABLE; 80007f4: 4b09 ldr r3, [pc, #36] ; (800081c ) 80007f6: 2200 movs r2, #0 80007f8: 621a str r2, [r3, #32] hsmbus1.Init.PacketErrorCheckMode = SMBUS_PEC_DISABLE; 80007fa: 4b08 ldr r3, [pc, #32] ; (800081c ) 80007fc: 2200 movs r2, #0 80007fe: 625a str r2, [r3, #36] ; 0x24 hsmbus1.Init.PeripheralMode = SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE; 8000800: 4b06 ldr r3, [pc, #24] ; (800081c ) 8000802: 2202 movs r2, #2 8000804: 629a str r2, [r3, #40] ; 0x28 if (HAL_SMBUS_Init(&hsmbus1) != HAL_OK) 8000806: 4805 ldr r0, [pc, #20] ; (800081c ) 8000808: f003 ffe4 bl 80047d4 800080c: 4603 mov r3, r0 800080e: 2b00 cmp r3, #0 8000810: d001 beq.n 8000816 { Error_Handler(); 8000812: f000 fa25 bl 8000c60 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000816: bf00 nop 8000818: bd80 pop {r7, pc} 800081a: bf00 nop 800081c: 20000588 .word 0x20000588 8000820: 40005400 .word 0x40005400 8000824: 000186a0 .word 0x000186a0 08000828 : * @brief RTC Initialization Function * @param None * @retval None */ static void MX_RTC_Init(void) { 8000828: b580 push {r7, lr} 800082a: b086 sub sp, #24 800082c: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */ RTC_TimeTypeDef sTime = {0}; 800082e: 1d3b adds r3, r7, #4 8000830: 2200 movs r2, #0 8000832: 601a str r2, [r3, #0] 8000834: 605a str r2, [r3, #4] 8000836: 609a str r2, [r3, #8] 8000838: 60da str r2, [r3, #12] 800083a: 611a str r2, [r3, #16] RTC_DateTypeDef sDate = {0}; 800083c: 2300 movs r3, #0 800083e: 603b str r3, [r7, #0] /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 8000840: 4b24 ldr r3, [pc, #144] ; (80008d4 ) 8000842: 4a25 ldr r2, [pc, #148] ; (80008d8 ) 8000844: 601a str r2, [r3, #0] hrtc.Init.HourFormat = RTC_HOURFORMAT_24; 8000846: 4b23 ldr r3, [pc, #140] ; (80008d4 ) 8000848: 2200 movs r2, #0 800084a: 605a str r2, [r3, #4] hrtc.Init.AsynchPrediv = 127; 800084c: 4b21 ldr r3, [pc, #132] ; (80008d4 ) 800084e: 227f movs r2, #127 ; 0x7f 8000850: 609a str r2, [r3, #8] hrtc.Init.SynchPrediv = 255; 8000852: 4b20 ldr r3, [pc, #128] ; (80008d4 ) 8000854: 22ff movs r2, #255 ; 0xff 8000856: 60da str r2, [r3, #12] hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; 8000858: 4b1e ldr r3, [pc, #120] ; (80008d4 ) 800085a: 2200 movs r2, #0 800085c: 611a str r2, [r3, #16] hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; 800085e: 4b1d ldr r3, [pc, #116] ; (80008d4 ) 8000860: 2200 movs r2, #0 8000862: 615a str r2, [r3, #20] hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; 8000864: 4b1b ldr r3, [pc, #108] ; (80008d4 ) 8000866: 2200 movs r2, #0 8000868: 619a str r2, [r3, #24] if (HAL_RTC_Init(&hrtc) != HAL_OK) 800086a: 481a ldr r0, [pc, #104] ; (80008d4 ) 800086c: f003 fd4a bl 8004304 8000870: 4603 mov r3, r0 8000872: 2b00 cmp r3, #0 8000874: d001 beq.n 800087a { Error_Handler(); 8000876: f000 f9f3 bl 8000c60 /* USER CODE END Check_RTC_BKUP */ /** Initialize RTC and set the Time and Date */ sTime.Hours = 0x0; 800087a: 2300 movs r3, #0 800087c: 713b strb r3, [r7, #4] sTime.Minutes = 0x0; 800087e: 2300 movs r3, #0 8000880: 717b strb r3, [r7, #5] sTime.Seconds = 0x0; 8000882: 2300 movs r3, #0 8000884: 71bb strb r3, [r7, #6] sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; 8000886: 2300 movs r3, #0 8000888: 613b str r3, [r7, #16] sTime.StoreOperation = RTC_STOREOPERATION_RESET; 800088a: 2300 movs r3, #0 800088c: 617b str r3, [r7, #20] if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) 800088e: 1d3b adds r3, r7, #4 8000890: 2201 movs r2, #1 8000892: 4619 mov r1, r3 8000894: 480f ldr r0, [pc, #60] ; (80008d4 ) 8000896: f003 fdc6 bl 8004426 800089a: 4603 mov r3, r0 800089c: 2b00 cmp r3, #0 800089e: d001 beq.n 80008a4 { Error_Handler(); 80008a0: f000 f9de bl 8000c60 } sDate.WeekDay = RTC_WEEKDAY_MONDAY; 80008a4: 2301 movs r3, #1 80008a6: 703b strb r3, [r7, #0] sDate.Month = RTC_MONTH_JANUARY; 80008a8: 2301 movs r3, #1 80008aa: 707b strb r3, [r7, #1] sDate.Date = 0x1; 80008ac: 2301 movs r3, #1 80008ae: 70bb strb r3, [r7, #2] sDate.Year = 0x0; 80008b0: 2300 movs r3, #0 80008b2: 70fb strb r3, [r7, #3] if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK) 80008b4: 463b mov r3, r7 80008b6: 2201 movs r2, #1 80008b8: 4619 mov r1, r3 80008ba: 4806 ldr r0, [pc, #24] ; (80008d4 ) 80008bc: f003 fe70 bl 80045a0 80008c0: 4603 mov r3, r0 80008c2: 2b00 cmp r3, #0 80008c4: d001 beq.n 80008ca { Error_Handler(); 80008c6: f000 f9cb bl 8000c60 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 80008ca: bf00 nop 80008cc: 3718 adds r7, #24 80008ce: 46bd mov sp, r7 80008d0: bd80 pop {r7, pc} 80008d2: bf00 nop 80008d4: 20000510 .word 0x20000510 80008d8: 40002800 .word 0x40002800 080008dc : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 80008dc: b580 push {r7, lr} 80008de: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 80008e0: 4b17 ldr r3, [pc, #92] ; (8000940 ) 80008e2: 4a18 ldr r2, [pc, #96] ; (8000944 ) 80008e4: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 80008e6: 4b16 ldr r3, [pc, #88] ; (8000940 ) 80008e8: f44f 7282 mov.w r2, #260 ; 0x104 80008ec: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 80008ee: 4b14 ldr r3, [pc, #80] ; (8000940 ) 80008f0: 2200 movs r2, #0 80008f2: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 80008f4: 4b12 ldr r3, [pc, #72] ; (8000940 ) 80008f6: 2200 movs r2, #0 80008f8: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 80008fa: 4b11 ldr r3, [pc, #68] ; (8000940 ) 80008fc: 2200 movs r2, #0 80008fe: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 8000900: 4b0f ldr r3, [pc, #60] ; (8000940 ) 8000902: 2200 movs r2, #0 8000904: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; 8000906: 4b0e ldr r3, [pc, #56] ; (8000940 ) 8000908: f44f 7200 mov.w r2, #512 ; 0x200 800090c: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 800090e: 4b0c ldr r3, [pc, #48] ; (8000940 ) 8000910: 2200 movs r2, #0 8000912: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 8000914: 4b0a ldr r3, [pc, #40] ; (8000940 ) 8000916: 2200 movs r2, #0 8000918: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 800091a: 4b09 ldr r3, [pc, #36] ; (8000940 ) 800091c: 2200 movs r2, #0 800091e: 625a str r2, [r3, #36] ; 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8000920: 4b07 ldr r3, [pc, #28] ; (8000940 ) 8000922: 2200 movs r2, #0 8000924: 629a str r2, [r3, #40] ; 0x28 hspi1.Init.CRCPolynomial = 10; 8000926: 4b06 ldr r3, [pc, #24] ; (8000940 ) 8000928: 220a movs r2, #10 800092a: 62da str r2, [r3, #44] ; 0x2c if (HAL_SPI_Init(&hspi1) != HAL_OK) 800092c: 4804 ldr r0, [pc, #16] ; (8000940 ) 800092e: f004 f80f bl 8004950 8000932: 4603 mov r3, r0 8000934: 2b00 cmp r3, #0 8000936: d001 beq.n 800093c { Error_Handler(); 8000938: f000 f992 bl 8000c60 } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 800093c: bf00 nop 800093e: bd80 pop {r7, pc} 8000940: 20000530 .word 0x20000530 8000944: 40013000 .word 0x40013000 08000948 : * @brief SPI2 Initialization Function * @param None * @retval None */ static void MX_SPI2_Init(void) { 8000948: b580 push {r7, lr} 800094a: af00 add r7, sp, #0 /* USER CODE BEGIN SPI2_Init 1 */ /* USER CODE END SPI2_Init 1 */ /* SPI2 parameter configuration*/ hspi2.Instance = SPI2; 800094c: 4b17 ldr r3, [pc, #92] ; (80009ac ) 800094e: 4a18 ldr r2, [pc, #96] ; (80009b0 ) 8000950: 601a str r2, [r3, #0] hspi2.Init.Mode = SPI_MODE_MASTER; 8000952: 4b16 ldr r3, [pc, #88] ; (80009ac ) 8000954: f44f 7282 mov.w r2, #260 ; 0x104 8000958: 605a str r2, [r3, #4] hspi2.Init.Direction = SPI_DIRECTION_2LINES; 800095a: 4b14 ldr r3, [pc, #80] ; (80009ac ) 800095c: 2200 movs r2, #0 800095e: 609a str r2, [r3, #8] hspi2.Init.DataSize = SPI_DATASIZE_8BIT; 8000960: 4b12 ldr r3, [pc, #72] ; (80009ac ) 8000962: 2200 movs r2, #0 8000964: 60da str r2, [r3, #12] hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 8000966: 4b11 ldr r3, [pc, #68] ; (80009ac ) 8000968: 2200 movs r2, #0 800096a: 611a str r2, [r3, #16] hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 800096c: 4b0f ldr r3, [pc, #60] ; (80009ac ) 800096e: 2200 movs r2, #0 8000970: 615a str r2, [r3, #20] hspi2.Init.NSS = SPI_NSS_SOFT; 8000972: 4b0e ldr r3, [pc, #56] ; (80009ac ) 8000974: f44f 7200 mov.w r2, #512 ; 0x200 8000978: 619a str r2, [r3, #24] hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 800097a: 4b0c ldr r3, [pc, #48] ; (80009ac ) 800097c: 2200 movs r2, #0 800097e: 61da str r2, [r3, #28] hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 8000980: 4b0a ldr r3, [pc, #40] ; (80009ac ) 8000982: 2200 movs r2, #0 8000984: 621a str r2, [r3, #32] hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 8000986: 4b09 ldr r3, [pc, #36] ; (80009ac ) 8000988: 2200 movs r2, #0 800098a: 625a str r2, [r3, #36] ; 0x24 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 800098c: 4b07 ldr r3, [pc, #28] ; (80009ac ) 800098e: 2200 movs r2, #0 8000990: 629a str r2, [r3, #40] ; 0x28 hspi2.Init.CRCPolynomial = 10; 8000992: 4b06 ldr r3, [pc, #24] ; (80009ac ) 8000994: 220a movs r2, #10 8000996: 62da str r2, [r3, #44] ; 0x2c if (HAL_SPI_Init(&hspi2) != HAL_OK) 8000998: 4804 ldr r0, [pc, #16] ; (80009ac ) 800099a: f003 ffd9 bl 8004950 800099e: 4603 mov r3, r0 80009a0: 2b00 cmp r3, #0 80009a2: d001 beq.n 80009a8 { Error_Handler(); 80009a4: f000 f95c bl 8000c60 } /* USER CODE BEGIN SPI2_Init 2 */ /* USER CODE END SPI2_Init 2 */ } 80009a8: bf00 nop 80009aa: bd80 pop {r7, pc} 80009ac: 200003d0 .word 0x200003d0 80009b0: 40003800 .word 0x40003800 080009b4 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80009b4: b580 push {r7, lr} 80009b6: b088 sub sp, #32 80009b8: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_SlaveConfigTypeDef sSlaveConfig = {0}; 80009ba: f107 030c add.w r3, r7, #12 80009be: 2200 movs r2, #0 80009c0: 601a str r2, [r3, #0] 80009c2: 605a str r2, [r3, #4] 80009c4: 609a str r2, [r3, #8] 80009c6: 60da str r2, [r3, #12] 80009c8: 611a str r2, [r3, #16] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80009ca: 1d3b adds r3, r7, #4 80009cc: 2200 movs r2, #0 80009ce: 601a str r2, [r3, #0] 80009d0: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80009d2: 4b21 ldr r3, [pc, #132] ; (8000a58 ) 80009d4: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 80009d8: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 80009da: 4b1f ldr r3, [pc, #124] ; (8000a58 ) 80009dc: 2200 movs r2, #0 80009de: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80009e0: 4b1d ldr r3, [pc, #116] ; (8000a58 ) 80009e2: 2200 movs r2, #0 80009e4: 609a str r2, [r3, #8] htim2.Init.Period = 4294967295; 80009e6: 4b1c ldr r3, [pc, #112] ; (8000a58 ) 80009e8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80009ec: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80009ee: 4b1a ldr r3, [pc, #104] ; (8000a58 ) 80009f0: 2200 movs r2, #0 80009f2: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80009f4: 4b18 ldr r3, [pc, #96] ; (8000a58 ) 80009f6: 2200 movs r2, #0 80009f8: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 80009fa: 4817 ldr r0, [pc, #92] ; (8000a58 ) 80009fc: f004 f831 bl 8004a62 8000a00: 4603 mov r3, r0 8000a02: 2b00 cmp r3, #0 8000a04: d001 beq.n 8000a0a { Error_Handler(); 8000a06: f000 f92b bl 8000c60 } sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1; 8000a0a: 2307 movs r3, #7 8000a0c: 60fb str r3, [r7, #12] sSlaveConfig.InputTrigger = TIM_TS_ETRF; 8000a0e: 2370 movs r3, #112 ; 0x70 8000a10: 613b str r3, [r7, #16] sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED; 8000a12: 2300 movs r3, #0 8000a14: 617b str r3, [r7, #20] sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1; 8000a16: 2300 movs r3, #0 8000a18: 61bb str r3, [r7, #24] sSlaveConfig.TriggerFilter = 0; 8000a1a: 2300 movs r3, #0 8000a1c: 61fb str r3, [r7, #28] if (HAL_TIM_SlaveConfigSynchro(&htim2, &sSlaveConfig) != HAL_OK) 8000a1e: f107 030c add.w r3, r7, #12 8000a22: 4619 mov r1, r3 8000a24: 480c ldr r0, [pc, #48] ; (8000a58 ) 8000a26: f004 f86b bl 8004b00 8000a2a: 4603 mov r3, r0 8000a2c: 2b00 cmp r3, #0 8000a2e: d001 beq.n 8000a34 { Error_Handler(); 8000a30: f000 f916 bl 8000c60 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000a34: 2300 movs r3, #0 8000a36: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000a38: 2300 movs r3, #0 8000a3a: 60bb str r3, [r7, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8000a3c: 1d3b adds r3, r7, #4 8000a3e: 4619 mov r1, r3 8000a40: 4805 ldr r0, [pc, #20] ; (8000a58 ) 8000a42: f004 fa4f bl 8004ee4 8000a46: 4603 mov r3, r0 8000a48: 2b00 cmp r3, #0 8000a4a: d001 beq.n 8000a50 { Error_Handler(); 8000a4c: f000 f908 bl 8000c60 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 8000a50: bf00 nop 8000a52: 3720 adds r7, #32 8000a54: 46bd mov sp, r7 8000a56: bd80 pop {r7, pc} 8000a58: 200005d8 .word 0x200005d8 08000a5c : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8000a5c: b580 push {r7, lr} 8000a5e: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8000a60: 4b11 ldr r3, [pc, #68] ; (8000aa8 ) 8000a62: 4a12 ldr r2, [pc, #72] ; (8000aac ) 8000a64: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8000a66: 4b10 ldr r3, [pc, #64] ; (8000aa8 ) 8000a68: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000a6c: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8000a6e: 4b0e ldr r3, [pc, #56] ; (8000aa8 ) 8000a70: 2200 movs r2, #0 8000a72: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8000a74: 4b0c ldr r3, [pc, #48] ; (8000aa8 ) 8000a76: 2200 movs r2, #0 8000a78: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8000a7a: 4b0b ldr r3, [pc, #44] ; (8000aa8 ) 8000a7c: 2200 movs r2, #0 8000a7e: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8000a80: 4b09 ldr r3, [pc, #36] ; (8000aa8 ) 8000a82: 220c movs r2, #12 8000a84: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000a86: 4b08 ldr r3, [pc, #32] ; (8000aa8 ) 8000a88: 2200 movs r2, #0 8000a8a: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8000a8c: 4b06 ldr r3, [pc, #24] ; (8000aa8 ) 8000a8e: 2200 movs r2, #0 8000a90: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8000a92: 4805 ldr r0, [pc, #20] ; (8000aa8 ) 8000a94: f004 faa2 bl 8004fdc 8000a98: 4603 mov r3, r0 8000a9a: 2b00 cmp r3, #0 8000a9c: d001 beq.n 8000aa2 { Error_Handler(); 8000a9e: f000 f8df bl 8000c60 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8000aa2: bf00 nop 8000aa4: bd80 pop {r7, pc} 8000aa6: bf00 nop 8000aa8: 200004b8 .word 0x200004b8 8000aac: 40011000 .word 0x40011000 08000ab0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000ab0: b580 push {r7, lr} 8000ab2: b08a sub sp, #40 ; 0x28 8000ab4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000ab6: f107 0314 add.w r3, r7, #20 8000aba: 2200 movs r2, #0 8000abc: 601a str r2, [r3, #0] 8000abe: 605a str r2, [r3, #4] 8000ac0: 609a str r2, [r3, #8] 8000ac2: 60da str r2, [r3, #12] 8000ac4: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000ac6: 2300 movs r3, #0 8000ac8: 613b str r3, [r7, #16] 8000aca: 4b60 ldr r3, [pc, #384] ; (8000c4c ) 8000acc: 6b1b ldr r3, [r3, #48] ; 0x30 8000ace: 4a5f ldr r2, [pc, #380] ; (8000c4c ) 8000ad0: f043 0304 orr.w r3, r3, #4 8000ad4: 6313 str r3, [r2, #48] ; 0x30 8000ad6: 4b5d ldr r3, [pc, #372] ; (8000c4c ) 8000ad8: 6b1b ldr r3, [r3, #48] ; 0x30 8000ada: f003 0304 and.w r3, r3, #4 8000ade: 613b str r3, [r7, #16] 8000ae0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000ae2: 2300 movs r3, #0 8000ae4: 60fb str r3, [r7, #12] 8000ae6: 4b59 ldr r3, [pc, #356] ; (8000c4c ) 8000ae8: 6b1b ldr r3, [r3, #48] ; 0x30 8000aea: 4a58 ldr r2, [pc, #352] ; (8000c4c ) 8000aec: f043 0380 orr.w r3, r3, #128 ; 0x80 8000af0: 6313 str r3, [r2, #48] ; 0x30 8000af2: 4b56 ldr r3, [pc, #344] ; (8000c4c ) 8000af4: 6b1b ldr r3, [r3, #48] ; 0x30 8000af6: f003 0380 and.w r3, r3, #128 ; 0x80 8000afa: 60fb str r3, [r7, #12] 8000afc: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000afe: 2300 movs r3, #0 8000b00: 60bb str r3, [r7, #8] 8000b02: 4b52 ldr r3, [pc, #328] ; (8000c4c ) 8000b04: 6b1b ldr r3, [r3, #48] ; 0x30 8000b06: 4a51 ldr r2, [pc, #324] ; (8000c4c ) 8000b08: f043 0301 orr.w r3, r3, #1 8000b0c: 6313 str r3, [r2, #48] ; 0x30 8000b0e: 4b4f ldr r3, [pc, #316] ; (8000c4c ) 8000b10: 6b1b ldr r3, [r3, #48] ; 0x30 8000b12: f003 0301 and.w r3, r3, #1 8000b16: 60bb str r3, [r7, #8] 8000b18: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000b1a: 2300 movs r3, #0 8000b1c: 607b str r3, [r7, #4] 8000b1e: 4b4b ldr r3, [pc, #300] ; (8000c4c ) 8000b20: 6b1b ldr r3, [r3, #48] ; 0x30 8000b22: 4a4a ldr r2, [pc, #296] ; (8000c4c ) 8000b24: f043 0302 orr.w r3, r3, #2 8000b28: 6313 str r3, [r2, #48] ; 0x30 8000b2a: 4b48 ldr r3, [pc, #288] ; (8000c4c ) 8000b2c: 6b1b ldr r3, [r3, #48] ; 0x30 8000b2e: f003 0302 and.w r3, r3, #2 8000b32: 607b str r3, [r7, #4] 8000b34: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000b36: 2300 movs r3, #0 8000b38: 603b str r3, [r7, #0] 8000b3a: 4b44 ldr r3, [pc, #272] ; (8000c4c ) 8000b3c: 6b1b ldr r3, [r3, #48] ; 0x30 8000b3e: 4a43 ldr r2, [pc, #268] ; (8000c4c ) 8000b40: f043 0308 orr.w r3, r3, #8 8000b44: 6313 str r3, [r2, #48] ; 0x30 8000b46: 4b41 ldr r3, [pc, #260] ; (8000c4c ) 8000b48: 6b1b ldr r3, [r3, #48] ; 0x30 8000b4a: f003 0308 and.w r3, r3, #8 8000b4e: 603b str r3, [r7, #0] 8000b50: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_3 8000b52: 2200 movs r2, #0 8000b54: f643 410b movw r1, #15371 ; 0x3c0b 8000b58: 483d ldr r0, [pc, #244] ; (8000c50 ) 8000b5a: f001 f957 bl 8001e0c |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10|GPIO_PIN_12 8000b5e: 2200 movs r2, #0 8000b60: f241 41c6 movw r1, #5318 ; 0x14c6 8000b64: 483b ldr r0, [pc, #236] ; (8000c54 ) 8000b66: f001 f951 bl 8001e0c |GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET); 8000b6a: 2200 movs r2, #0 8000b6c: f44f 4100 mov.w r1, #32768 ; 0x8000 8000b70: 4839 ldr r0, [pc, #228] ; (8000c58 ) 8000b72: f001 f94b bl 8001e0c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_RESET); 8000b76: 2200 movs r2, #0 8000b78: 2104 movs r1, #4 8000b7a: 4838 ldr r0, [pc, #224] ; (8000c5c ) 8000b7c: f001 f946 bl 8001e0c /*Configure GPIO pins : PC13 PC0 PC1 PC3 PC10 PC11 PC12 */ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_3 8000b80: f643 430b movw r3, #15371 ; 0x3c0b 8000b84: 617b str r3, [r7, #20] |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000b86: 2301 movs r3, #1 8000b88: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b8a: 2300 movs r3, #0 8000b8c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000b8e: 2300 movs r3, #0 8000b90: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000b92: f107 0314 add.w r3, r7, #20 8000b96: 4619 mov r1, r3 8000b98: 482d ldr r0, [pc, #180] ; (8000c50 ) 8000b9a: f000 ffa3 bl 8001ae4 /*Configure GPIO pins : PC2 PC6 PC7 PC8 PC9 */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8 8000b9e: f44f 7371 mov.w r3, #964 ; 0x3c4 8000ba2: 617b str r3, [r7, #20] |GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000ba4: 2300 movs r3, #0 8000ba6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000ba8: 2300 movs r3, #0 8000baa: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000bac: f107 0314 add.w r3, r7, #20 8000bb0: 4619 mov r1, r3 8000bb2: 4827 ldr r0, [pc, #156] ; (8000c50 ) 8000bb4: f000 ff96 bl 8001ae4 /*Configure GPIO pin : PA1 */ GPIO_InitStruct.Pin = GPIO_PIN_1; 8000bb8: 2302 movs r3, #2 8000bba: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000bbc: f44f 1388 mov.w r3, #1114112 ; 0x110000 8000bc0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bc2: 2300 movs r3, #0 8000bc4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000bc6: f107 0314 add.w r3, r7, #20 8000bca: 4619 mov r1, r3 8000bcc: 4822 ldr r0, [pc, #136] ; (8000c58 ) 8000bce: f000 ff89 bl 8001ae4 /*Configure GPIO pins : PB1 PB2 PB10 PB12 PB6 PB7 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10|GPIO_PIN_12 8000bd2: f241 43c6 movw r3, #5318 ; 0x14c6 8000bd6: 617b str r3, [r7, #20] |GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000bd8: 2301 movs r3, #1 8000bda: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bdc: 2300 movs r3, #0 8000bde: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000be0: 2300 movs r3, #0 8000be2: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000be4: f107 0314 add.w r3, r7, #20 8000be8: 4619 mov r1, r3 8000bea: 481a ldr r0, [pc, #104] ; (8000c54 ) 8000bec: f000 ff7a bl 8001ae4 /*Configure GPIO pin : PA8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000bf0: f44f 7380 mov.w r3, #256 ; 0x100 8000bf4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000bf6: 2300 movs r3, #0 8000bf8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bfa: 2300 movs r3, #0 8000bfc: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000bfe: f107 0314 add.w r3, r7, #20 8000c02: 4619 mov r1, r3 8000c04: 4814 ldr r0, [pc, #80] ; (8000c58 ) 8000c06: f000 ff6d bl 8001ae4 /*Configure GPIO pin : PA15 */ GPIO_InitStruct.Pin = GPIO_PIN_15; 8000c0a: f44f 4300 mov.w r3, #32768 ; 0x8000 8000c0e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c10: 2301 movs r3, #1 8000c12: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c14: 2300 movs r3, #0 8000c16: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c18: 2300 movs r3, #0 8000c1a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000c1c: f107 0314 add.w r3, r7, #20 8000c20: 4619 mov r1, r3 8000c22: 480d ldr r0, [pc, #52] ; (8000c58 ) 8000c24: f000 ff5e bl 8001ae4 /*Configure GPIO pin : PD2 */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8000c28: 2304 movs r3, #4 8000c2a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c2c: 2301 movs r3, #1 8000c2e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c30: 2300 movs r3, #0 8000c32: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c34: 2300 movs r3, #0 8000c36: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000c38: f107 0314 add.w r3, r7, #20 8000c3c: 4619 mov r1, r3 8000c3e: 4807 ldr r0, [pc, #28] ; (8000c5c ) 8000c40: f000 ff50 bl 8001ae4 } 8000c44: bf00 nop 8000c46: 3728 adds r7, #40 ; 0x28 8000c48: 46bd mov sp, r7 8000c4a: bd80 pop {r7, pc} 8000c4c: 40023800 .word 0x40023800 8000c50: 40020800 .word 0x40020800 8000c54: 40020400 .word 0x40020400 8000c58: 40020000 .word 0x40020000 8000c5c: 40020c00 .word 0x40020c00 08000c60 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000c60: b480 push {r7} 8000c62: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000c64: b672 cpsid i } 8000c66: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000c68: e7fe b.n 8000c68 ... 08000c6c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000c6c: b480 push {r7} 8000c6e: b083 sub sp, #12 8000c70: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000c72: 2300 movs r3, #0 8000c74: 607b str r3, [r7, #4] 8000c76: 4b10 ldr r3, [pc, #64] ; (8000cb8 ) 8000c78: 6c5b ldr r3, [r3, #68] ; 0x44 8000c7a: 4a0f ldr r2, [pc, #60] ; (8000cb8 ) 8000c7c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8000c80: 6453 str r3, [r2, #68] ; 0x44 8000c82: 4b0d ldr r3, [pc, #52] ; (8000cb8 ) 8000c84: 6c5b ldr r3, [r3, #68] ; 0x44 8000c86: f403 4380 and.w r3, r3, #16384 ; 0x4000 8000c8a: 607b str r3, [r7, #4] 8000c8c: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000c8e: 2300 movs r3, #0 8000c90: 603b str r3, [r7, #0] 8000c92: 4b09 ldr r3, [pc, #36] ; (8000cb8 ) 8000c94: 6c1b ldr r3, [r3, #64] ; 0x40 8000c96: 4a08 ldr r2, [pc, #32] ; (8000cb8 ) 8000c98: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000c9c: 6413 str r3, [r2, #64] ; 0x40 8000c9e: 4b06 ldr r3, [pc, #24] ; (8000cb8 ) 8000ca0: 6c1b ldr r3, [r3, #64] ; 0x40 8000ca2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000ca6: 603b str r3, [r7, #0] 8000ca8: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000caa: bf00 nop 8000cac: 370c adds r7, #12 8000cae: 46bd mov sp, r7 8000cb0: f85d 7b04 ldr.w r7, [sp], #4 8000cb4: 4770 bx lr 8000cb6: bf00 nop 8000cb8: 40023800 .word 0x40023800 08000cbc : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8000cbc: b580 push {r7, lr} 8000cbe: b08a sub sp, #40 ; 0x28 8000cc0: af00 add r7, sp, #0 8000cc2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000cc4: f107 0314 add.w r3, r7, #20 8000cc8: 2200 movs r2, #0 8000cca: 601a str r2, [r3, #0] 8000ccc: 605a str r2, [r3, #4] 8000cce: 609a str r2, [r3, #8] 8000cd0: 60da str r2, [r3, #12] 8000cd2: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8000cd4: 687b ldr r3, [r7, #4] 8000cd6: 681b ldr r3, [r3, #0] 8000cd8: 4a21 ldr r2, [pc, #132] ; (8000d60 ) 8000cda: 4293 cmp r3, r2 8000cdc: d10e bne.n 8000cfc { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8000cde: 2300 movs r3, #0 8000ce0: 613b str r3, [r7, #16] 8000ce2: 4b20 ldr r3, [pc, #128] ; (8000d64 ) 8000ce4: 6c5b ldr r3, [r3, #68] ; 0x44 8000ce6: 4a1f ldr r2, [pc, #124] ; (8000d64 ) 8000ce8: f443 7380 orr.w r3, r3, #256 ; 0x100 8000cec: 6453 str r3, [r2, #68] ; 0x44 8000cee: 4b1d ldr r3, [pc, #116] ; (8000d64 ) 8000cf0: 6c5b ldr r3, [r3, #68] ; 0x44 8000cf2: f403 7380 and.w r3, r3, #256 ; 0x100 8000cf6: 613b str r3, [r7, #16] 8000cf8: 693b ldr r3, [r7, #16] /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8000cfa: e02c b.n 8000d56 else if(hadc->Instance==ADC2) 8000cfc: 687b ldr r3, [r7, #4] 8000cfe: 681b ldr r3, [r3, #0] 8000d00: 4a19 ldr r2, [pc, #100] ; (8000d68 ) 8000d02: 4293 cmp r3, r2 8000d04: d127 bne.n 8000d56 __HAL_RCC_ADC2_CLK_ENABLE(); 8000d06: 2300 movs r3, #0 8000d08: 60fb str r3, [r7, #12] 8000d0a: 4b16 ldr r3, [pc, #88] ; (8000d64 ) 8000d0c: 6c5b ldr r3, [r3, #68] ; 0x44 8000d0e: 4a15 ldr r2, [pc, #84] ; (8000d64 ) 8000d10: f443 7300 orr.w r3, r3, #512 ; 0x200 8000d14: 6453 str r3, [r2, #68] ; 0x44 8000d16: 4b13 ldr r3, [pc, #76] ; (8000d64 ) 8000d18: 6c5b ldr r3, [r3, #68] ; 0x44 8000d1a: f403 7300 and.w r3, r3, #512 ; 0x200 8000d1e: 60fb str r3, [r7, #12] 8000d20: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000d22: 2300 movs r3, #0 8000d24: 60bb str r3, [r7, #8] 8000d26: 4b0f ldr r3, [pc, #60] ; (8000d64 ) 8000d28: 6b1b ldr r3, [r3, #48] ; 0x30 8000d2a: 4a0e ldr r2, [pc, #56] ; (8000d64 ) 8000d2c: f043 0304 orr.w r3, r3, #4 8000d30: 6313 str r3, [r2, #48] ; 0x30 8000d32: 4b0c ldr r3, [pc, #48] ; (8000d64 ) 8000d34: 6b1b ldr r3, [r3, #48] ; 0x30 8000d36: f003 0304 and.w r3, r3, #4 8000d3a: 60bb str r3, [r7, #8] 8000d3c: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_4; 8000d3e: 2310 movs r3, #16 8000d40: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000d42: 2303 movs r3, #3 8000d44: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d46: 2300 movs r3, #0 8000d48: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000d4a: f107 0314 add.w r3, r7, #20 8000d4e: 4619 mov r1, r3 8000d50: 4806 ldr r0, [pc, #24] ; (8000d6c ) 8000d52: f000 fec7 bl 8001ae4 } 8000d56: bf00 nop 8000d58: 3728 adds r7, #40 ; 0x28 8000d5a: 46bd mov sp, r7 8000d5c: bd80 pop {r7, pc} 8000d5e: bf00 nop 8000d60: 40012000 .word 0x40012000 8000d64: 40023800 .word 0x40023800 8000d68: 40012100 .word 0x40012100 8000d6c: 40020800 .word 0x40020800 08000d70 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 8000d70: b580 push {r7, lr} 8000d72: b08a sub sp, #40 ; 0x28 8000d74: af00 add r7, sp, #0 8000d76: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000d78: f107 0314 add.w r3, r7, #20 8000d7c: 2200 movs r2, #0 8000d7e: 601a str r2, [r3, #0] 8000d80: 605a str r2, [r3, #4] 8000d82: 609a str r2, [r3, #8] 8000d84: 60da str r2, [r3, #12] 8000d86: 611a str r2, [r3, #16] if(hdac->Instance==DAC) 8000d88: 687b ldr r3, [r7, #4] 8000d8a: 681b ldr r3, [r3, #0] 8000d8c: 4a17 ldr r2, [pc, #92] ; (8000dec ) 8000d8e: 4293 cmp r3, r2 8000d90: d127 bne.n 8000de2 { /* USER CODE BEGIN DAC_MspInit 0 */ /* USER CODE END DAC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC_CLK_ENABLE(); 8000d92: 2300 movs r3, #0 8000d94: 613b str r3, [r7, #16] 8000d96: 4b16 ldr r3, [pc, #88] ; (8000df0 ) 8000d98: 6c1b ldr r3, [r3, #64] ; 0x40 8000d9a: 4a15 ldr r2, [pc, #84] ; (8000df0 ) 8000d9c: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8000da0: 6413 str r3, [r2, #64] ; 0x40 8000da2: 4b13 ldr r3, [pc, #76] ; (8000df0 ) 8000da4: 6c1b ldr r3, [r3, #64] ; 0x40 8000da6: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8000daa: 613b str r3, [r7, #16] 8000dac: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000dae: 2300 movs r3, #0 8000db0: 60fb str r3, [r7, #12] 8000db2: 4b0f ldr r3, [pc, #60] ; (8000df0 ) 8000db4: 6b1b ldr r3, [r3, #48] ; 0x30 8000db6: 4a0e ldr r2, [pc, #56] ; (8000df0 ) 8000db8: f043 0301 orr.w r3, r3, #1 8000dbc: 6313 str r3, [r2, #48] ; 0x30 8000dbe: 4b0c ldr r3, [pc, #48] ; (8000df0 ) 8000dc0: 6b1b ldr r3, [r3, #48] ; 0x30 8000dc2: f003 0301 and.w r3, r3, #1 8000dc6: 60fb str r3, [r7, #12] 8000dc8: 68fb ldr r3, [r7, #12] /**DAC GPIO Configuration PA4 ------> DAC_OUT1 PA5 ------> DAC_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8000dca: 2330 movs r3, #48 ; 0x30 8000dcc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000dce: 2303 movs r3, #3 8000dd0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000dd2: 2300 movs r3, #0 8000dd4: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000dd6: f107 0314 add.w r3, r7, #20 8000dda: 4619 mov r1, r3 8000ddc: 4805 ldr r0, [pc, #20] ; (8000df4 ) 8000dde: f000 fe81 bl 8001ae4 /* USER CODE BEGIN DAC_MspInit 1 */ /* USER CODE END DAC_MspInit 1 */ } } 8000de2: bf00 nop 8000de4: 3728 adds r7, #40 ; 0x28 8000de6: 46bd mov sp, r7 8000de8: bd80 pop {r7, pc} 8000dea: bf00 nop 8000dec: 40007400 .word 0x40007400 8000df0: 40023800 .word 0x40023800 8000df4: 40020000 .word 0x40020000 08000df8 : * This function configures the hardware resources used in this example * @param hsmbus: SMBUS handle pointer * @retval None */ void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef* hsmbus) { 8000df8: b580 push {r7, lr} 8000dfa: b08a sub sp, #40 ; 0x28 8000dfc: af00 add r7, sp, #0 8000dfe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e00: f107 0314 add.w r3, r7, #20 8000e04: 2200 movs r2, #0 8000e06: 601a str r2, [r3, #0] 8000e08: 605a str r2, [r3, #4] 8000e0a: 609a str r2, [r3, #8] 8000e0c: 60da str r2, [r3, #12] 8000e0e: 611a str r2, [r3, #16] if(hsmbus->Instance==I2C1) 8000e10: 687b ldr r3, [r7, #4] 8000e12: 681b ldr r3, [r3, #0] 8000e14: 4a19 ldr r2, [pc, #100] ; (8000e7c ) 8000e16: 4293 cmp r3, r2 8000e18: d12c bne.n 8000e74 { /* USER CODE BEGIN I2C1_MspInit 0 */ /* USER CODE END I2C1_MspInit 0 */ __HAL_RCC_GPIOB_CLK_ENABLE(); 8000e1a: 2300 movs r3, #0 8000e1c: 613b str r3, [r7, #16] 8000e1e: 4b18 ldr r3, [pc, #96] ; (8000e80 ) 8000e20: 6b1b ldr r3, [r3, #48] ; 0x30 8000e22: 4a17 ldr r2, [pc, #92] ; (8000e80 ) 8000e24: f043 0302 orr.w r3, r3, #2 8000e28: 6313 str r3, [r2, #48] ; 0x30 8000e2a: 4b15 ldr r3, [pc, #84] ; (8000e80 ) 8000e2c: 6b1b ldr r3, [r3, #48] ; 0x30 8000e2e: f003 0302 and.w r3, r3, #2 8000e32: 613b str r3, [r7, #16] 8000e34: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 8000e36: f44f 7340 mov.w r3, #768 ; 0x300 8000e3a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000e3c: 2312 movs r3, #18 8000e3e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e40: 2300 movs r3, #0 8000e42: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000e44: 2303 movs r3, #3 8000e46: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 8000e48: 2304 movs r3, #4 8000e4a: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000e4c: f107 0314 add.w r3, r7, #20 8000e50: 4619 mov r1, r3 8000e52: 480c ldr r0, [pc, #48] ; (8000e84 ) 8000e54: f000 fe46 bl 8001ae4 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8000e58: 2300 movs r3, #0 8000e5a: 60fb str r3, [r7, #12] 8000e5c: 4b08 ldr r3, [pc, #32] ; (8000e80 ) 8000e5e: 6c1b ldr r3, [r3, #64] ; 0x40 8000e60: 4a07 ldr r2, [pc, #28] ; (8000e80 ) 8000e62: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8000e66: 6413 str r3, [r2, #64] ; 0x40 8000e68: 4b05 ldr r3, [pc, #20] ; (8000e80 ) 8000e6a: 6c1b ldr r3, [r3, #64] ; 0x40 8000e6c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8000e70: 60fb str r3, [r7, #12] 8000e72: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000e74: bf00 nop 8000e76: 3728 adds r7, #40 ; 0x28 8000e78: 46bd mov sp, r7 8000e7a: bd80 pop {r7, pc} 8000e7c: 40005400 .word 0x40005400 8000e80: 40023800 .word 0x40023800 8000e84: 40020400 .word 0x40020400 08000e88 : * This function configures the hardware resources used in this example * @param hrtc: RTC handle pointer * @retval None */ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { 8000e88: b580 push {r7, lr} 8000e8a: b09a sub sp, #104 ; 0x68 8000e8c: af00 add r7, sp, #0 8000e8e: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000e90: f107 030c add.w r3, r7, #12 8000e94: 225c movs r2, #92 ; 0x5c 8000e96: 2100 movs r1, #0 8000e98: 4618 mov r0, r3 8000e9a: f008 f84d bl 8008f38 if(hrtc->Instance==RTC) 8000e9e: 687b ldr r3, [r7, #4] 8000ea0: 681b ldr r3, [r3, #0] 8000ea2: 4a0c ldr r2, [pc, #48] ; (8000ed4 ) 8000ea4: 4293 cmp r3, r2 8000ea6: d111 bne.n 8000ecc /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; 8000ea8: 2320 movs r3, #32 8000eaa: 60fb str r3, [r7, #12] PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 8000eac: f44f 7380 mov.w r3, #256 ; 0x100 8000eb0: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000eb2: f107 030c add.w r3, r7, #12 8000eb6: 4618 mov r0, r3 8000eb8: f002 faaa bl 8003410 8000ebc: 4603 mov r3, r0 8000ebe: 2b00 cmp r3, #0 8000ec0: d001 beq.n 8000ec6 { Error_Handler(); 8000ec2: f7ff fecd bl 8000c60 } /* Peripheral clock enable */ __HAL_RCC_RTC_ENABLE(); 8000ec6: 4b04 ldr r3, [pc, #16] ; (8000ed8 ) 8000ec8: 2201 movs r2, #1 8000eca: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 8000ecc: bf00 nop 8000ece: 3768 adds r7, #104 ; 0x68 8000ed0: 46bd mov sp, r7 8000ed2: bd80 pop {r7, pc} 8000ed4: 40002800 .word 0x40002800 8000ed8: 42470e3c .word 0x42470e3c 08000edc : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8000edc: b580 push {r7, lr} 8000ede: b08c sub sp, #48 ; 0x30 8000ee0: af00 add r7, sp, #0 8000ee2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000ee4: f107 031c add.w r3, r7, #28 8000ee8: 2200 movs r2, #0 8000eea: 601a str r2, [r3, #0] 8000eec: 605a str r2, [r3, #4] 8000eee: 609a str r2, [r3, #8] 8000ef0: 60da str r2, [r3, #12] 8000ef2: 611a str r2, [r3, #16] if(hspi->Instance==SPI1) 8000ef4: 687b ldr r3, [r7, #4] 8000ef6: 681b ldr r3, [r3, #0] 8000ef8: 4a32 ldr r2, [pc, #200] ; (8000fc4 ) 8000efa: 4293 cmp r3, r2 8000efc: d12c bne.n 8000f58 { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 8000efe: 2300 movs r3, #0 8000f00: 61bb str r3, [r7, #24] 8000f02: 4b31 ldr r3, [pc, #196] ; (8000fc8 ) 8000f04: 6c5b ldr r3, [r3, #68] ; 0x44 8000f06: 4a30 ldr r2, [pc, #192] ; (8000fc8 ) 8000f08: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8000f0c: 6453 str r3, [r2, #68] ; 0x44 8000f0e: 4b2e ldr r3, [pc, #184] ; (8000fc8 ) 8000f10: 6c5b ldr r3, [r3, #68] ; 0x44 8000f12: f403 5380 and.w r3, r3, #4096 ; 0x1000 8000f16: 61bb str r3, [r7, #24] 8000f18: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000f1a: 2300 movs r3, #0 8000f1c: 617b str r3, [r7, #20] 8000f1e: 4b2a ldr r3, [pc, #168] ; (8000fc8 ) 8000f20: 6b1b ldr r3, [r3, #48] ; 0x30 8000f22: 4a29 ldr r2, [pc, #164] ; (8000fc8 ) 8000f24: f043 0302 orr.w r3, r3, #2 8000f28: 6313 str r3, [r2, #48] ; 0x30 8000f2a: 4b27 ldr r3, [pc, #156] ; (8000fc8 ) 8000f2c: 6b1b ldr r3, [r3, #48] ; 0x30 8000f2e: f003 0302 and.w r3, r3, #2 8000f32: 617b str r3, [r7, #20] 8000f34: 697b ldr r3, [r7, #20] /**SPI1 GPIO Configuration PB3 ------> SPI1_SCK PB4 ------> SPI1_MISO PB5 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; 8000f36: 2338 movs r3, #56 ; 0x38 8000f38: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f3a: 2302 movs r3, #2 8000f3c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f3e: 2300 movs r3, #0 8000f40: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000f42: 2303 movs r3, #3 8000f44: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; 8000f46: 2305 movs r3, #5 8000f48: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000f4a: f107 031c add.w r3, r7, #28 8000f4e: 4619 mov r1, r3 8000f50: 481e ldr r0, [pc, #120] ; (8000fcc ) 8000f52: f000 fdc7 bl 8001ae4 /* USER CODE BEGIN SPI2_MspInit 1 */ /* USER CODE END SPI2_MspInit 1 */ } } 8000f56: e031 b.n 8000fbc else if(hspi->Instance==SPI2) 8000f58: 687b ldr r3, [r7, #4] 8000f5a: 681b ldr r3, [r3, #0] 8000f5c: 4a1c ldr r2, [pc, #112] ; (8000fd0 ) 8000f5e: 4293 cmp r3, r2 8000f60: d12c bne.n 8000fbc __HAL_RCC_SPI2_CLK_ENABLE(); 8000f62: 2300 movs r3, #0 8000f64: 613b str r3, [r7, #16] 8000f66: 4b18 ldr r3, [pc, #96] ; (8000fc8 ) 8000f68: 6c1b ldr r3, [r3, #64] ; 0x40 8000f6a: 4a17 ldr r2, [pc, #92] ; (8000fc8 ) 8000f6c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8000f70: 6413 str r3, [r2, #64] ; 0x40 8000f72: 4b15 ldr r3, [pc, #84] ; (8000fc8 ) 8000f74: 6c1b ldr r3, [r3, #64] ; 0x40 8000f76: f403 4380 and.w r3, r3, #16384 ; 0x4000 8000f7a: 613b str r3, [r7, #16] 8000f7c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000f7e: 2300 movs r3, #0 8000f80: 60fb str r3, [r7, #12] 8000f82: 4b11 ldr r3, [pc, #68] ; (8000fc8 ) 8000f84: 6b1b ldr r3, [r3, #48] ; 0x30 8000f86: 4a10 ldr r2, [pc, #64] ; (8000fc8 ) 8000f88: f043 0302 orr.w r3, r3, #2 8000f8c: 6313 str r3, [r2, #48] ; 0x30 8000f8e: 4b0e ldr r3, [pc, #56] ; (8000fc8 ) 8000f90: 6b1b ldr r3, [r3, #48] ; 0x30 8000f92: f003 0302 and.w r3, r3, #2 8000f96: 60fb str r3, [r7, #12] 8000f98: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; 8000f9a: f44f 4360 mov.w r3, #57344 ; 0xe000 8000f9e: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000fa0: 2302 movs r3, #2 8000fa2: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fa4: 2300 movs r3, #0 8000fa6: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000fa8: 2303 movs r3, #3 8000faa: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; 8000fac: 2305 movs r3, #5 8000fae: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000fb0: f107 031c add.w r3, r7, #28 8000fb4: 4619 mov r1, r3 8000fb6: 4805 ldr r0, [pc, #20] ; (8000fcc ) 8000fb8: f000 fd94 bl 8001ae4 } 8000fbc: bf00 nop 8000fbe: 3730 adds r7, #48 ; 0x30 8000fc0: 46bd mov sp, r7 8000fc2: bd80 pop {r7, pc} 8000fc4: 40013000 .word 0x40013000 8000fc8: 40023800 .word 0x40023800 8000fcc: 40020400 .word 0x40020400 8000fd0: 40003800 .word 0x40003800 08000fd4 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8000fd4: b580 push {r7, lr} 8000fd6: b08a sub sp, #40 ; 0x28 8000fd8: af00 add r7, sp, #0 8000fda: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000fdc: f107 0314 add.w r3, r7, #20 8000fe0: 2200 movs r2, #0 8000fe2: 601a str r2, [r3, #0] 8000fe4: 605a str r2, [r3, #4] 8000fe6: 609a str r2, [r3, #8] 8000fe8: 60da str r2, [r3, #12] 8000fea: 611a str r2, [r3, #16] if(htim_base->Instance==TIM2) 8000fec: 687b ldr r3, [r7, #4] 8000fee: 681b ldr r3, [r3, #0] 8000ff0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8000ff4: d12b bne.n 800104e { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8000ff6: 2300 movs r3, #0 8000ff8: 613b str r3, [r7, #16] 8000ffa: 4b17 ldr r3, [pc, #92] ; (8001058 ) 8000ffc: 6c1b ldr r3, [r3, #64] ; 0x40 8000ffe: 4a16 ldr r2, [pc, #88] ; (8001058 ) 8001000: f043 0301 orr.w r3, r3, #1 8001004: 6413 str r3, [r2, #64] ; 0x40 8001006: 4b14 ldr r3, [pc, #80] ; (8001058 ) 8001008: 6c1b ldr r3, [r3, #64] ; 0x40 800100a: f003 0301 and.w r3, r3, #1 800100e: 613b str r3, [r7, #16] 8001010: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001012: 2300 movs r3, #0 8001014: 60fb str r3, [r7, #12] 8001016: 4b10 ldr r3, [pc, #64] ; (8001058 ) 8001018: 6b1b ldr r3, [r3, #48] ; 0x30 800101a: 4a0f ldr r2, [pc, #60] ; (8001058 ) 800101c: f043 0301 orr.w r3, r3, #1 8001020: 6313 str r3, [r2, #48] ; 0x30 8001022: 4b0d ldr r3, [pc, #52] ; (8001058 ) 8001024: 6b1b ldr r3, [r3, #48] ; 0x30 8001026: f003 0301 and.w r3, r3, #1 800102a: 60fb str r3, [r7, #12] 800102c: 68fb ldr r3, [r7, #12] /**TIM2 GPIO Configuration PA0-WKUP ------> TIM2_ETR */ GPIO_InitStruct.Pin = GPIO_PIN_0; 800102e: 2301 movs r3, #1 8001030: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001032: 2302 movs r3, #2 8001034: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001036: 2300 movs r3, #0 8001038: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800103a: 2300 movs r3, #0 800103c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 800103e: 2301 movs r3, #1 8001040: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001042: f107 0314 add.w r3, r7, #20 8001046: 4619 mov r1, r3 8001048: 4804 ldr r0, [pc, #16] ; (800105c ) 800104a: f000 fd4b bl 8001ae4 /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 800104e: bf00 nop 8001050: 3728 adds r7, #40 ; 0x28 8001052: 46bd mov sp, r7 8001054: bd80 pop {r7, pc} 8001056: bf00 nop 8001058: 40023800 .word 0x40023800 800105c: 40020000 .word 0x40020000 08001060 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8001060: b580 push {r7, lr} 8001062: b08a sub sp, #40 ; 0x28 8001064: af00 add r7, sp, #0 8001066: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001068: f107 0314 add.w r3, r7, #20 800106c: 2200 movs r2, #0 800106e: 601a str r2, [r3, #0] 8001070: 605a str r2, [r3, #4] 8001072: 609a str r2, [r3, #8] 8001074: 60da str r2, [r3, #12] 8001076: 611a str r2, [r3, #16] if(huart->Instance==USART1) 8001078: 687b ldr r3, [r7, #4] 800107a: 681b ldr r3, [r3, #0] 800107c: 4a19 ldr r2, [pc, #100] ; (80010e4 ) 800107e: 4293 cmp r3, r2 8001080: d12c bne.n 80010dc { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8001082: 2300 movs r3, #0 8001084: 613b str r3, [r7, #16] 8001086: 4b18 ldr r3, [pc, #96] ; (80010e8 ) 8001088: 6c5b ldr r3, [r3, #68] ; 0x44 800108a: 4a17 ldr r2, [pc, #92] ; (80010e8 ) 800108c: f043 0310 orr.w r3, r3, #16 8001090: 6453 str r3, [r2, #68] ; 0x44 8001092: 4b15 ldr r3, [pc, #84] ; (80010e8 ) 8001094: 6c5b ldr r3, [r3, #68] ; 0x44 8001096: f003 0310 and.w r3, r3, #16 800109a: 613b str r3, [r7, #16] 800109c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800109e: 2300 movs r3, #0 80010a0: 60fb str r3, [r7, #12] 80010a2: 4b11 ldr r3, [pc, #68] ; (80010e8 ) 80010a4: 6b1b ldr r3, [r3, #48] ; 0x30 80010a6: 4a10 ldr r2, [pc, #64] ; (80010e8 ) 80010a8: f043 0301 orr.w r3, r3, #1 80010ac: 6313 str r3, [r2, #48] ; 0x30 80010ae: 4b0e ldr r3, [pc, #56] ; (80010e8 ) 80010b0: 6b1b ldr r3, [r3, #48] ; 0x30 80010b2: f003 0301 and.w r3, r3, #1 80010b6: 60fb str r3, [r7, #12] 80010b8: 68fb ldr r3, [r7, #12] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 80010ba: f44f 63c0 mov.w r3, #1536 ; 0x600 80010be: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010c0: 2302 movs r3, #2 80010c2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80010c4: 2300 movs r3, #0 80010c6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80010c8: 2303 movs r3, #3 80010ca: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 80010cc: 2307 movs r3, #7 80010ce: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80010d0: f107 0314 add.w r3, r7, #20 80010d4: 4619 mov r1, r3 80010d6: 4805 ldr r0, [pc, #20] ; (80010ec ) 80010d8: f000 fd04 bl 8001ae4 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 80010dc: bf00 nop 80010de: 3728 adds r7, #40 ; 0x28 80010e0: 46bd mov sp, r7 80010e2: bd80 pop {r7, pc} 80010e4: 40011000 .word 0x40011000 80010e8: 40023800 .word 0x40023800 80010ec: 40020000 .word 0x40020000 080010f0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80010f0: b480 push {r7} 80010f2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80010f4: e7fe b.n 80010f4 080010f6 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80010f6: b480 push {r7} 80010f8: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80010fa: e7fe b.n 80010fa 080010fc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80010fc: b480 push {r7} 80010fe: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001100: e7fe b.n 8001100 08001102 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001102: b480 push {r7} 8001104: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001106: e7fe b.n 8001106 08001108 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001108: b480 push {r7} 800110a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800110c: e7fe b.n 800110c 0800110e : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800110e: b480 push {r7} 8001110: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001112: bf00 nop 8001114: 46bd mov sp, r7 8001116: f85d 7b04 ldr.w r7, [sp], #4 800111a: 4770 bx lr 0800111c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800111c: b480 push {r7} 800111e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001120: bf00 nop 8001122: 46bd mov sp, r7 8001124: f85d 7b04 ldr.w r7, [sp], #4 8001128: 4770 bx lr 0800112a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800112a: b480 push {r7} 800112c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800112e: bf00 nop 8001130: 46bd mov sp, r7 8001132: f85d 7b04 ldr.w r7, [sp], #4 8001136: 4770 bx lr 08001138 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001138: b580 push {r7, lr} 800113a: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800113c: f000 f89a bl 8001274 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001140: bf00 nop 8001142: bd80 pop {r7, pc} 08001144 : /** * @brief This function handles USB On The Go FS global interrupt. */ void OTG_FS_IRQHandler(void) { 8001144: b580 push {r7, lr} 8001146: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_FS_IRQn 0 */ /* USER CODE END OTG_FS_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); 8001148: 4802 ldr r0, [pc, #8] ; (8001154 ) 800114a: f000 ffcf bl 80020ec /* USER CODE BEGIN OTG_FS_IRQn 1 */ /* USER CODE END OTG_FS_IRQn 1 */ } 800114e: bf00 nop 8001150: bd80 pop {r7, pc} 8001152: bf00 nop 8001154: 20001af4 .word 0x20001af4 08001158 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8001158: b480 push {r7} 800115a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 800115c: 4b06 ldr r3, [pc, #24] ; (8001178 ) 800115e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001162: 4a05 ldr r2, [pc, #20] ; (8001178 ) 8001164: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8001168: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 800116c: bf00 nop 800116e: 46bd mov sp, r7 8001170: f85d 7b04 ldr.w r7, [sp], #4 8001174: 4770 bx lr 8001176: bf00 nop 8001178: e000ed00 .word 0xe000ed00 0800117c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 800117c: f8df d034 ldr.w sp, [pc, #52] ; 80011b4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001180: 480d ldr r0, [pc, #52] ; (80011b8 ) ldr r1, =_edata 8001182: 490e ldr r1, [pc, #56] ; (80011bc ) ldr r2, =_sidata 8001184: 4a0e ldr r2, [pc, #56] ; (80011c0 ) movs r3, #0 8001186: 2300 movs r3, #0 b LoopCopyDataInit 8001188: e002 b.n 8001190 0800118a : CopyDataInit: ldr r4, [r2, r3] 800118a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800118c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800118e: 3304 adds r3, #4 08001190 : LoopCopyDataInit: adds r4, r0, r3 8001190: 18c4 adds r4, r0, r3 cmp r4, r1 8001192: 428c cmp r4, r1 bcc CopyDataInit 8001194: d3f9 bcc.n 800118a /* Zero fill the bss segment. */ ldr r2, =_sbss 8001196: 4a0b ldr r2, [pc, #44] ; (80011c4 ) ldr r4, =_ebss 8001198: 4c0b ldr r4, [pc, #44] ; (80011c8 ) movs r3, #0 800119a: 2300 movs r3, #0 b LoopFillZerobss 800119c: e001 b.n 80011a2 0800119e : FillZerobss: str r3, [r2] 800119e: 6013 str r3, [r2, #0] adds r2, r2, #4 80011a0: 3204 adds r2, #4 080011a2 : LoopFillZerobss: cmp r2, r4 80011a2: 42a2 cmp r2, r4 bcc FillZerobss 80011a4: d3fb bcc.n 800119e /* Call the clock system intitialization function.*/ bl SystemInit 80011a6: f7ff ffd7 bl 8001158 /* Call static constructors */ bl __libc_init_array 80011aa: f007 fea1 bl 8008ef0 <__libc_init_array> /* Call the application's entry point.*/ bl main 80011ae: f7ff f9a5 bl 80004fc
bx lr 80011b2: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80011b4: 20020000 .word 0x20020000 ldr r0, =_sdata 80011b8: 20000000 .word 0x20000000 ldr r1, =_edata 80011bc: 20000190 .word 0x20000190 ldr r2, =_sidata 80011c0: 08008fd0 .word 0x08008fd0 ldr r2, =_sbss 80011c4: 20000190 .word 0x20000190 ldr r4, =_ebss 80011c8: 20001efc .word 0x20001efc 080011cc : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80011cc: e7fe b.n 80011cc ... 080011d0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80011d0: b580 push {r7, lr} 80011d2: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 80011d4: 4b0e ldr r3, [pc, #56] ; (8001210 ) 80011d6: 681b ldr r3, [r3, #0] 80011d8: 4a0d ldr r2, [pc, #52] ; (8001210 ) 80011da: f443 7300 orr.w r3, r3, #512 ; 0x200 80011de: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 80011e0: 4b0b ldr r3, [pc, #44] ; (8001210 ) 80011e2: 681b ldr r3, [r3, #0] 80011e4: 4a0a ldr r2, [pc, #40] ; (8001210 ) 80011e6: f443 6380 orr.w r3, r3, #1024 ; 0x400 80011ea: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80011ec: 4b08 ldr r3, [pc, #32] ; (8001210 ) 80011ee: 681b ldr r3, [r3, #0] 80011f0: 4a07 ldr r2, [pc, #28] ; (8001210 ) 80011f2: f443 7380 orr.w r3, r3, #256 ; 0x100 80011f6: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80011f8: 2003 movs r0, #3 80011fa: f000 fbc1 bl 8001980 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80011fe: 200f movs r0, #15 8001200: f000 f808 bl 8001214 /* Init the low level hardware */ HAL_MspInit(); 8001204: f7ff fd32 bl 8000c6c /* Return function status */ return HAL_OK; 8001208: 2300 movs r3, #0 } 800120a: 4618 mov r0, r3 800120c: bd80 pop {r7, pc} 800120e: bf00 nop 8001210: 40023c00 .word 0x40023c00 08001214 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001214: b580 push {r7, lr} 8001216: b082 sub sp, #8 8001218: af00 add r7, sp, #0 800121a: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800121c: 4b12 ldr r3, [pc, #72] ; (8001268 ) 800121e: 681a ldr r2, [r3, #0] 8001220: 4b12 ldr r3, [pc, #72] ; (800126c ) 8001222: 781b ldrb r3, [r3, #0] 8001224: 4619 mov r1, r3 8001226: f44f 737a mov.w r3, #1000 ; 0x3e8 800122a: fbb3 f3f1 udiv r3, r3, r1 800122e: fbb2 f3f3 udiv r3, r2, r3 8001232: 4618 mov r0, r3 8001234: f000 fbd9 bl 80019ea 8001238: 4603 mov r3, r0 800123a: 2b00 cmp r3, #0 800123c: d001 beq.n 8001242 { return HAL_ERROR; 800123e: 2301 movs r3, #1 8001240: e00e b.n 8001260 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001242: 687b ldr r3, [r7, #4] 8001244: 2b0f cmp r3, #15 8001246: d80a bhi.n 800125e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001248: 2200 movs r2, #0 800124a: 6879 ldr r1, [r7, #4] 800124c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001250: f000 fba1 bl 8001996 uwTickPrio = TickPriority; 8001254: 4a06 ldr r2, [pc, #24] ; (8001270 ) 8001256: 687b ldr r3, [r7, #4] 8001258: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800125a: 2300 movs r3, #0 800125c: e000 b.n 8001260 return HAL_ERROR; 800125e: 2301 movs r3, #1 } 8001260: 4618 mov r0, r3 8001262: 3708 adds r7, #8 8001264: 46bd mov sp, r7 8001266: bd80 pop {r7, pc} 8001268: 20000000 .word 0x20000000 800126c: 20000008 .word 0x20000008 8001270: 20000004 .word 0x20000004 08001274 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001274: b480 push {r7} 8001276: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001278: 4b06 ldr r3, [pc, #24] ; (8001294 ) 800127a: 781b ldrb r3, [r3, #0] 800127c: 461a mov r2, r3 800127e: 4b06 ldr r3, [pc, #24] ; (8001298 ) 8001280: 681b ldr r3, [r3, #0] 8001282: 4413 add r3, r2 8001284: 4a04 ldr r2, [pc, #16] ; (8001298 ) 8001286: 6013 str r3, [r2, #0] } 8001288: bf00 nop 800128a: 46bd mov sp, r7 800128c: f85d 7b04 ldr.w r7, [sp], #4 8001290: 4770 bx lr 8001292: bf00 nop 8001294: 20000008 .word 0x20000008 8001298: 20000620 .word 0x20000620 0800129c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800129c: b480 push {r7} 800129e: af00 add r7, sp, #0 return uwTick; 80012a0: 4b03 ldr r3, [pc, #12] ; (80012b0 ) 80012a2: 681b ldr r3, [r3, #0] } 80012a4: 4618 mov r0, r3 80012a6: 46bd mov sp, r7 80012a8: f85d 7b04 ldr.w r7, [sp], #4 80012ac: 4770 bx lr 80012ae: bf00 nop 80012b0: 20000620 .word 0x20000620 080012b4 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80012b4: b580 push {r7, lr} 80012b6: b084 sub sp, #16 80012b8: af00 add r7, sp, #0 80012ba: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80012bc: f7ff ffee bl 800129c 80012c0: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80012c2: 687b ldr r3, [r7, #4] 80012c4: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80012c6: 68fb ldr r3, [r7, #12] 80012c8: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80012cc: d005 beq.n 80012da { wait += (uint32_t)(uwTickFreq); 80012ce: 4b0a ldr r3, [pc, #40] ; (80012f8 ) 80012d0: 781b ldrb r3, [r3, #0] 80012d2: 461a mov r2, r3 80012d4: 68fb ldr r3, [r7, #12] 80012d6: 4413 add r3, r2 80012d8: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 80012da: bf00 nop 80012dc: f7ff ffde bl 800129c 80012e0: 4602 mov r2, r0 80012e2: 68bb ldr r3, [r7, #8] 80012e4: 1ad3 subs r3, r2, r3 80012e6: 68fa ldr r2, [r7, #12] 80012e8: 429a cmp r2, r3 80012ea: d8f7 bhi.n 80012dc { } } 80012ec: bf00 nop 80012ee: bf00 nop 80012f0: 3710 adds r7, #16 80012f2: 46bd mov sp, r7 80012f4: bd80 pop {r7, pc} 80012f6: bf00 nop 80012f8: 20000008 .word 0x20000008 080012fc : * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 80012fc: b580 push {r7, lr} 80012fe: b084 sub sp, #16 8001300: af00 add r7, sp, #0 8001302: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001304: 2300 movs r3, #0 8001306: 73fb strb r3, [r7, #15] /* Check ADC handle */ if(hadc == NULL) 8001308: 687b ldr r3, [r7, #4] 800130a: 2b00 cmp r3, #0 800130c: d101 bne.n 8001312 { return HAL_ERROR; 800130e: 2301 movs r3, #1 8001310: e033 b.n 800137a if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); } if(hadc->State == HAL_ADC_STATE_RESET) 8001312: 687b ldr r3, [r7, #4] 8001314: 6c1b ldr r3, [r3, #64] ; 0x40 8001316: 2b00 cmp r3, #0 8001318: d109 bne.n 800132e /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800131a: 6878 ldr r0, [r7, #4] 800131c: f7ff fcce bl 8000cbc #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8001320: 687b ldr r3, [r7, #4] 8001322: 2200 movs r2, #0 8001324: 645a str r2, [r3, #68] ; 0x44 /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8001326: 687b ldr r3, [r7, #4] 8001328: 2200 movs r2, #0 800132a: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800132e: 687b ldr r3, [r7, #4] 8001330: 6c1b ldr r3, [r3, #64] ; 0x40 8001332: f003 0310 and.w r3, r3, #16 8001336: 2b00 cmp r3, #0 8001338: d118 bne.n 800136c { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800133a: 687b ldr r3, [r7, #4] 800133c: 6c1b ldr r3, [r3, #64] ; 0x40 800133e: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8001342: f023 0302 bic.w r3, r3, #2 8001346: f043 0202 orr.w r2, r3, #2 800134a: 687b ldr r3, [r7, #4] 800134c: 641a str r2, [r3, #64] ; 0x40 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set ADC parameters */ ADC_Init(hadc); 800134e: 6878 ldr r0, [r7, #4] 8001350: f000 f94a bl 80015e8 /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001354: 687b ldr r3, [r7, #4] 8001356: 2200 movs r2, #0 8001358: 645a str r2, [r3, #68] ; 0x44 /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800135a: 687b ldr r3, [r7, #4] 800135c: 6c1b ldr r3, [r3, #64] ; 0x40 800135e: f023 0303 bic.w r3, r3, #3 8001362: f043 0201 orr.w r2, r3, #1 8001366: 687b ldr r3, [r7, #4] 8001368: 641a str r2, [r3, #64] ; 0x40 800136a: e001 b.n 8001370 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { tmp_hal_status = HAL_ERROR; 800136c: 2301 movs r3, #1 800136e: 73fb strb r3, [r7, #15] } /* Release Lock */ __HAL_UNLOCK(hadc); 8001370: 687b ldr r3, [r7, #4] 8001372: 2200 movs r2, #0 8001374: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Return function status */ return tmp_hal_status; 8001378: 7bfb ldrb r3, [r7, #15] } 800137a: 4618 mov r0, r3 800137c: 3710 adds r7, #16 800137e: 46bd mov sp, r7 8001380: bd80 pop {r7, pc} ... 08001384 : * the configuration information for the specified ADC. * @param sConfig ADC configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8001384: b480 push {r7} 8001386: b085 sub sp, #20 8001388: af00 add r7, sp, #0 800138a: 6078 str r0, [r7, #4] 800138c: 6039 str r1, [r7, #0] __IO uint32_t counter = 0U; 800138e: 2300 movs r3, #0 8001390: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8001392: 687b ldr r3, [r7, #4] 8001394: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8001398: 2b01 cmp r3, #1 800139a: d101 bne.n 80013a0 800139c: 2302 movs r3, #2 800139e: e113 b.n 80015c8 80013a0: 687b ldr r3, [r7, #4] 80013a2: 2201 movs r2, #1 80013a4: f883 203c strb.w r2, [r3, #60] ; 0x3c /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (sConfig->Channel > ADC_CHANNEL_9) 80013a8: 683b ldr r3, [r7, #0] 80013aa: 681b ldr r3, [r3, #0] 80013ac: 2b09 cmp r3, #9 80013ae: d925 bls.n 80013fc { /* Clear the old sample time */ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); 80013b0: 687b ldr r3, [r7, #4] 80013b2: 681b ldr r3, [r3, #0] 80013b4: 68d9 ldr r1, [r3, #12] 80013b6: 683b ldr r3, [r7, #0] 80013b8: 681b ldr r3, [r3, #0] 80013ba: b29b uxth r3, r3 80013bc: 461a mov r2, r3 80013be: 4613 mov r3, r2 80013c0: 005b lsls r3, r3, #1 80013c2: 4413 add r3, r2 80013c4: 3b1e subs r3, #30 80013c6: 2207 movs r2, #7 80013c8: fa02 f303 lsl.w r3, r2, r3 80013cc: 43da mvns r2, r3 80013ce: 687b ldr r3, [r7, #4] 80013d0: 681b ldr r3, [r3, #0] 80013d2: 400a ands r2, r1 80013d4: 60da str r2, [r3, #12] /* Set the new sample time */ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); 80013d6: 687b ldr r3, [r7, #4] 80013d8: 681b ldr r3, [r3, #0] 80013da: 68d9 ldr r1, [r3, #12] 80013dc: 683b ldr r3, [r7, #0] 80013de: 689a ldr r2, [r3, #8] 80013e0: 683b ldr r3, [r7, #0] 80013e2: 681b ldr r3, [r3, #0] 80013e4: b29b uxth r3, r3 80013e6: 4618 mov r0, r3 80013e8: 4603 mov r3, r0 80013ea: 005b lsls r3, r3, #1 80013ec: 4403 add r3, r0 80013ee: 3b1e subs r3, #30 80013f0: 409a lsls r2, r3 80013f2: 687b ldr r3, [r7, #4] 80013f4: 681b ldr r3, [r3, #0] 80013f6: 430a orrs r2, r1 80013f8: 60da str r2, [r3, #12] 80013fa: e022 b.n 8001442 } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Clear the old sample time */ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); 80013fc: 687b ldr r3, [r7, #4] 80013fe: 681b ldr r3, [r3, #0] 8001400: 6919 ldr r1, [r3, #16] 8001402: 683b ldr r3, [r7, #0] 8001404: 681b ldr r3, [r3, #0] 8001406: b29b uxth r3, r3 8001408: 461a mov r2, r3 800140a: 4613 mov r3, r2 800140c: 005b lsls r3, r3, #1 800140e: 4413 add r3, r2 8001410: 2207 movs r2, #7 8001412: fa02 f303 lsl.w r3, r2, r3 8001416: 43da mvns r2, r3 8001418: 687b ldr r3, [r7, #4] 800141a: 681b ldr r3, [r3, #0] 800141c: 400a ands r2, r1 800141e: 611a str r2, [r3, #16] /* Set the new sample time */ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); 8001420: 687b ldr r3, [r7, #4] 8001422: 681b ldr r3, [r3, #0] 8001424: 6919 ldr r1, [r3, #16] 8001426: 683b ldr r3, [r7, #0] 8001428: 689a ldr r2, [r3, #8] 800142a: 683b ldr r3, [r7, #0] 800142c: 681b ldr r3, [r3, #0] 800142e: b29b uxth r3, r3 8001430: 4618 mov r0, r3 8001432: 4603 mov r3, r0 8001434: 005b lsls r3, r3, #1 8001436: 4403 add r3, r0 8001438: 409a lsls r2, r3 800143a: 687b ldr r3, [r7, #4] 800143c: 681b ldr r3, [r3, #0] 800143e: 430a orrs r2, r1 8001440: 611a str r2, [r3, #16] } /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8001442: 683b ldr r3, [r7, #0] 8001444: 685b ldr r3, [r3, #4] 8001446: 2b06 cmp r3, #6 8001448: d824 bhi.n 8001494 { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); 800144a: 687b ldr r3, [r7, #4] 800144c: 681b ldr r3, [r3, #0] 800144e: 6b59 ldr r1, [r3, #52] ; 0x34 8001450: 683b ldr r3, [r7, #0] 8001452: 685a ldr r2, [r3, #4] 8001454: 4613 mov r3, r2 8001456: 009b lsls r3, r3, #2 8001458: 4413 add r3, r2 800145a: 3b05 subs r3, #5 800145c: 221f movs r2, #31 800145e: fa02 f303 lsl.w r3, r2, r3 8001462: 43da mvns r2, r3 8001464: 687b ldr r3, [r7, #4] 8001466: 681b ldr r3, [r3, #0] 8001468: 400a ands r2, r1 800146a: 635a str r2, [r3, #52] ; 0x34 /* Set the SQx bits for the selected rank */ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); 800146c: 687b ldr r3, [r7, #4] 800146e: 681b ldr r3, [r3, #0] 8001470: 6b59 ldr r1, [r3, #52] ; 0x34 8001472: 683b ldr r3, [r7, #0] 8001474: 681b ldr r3, [r3, #0] 8001476: b29b uxth r3, r3 8001478: 4618 mov r0, r3 800147a: 683b ldr r3, [r7, #0] 800147c: 685a ldr r2, [r3, #4] 800147e: 4613 mov r3, r2 8001480: 009b lsls r3, r3, #2 8001482: 4413 add r3, r2 8001484: 3b05 subs r3, #5 8001486: fa00 f203 lsl.w r2, r0, r3 800148a: 687b ldr r3, [r7, #4] 800148c: 681b ldr r3, [r3, #0] 800148e: 430a orrs r2, r1 8001490: 635a str r2, [r3, #52] ; 0x34 8001492: e04c b.n 800152e } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 8001494: 683b ldr r3, [r7, #0] 8001496: 685b ldr r3, [r3, #4] 8001498: 2b0c cmp r3, #12 800149a: d824 bhi.n 80014e6 { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); 800149c: 687b ldr r3, [r7, #4] 800149e: 681b ldr r3, [r3, #0] 80014a0: 6b19 ldr r1, [r3, #48] ; 0x30 80014a2: 683b ldr r3, [r7, #0] 80014a4: 685a ldr r2, [r3, #4] 80014a6: 4613 mov r3, r2 80014a8: 009b lsls r3, r3, #2 80014aa: 4413 add r3, r2 80014ac: 3b23 subs r3, #35 ; 0x23 80014ae: 221f movs r2, #31 80014b0: fa02 f303 lsl.w r3, r2, r3 80014b4: 43da mvns r2, r3 80014b6: 687b ldr r3, [r7, #4] 80014b8: 681b ldr r3, [r3, #0] 80014ba: 400a ands r2, r1 80014bc: 631a str r2, [r3, #48] ; 0x30 /* Set the SQx bits for the selected rank */ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); 80014be: 687b ldr r3, [r7, #4] 80014c0: 681b ldr r3, [r3, #0] 80014c2: 6b19 ldr r1, [r3, #48] ; 0x30 80014c4: 683b ldr r3, [r7, #0] 80014c6: 681b ldr r3, [r3, #0] 80014c8: b29b uxth r3, r3 80014ca: 4618 mov r0, r3 80014cc: 683b ldr r3, [r7, #0] 80014ce: 685a ldr r2, [r3, #4] 80014d0: 4613 mov r3, r2 80014d2: 009b lsls r3, r3, #2 80014d4: 4413 add r3, r2 80014d6: 3b23 subs r3, #35 ; 0x23 80014d8: fa00 f203 lsl.w r2, r0, r3 80014dc: 687b ldr r3, [r7, #4] 80014de: 681b ldr r3, [r3, #0] 80014e0: 430a orrs r2, r1 80014e2: 631a str r2, [r3, #48] ; 0x30 80014e4: e023 b.n 800152e } /* For Rank 13 to 16 */ else { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); 80014e6: 687b ldr r3, [r7, #4] 80014e8: 681b ldr r3, [r3, #0] 80014ea: 6ad9 ldr r1, [r3, #44] ; 0x2c 80014ec: 683b ldr r3, [r7, #0] 80014ee: 685a ldr r2, [r3, #4] 80014f0: 4613 mov r3, r2 80014f2: 009b lsls r3, r3, #2 80014f4: 4413 add r3, r2 80014f6: 3b41 subs r3, #65 ; 0x41 80014f8: 221f movs r2, #31 80014fa: fa02 f303 lsl.w r3, r2, r3 80014fe: 43da mvns r2, r3 8001500: 687b ldr r3, [r7, #4] 8001502: 681b ldr r3, [r3, #0] 8001504: 400a ands r2, r1 8001506: 62da str r2, [r3, #44] ; 0x2c /* Set the SQx bits for the selected rank */ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); 8001508: 687b ldr r3, [r7, #4] 800150a: 681b ldr r3, [r3, #0] 800150c: 6ad9 ldr r1, [r3, #44] ; 0x2c 800150e: 683b ldr r3, [r7, #0] 8001510: 681b ldr r3, [r3, #0] 8001512: b29b uxth r3, r3 8001514: 4618 mov r0, r3 8001516: 683b ldr r3, [r7, #0] 8001518: 685a ldr r2, [r3, #4] 800151a: 4613 mov r3, r2 800151c: 009b lsls r3, r3, #2 800151e: 4413 add r3, r2 8001520: 3b41 subs r3, #65 ; 0x41 8001522: fa00 f203 lsl.w r2, r0, r3 8001526: 687b ldr r3, [r7, #4] 8001528: 681b ldr r3, [r3, #0] 800152a: 430a orrs r2, r1 800152c: 62da str r2, [r3, #44] ; 0x2c } /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ /* control register) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); 800152e: 4b29 ldr r3, [pc, #164] ; (80015d4 ) 8001530: 60fb str r3, [r7, #12] /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) 8001532: 687b ldr r3, [r7, #4] 8001534: 681b ldr r3, [r3, #0] 8001536: 4a28 ldr r2, [pc, #160] ; (80015d8 ) 8001538: 4293 cmp r3, r2 800153a: d10f bne.n 800155c 800153c: 683b ldr r3, [r7, #0] 800153e: 681b ldr r3, [r3, #0] 8001540: 2b12 cmp r3, #18 8001542: d10b bne.n 800155c { /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT) { tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE; 8001544: 68fb ldr r3, [r7, #12] 8001546: 685b ldr r3, [r3, #4] 8001548: f423 0200 bic.w r2, r3, #8388608 ; 0x800000 800154c: 68fb ldr r3, [r7, #12] 800154e: 605a str r2, [r3, #4] } /* Enable the VBAT channel*/ tmpADC_Common->CCR |= ADC_CCR_VBATE; 8001550: 68fb ldr r3, [r7, #12] 8001552: 685b ldr r3, [r3, #4] 8001554: f443 0280 orr.w r2, r3, #4194304 ; 0x400000 8001558: 68fb ldr r3, [r7, #12] 800155a: 605a str r2, [r3, #4] } /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or Channel_17 is selected for VREFINT enable TSVREFE */ if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) 800155c: 687b ldr r3, [r7, #4] 800155e: 681b ldr r3, [r3, #0] 8001560: 4a1d ldr r2, [pc, #116] ; (80015d8 ) 8001562: 4293 cmp r3, r2 8001564: d12b bne.n 80015be 8001566: 683b ldr r3, [r7, #0] 8001568: 681b ldr r3, [r3, #0] 800156a: 4a1c ldr r2, [pc, #112] ; (80015dc ) 800156c: 4293 cmp r3, r2 800156e: d003 beq.n 8001578 8001570: 683b ldr r3, [r7, #0] 8001572: 681b ldr r3, [r3, #0] 8001574: 2b11 cmp r3, #17 8001576: d122 bne.n 80015be { /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT) { tmpADC_Common->CCR &= ~ADC_CCR_VBATE; 8001578: 68fb ldr r3, [r7, #12] 800157a: 685b ldr r3, [r3, #4] 800157c: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 8001580: 68fb ldr r3, [r7, #12] 8001582: 605a str r2, [r3, #4] } /* Enable the Temperature sensor and VREFINT channel*/ tmpADC_Common->CCR |= ADC_CCR_TSVREFE; 8001584: 68fb ldr r3, [r7, #12] 8001586: 685b ldr r3, [r3, #4] 8001588: f443 0200 orr.w r2, r3, #8388608 ; 0x800000 800158c: 68fb ldr r3, [r7, #12] 800158e: 605a str r2, [r3, #4] if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8001590: 683b ldr r3, [r7, #0] 8001592: 681b ldr r3, [r3, #0] 8001594: 4a11 ldr r2, [pc, #68] ; (80015dc ) 8001596: 4293 cmp r3, r2 8001598: d111 bne.n 80015be { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800159a: 4b11 ldr r3, [pc, #68] ; (80015e0 ) 800159c: 681b ldr r3, [r3, #0] 800159e: 4a11 ldr r2, [pc, #68] ; (80015e4 ) 80015a0: fba2 2303 umull r2, r3, r2, r3 80015a4: 0c9a lsrs r2, r3, #18 80015a6: 4613 mov r3, r2 80015a8: 009b lsls r3, r3, #2 80015aa: 4413 add r3, r2 80015ac: 005b lsls r3, r3, #1 80015ae: 60bb str r3, [r7, #8] while(counter != 0U) 80015b0: e002 b.n 80015b8 { counter--; 80015b2: 68bb ldr r3, [r7, #8] 80015b4: 3b01 subs r3, #1 80015b6: 60bb str r3, [r7, #8] while(counter != 0U) 80015b8: 68bb ldr r3, [r7, #8] 80015ba: 2b00 cmp r3, #0 80015bc: d1f9 bne.n 80015b2 } } } /* Process unlocked */ __HAL_UNLOCK(hadc); 80015be: 687b ldr r3, [r7, #4] 80015c0: 2200 movs r2, #0 80015c2: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Return function status */ return HAL_OK; 80015c6: 2300 movs r3, #0 } 80015c8: 4618 mov r0, r3 80015ca: 3714 adds r7, #20 80015cc: 46bd mov sp, r7 80015ce: f85d 7b04 ldr.w r7, [sp], #4 80015d2: 4770 bx lr 80015d4: 40012300 .word 0x40012300 80015d8: 40012000 .word 0x40012000 80015dc: 10000012 .word 0x10000012 80015e0: 20000000 .word 0x20000000 80015e4: 431bde83 .word 0x431bde83 080015e8 : * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ static void ADC_Init(ADC_HandleTypeDef* hadc) { 80015e8: b480 push {r7} 80015ea: b085 sub sp, #20 80015ec: af00 add r7, sp, #0 80015ee: 6078 str r0, [r7, #4] /* Set ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ /* control register) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); 80015f0: 4b79 ldr r3, [pc, #484] ; (80017d8 ) 80015f2: 60fb str r3, [r7, #12] /* Set the ADC clock prescaler */ tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE); 80015f4: 68fb ldr r3, [r7, #12] 80015f6: 685b ldr r3, [r3, #4] 80015f8: f423 3240 bic.w r2, r3, #196608 ; 0x30000 80015fc: 68fb ldr r3, [r7, #12] 80015fe: 605a str r2, [r3, #4] tmpADC_Common->CCR |= hadc->Init.ClockPrescaler; 8001600: 68fb ldr r3, [r7, #12] 8001602: 685a ldr r2, [r3, #4] 8001604: 687b ldr r3, [r7, #4] 8001606: 685b ldr r3, [r3, #4] 8001608: 431a orrs r2, r3 800160a: 68fb ldr r3, [r7, #12] 800160c: 605a str r2, [r3, #4] /* Set ADC scan mode */ hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); 800160e: 687b ldr r3, [r7, #4] 8001610: 681b ldr r3, [r3, #0] 8001612: 685a ldr r2, [r3, #4] 8001614: 687b ldr r3, [r7, #4] 8001616: 681b ldr r3, [r3, #0] 8001618: f422 7280 bic.w r2, r2, #256 ; 0x100 800161c: 605a str r2, [r3, #4] hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); 800161e: 687b ldr r3, [r7, #4] 8001620: 681b ldr r3, [r3, #0] 8001622: 6859 ldr r1, [r3, #4] 8001624: 687b ldr r3, [r7, #4] 8001626: 691b ldr r3, [r3, #16] 8001628: 021a lsls r2, r3, #8 800162a: 687b ldr r3, [r7, #4] 800162c: 681b ldr r3, [r3, #0] 800162e: 430a orrs r2, r1 8001630: 605a str r2, [r3, #4] /* Set ADC resolution */ hadc->Instance->CR1 &= ~(ADC_CR1_RES); 8001632: 687b ldr r3, [r7, #4] 8001634: 681b ldr r3, [r3, #0] 8001636: 685a ldr r2, [r3, #4] 8001638: 687b ldr r3, [r7, #4] 800163a: 681b ldr r3, [r3, #0] 800163c: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000 8001640: 605a str r2, [r3, #4] hadc->Instance->CR1 |= hadc->Init.Resolution; 8001642: 687b ldr r3, [r7, #4] 8001644: 681b ldr r3, [r3, #0] 8001646: 6859 ldr r1, [r3, #4] 8001648: 687b ldr r3, [r7, #4] 800164a: 689a ldr r2, [r3, #8] 800164c: 687b ldr r3, [r7, #4] 800164e: 681b ldr r3, [r3, #0] 8001650: 430a orrs r2, r1 8001652: 605a str r2, [r3, #4] /* Set ADC data alignment */ hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); 8001654: 687b ldr r3, [r7, #4] 8001656: 681b ldr r3, [r3, #0] 8001658: 689a ldr r2, [r3, #8] 800165a: 687b ldr r3, [r7, #4] 800165c: 681b ldr r3, [r3, #0] 800165e: f422 6200 bic.w r2, r2, #2048 ; 0x800 8001662: 609a str r2, [r3, #8] hadc->Instance->CR2 |= hadc->Init.DataAlign; 8001664: 687b ldr r3, [r7, #4] 8001666: 681b ldr r3, [r3, #0] 8001668: 6899 ldr r1, [r3, #8] 800166a: 687b ldr r3, [r7, #4] 800166c: 68da ldr r2, [r3, #12] 800166e: 687b ldr r3, [r7, #4] 8001670: 681b ldr r3, [r3, #0] 8001672: 430a orrs r2, r1 8001674: 609a str r2, [r3, #8] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8001676: 687b ldr r3, [r7, #4] 8001678: 6a9b ldr r3, [r3, #40] ; 0x28 800167a: 4a58 ldr r2, [pc, #352] ; (80017dc ) 800167c: 4293 cmp r3, r2 800167e: d022 beq.n 80016c6 { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); 8001680: 687b ldr r3, [r7, #4] 8001682: 681b ldr r3, [r3, #0] 8001684: 689a ldr r2, [r3, #8] 8001686: 687b ldr r3, [r7, #4] 8001688: 681b ldr r3, [r3, #0] 800168a: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 800168e: 609a str r2, [r3, #8] hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; 8001690: 687b ldr r3, [r7, #4] 8001692: 681b ldr r3, [r3, #0] 8001694: 6899 ldr r1, [r3, #8] 8001696: 687b ldr r3, [r7, #4] 8001698: 6a9a ldr r2, [r3, #40] ; 0x28 800169a: 687b ldr r3, [r7, #4] 800169c: 681b ldr r3, [r3, #0] 800169e: 430a orrs r2, r1 80016a0: 609a str r2, [r3, #8] /* Select external trigger polarity */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); 80016a2: 687b ldr r3, [r7, #4] 80016a4: 681b ldr r3, [r3, #0] 80016a6: 689a ldr r2, [r3, #8] 80016a8: 687b ldr r3, [r7, #4] 80016aa: 681b ldr r3, [r3, #0] 80016ac: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000 80016b0: 609a str r2, [r3, #8] hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; 80016b2: 687b ldr r3, [r7, #4] 80016b4: 681b ldr r3, [r3, #0] 80016b6: 6899 ldr r1, [r3, #8] 80016b8: 687b ldr r3, [r7, #4] 80016ba: 6ada ldr r2, [r3, #44] ; 0x2c 80016bc: 687b ldr r3, [r7, #4] 80016be: 681b ldr r3, [r3, #0] 80016c0: 430a orrs r2, r1 80016c2: 609a str r2, [r3, #8] 80016c4: e00f b.n 80016e6 } else { /* Reset the external trigger */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); 80016c6: 687b ldr r3, [r7, #4] 80016c8: 681b ldr r3, [r3, #0] 80016ca: 689a ldr r2, [r3, #8] 80016cc: 687b ldr r3, [r7, #4] 80016ce: 681b ldr r3, [r3, #0] 80016d0: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 80016d4: 609a str r2, [r3, #8] hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); 80016d6: 687b ldr r3, [r7, #4] 80016d8: 681b ldr r3, [r3, #0] 80016da: 689a ldr r2, [r3, #8] 80016dc: 687b ldr r3, [r7, #4] 80016de: 681b ldr r3, [r3, #0] 80016e0: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000 80016e4: 609a str r2, [r3, #8] } /* Enable or disable ADC continuous conversion mode */ hadc->Instance->CR2 &= ~(ADC_CR2_CONT); 80016e6: 687b ldr r3, [r7, #4] 80016e8: 681b ldr r3, [r3, #0] 80016ea: 689a ldr r2, [r3, #8] 80016ec: 687b ldr r3, [r7, #4] 80016ee: 681b ldr r3, [r3, #0] 80016f0: f022 0202 bic.w r2, r2, #2 80016f4: 609a str r2, [r3, #8] hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); 80016f6: 687b ldr r3, [r7, #4] 80016f8: 681b ldr r3, [r3, #0] 80016fa: 6899 ldr r1, [r3, #8] 80016fc: 687b ldr r3, [r7, #4] 80016fe: 7e1b ldrb r3, [r3, #24] 8001700: 005a lsls r2, r3, #1 8001702: 687b ldr r3, [r7, #4] 8001704: 681b ldr r3, [r3, #0] 8001706: 430a orrs r2, r1 8001708: 609a str r2, [r3, #8] if(hadc->Init.DiscontinuousConvMode != DISABLE) 800170a: 687b ldr r3, [r7, #4] 800170c: f893 3020 ldrb.w r3, [r3, #32] 8001710: 2b00 cmp r3, #0 8001712: d01b beq.n 800174c { assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); /* Enable the selected ADC regular discontinuous mode */ hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; 8001714: 687b ldr r3, [r7, #4] 8001716: 681b ldr r3, [r3, #0] 8001718: 685a ldr r2, [r3, #4] 800171a: 687b ldr r3, [r7, #4] 800171c: 681b ldr r3, [r3, #0] 800171e: f442 6200 orr.w r2, r2, #2048 ; 0x800 8001722: 605a str r2, [r3, #4] /* Set the number of channels to be converted in discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); 8001724: 687b ldr r3, [r7, #4] 8001726: 681b ldr r3, [r3, #0] 8001728: 685a ldr r2, [r3, #4] 800172a: 687b ldr r3, [r7, #4] 800172c: 681b ldr r3, [r3, #0] 800172e: f422 4260 bic.w r2, r2, #57344 ; 0xe000 8001732: 605a str r2, [r3, #4] hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); 8001734: 687b ldr r3, [r7, #4] 8001736: 681b ldr r3, [r3, #0] 8001738: 6859 ldr r1, [r3, #4] 800173a: 687b ldr r3, [r7, #4] 800173c: 6a5b ldr r3, [r3, #36] ; 0x24 800173e: 3b01 subs r3, #1 8001740: 035a lsls r2, r3, #13 8001742: 687b ldr r3, [r7, #4] 8001744: 681b ldr r3, [r3, #0] 8001746: 430a orrs r2, r1 8001748: 605a str r2, [r3, #4] 800174a: e007 b.n 800175c } else { /* Disable the selected ADC regular discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); 800174c: 687b ldr r3, [r7, #4] 800174e: 681b ldr r3, [r3, #0] 8001750: 685a ldr r2, [r3, #4] 8001752: 687b ldr r3, [r7, #4] 8001754: 681b ldr r3, [r3, #0] 8001756: f422 6200 bic.w r2, r2, #2048 ; 0x800 800175a: 605a str r2, [r3, #4] } /* Set ADC number of conversion */ hadc->Instance->SQR1 &= ~(ADC_SQR1_L); 800175c: 687b ldr r3, [r7, #4] 800175e: 681b ldr r3, [r3, #0] 8001760: 6ada ldr r2, [r3, #44] ; 0x2c 8001762: 687b ldr r3, [r7, #4] 8001764: 681b ldr r3, [r3, #0] 8001766: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000 800176a: 62da str r2, [r3, #44] ; 0x2c hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); 800176c: 687b ldr r3, [r7, #4] 800176e: 681b ldr r3, [r3, #0] 8001770: 6ad9 ldr r1, [r3, #44] ; 0x2c 8001772: 687b ldr r3, [r7, #4] 8001774: 69db ldr r3, [r3, #28] 8001776: 3b01 subs r3, #1 8001778: 051a lsls r2, r3, #20 800177a: 687b ldr r3, [r7, #4] 800177c: 681b ldr r3, [r3, #0] 800177e: 430a orrs r2, r1 8001780: 62da str r2, [r3, #44] ; 0x2c /* Enable or disable ADC DMA continuous request */ hadc->Instance->CR2 &= ~(ADC_CR2_DDS); 8001782: 687b ldr r3, [r7, #4] 8001784: 681b ldr r3, [r3, #0] 8001786: 689a ldr r2, [r3, #8] 8001788: 687b ldr r3, [r7, #4] 800178a: 681b ldr r3, [r3, #0] 800178c: f422 7200 bic.w r2, r2, #512 ; 0x200 8001790: 609a str r2, [r3, #8] hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); 8001792: 687b ldr r3, [r7, #4] 8001794: 681b ldr r3, [r3, #0] 8001796: 6899 ldr r1, [r3, #8] 8001798: 687b ldr r3, [r7, #4] 800179a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 800179e: 025a lsls r2, r3, #9 80017a0: 687b ldr r3, [r7, #4] 80017a2: 681b ldr r3, [r3, #0] 80017a4: 430a orrs r2, r1 80017a6: 609a str r2, [r3, #8] /* Enable or disable ADC end of conversion selection */ hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); 80017a8: 687b ldr r3, [r7, #4] 80017aa: 681b ldr r3, [r3, #0] 80017ac: 689a ldr r2, [r3, #8] 80017ae: 687b ldr r3, [r7, #4] 80017b0: 681b ldr r3, [r3, #0] 80017b2: f422 6280 bic.w r2, r2, #1024 ; 0x400 80017b6: 609a str r2, [r3, #8] hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); 80017b8: 687b ldr r3, [r7, #4] 80017ba: 681b ldr r3, [r3, #0] 80017bc: 6899 ldr r1, [r3, #8] 80017be: 687b ldr r3, [r7, #4] 80017c0: 695b ldr r3, [r3, #20] 80017c2: 029a lsls r2, r3, #10 80017c4: 687b ldr r3, [r7, #4] 80017c6: 681b ldr r3, [r3, #0] 80017c8: 430a orrs r2, r1 80017ca: 609a str r2, [r3, #8] } 80017cc: bf00 nop 80017ce: 3714 adds r7, #20 80017d0: 46bd mov sp, r7 80017d2: f85d 7b04 ldr.w r7, [sp], #4 80017d6: 4770 bx lr 80017d8: 40012300 .word 0x40012300 80017dc: 0f000001 .word 0x0f000001 080017e0 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80017e0: b480 push {r7} 80017e2: b085 sub sp, #20 80017e4: af00 add r7, sp, #0 80017e6: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80017e8: 687b ldr r3, [r7, #4] 80017ea: f003 0307 and.w r3, r3, #7 80017ee: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80017f0: 4b0c ldr r3, [pc, #48] ; (8001824 <__NVIC_SetPriorityGrouping+0x44>) 80017f2: 68db ldr r3, [r3, #12] 80017f4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80017f6: 68ba ldr r2, [r7, #8] 80017f8: f64f 03ff movw r3, #63743 ; 0xf8ff 80017fc: 4013 ands r3, r2 80017fe: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001800: 68fb ldr r3, [r7, #12] 8001802: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001804: 68bb ldr r3, [r7, #8] 8001806: 4313 orrs r3, r2 reg_value = (reg_value | 8001808: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800180c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001810: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001812: 4a04 ldr r2, [pc, #16] ; (8001824 <__NVIC_SetPriorityGrouping+0x44>) 8001814: 68bb ldr r3, [r7, #8] 8001816: 60d3 str r3, [r2, #12] } 8001818: bf00 nop 800181a: 3714 adds r7, #20 800181c: 46bd mov sp, r7 800181e: f85d 7b04 ldr.w r7, [sp], #4 8001822: 4770 bx lr 8001824: e000ed00 .word 0xe000ed00 08001828 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001828: b480 push {r7} 800182a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800182c: 4b04 ldr r3, [pc, #16] ; (8001840 <__NVIC_GetPriorityGrouping+0x18>) 800182e: 68db ldr r3, [r3, #12] 8001830: 0a1b lsrs r3, r3, #8 8001832: f003 0307 and.w r3, r3, #7 } 8001836: 4618 mov r0, r3 8001838: 46bd mov sp, r7 800183a: f85d 7b04 ldr.w r7, [sp], #4 800183e: 4770 bx lr 8001840: e000ed00 .word 0xe000ed00 08001844 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001844: b480 push {r7} 8001846: b083 sub sp, #12 8001848: af00 add r7, sp, #0 800184a: 4603 mov r3, r0 800184c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800184e: f997 3007 ldrsb.w r3, [r7, #7] 8001852: 2b00 cmp r3, #0 8001854: db0b blt.n 800186e <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001856: 79fb ldrb r3, [r7, #7] 8001858: f003 021f and.w r2, r3, #31 800185c: 4907 ldr r1, [pc, #28] ; (800187c <__NVIC_EnableIRQ+0x38>) 800185e: f997 3007 ldrsb.w r3, [r7, #7] 8001862: 095b lsrs r3, r3, #5 8001864: 2001 movs r0, #1 8001866: fa00 f202 lsl.w r2, r0, r2 800186a: f841 2023 str.w r2, [r1, r3, lsl #2] } } 800186e: bf00 nop 8001870: 370c adds r7, #12 8001872: 46bd mov sp, r7 8001874: f85d 7b04 ldr.w r7, [sp], #4 8001878: 4770 bx lr 800187a: bf00 nop 800187c: e000e100 .word 0xe000e100 08001880 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001880: b480 push {r7} 8001882: b083 sub sp, #12 8001884: af00 add r7, sp, #0 8001886: 4603 mov r3, r0 8001888: 6039 str r1, [r7, #0] 800188a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800188c: f997 3007 ldrsb.w r3, [r7, #7] 8001890: 2b00 cmp r3, #0 8001892: db0a blt.n 80018aa <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001894: 683b ldr r3, [r7, #0] 8001896: b2da uxtb r2, r3 8001898: 490c ldr r1, [pc, #48] ; (80018cc <__NVIC_SetPriority+0x4c>) 800189a: f997 3007 ldrsb.w r3, [r7, #7] 800189e: 0112 lsls r2, r2, #4 80018a0: b2d2 uxtb r2, r2 80018a2: 440b add r3, r1 80018a4: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80018a8: e00a b.n 80018c0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80018aa: 683b ldr r3, [r7, #0] 80018ac: b2da uxtb r2, r3 80018ae: 4908 ldr r1, [pc, #32] ; (80018d0 <__NVIC_SetPriority+0x50>) 80018b0: 79fb ldrb r3, [r7, #7] 80018b2: f003 030f and.w r3, r3, #15 80018b6: 3b04 subs r3, #4 80018b8: 0112 lsls r2, r2, #4 80018ba: b2d2 uxtb r2, r2 80018bc: 440b add r3, r1 80018be: 761a strb r2, [r3, #24] } 80018c0: bf00 nop 80018c2: 370c adds r7, #12 80018c4: 46bd mov sp, r7 80018c6: f85d 7b04 ldr.w r7, [sp], #4 80018ca: 4770 bx lr 80018cc: e000e100 .word 0xe000e100 80018d0: e000ed00 .word 0xe000ed00 080018d4 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80018d4: b480 push {r7} 80018d6: b089 sub sp, #36 ; 0x24 80018d8: af00 add r7, sp, #0 80018da: 60f8 str r0, [r7, #12] 80018dc: 60b9 str r1, [r7, #8] 80018de: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80018e0: 68fb ldr r3, [r7, #12] 80018e2: f003 0307 and.w r3, r3, #7 80018e6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80018e8: 69fb ldr r3, [r7, #28] 80018ea: f1c3 0307 rsb r3, r3, #7 80018ee: 2b04 cmp r3, #4 80018f0: bf28 it cs 80018f2: 2304 movcs r3, #4 80018f4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80018f6: 69fb ldr r3, [r7, #28] 80018f8: 3304 adds r3, #4 80018fa: 2b06 cmp r3, #6 80018fc: d902 bls.n 8001904 80018fe: 69fb ldr r3, [r7, #28] 8001900: 3b03 subs r3, #3 8001902: e000 b.n 8001906 8001904: 2300 movs r3, #0 8001906: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001908: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 800190c: 69bb ldr r3, [r7, #24] 800190e: fa02 f303 lsl.w r3, r2, r3 8001912: 43da mvns r2, r3 8001914: 68bb ldr r3, [r7, #8] 8001916: 401a ands r2, r3 8001918: 697b ldr r3, [r7, #20] 800191a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800191c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 8001920: 697b ldr r3, [r7, #20] 8001922: fa01 f303 lsl.w r3, r1, r3 8001926: 43d9 mvns r1, r3 8001928: 687b ldr r3, [r7, #4] 800192a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800192c: 4313 orrs r3, r2 ); } 800192e: 4618 mov r0, r3 8001930: 3724 adds r7, #36 ; 0x24 8001932: 46bd mov sp, r7 8001934: f85d 7b04 ldr.w r7, [sp], #4 8001938: 4770 bx lr ... 0800193c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800193c: b580 push {r7, lr} 800193e: b082 sub sp, #8 8001940: af00 add r7, sp, #0 8001942: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001944: 687b ldr r3, [r7, #4] 8001946: 3b01 subs r3, #1 8001948: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800194c: d301 bcc.n 8001952 { return (1UL); /* Reload value impossible */ 800194e: 2301 movs r3, #1 8001950: e00f b.n 8001972 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001952: 4a0a ldr r2, [pc, #40] ; (800197c ) 8001954: 687b ldr r3, [r7, #4] 8001956: 3b01 subs r3, #1 8001958: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800195a: 210f movs r1, #15 800195c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001960: f7ff ff8e bl 8001880 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001964: 4b05 ldr r3, [pc, #20] ; (800197c ) 8001966: 2200 movs r2, #0 8001968: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800196a: 4b04 ldr r3, [pc, #16] ; (800197c ) 800196c: 2207 movs r2, #7 800196e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001970: 2300 movs r3, #0 } 8001972: 4618 mov r0, r3 8001974: 3708 adds r7, #8 8001976: 46bd mov sp, r7 8001978: bd80 pop {r7, pc} 800197a: bf00 nop 800197c: e000e010 .word 0xe000e010 08001980 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001980: b580 push {r7, lr} 8001982: b082 sub sp, #8 8001984: af00 add r7, sp, #0 8001986: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001988: 6878 ldr r0, [r7, #4] 800198a: f7ff ff29 bl 80017e0 <__NVIC_SetPriorityGrouping> } 800198e: bf00 nop 8001990: 3708 adds r7, #8 8001992: 46bd mov sp, r7 8001994: bd80 pop {r7, pc} 08001996 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001996: b580 push {r7, lr} 8001998: b086 sub sp, #24 800199a: af00 add r7, sp, #0 800199c: 4603 mov r3, r0 800199e: 60b9 str r1, [r7, #8] 80019a0: 607a str r2, [r7, #4] 80019a2: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80019a4: 2300 movs r3, #0 80019a6: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80019a8: f7ff ff3e bl 8001828 <__NVIC_GetPriorityGrouping> 80019ac: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80019ae: 687a ldr r2, [r7, #4] 80019b0: 68b9 ldr r1, [r7, #8] 80019b2: 6978 ldr r0, [r7, #20] 80019b4: f7ff ff8e bl 80018d4 80019b8: 4602 mov r2, r0 80019ba: f997 300f ldrsb.w r3, [r7, #15] 80019be: 4611 mov r1, r2 80019c0: 4618 mov r0, r3 80019c2: f7ff ff5d bl 8001880 <__NVIC_SetPriority> } 80019c6: bf00 nop 80019c8: 3718 adds r7, #24 80019ca: 46bd mov sp, r7 80019cc: bd80 pop {r7, pc} 080019ce : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80019ce: b580 push {r7, lr} 80019d0: b082 sub sp, #8 80019d2: af00 add r7, sp, #0 80019d4: 4603 mov r3, r0 80019d6: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80019d8: f997 3007 ldrsb.w r3, [r7, #7] 80019dc: 4618 mov r0, r3 80019de: f7ff ff31 bl 8001844 <__NVIC_EnableIRQ> } 80019e2: bf00 nop 80019e4: 3708 adds r7, #8 80019e6: 46bd mov sp, r7 80019e8: bd80 pop {r7, pc} 080019ea : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80019ea: b580 push {r7, lr} 80019ec: b082 sub sp, #8 80019ee: af00 add r7, sp, #0 80019f0: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80019f2: 6878 ldr r0, [r7, #4] 80019f4: f7ff ffa2 bl 800193c 80019f8: 4603 mov r3, r0 } 80019fa: 4618 mov r0, r3 80019fc: 3708 adds r7, #8 80019fe: 46bd mov sp, r7 8001a00: bd80 pop {r7, pc} 08001a02 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 8001a02: b580 push {r7, lr} 8001a04: b082 sub sp, #8 8001a06: af00 add r7, sp, #0 8001a08: 6078 str r0, [r7, #4] /* Check DAC handle */ if (hdac == NULL) 8001a0a: 687b ldr r3, [r7, #4] 8001a0c: 2b00 cmp r3, #0 8001a0e: d101 bne.n 8001a14 { return HAL_ERROR; 8001a10: 2301 movs r3, #1 8001a12: e014 b.n 8001a3e } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 8001a14: 687b ldr r3, [r7, #4] 8001a16: 791b ldrb r3, [r3, #4] 8001a18: b2db uxtb r3, r3 8001a1a: 2b00 cmp r3, #0 8001a1c: d105 bne.n 8001a2a hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 8001a1e: 687b ldr r3, [r7, #4] 8001a20: 2200 movs r2, #0 8001a22: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 8001a24: 6878 ldr r0, [r7, #4] 8001a26: f7ff f9a3 bl 8000d70 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 8001a2a: 687b ldr r3, [r7, #4] 8001a2c: 2202 movs r2, #2 8001a2e: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8001a30: 687b ldr r3, [r7, #4] 8001a32: 2200 movs r2, #0 8001a34: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 8001a36: 687b ldr r3, [r7, #4] 8001a38: 2201 movs r2, #1 8001a3a: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 8001a3c: 2300 movs r3, #0 } 8001a3e: 4618 mov r0, r3 8001a40: 3708 adds r7, #8 8001a42: 46bd mov sp, r7 8001a44: bd80 pop {r7, pc} 08001a46 : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 8001a46: b480 push {r7} 8001a48: b087 sub sp, #28 8001a4a: af00 add r7, sp, #0 8001a4c: 60f8 str r0, [r7, #12] 8001a4e: 60b9 str r1, [r7, #8] 8001a50: 607a str r2, [r7, #4] assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8001a52: 68fb ldr r3, [r7, #12] 8001a54: 795b ldrb r3, [r3, #5] 8001a56: 2b01 cmp r3, #1 8001a58: d101 bne.n 8001a5e 8001a5a: 2302 movs r3, #2 8001a5c: e03c b.n 8001ad8 8001a5e: 68fb ldr r3, [r7, #12] 8001a60: 2201 movs r2, #1 8001a62: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8001a64: 68fb ldr r3, [r7, #12] 8001a66: 2202 movs r2, #2 8001a68: 711a strb r2, [r3, #4] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 8001a6a: 68fb ldr r3, [r7, #12] 8001a6c: 681b ldr r3, [r3, #0] 8001a6e: 681b ldr r3, [r3, #0] 8001a70: 617b str r3, [r7, #20] /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL)); 8001a72: 687b ldr r3, [r7, #4] 8001a74: f003 0310 and.w r3, r3, #16 8001a78: f640 72fe movw r2, #4094 ; 0xffe 8001a7c: fa02 f303 lsl.w r3, r2, r3 8001a80: 43db mvns r3, r3 8001a82: 697a ldr r2, [r7, #20] 8001a84: 4013 ands r3, r2 8001a86: 617b str r3, [r7, #20] /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); 8001a88: 68bb ldr r3, [r7, #8] 8001a8a: 681a ldr r2, [r3, #0] 8001a8c: 68bb ldr r3, [r7, #8] 8001a8e: 685b ldr r3, [r3, #4] 8001a90: 4313 orrs r3, r2 8001a92: 613b str r3, [r7, #16] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8001a94: 687b ldr r3, [r7, #4] 8001a96: f003 0310 and.w r3, r3, #16 8001a9a: 693a ldr r2, [r7, #16] 8001a9c: fa02 f303 lsl.w r3, r2, r3 8001aa0: 697a ldr r2, [r7, #20] 8001aa2: 4313 orrs r3, r2 8001aa4: 617b str r3, [r7, #20] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8001aa6: 68fb ldr r3, [r7, #12] 8001aa8: 681b ldr r3, [r3, #0] 8001aaa: 697a ldr r2, [r7, #20] 8001aac: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8001aae: 68fb ldr r3, [r7, #12] 8001ab0: 681b ldr r3, [r3, #0] 8001ab2: 6819 ldr r1, [r3, #0] 8001ab4: 687b ldr r3, [r7, #4] 8001ab6: f003 0310 and.w r3, r3, #16 8001aba: 22c0 movs r2, #192 ; 0xc0 8001abc: fa02 f303 lsl.w r3, r2, r3 8001ac0: 43da mvns r2, r3 8001ac2: 68fb ldr r3, [r7, #12] 8001ac4: 681b ldr r3, [r3, #0] 8001ac6: 400a ands r2, r1 8001ac8: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8001aca: 68fb ldr r3, [r7, #12] 8001acc: 2201 movs r2, #1 8001ace: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8001ad0: 68fb ldr r3, [r7, #12] 8001ad2: 2200 movs r2, #0 8001ad4: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8001ad6: 2300 movs r3, #0 } 8001ad8: 4618 mov r0, r3 8001ada: 371c adds r7, #28 8001adc: 46bd mov sp, r7 8001ade: f85d 7b04 ldr.w r7, [sp], #4 8001ae2: 4770 bx lr 08001ae4 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001ae4: b480 push {r7} 8001ae6: b089 sub sp, #36 ; 0x24 8001ae8: af00 add r7, sp, #0 8001aea: 6078 str r0, [r7, #4] 8001aec: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8001aee: 2300 movs r3, #0 8001af0: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8001af2: 2300 movs r3, #0 8001af4: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8001af6: 2300 movs r3, #0 8001af8: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8001afa: 2300 movs r3, #0 8001afc: 61fb str r3, [r7, #28] 8001afe: e165 b.n 8001dcc { /* Get the IO position */ ioposition = 0x01U << position; 8001b00: 2201 movs r2, #1 8001b02: 69fb ldr r3, [r7, #28] 8001b04: fa02 f303 lsl.w r3, r2, r3 8001b08: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001b0a: 683b ldr r3, [r7, #0] 8001b0c: 681b ldr r3, [r3, #0] 8001b0e: 697a ldr r2, [r7, #20] 8001b10: 4013 ands r3, r2 8001b12: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8001b14: 693a ldr r2, [r7, #16] 8001b16: 697b ldr r3, [r7, #20] 8001b18: 429a cmp r2, r3 8001b1a: f040 8154 bne.w 8001dc6 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001b1e: 683b ldr r3, [r7, #0] 8001b20: 685b ldr r3, [r3, #4] 8001b22: f003 0303 and.w r3, r3, #3 8001b26: 2b01 cmp r3, #1 8001b28: d005 beq.n 8001b36 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001b2a: 683b ldr r3, [r7, #0] 8001b2c: 685b ldr r3, [r3, #4] 8001b2e: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001b32: 2b02 cmp r3, #2 8001b34: d130 bne.n 8001b98 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001b36: 687b ldr r3, [r7, #4] 8001b38: 689b ldr r3, [r3, #8] 8001b3a: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8001b3c: 69fb ldr r3, [r7, #28] 8001b3e: 005b lsls r3, r3, #1 8001b40: 2203 movs r2, #3 8001b42: fa02 f303 lsl.w r3, r2, r3 8001b46: 43db mvns r3, r3 8001b48: 69ba ldr r2, [r7, #24] 8001b4a: 4013 ands r3, r2 8001b4c: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8001b4e: 683b ldr r3, [r7, #0] 8001b50: 68da ldr r2, [r3, #12] 8001b52: 69fb ldr r3, [r7, #28] 8001b54: 005b lsls r3, r3, #1 8001b56: fa02 f303 lsl.w r3, r2, r3 8001b5a: 69ba ldr r2, [r7, #24] 8001b5c: 4313 orrs r3, r2 8001b5e: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8001b60: 687b ldr r3, [r7, #4] 8001b62: 69ba ldr r2, [r7, #24] 8001b64: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001b66: 687b ldr r3, [r7, #4] 8001b68: 685b ldr r3, [r3, #4] 8001b6a: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8001b6c: 2201 movs r2, #1 8001b6e: 69fb ldr r3, [r7, #28] 8001b70: fa02 f303 lsl.w r3, r2, r3 8001b74: 43db mvns r3, r3 8001b76: 69ba ldr r2, [r7, #24] 8001b78: 4013 ands r3, r2 8001b7a: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001b7c: 683b ldr r3, [r7, #0] 8001b7e: 685b ldr r3, [r3, #4] 8001b80: 091b lsrs r3, r3, #4 8001b82: f003 0201 and.w r2, r3, #1 8001b86: 69fb ldr r3, [r7, #28] 8001b88: fa02 f303 lsl.w r3, r2, r3 8001b8c: 69ba ldr r2, [r7, #24] 8001b8e: 4313 orrs r3, r2 8001b90: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8001b92: 687b ldr r3, [r7, #4] 8001b94: 69ba ldr r2, [r7, #24] 8001b96: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001b98: 683b ldr r3, [r7, #0] 8001b9a: 685b ldr r3, [r3, #4] 8001b9c: f003 0303 and.w r3, r3, #3 8001ba0: 2b03 cmp r3, #3 8001ba2: d017 beq.n 8001bd4 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001ba4: 687b ldr r3, [r7, #4] 8001ba6: 68db ldr r3, [r3, #12] 8001ba8: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8001baa: 69fb ldr r3, [r7, #28] 8001bac: 005b lsls r3, r3, #1 8001bae: 2203 movs r2, #3 8001bb0: fa02 f303 lsl.w r3, r2, r3 8001bb4: 43db mvns r3, r3 8001bb6: 69ba ldr r2, [r7, #24] 8001bb8: 4013 ands r3, r2 8001bba: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001bbc: 683b ldr r3, [r7, #0] 8001bbe: 689a ldr r2, [r3, #8] 8001bc0: 69fb ldr r3, [r7, #28] 8001bc2: 005b lsls r3, r3, #1 8001bc4: fa02 f303 lsl.w r3, r2, r3 8001bc8: 69ba ldr r2, [r7, #24] 8001bca: 4313 orrs r3, r2 8001bcc: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8001bce: 687b ldr r3, [r7, #4] 8001bd0: 69ba ldr r2, [r7, #24] 8001bd2: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001bd4: 683b ldr r3, [r7, #0] 8001bd6: 685b ldr r3, [r3, #4] 8001bd8: f003 0303 and.w r3, r3, #3 8001bdc: 2b02 cmp r3, #2 8001bde: d123 bne.n 8001c28 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001be0: 69fb ldr r3, [r7, #28] 8001be2: 08da lsrs r2, r3, #3 8001be4: 687b ldr r3, [r7, #4] 8001be6: 3208 adds r2, #8 8001be8: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001bec: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8001bee: 69fb ldr r3, [r7, #28] 8001bf0: f003 0307 and.w r3, r3, #7 8001bf4: 009b lsls r3, r3, #2 8001bf6: 220f movs r2, #15 8001bf8: fa02 f303 lsl.w r3, r2, r3 8001bfc: 43db mvns r3, r3 8001bfe: 69ba ldr r2, [r7, #24] 8001c00: 4013 ands r3, r2 8001c02: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8001c04: 683b ldr r3, [r7, #0] 8001c06: 691a ldr r2, [r3, #16] 8001c08: 69fb ldr r3, [r7, #28] 8001c0a: f003 0307 and.w r3, r3, #7 8001c0e: 009b lsls r3, r3, #2 8001c10: fa02 f303 lsl.w r3, r2, r3 8001c14: 69ba ldr r2, [r7, #24] 8001c16: 4313 orrs r3, r2 8001c18: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001c1a: 69fb ldr r3, [r7, #28] 8001c1c: 08da lsrs r2, r3, #3 8001c1e: 687b ldr r3, [r7, #4] 8001c20: 3208 adds r2, #8 8001c22: 69b9 ldr r1, [r7, #24] 8001c24: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001c28: 687b ldr r3, [r7, #4] 8001c2a: 681b ldr r3, [r3, #0] 8001c2c: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8001c2e: 69fb ldr r3, [r7, #28] 8001c30: 005b lsls r3, r3, #1 8001c32: 2203 movs r2, #3 8001c34: fa02 f303 lsl.w r3, r2, r3 8001c38: 43db mvns r3, r3 8001c3a: 69ba ldr r2, [r7, #24] 8001c3c: 4013 ands r3, r2 8001c3e: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001c40: 683b ldr r3, [r7, #0] 8001c42: 685b ldr r3, [r3, #4] 8001c44: f003 0203 and.w r2, r3, #3 8001c48: 69fb ldr r3, [r7, #28] 8001c4a: 005b lsls r3, r3, #1 8001c4c: fa02 f303 lsl.w r3, r2, r3 8001c50: 69ba ldr r2, [r7, #24] 8001c52: 4313 orrs r3, r2 8001c54: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001c56: 687b ldr r3, [r7, #4] 8001c58: 69ba ldr r2, [r7, #24] 8001c5a: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001c5c: 683b ldr r3, [r7, #0] 8001c5e: 685b ldr r3, [r3, #4] 8001c60: f403 3340 and.w r3, r3, #196608 ; 0x30000 8001c64: 2b00 cmp r3, #0 8001c66: f000 80ae beq.w 8001dc6 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001c6a: 2300 movs r3, #0 8001c6c: 60fb str r3, [r7, #12] 8001c6e: 4b5d ldr r3, [pc, #372] ; (8001de4 ) 8001c70: 6c5b ldr r3, [r3, #68] ; 0x44 8001c72: 4a5c ldr r2, [pc, #368] ; (8001de4 ) 8001c74: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8001c78: 6453 str r3, [r2, #68] ; 0x44 8001c7a: 4b5a ldr r3, [pc, #360] ; (8001de4 ) 8001c7c: 6c5b ldr r3, [r3, #68] ; 0x44 8001c7e: f403 4380 and.w r3, r3, #16384 ; 0x4000 8001c82: 60fb str r3, [r7, #12] 8001c84: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001c86: 4a58 ldr r2, [pc, #352] ; (8001de8 ) 8001c88: 69fb ldr r3, [r7, #28] 8001c8a: 089b lsrs r3, r3, #2 8001c8c: 3302 adds r3, #2 8001c8e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001c92: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8001c94: 69fb ldr r3, [r7, #28] 8001c96: f003 0303 and.w r3, r3, #3 8001c9a: 009b lsls r3, r3, #2 8001c9c: 220f movs r2, #15 8001c9e: fa02 f303 lsl.w r3, r2, r3 8001ca2: 43db mvns r3, r3 8001ca4: 69ba ldr r2, [r7, #24] 8001ca6: 4013 ands r3, r2 8001ca8: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8001caa: 687b ldr r3, [r7, #4] 8001cac: 4a4f ldr r2, [pc, #316] ; (8001dec ) 8001cae: 4293 cmp r3, r2 8001cb0: d025 beq.n 8001cfe 8001cb2: 687b ldr r3, [r7, #4] 8001cb4: 4a4e ldr r2, [pc, #312] ; (8001df0 ) 8001cb6: 4293 cmp r3, r2 8001cb8: d01f beq.n 8001cfa 8001cba: 687b ldr r3, [r7, #4] 8001cbc: 4a4d ldr r2, [pc, #308] ; (8001df4 ) 8001cbe: 4293 cmp r3, r2 8001cc0: d019 beq.n 8001cf6 8001cc2: 687b ldr r3, [r7, #4] 8001cc4: 4a4c ldr r2, [pc, #304] ; (8001df8 ) 8001cc6: 4293 cmp r3, r2 8001cc8: d013 beq.n 8001cf2 8001cca: 687b ldr r3, [r7, #4] 8001ccc: 4a4b ldr r2, [pc, #300] ; (8001dfc ) 8001cce: 4293 cmp r3, r2 8001cd0: d00d beq.n 8001cee 8001cd2: 687b ldr r3, [r7, #4] 8001cd4: 4a4a ldr r2, [pc, #296] ; (8001e00 ) 8001cd6: 4293 cmp r3, r2 8001cd8: d007 beq.n 8001cea 8001cda: 687b ldr r3, [r7, #4] 8001cdc: 4a49 ldr r2, [pc, #292] ; (8001e04 ) 8001cde: 4293 cmp r3, r2 8001ce0: d101 bne.n 8001ce6 8001ce2: 2306 movs r3, #6 8001ce4: e00c b.n 8001d00 8001ce6: 2307 movs r3, #7 8001ce8: e00a b.n 8001d00 8001cea: 2305 movs r3, #5 8001cec: e008 b.n 8001d00 8001cee: 2304 movs r3, #4 8001cf0: e006 b.n 8001d00 8001cf2: 2303 movs r3, #3 8001cf4: e004 b.n 8001d00 8001cf6: 2302 movs r3, #2 8001cf8: e002 b.n 8001d00 8001cfa: 2301 movs r3, #1 8001cfc: e000 b.n 8001d00 8001cfe: 2300 movs r3, #0 8001d00: 69fa ldr r2, [r7, #28] 8001d02: f002 0203 and.w r2, r2, #3 8001d06: 0092 lsls r2, r2, #2 8001d08: 4093 lsls r3, r2 8001d0a: 69ba ldr r2, [r7, #24] 8001d0c: 4313 orrs r3, r2 8001d0e: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8001d10: 4935 ldr r1, [pc, #212] ; (8001de8 ) 8001d12: 69fb ldr r3, [r7, #28] 8001d14: 089b lsrs r3, r3, #2 8001d16: 3302 adds r3, #2 8001d18: 69ba ldr r2, [r7, #24] 8001d1a: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8001d1e: 4b3a ldr r3, [pc, #232] ; (8001e08 ) 8001d20: 681b ldr r3, [r3, #0] 8001d22: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001d24: 693b ldr r3, [r7, #16] 8001d26: 43db mvns r3, r3 8001d28: 69ba ldr r2, [r7, #24] 8001d2a: 4013 ands r3, r2 8001d2c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001d2e: 683b ldr r3, [r7, #0] 8001d30: 685b ldr r3, [r3, #4] 8001d32: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001d36: 2b00 cmp r3, #0 8001d38: d003 beq.n 8001d42 { temp |= iocurrent; 8001d3a: 69ba ldr r2, [r7, #24] 8001d3c: 693b ldr r3, [r7, #16] 8001d3e: 4313 orrs r3, r2 8001d40: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8001d42: 4a31 ldr r2, [pc, #196] ; (8001e08 ) 8001d44: 69bb ldr r3, [r7, #24] 8001d46: 6013 str r3, [r2, #0] temp = EXTI->EMR; 8001d48: 4b2f ldr r3, [pc, #188] ; (8001e08 ) 8001d4a: 685b ldr r3, [r3, #4] 8001d4c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001d4e: 693b ldr r3, [r7, #16] 8001d50: 43db mvns r3, r3 8001d52: 69ba ldr r2, [r7, #24] 8001d54: 4013 ands r3, r2 8001d56: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001d58: 683b ldr r3, [r7, #0] 8001d5a: 685b ldr r3, [r3, #4] 8001d5c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001d60: 2b00 cmp r3, #0 8001d62: d003 beq.n 8001d6c { temp |= iocurrent; 8001d64: 69ba ldr r2, [r7, #24] 8001d66: 693b ldr r3, [r7, #16] 8001d68: 4313 orrs r3, r2 8001d6a: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8001d6c: 4a26 ldr r2, [pc, #152] ; (8001e08 ) 8001d6e: 69bb ldr r3, [r7, #24] 8001d70: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8001d72: 4b25 ldr r3, [pc, #148] ; (8001e08 ) 8001d74: 689b ldr r3, [r3, #8] 8001d76: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001d78: 693b ldr r3, [r7, #16] 8001d7a: 43db mvns r3, r3 8001d7c: 69ba ldr r2, [r7, #24] 8001d7e: 4013 ands r3, r2 8001d80: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001d82: 683b ldr r3, [r7, #0] 8001d84: 685b ldr r3, [r3, #4] 8001d86: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001d8a: 2b00 cmp r3, #0 8001d8c: d003 beq.n 8001d96 { temp |= iocurrent; 8001d8e: 69ba ldr r2, [r7, #24] 8001d90: 693b ldr r3, [r7, #16] 8001d92: 4313 orrs r3, r2 8001d94: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8001d96: 4a1c ldr r2, [pc, #112] ; (8001e08 ) 8001d98: 69bb ldr r3, [r7, #24] 8001d9a: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8001d9c: 4b1a ldr r3, [pc, #104] ; (8001e08 ) 8001d9e: 68db ldr r3, [r3, #12] 8001da0: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001da2: 693b ldr r3, [r7, #16] 8001da4: 43db mvns r3, r3 8001da6: 69ba ldr r2, [r7, #24] 8001da8: 4013 ands r3, r2 8001daa: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001dac: 683b ldr r3, [r7, #0] 8001dae: 685b ldr r3, [r3, #4] 8001db0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8001db4: 2b00 cmp r3, #0 8001db6: d003 beq.n 8001dc0 { temp |= iocurrent; 8001db8: 69ba ldr r2, [r7, #24] 8001dba: 693b ldr r3, [r7, #16] 8001dbc: 4313 orrs r3, r2 8001dbe: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8001dc0: 4a11 ldr r2, [pc, #68] ; (8001e08 ) 8001dc2: 69bb ldr r3, [r7, #24] 8001dc4: 60d3 str r3, [r2, #12] for(position = 0U; position < GPIO_NUMBER; position++) 8001dc6: 69fb ldr r3, [r7, #28] 8001dc8: 3301 adds r3, #1 8001dca: 61fb str r3, [r7, #28] 8001dcc: 69fb ldr r3, [r7, #28] 8001dce: 2b0f cmp r3, #15 8001dd0: f67f ae96 bls.w 8001b00 } } } } 8001dd4: bf00 nop 8001dd6: bf00 nop 8001dd8: 3724 adds r7, #36 ; 0x24 8001dda: 46bd mov sp, r7 8001ddc: f85d 7b04 ldr.w r7, [sp], #4 8001de0: 4770 bx lr 8001de2: bf00 nop 8001de4: 40023800 .word 0x40023800 8001de8: 40013800 .word 0x40013800 8001dec: 40020000 .word 0x40020000 8001df0: 40020400 .word 0x40020400 8001df4: 40020800 .word 0x40020800 8001df8: 40020c00 .word 0x40020c00 8001dfc: 40021000 .word 0x40021000 8001e00: 40021400 .word 0x40021400 8001e04: 40021800 .word 0x40021800 8001e08: 40013c00 .word 0x40013c00 08001e0c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001e0c: b480 push {r7} 8001e0e: b083 sub sp, #12 8001e10: af00 add r7, sp, #0 8001e12: 6078 str r0, [r7, #4] 8001e14: 460b mov r3, r1 8001e16: 807b strh r3, [r7, #2] 8001e18: 4613 mov r3, r2 8001e1a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8001e1c: 787b ldrb r3, [r7, #1] 8001e1e: 2b00 cmp r3, #0 8001e20: d003 beq.n 8001e2a { GPIOx->BSRR = GPIO_Pin; 8001e22: 887a ldrh r2, [r7, #2] 8001e24: 687b ldr r3, [r7, #4] 8001e26: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8001e28: e003 b.n 8001e32 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8001e2a: 887b ldrh r3, [r7, #2] 8001e2c: 041a lsls r2, r3, #16 8001e2e: 687b ldr r3, [r7, #4] 8001e30: 619a str r2, [r3, #24] } 8001e32: bf00 nop 8001e34: 370c adds r7, #12 8001e36: 46bd mov sp, r7 8001e38: f85d 7b04 ldr.w r7, [sp], #4 8001e3c: 4770 bx lr 08001e3e : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { 8001e3e: b5f0 push {r4, r5, r6, r7, lr} 8001e40: b08f sub sp, #60 ; 0x3c 8001e42: af0a add r7, sp, #40 ; 0x28 8001e44: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx; uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) 8001e46: 687b ldr r3, [r7, #4] 8001e48: 2b00 cmp r3, #0 8001e4a: d101 bne.n 8001e50 { return HAL_ERROR; 8001e4c: 2301 movs r3, #1 8001e4e: e116 b.n 800207e } /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); USBx = hpcd->Instance; 8001e50: 687b ldr r3, [r7, #4] 8001e52: 681b ldr r3, [r3, #0] 8001e54: 60bb str r3, [r7, #8] if (hpcd->State == HAL_PCD_STATE_RESET) 8001e56: 687b ldr r3, [r7, #4] 8001e58: f893 33bd ldrb.w r3, [r3, #957] ; 0x3bd 8001e5c: b2db uxtb r3, r3 8001e5e: 2b00 cmp r3, #0 8001e60: d106 bne.n 8001e70 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; 8001e62: 687b ldr r3, [r7, #4] 8001e64: 2200 movs r2, #0 8001e66: f883 23bc strb.w r2, [r3, #956] ; 0x3bc /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); 8001e6a: 6878 ldr r0, [r7, #4] 8001e6c: f006 fcbc bl 80087e8 #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; 8001e70: 687b ldr r3, [r7, #4] 8001e72: 2203 movs r2, #3 8001e74: f883 23bd strb.w r2, [r3, #957] ; 0x3bd /* Disable DMA mode for FS instance */ if ((USBx->CID & (0x1U << 8)) == 0U) 8001e78: 68bb ldr r3, [r7, #8] 8001e7a: 6bdb ldr r3, [r3, #60] ; 0x3c 8001e7c: f403 7380 and.w r3, r3, #256 ; 0x100 8001e80: 2b00 cmp r3, #0 8001e82: d102 bne.n 8001e8a { hpcd->Init.dma_enable = 0U; 8001e84: 687b ldr r3, [r7, #4] 8001e86: 2200 movs r2, #0 8001e88: 611a str r2, [r3, #16] } /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 681b ldr r3, [r3, #0] 8001e8e: 4618 mov r0, r3 8001e90: f003 fbcf bl 8005632 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) 8001e94: 687b ldr r3, [r7, #4] 8001e96: 681b ldr r3, [r3, #0] 8001e98: 603b str r3, [r7, #0] 8001e9a: 687e ldr r6, [r7, #4] 8001e9c: 466d mov r5, sp 8001e9e: f106 0410 add.w r4, r6, #16 8001ea2: cc0f ldmia r4!, {r0, r1, r2, r3} 8001ea4: c50f stmia r5!, {r0, r1, r2, r3} 8001ea6: cc0f ldmia r4!, {r0, r1, r2, r3} 8001ea8: c50f stmia r5!, {r0, r1, r2, r3} 8001eaa: e894 0003 ldmia.w r4, {r0, r1} 8001eae: e885 0003 stmia.w r5, {r0, r1} 8001eb2: 1d33 adds r3, r6, #4 8001eb4: cb0e ldmia r3, {r1, r2, r3} 8001eb6: 6838 ldr r0, [r7, #0] 8001eb8: f003 faa6 bl 8005408 8001ebc: 4603 mov r3, r0 8001ebe: 2b00 cmp r3, #0 8001ec0: d005 beq.n 8001ece { hpcd->State = HAL_PCD_STATE_ERROR; 8001ec2: 687b ldr r3, [r7, #4] 8001ec4: 2202 movs r2, #2 8001ec6: f883 23bd strb.w r2, [r3, #957] ; 0x3bd return HAL_ERROR; 8001eca: 2301 movs r3, #1 8001ecc: e0d7 b.n 800207e } /* Force Device Mode*/ (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); 8001ece: 687b ldr r3, [r7, #4] 8001ed0: 681b ldr r3, [r3, #0] 8001ed2: 2100 movs r1, #0 8001ed4: 4618 mov r0, r3 8001ed6: f003 fbbd bl 8005654 /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001eda: 2300 movs r3, #0 8001edc: 73fb strb r3, [r7, #15] 8001ede: e04a b.n 8001f76 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; 8001ee0: 7bfa ldrb r2, [r7, #15] 8001ee2: 6879 ldr r1, [r7, #4] 8001ee4: 4613 mov r3, r2 8001ee6: 00db lsls r3, r3, #3 8001ee8: 1a9b subs r3, r3, r2 8001eea: 009b lsls r3, r3, #2 8001eec: 440b add r3, r1 8001eee: 333d adds r3, #61 ; 0x3d 8001ef0: 2201 movs r2, #1 8001ef2: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; 8001ef4: 7bfa ldrb r2, [r7, #15] 8001ef6: 6879 ldr r1, [r7, #4] 8001ef8: 4613 mov r3, r2 8001efa: 00db lsls r3, r3, #3 8001efc: 1a9b subs r3, r3, r2 8001efe: 009b lsls r3, r3, #2 8001f00: 440b add r3, r1 8001f02: 333c adds r3, #60 ; 0x3c 8001f04: 7bfa ldrb r2, [r7, #15] 8001f06: 701a strb r2, [r3, #0] hpcd->IN_ep[i].tx_fifo_num = i; 8001f08: 7bfa ldrb r2, [r7, #15] 8001f0a: 7bfb ldrb r3, [r7, #15] 8001f0c: b298 uxth r0, r3 8001f0e: 6879 ldr r1, [r7, #4] 8001f10: 4613 mov r3, r2 8001f12: 00db lsls r3, r3, #3 8001f14: 1a9b subs r3, r3, r2 8001f16: 009b lsls r3, r3, #2 8001f18: 440b add r3, r1 8001f1a: 3342 adds r3, #66 ; 0x42 8001f1c: 4602 mov r2, r0 8001f1e: 801a strh r2, [r3, #0] /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; 8001f20: 7bfa ldrb r2, [r7, #15] 8001f22: 6879 ldr r1, [r7, #4] 8001f24: 4613 mov r3, r2 8001f26: 00db lsls r3, r3, #3 8001f28: 1a9b subs r3, r3, r2 8001f2a: 009b lsls r3, r3, #2 8001f2c: 440b add r3, r1 8001f2e: 333f adds r3, #63 ; 0x3f 8001f30: 2200 movs r2, #0 8001f32: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; 8001f34: 7bfa ldrb r2, [r7, #15] 8001f36: 6879 ldr r1, [r7, #4] 8001f38: 4613 mov r3, r2 8001f3a: 00db lsls r3, r3, #3 8001f3c: 1a9b subs r3, r3, r2 8001f3e: 009b lsls r3, r3, #2 8001f40: 440b add r3, r1 8001f42: 3344 adds r3, #68 ; 0x44 8001f44: 2200 movs r2, #0 8001f46: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; 8001f48: 7bfa ldrb r2, [r7, #15] 8001f4a: 6879 ldr r1, [r7, #4] 8001f4c: 4613 mov r3, r2 8001f4e: 00db lsls r3, r3, #3 8001f50: 1a9b subs r3, r3, r2 8001f52: 009b lsls r3, r3, #2 8001f54: 440b add r3, r1 8001f56: 3348 adds r3, #72 ; 0x48 8001f58: 2200 movs r2, #0 8001f5a: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; 8001f5c: 7bfa ldrb r2, [r7, #15] 8001f5e: 6879 ldr r1, [r7, #4] 8001f60: 4613 mov r3, r2 8001f62: 00db lsls r3, r3, #3 8001f64: 1a9b subs r3, r3, r2 8001f66: 009b lsls r3, r3, #2 8001f68: 440b add r3, r1 8001f6a: 3350 adds r3, #80 ; 0x50 8001f6c: 2200 movs r2, #0 8001f6e: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001f70: 7bfb ldrb r3, [r7, #15] 8001f72: 3301 adds r3, #1 8001f74: 73fb strb r3, [r7, #15] 8001f76: 7bfa ldrb r2, [r7, #15] 8001f78: 687b ldr r3, [r7, #4] 8001f7a: 685b ldr r3, [r3, #4] 8001f7c: 429a cmp r2, r3 8001f7e: d3af bcc.n 8001ee0 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8001f80: 2300 movs r3, #0 8001f82: 73fb strb r3, [r7, #15] 8001f84: e044 b.n 8002010 { hpcd->OUT_ep[i].is_in = 0U; 8001f86: 7bfa ldrb r2, [r7, #15] 8001f88: 6879 ldr r1, [r7, #4] 8001f8a: 4613 mov r3, r2 8001f8c: 00db lsls r3, r3, #3 8001f8e: 1a9b subs r3, r3, r2 8001f90: 009b lsls r3, r3, #2 8001f92: 440b add r3, r1 8001f94: f203 13fd addw r3, r3, #509 ; 0x1fd 8001f98: 2200 movs r2, #0 8001f9a: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; 8001f9c: 7bfa ldrb r2, [r7, #15] 8001f9e: 6879 ldr r1, [r7, #4] 8001fa0: 4613 mov r3, r2 8001fa2: 00db lsls r3, r3, #3 8001fa4: 1a9b subs r3, r3, r2 8001fa6: 009b lsls r3, r3, #2 8001fa8: 440b add r3, r1 8001faa: f503 73fe add.w r3, r3, #508 ; 0x1fc 8001fae: 7bfa ldrb r2, [r7, #15] 8001fb0: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; 8001fb2: 7bfa ldrb r2, [r7, #15] 8001fb4: 6879 ldr r1, [r7, #4] 8001fb6: 4613 mov r3, r2 8001fb8: 00db lsls r3, r3, #3 8001fba: 1a9b subs r3, r3, r2 8001fbc: 009b lsls r3, r3, #2 8001fbe: 440b add r3, r1 8001fc0: f203 13ff addw r3, r3, #511 ; 0x1ff 8001fc4: 2200 movs r2, #0 8001fc6: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; 8001fc8: 7bfa ldrb r2, [r7, #15] 8001fca: 6879 ldr r1, [r7, #4] 8001fcc: 4613 mov r3, r2 8001fce: 00db lsls r3, r3, #3 8001fd0: 1a9b subs r3, r3, r2 8001fd2: 009b lsls r3, r3, #2 8001fd4: 440b add r3, r1 8001fd6: f503 7301 add.w r3, r3, #516 ; 0x204 8001fda: 2200 movs r2, #0 8001fdc: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; 8001fde: 7bfa ldrb r2, [r7, #15] 8001fe0: 6879 ldr r1, [r7, #4] 8001fe2: 4613 mov r3, r2 8001fe4: 00db lsls r3, r3, #3 8001fe6: 1a9b subs r3, r3, r2 8001fe8: 009b lsls r3, r3, #2 8001fea: 440b add r3, r1 8001fec: f503 7302 add.w r3, r3, #520 ; 0x208 8001ff0: 2200 movs r2, #0 8001ff2: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; 8001ff4: 7bfa ldrb r2, [r7, #15] 8001ff6: 6879 ldr r1, [r7, #4] 8001ff8: 4613 mov r3, r2 8001ffa: 00db lsls r3, r3, #3 8001ffc: 1a9b subs r3, r3, r2 8001ffe: 009b lsls r3, r3, #2 8002000: 440b add r3, r1 8002002: f503 7304 add.w r3, r3, #528 ; 0x210 8002006: 2200 movs r2, #0 8002008: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 800200a: 7bfb ldrb r3, [r7, #15] 800200c: 3301 adds r3, #1 800200e: 73fb strb r3, [r7, #15] 8002010: 7bfa ldrb r2, [r7, #15] 8002012: 687b ldr r3, [r7, #4] 8002014: 685b ldr r3, [r3, #4] 8002016: 429a cmp r2, r3 8002018: d3b5 bcc.n 8001f86 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) 800201a: 687b ldr r3, [r7, #4] 800201c: 681b ldr r3, [r3, #0] 800201e: 603b str r3, [r7, #0] 8002020: 687e ldr r6, [r7, #4] 8002022: 466d mov r5, sp 8002024: f106 0410 add.w r4, r6, #16 8002028: cc0f ldmia r4!, {r0, r1, r2, r3} 800202a: c50f stmia r5!, {r0, r1, r2, r3} 800202c: cc0f ldmia r4!, {r0, r1, r2, r3} 800202e: c50f stmia r5!, {r0, r1, r2, r3} 8002030: e894 0003 ldmia.w r4, {r0, r1} 8002034: e885 0003 stmia.w r5, {r0, r1} 8002038: 1d33 adds r3, r6, #4 800203a: cb0e ldmia r3, {r1, r2, r3} 800203c: 6838 ldr r0, [r7, #0] 800203e: f003 fb55 bl 80056ec 8002042: 4603 mov r3, r0 8002044: 2b00 cmp r3, #0 8002046: d005 beq.n 8002054 { hpcd->State = HAL_PCD_STATE_ERROR; 8002048: 687b ldr r3, [r7, #4] 800204a: 2202 movs r2, #2 800204c: f883 23bd strb.w r2, [r3, #957] ; 0x3bd return HAL_ERROR; 8002050: 2301 movs r3, #1 8002052: e014 b.n 800207e } hpcd->USB_Address = 0U; 8002054: 687b ldr r3, [r7, #4] 8002056: 2200 movs r2, #0 8002058: f883 2038 strb.w r2, [r3, #56] ; 0x38 hpcd->State = HAL_PCD_STATE_READY; 800205c: 687b ldr r3, [r7, #4] 800205e: 2201 movs r2, #1 8002060: f883 23bd strb.w r2, [r3, #957] ; 0x3bd #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) 8002064: 687b ldr r3, [r7, #4] 8002066: 6a5b ldr r3, [r3, #36] ; 0x24 8002068: 2b01 cmp r3, #1 800206a: d102 bne.n 8002072 { (void)HAL_PCDEx_ActivateLPM(hpcd); 800206c: 6878 ldr r0, [r7, #4] 800206e: f001 f891 bl 8003194 } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ (void)USB_DevDisconnect(hpcd->Instance); 8002072: 687b ldr r3, [r7, #4] 8002074: 681b ldr r3, [r3, #0] 8002076: 4618 mov r0, r3 8002078: f004 fbc4 bl 8006804 return HAL_OK; 800207c: 2300 movs r3, #0 } 800207e: 4618 mov r0, r3 8002080: 3714 adds r7, #20 8002082: 46bd mov sp, r7 8002084: bdf0 pop {r4, r5, r6, r7, pc} 08002086 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { 8002086: b580 push {r7, lr} 8002088: b084 sub sp, #16 800208a: af00 add r7, sp, #0 800208c: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800208e: 687b ldr r3, [r7, #4] 8002090: 681b ldr r3, [r3, #0] 8002092: 60fb str r3, [r7, #12] __HAL_LOCK(hpcd); 8002094: 687b ldr r3, [r7, #4] 8002096: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 800209a: 2b01 cmp r3, #1 800209c: d101 bne.n 80020a2 800209e: 2302 movs r3, #2 80020a0: e020 b.n 80020e4 80020a2: 687b ldr r3, [r7, #4] 80020a4: 2201 movs r2, #1 80020a6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc if ((hpcd->Init.battery_charging_enable == 1U) && 80020aa: 687b ldr r3, [r7, #4] 80020ac: 6a9b ldr r3, [r3, #40] ; 0x28 80020ae: 2b01 cmp r3, #1 80020b0: d109 bne.n 80020c6 (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) 80020b2: 687b ldr r3, [r7, #4] 80020b4: 699b ldr r3, [r3, #24] if ((hpcd->Init.battery_charging_enable == 1U) && 80020b6: 2b01 cmp r3, #1 80020b8: d005 beq.n 80020c6 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 80020ba: 68fb ldr r3, [r7, #12] 80020bc: 6b9b ldr r3, [r3, #56] ; 0x38 80020be: f443 3280 orr.w r2, r3, #65536 ; 0x10000 80020c2: 68fb ldr r3, [r7, #12] 80020c4: 639a str r2, [r3, #56] ; 0x38 } __HAL_PCD_ENABLE(hpcd); 80020c6: 687b ldr r3, [r7, #4] 80020c8: 681b ldr r3, [r3, #0] 80020ca: 4618 mov r0, r3 80020cc: f003 faa0 bl 8005610 (void)USB_DevConnect(hpcd->Instance); 80020d0: 687b ldr r3, [r7, #4] 80020d2: 681b ldr r3, [r3, #0] 80020d4: 4618 mov r0, r3 80020d6: f004 fb74 bl 80067c2 __HAL_UNLOCK(hpcd); 80020da: 687b ldr r3, [r7, #4] 80020dc: 2200 movs r2, #0 80020de: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 80020e2: 2300 movs r3, #0 } 80020e4: 4618 mov r0, r3 80020e6: 3710 adds r7, #16 80020e8: 46bd mov sp, r7 80020ea: bd80 pop {r7, pc} 080020ec : * @brief Handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { 80020ec: b590 push {r4, r7, lr} 80020ee: b08d sub sp, #52 ; 0x34 80020f0: af00 add r7, sp, #0 80020f2: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 80020f4: 687b ldr r3, [r7, #4] 80020f6: 681b ldr r3, [r3, #0] 80020f8: 623b str r3, [r7, #32] uint32_t USBx_BASE = (uint32_t)USBx; 80020fa: 6a3b ldr r3, [r7, #32] 80020fc: 61fb str r3, [r7, #28] uint32_t epnum; uint32_t fifoemptymsk; uint32_t temp; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) 80020fe: 687b ldr r3, [r7, #4] 8002100: 681b ldr r3, [r3, #0] 8002102: 4618 mov r0, r3 8002104: f004 fc32 bl 800696c 8002108: 4603 mov r3, r0 800210a: 2b00 cmp r3, #0 800210c: f040 83ca bne.w 80028a4 { /* avoid spurious interrupt */ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 8002110: 687b ldr r3, [r7, #4] 8002112: 681b ldr r3, [r3, #0] 8002114: 4618 mov r0, r3 8002116: f004 fb96 bl 8006846 800211a: 4603 mov r3, r0 800211c: 2b00 cmp r3, #0 800211e: f000 83c0 beq.w 80028a2 { return; } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) 8002122: 687b ldr r3, [r7, #4] 8002124: 681b ldr r3, [r3, #0] 8002126: 4618 mov r0, r3 8002128: f004 fb8d bl 8006846 800212c: 4603 mov r3, r0 800212e: f003 0302 and.w r3, r3, #2 8002132: 2b02 cmp r3, #2 8002134: d107 bne.n 8002146 { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); 8002136: 687b ldr r3, [r7, #4] 8002138: 681b ldr r3, [r3, #0] 800213a: 695a ldr r2, [r3, #20] 800213c: 687b ldr r3, [r7, #4] 800213e: 681b ldr r3, [r3, #0] 8002140: f002 0202 and.w r2, r2, #2 8002144: 615a str r2, [r3, #20] } /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) 8002146: 687b ldr r3, [r7, #4] 8002148: 681b ldr r3, [r3, #0] 800214a: 4618 mov r0, r3 800214c: f004 fb7b bl 8006846 8002150: 4603 mov r3, r0 8002152: f003 0310 and.w r3, r3, #16 8002156: 2b10 cmp r3, #16 8002158: d161 bne.n 800221e { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 800215a: 687b ldr r3, [r7, #4] 800215c: 681b ldr r3, [r3, #0] 800215e: 699a ldr r2, [r3, #24] 8002160: 687b ldr r3, [r7, #4] 8002162: 681b ldr r3, [r3, #0] 8002164: f022 0210 bic.w r2, r2, #16 8002168: 619a str r2, [r3, #24] temp = USBx->GRXSTSP; 800216a: 6a3b ldr r3, [r7, #32] 800216c: 6a1b ldr r3, [r3, #32] 800216e: 61bb str r3, [r7, #24] ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; 8002170: 69bb ldr r3, [r7, #24] 8002172: f003 020f and.w r2, r3, #15 8002176: 4613 mov r3, r2 8002178: 00db lsls r3, r3, #3 800217a: 1a9b subs r3, r3, r2 800217c: 009b lsls r3, r3, #2 800217e: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002182: 687a ldr r2, [r7, #4] 8002184: 4413 add r3, r2 8002186: 3304 adds r3, #4 8002188: 617b str r3, [r7, #20] if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) 800218a: 69bb ldr r3, [r7, #24] 800218c: 0c5b lsrs r3, r3, #17 800218e: f003 030f and.w r3, r3, #15 8002192: 2b02 cmp r3, #2 8002194: d124 bne.n 80021e0 { if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) 8002196: 69ba ldr r2, [r7, #24] 8002198: f647 73f0 movw r3, #32752 ; 0x7ff0 800219c: 4013 ands r3, r2 800219e: 2b00 cmp r3, #0 80021a0: d035 beq.n 800220e { (void)USB_ReadPacket(USBx, ep->xfer_buff, 80021a2: 697b ldr r3, [r7, #20] 80021a4: 68d9 ldr r1, [r3, #12] (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); 80021a6: 69bb ldr r3, [r7, #24] 80021a8: 091b lsrs r3, r3, #4 80021aa: b29b uxth r3, r3 (void)USB_ReadPacket(USBx, ep->xfer_buff, 80021ac: f3c3 030a ubfx r3, r3, #0, #11 80021b0: b29b uxth r3, r3 80021b2: 461a mov r2, r3 80021b4: 6a38 ldr r0, [r7, #32] 80021b6: f004 f9b2 bl 800651e ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 80021ba: 697b ldr r3, [r7, #20] 80021bc: 68da ldr r2, [r3, #12] 80021be: 69bb ldr r3, [r7, #24] 80021c0: 091b lsrs r3, r3, #4 80021c2: f3c3 030a ubfx r3, r3, #0, #11 80021c6: 441a add r2, r3 80021c8: 697b ldr r3, [r7, #20] 80021ca: 60da str r2, [r3, #12] ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 80021cc: 697b ldr r3, [r7, #20] 80021ce: 699a ldr r2, [r3, #24] 80021d0: 69bb ldr r3, [r7, #24] 80021d2: 091b lsrs r3, r3, #4 80021d4: f3c3 030a ubfx r3, r3, #0, #11 80021d8: 441a add r2, r3 80021da: 697b ldr r3, [r7, #20] 80021dc: 619a str r2, [r3, #24] 80021de: e016 b.n 800220e } } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) 80021e0: 69bb ldr r3, [r7, #24] 80021e2: 0c5b lsrs r3, r3, #17 80021e4: f003 030f and.w r3, r3, #15 80021e8: 2b06 cmp r3, #6 80021ea: d110 bne.n 800220e { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); 80021ec: 687b ldr r3, [r7, #4] 80021ee: f503 7371 add.w r3, r3, #964 ; 0x3c4 80021f2: 2208 movs r2, #8 80021f4: 4619 mov r1, r3 80021f6: 6a38 ldr r0, [r7, #32] 80021f8: f004 f991 bl 800651e ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; 80021fc: 697b ldr r3, [r7, #20] 80021fe: 699a ldr r2, [r3, #24] 8002200: 69bb ldr r3, [r7, #24] 8002202: 091b lsrs r3, r3, #4 8002204: f3c3 030a ubfx r3, r3, #0, #11 8002208: 441a add r2, r3 800220a: 697b ldr r3, [r7, #20] 800220c: 619a str r2, [r3, #24] } else { /* ... */ } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); 800220e: 687b ldr r3, [r7, #4] 8002210: 681b ldr r3, [r3, #0] 8002212: 699a ldr r2, [r3, #24] 8002214: 687b ldr r3, [r7, #4] 8002216: 681b ldr r3, [r3, #0] 8002218: f042 0210 orr.w r2, r2, #16 800221c: 619a str r2, [r3, #24] } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) 800221e: 687b ldr r3, [r7, #4] 8002220: 681b ldr r3, [r3, #0] 8002222: 4618 mov r0, r3 8002224: f004 fb0f bl 8006846 8002228: 4603 mov r3, r0 800222a: f403 2300 and.w r3, r3, #524288 ; 0x80000 800222e: f5b3 2f00 cmp.w r3, #524288 ; 0x80000 8002232: d16e bne.n 8002312 { epnum = 0U; 8002234: 2300 movs r3, #0 8002236: 627b str r3, [r7, #36] ; 0x24 /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); 8002238: 687b ldr r3, [r7, #4] 800223a: 681b ldr r3, [r3, #0] 800223c: 4618 mov r0, r3 800223e: f004 fb15 bl 800686c 8002242: 62b8 str r0, [r7, #40] ; 0x28 while (ep_intr != 0U) 8002244: e062 b.n 800230c { if ((ep_intr & 0x1U) != 0U) 8002246: 6abb ldr r3, [r7, #40] ; 0x28 8002248: f003 0301 and.w r3, r3, #1 800224c: 2b00 cmp r3, #0 800224e: d057 beq.n 8002300 { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002250: 687b ldr r3, [r7, #4] 8002252: 681b ldr r3, [r3, #0] 8002254: 6a7a ldr r2, [r7, #36] ; 0x24 8002256: b2d2 uxtb r2, r2 8002258: 4611 mov r1, r2 800225a: 4618 mov r0, r3 800225c: f004 fb3a bl 80068d4 8002260: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) 8002262: 693b ldr r3, [r7, #16] 8002264: f003 0301 and.w r3, r3, #1 8002268: 2b00 cmp r3, #0 800226a: d00c beq.n 8002286 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); 800226c: 6a7b ldr r3, [r7, #36] ; 0x24 800226e: 015a lsls r2, r3, #5 8002270: 69fb ldr r3, [r7, #28] 8002272: 4413 add r3, r2 8002274: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002278: 461a mov r2, r3 800227a: 2301 movs r3, #1 800227c: 6093 str r3, [r2, #8] (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); 800227e: 6a79 ldr r1, [r7, #36] ; 0x24 8002280: 6878 ldr r0, [r7, #4] 8002282: f000 fddd bl 8002e40 } if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) 8002286: 693b ldr r3, [r7, #16] 8002288: f003 0308 and.w r3, r3, #8 800228c: 2b00 cmp r3, #0 800228e: d00c beq.n 80022aa { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); 8002290: 6a7b ldr r3, [r7, #36] ; 0x24 8002292: 015a lsls r2, r3, #5 8002294: 69fb ldr r3, [r7, #28] 8002296: 4413 add r3, r2 8002298: f503 6330 add.w r3, r3, #2816 ; 0xb00 800229c: 461a mov r2, r3 800229e: 2308 movs r3, #8 80022a0: 6093 str r3, [r2, #8] /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); 80022a2: 6a79 ldr r1, [r7, #36] ; 0x24 80022a4: 6878 ldr r0, [r7, #4] 80022a6: f000 fed7 bl 8003058 } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) 80022aa: 693b ldr r3, [r7, #16] 80022ac: f003 0310 and.w r3, r3, #16 80022b0: 2b00 cmp r3, #0 80022b2: d008 beq.n 80022c6 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); 80022b4: 6a7b ldr r3, [r7, #36] ; 0x24 80022b6: 015a lsls r2, r3, #5 80022b8: 69fb ldr r3, [r7, #28] 80022ba: 4413 add r3, r2 80022bc: f503 6330 add.w r3, r3, #2816 ; 0xb00 80022c0: 461a mov r2, r3 80022c2: 2310 movs r3, #16 80022c4: 6093 str r3, [r2, #8] } /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 80022c6: 693b ldr r3, [r7, #16] 80022c8: f003 0320 and.w r3, r3, #32 80022cc: 2b00 cmp r3, #0 80022ce: d008 beq.n 80022e2 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 80022d0: 6a7b ldr r3, [r7, #36] ; 0x24 80022d2: 015a lsls r2, r3, #5 80022d4: 69fb ldr r3, [r7, #28] 80022d6: 4413 add r3, r2 80022d8: f503 6330 add.w r3, r3, #2816 ; 0xb00 80022dc: 461a mov r2, r3 80022de: 2320 movs r3, #32 80022e0: 6093 str r3, [r2, #8] } /* Clear OUT NAK interrupt */ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) 80022e2: 693b ldr r3, [r7, #16] 80022e4: f403 5300 and.w r3, r3, #8192 ; 0x2000 80022e8: 2b00 cmp r3, #0 80022ea: d009 beq.n 8002300 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); 80022ec: 6a7b ldr r3, [r7, #36] ; 0x24 80022ee: 015a lsls r2, r3, #5 80022f0: 69fb ldr r3, [r7, #28] 80022f2: 4413 add r3, r2 80022f4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80022f8: 461a mov r2, r3 80022fa: f44f 5300 mov.w r3, #8192 ; 0x2000 80022fe: 6093 str r3, [r2, #8] } } epnum++; 8002300: 6a7b ldr r3, [r7, #36] ; 0x24 8002302: 3301 adds r3, #1 8002304: 627b str r3, [r7, #36] ; 0x24 ep_intr >>= 1U; 8002306: 6abb ldr r3, [r7, #40] ; 0x28 8002308: 085b lsrs r3, r3, #1 800230a: 62bb str r3, [r7, #40] ; 0x28 while (ep_intr != 0U) 800230c: 6abb ldr r3, [r7, #40] ; 0x28 800230e: 2b00 cmp r3, #0 8002310: d199 bne.n 8002246 } } if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) 8002312: 687b ldr r3, [r7, #4] 8002314: 681b ldr r3, [r3, #0] 8002316: 4618 mov r0, r3 8002318: f004 fa95 bl 8006846 800231c: 4603 mov r3, r0 800231e: f403 2380 and.w r3, r3, #262144 ; 0x40000 8002322: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 8002326: f040 80c0 bne.w 80024aa { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); 800232a: 687b ldr r3, [r7, #4] 800232c: 681b ldr r3, [r3, #0] 800232e: 4618 mov r0, r3 8002330: f004 fab6 bl 80068a0 8002334: 62b8 str r0, [r7, #40] ; 0x28 epnum = 0U; 8002336: 2300 movs r3, #0 8002338: 627b str r3, [r7, #36] ; 0x24 while (ep_intr != 0U) 800233a: e0b2 b.n 80024a2 { if ((ep_intr & 0x1U) != 0U) /* In ITR */ 800233c: 6abb ldr r3, [r7, #40] ; 0x28 800233e: f003 0301 and.w r3, r3, #1 8002342: 2b00 cmp r3, #0 8002344: f000 80a7 beq.w 8002496 { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); 8002348: 687b ldr r3, [r7, #4] 800234a: 681b ldr r3, [r3, #0] 800234c: 6a7a ldr r2, [r7, #36] ; 0x24 800234e: b2d2 uxtb r2, r2 8002350: 4611 mov r1, r2 8002352: 4618 mov r0, r3 8002354: f004 fadc bl 8006910 8002358: 6138 str r0, [r7, #16] if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) 800235a: 693b ldr r3, [r7, #16] 800235c: f003 0301 and.w r3, r3, #1 8002360: 2b00 cmp r3, #0 8002362: d057 beq.n 8002414 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8002364: 6a7b ldr r3, [r7, #36] ; 0x24 8002366: f003 030f and.w r3, r3, #15 800236a: 2201 movs r2, #1 800236c: fa02 f303 lsl.w r3, r2, r3 8002370: 60fb str r3, [r7, #12] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8002372: 69fb ldr r3, [r7, #28] 8002374: f503 6300 add.w r3, r3, #2048 ; 0x800 8002378: 6b5a ldr r2, [r3, #52] ; 0x34 800237a: 68fb ldr r3, [r7, #12] 800237c: 43db mvns r3, r3 800237e: 69f9 ldr r1, [r7, #28] 8002380: f501 6100 add.w r1, r1, #2048 ; 0x800 8002384: 4013 ands r3, r2 8002386: 634b str r3, [r1, #52] ; 0x34 CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); 8002388: 6a7b ldr r3, [r7, #36] ; 0x24 800238a: 015a lsls r2, r3, #5 800238c: 69fb ldr r3, [r7, #28] 800238e: 4413 add r3, r2 8002390: f503 6310 add.w r3, r3, #2304 ; 0x900 8002394: 461a mov r2, r3 8002396: 2301 movs r3, #1 8002398: 6093 str r3, [r2, #8] if (hpcd->Init.dma_enable == 1U) 800239a: 687b ldr r3, [r7, #4] 800239c: 691b ldr r3, [r3, #16] 800239e: 2b01 cmp r3, #1 80023a0: d132 bne.n 8002408 { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 80023a2: 6879 ldr r1, [r7, #4] 80023a4: 6a7a ldr r2, [r7, #36] ; 0x24 80023a6: 4613 mov r3, r2 80023a8: 00db lsls r3, r3, #3 80023aa: 1a9b subs r3, r3, r2 80023ac: 009b lsls r3, r3, #2 80023ae: 440b add r3, r1 80023b0: 3348 adds r3, #72 ; 0x48 80023b2: 6819 ldr r1, [r3, #0] 80023b4: 6878 ldr r0, [r7, #4] 80023b6: 6a7a ldr r2, [r7, #36] ; 0x24 80023b8: 4613 mov r3, r2 80023ba: 00db lsls r3, r3, #3 80023bc: 1a9b subs r3, r3, r2 80023be: 009b lsls r3, r3, #2 80023c0: 4403 add r3, r0 80023c2: 3344 adds r3, #68 ; 0x44 80023c4: 681b ldr r3, [r3, #0] 80023c6: 4419 add r1, r3 80023c8: 6878 ldr r0, [r7, #4] 80023ca: 6a7a ldr r2, [r7, #36] ; 0x24 80023cc: 4613 mov r3, r2 80023ce: 00db lsls r3, r3, #3 80023d0: 1a9b subs r3, r3, r2 80023d2: 009b lsls r3, r3, #2 80023d4: 4403 add r3, r0 80023d6: 3348 adds r3, #72 ; 0x48 80023d8: 6019 str r1, [r3, #0] /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) 80023da: 6a7b ldr r3, [r7, #36] ; 0x24 80023dc: 2b00 cmp r3, #0 80023de: d113 bne.n 8002408 80023e0: 6879 ldr r1, [r7, #4] 80023e2: 6a7a ldr r2, [r7, #36] ; 0x24 80023e4: 4613 mov r3, r2 80023e6: 00db lsls r3, r3, #3 80023e8: 1a9b subs r3, r3, r2 80023ea: 009b lsls r3, r3, #2 80023ec: 440b add r3, r1 80023ee: 3350 adds r3, #80 ; 0x50 80023f0: 681b ldr r3, [r3, #0] 80023f2: 2b00 cmp r3, #0 80023f4: d108 bne.n 8002408 { /* prepare to rx more setup packets */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 80023f6: 687b ldr r3, [r7, #4] 80023f8: 6818 ldr r0, [r3, #0] 80023fa: 687b ldr r3, [r7, #4] 80023fc: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002400: 461a mov r2, r3 8002402: 2101 movs r1, #1 8002404: f004 fae4 bl 80069d0 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); 8002408: 6a7b ldr r3, [r7, #36] ; 0x24 800240a: b2db uxtb r3, r3 800240c: 4619 mov r1, r3 800240e: 6878 ldr r0, [r7, #4] 8002410: f006 fa8d bl 800892e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) 8002414: 693b ldr r3, [r7, #16] 8002416: f003 0308 and.w r3, r3, #8 800241a: 2b00 cmp r3, #0 800241c: d008 beq.n 8002430 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); 800241e: 6a7b ldr r3, [r7, #36] ; 0x24 8002420: 015a lsls r2, r3, #5 8002422: 69fb ldr r3, [r7, #28] 8002424: 4413 add r3, r2 8002426: f503 6310 add.w r3, r3, #2304 ; 0x900 800242a: 461a mov r2, r3 800242c: 2308 movs r3, #8 800242e: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) 8002430: 693b ldr r3, [r7, #16] 8002432: f003 0310 and.w r3, r3, #16 8002436: 2b00 cmp r3, #0 8002438: d008 beq.n 800244c { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); 800243a: 6a7b ldr r3, [r7, #36] ; 0x24 800243c: 015a lsls r2, r3, #5 800243e: 69fb ldr r3, [r7, #28] 8002440: 4413 add r3, r2 8002442: f503 6310 add.w r3, r3, #2304 ; 0x900 8002446: 461a mov r2, r3 8002448: 2310 movs r3, #16 800244a: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) 800244c: 693b ldr r3, [r7, #16] 800244e: f003 0340 and.w r3, r3, #64 ; 0x40 8002452: 2b00 cmp r3, #0 8002454: d008 beq.n 8002468 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); 8002456: 6a7b ldr r3, [r7, #36] ; 0x24 8002458: 015a lsls r2, r3, #5 800245a: 69fb ldr r3, [r7, #28] 800245c: 4413 add r3, r2 800245e: f503 6310 add.w r3, r3, #2304 ; 0x900 8002462: 461a mov r2, r3 8002464: 2340 movs r3, #64 ; 0x40 8002466: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) 8002468: 693b ldr r3, [r7, #16] 800246a: f003 0302 and.w r3, r3, #2 800246e: 2b00 cmp r3, #0 8002470: d008 beq.n 8002484 { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); 8002472: 6a7b ldr r3, [r7, #36] ; 0x24 8002474: 015a lsls r2, r3, #5 8002476: 69fb ldr r3, [r7, #28] 8002478: 4413 add r3, r2 800247a: f503 6310 add.w r3, r3, #2304 ; 0x900 800247e: 461a mov r2, r3 8002480: 2302 movs r3, #2 8002482: 6093 str r3, [r2, #8] } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) 8002484: 693b ldr r3, [r7, #16] 8002486: f003 0380 and.w r3, r3, #128 ; 0x80 800248a: 2b00 cmp r3, #0 800248c: d003 beq.n 8002496 { (void)PCD_WriteEmptyTxFifo(hpcd, epnum); 800248e: 6a79 ldr r1, [r7, #36] ; 0x24 8002490: 6878 ldr r0, [r7, #4] 8002492: f000 fc48 bl 8002d26 } } epnum++; 8002496: 6a7b ldr r3, [r7, #36] ; 0x24 8002498: 3301 adds r3, #1 800249a: 627b str r3, [r7, #36] ; 0x24 ep_intr >>= 1U; 800249c: 6abb ldr r3, [r7, #40] ; 0x28 800249e: 085b lsrs r3, r3, #1 80024a0: 62bb str r3, [r7, #40] ; 0x28 while (ep_intr != 0U) 80024a2: 6abb ldr r3, [r7, #40] ; 0x28 80024a4: 2b00 cmp r3, #0 80024a6: f47f af49 bne.w 800233c } } /* Handle Resume Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) 80024aa: 687b ldr r3, [r7, #4] 80024ac: 681b ldr r3, [r3, #0] 80024ae: 4618 mov r0, r3 80024b0: f004 f9c9 bl 8006846 80024b4: 4603 mov r3, r0 80024b6: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 80024ba: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 80024be: d122 bne.n 8002506 { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80024c0: 69fb ldr r3, [r7, #28] 80024c2: f503 6300 add.w r3, r3, #2048 ; 0x800 80024c6: 685b ldr r3, [r3, #4] 80024c8: 69fa ldr r2, [r7, #28] 80024ca: f502 6200 add.w r2, r2, #2048 ; 0x800 80024ce: f023 0301 bic.w r3, r3, #1 80024d2: 6053 str r3, [r2, #4] if (hpcd->LPM_State == LPM_L1) 80024d4: 687b ldr r3, [r7, #4] 80024d6: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4 80024da: 2b01 cmp r3, #1 80024dc: d108 bne.n 80024f0 { hpcd->LPM_State = LPM_L0; 80024de: 687b ldr r3, [r7, #4] 80024e0: 2200 movs r2, #0 80024e2: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); 80024e6: 2100 movs r1, #0 80024e8: 6878 ldr r0, [r7, #4] 80024ea: f006 fc6f bl 8008dcc 80024ee: e002 b.n 80024f6 else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); 80024f0: 6878 ldr r0, [r7, #4] 80024f2: f006 fa93 bl 8008a1c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); 80024f6: 687b ldr r3, [r7, #4] 80024f8: 681b ldr r3, [r3, #0] 80024fa: 695a ldr r2, [r3, #20] 80024fc: 687b ldr r3, [r7, #4] 80024fe: 681b ldr r3, [r3, #0] 8002500: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000 8002504: 615a str r2, [r3, #20] } /* Handle Suspend Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) 8002506: 687b ldr r3, [r7, #4] 8002508: 681b ldr r3, [r3, #0] 800250a: 4618 mov r0, r3 800250c: f004 f99b bl 8006846 8002510: 4603 mov r3, r0 8002512: f403 6300 and.w r3, r3, #2048 ; 0x800 8002516: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800251a: d112 bne.n 8002542 { if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 800251c: 69fb ldr r3, [r7, #28] 800251e: f503 6300 add.w r3, r3, #2048 ; 0x800 8002522: 689b ldr r3, [r3, #8] 8002524: f003 0301 and.w r3, r3, #1 8002528: 2b01 cmp r3, #1 800252a: d102 bne.n 8002532 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 800252c: 6878 ldr r0, [r7, #4] 800252e: f006 fa4f bl 80089d0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); 8002532: 687b ldr r3, [r7, #4] 8002534: 681b ldr r3, [r3, #0] 8002536: 695a ldr r2, [r3, #20] 8002538: 687b ldr r3, [r7, #4] 800253a: 681b ldr r3, [r3, #0] 800253c: f402 6200 and.w r2, r2, #2048 ; 0x800 8002540: 615a str r2, [r3, #20] } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) 8002542: 687b ldr r3, [r7, #4] 8002544: 681b ldr r3, [r3, #0] 8002546: 4618 mov r0, r3 8002548: f004 f97d bl 8006846 800254c: 4603 mov r3, r0 800254e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8002552: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8002556: d121 bne.n 800259c { __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); 8002558: 687b ldr r3, [r7, #4] 800255a: 681b ldr r3, [r3, #0] 800255c: 695a ldr r2, [r3, #20] 800255e: 687b ldr r3, [r7, #4] 8002560: 681b ldr r3, [r3, #0] 8002562: f002 6200 and.w r2, r2, #134217728 ; 0x8000000 8002566: 615a str r2, [r3, #20] if (hpcd->LPM_State == LPM_L0) 8002568: 687b ldr r3, [r7, #4] 800256a: f893 33f4 ldrb.w r3, [r3, #1012] ; 0x3f4 800256e: 2b00 cmp r3, #0 8002570: d111 bne.n 8002596 { hpcd->LPM_State = LPM_L1; 8002572: 687b ldr r3, [r7, #4] 8002574: 2201 movs r2, #1 8002576: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; 800257a: 687b ldr r3, [r7, #4] 800257c: 681b ldr r3, [r3, #0] 800257e: 6d5b ldr r3, [r3, #84] ; 0x54 8002580: 089b lsrs r3, r3, #2 8002582: f003 020f and.w r2, r3, #15 8002586: 687b ldr r3, [r7, #4] 8002588: f8c3 23f8 str.w r2, [r3, #1016] ; 0x3f8 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); 800258c: 2101 movs r1, #1 800258e: 6878 ldr r0, [r7, #4] 8002590: f006 fc1c bl 8008dcc 8002594: e002 b.n 800259c else { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); 8002596: 6878 ldr r0, [r7, #4] 8002598: f006 fa1a bl 80089d0 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) 800259c: 687b ldr r3, [r7, #4] 800259e: 681b ldr r3, [r3, #0] 80025a0: 4618 mov r0, r3 80025a2: f004 f950 bl 8006846 80025a6: 4603 mov r3, r0 80025a8: f403 5380 and.w r3, r3, #4096 ; 0x1000 80025ac: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80025b0: f040 80c7 bne.w 8002742 { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 80025b4: 69fb ldr r3, [r7, #28] 80025b6: f503 6300 add.w r3, r3, #2048 ; 0x800 80025ba: 685b ldr r3, [r3, #4] 80025bc: 69fa ldr r2, [r7, #28] 80025be: f502 6200 add.w r2, r2, #2048 ; 0x800 80025c2: f023 0301 bic.w r3, r3, #1 80025c6: 6053 str r3, [r2, #4] (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); 80025c8: 687b ldr r3, [r7, #4] 80025ca: 681b ldr r3, [r3, #0] 80025cc: 2110 movs r1, #16 80025ce: 4618 mov r0, r3 80025d0: f003 f9ea bl 80059a8 for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 80025d4: 2300 movs r3, #0 80025d6: 62fb str r3, [r7, #44] ; 0x2c 80025d8: e056 b.n 8002688 { USBx_INEP(i)->DIEPINT = 0xFB7FU; 80025da: 6afb ldr r3, [r7, #44] ; 0x2c 80025dc: 015a lsls r2, r3, #5 80025de: 69fb ldr r3, [r7, #28] 80025e0: 4413 add r3, r2 80025e2: f503 6310 add.w r3, r3, #2304 ; 0x900 80025e6: 461a mov r2, r3 80025e8: f64f 337f movw r3, #64383 ; 0xfb7f 80025ec: 6093 str r3, [r2, #8] USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 80025ee: 6afb ldr r3, [r7, #44] ; 0x2c 80025f0: 015a lsls r2, r3, #5 80025f2: 69fb ldr r3, [r7, #28] 80025f4: 4413 add r3, r2 80025f6: f503 6310 add.w r3, r3, #2304 ; 0x900 80025fa: 681b ldr r3, [r3, #0] 80025fc: 6afa ldr r2, [r7, #44] ; 0x2c 80025fe: 0151 lsls r1, r2, #5 8002600: 69fa ldr r2, [r7, #28] 8002602: 440a add r2, r1 8002604: f502 6210 add.w r2, r2, #2304 ; 0x900 8002608: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 800260c: 6013 str r3, [r2, #0] USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 800260e: 6afb ldr r3, [r7, #44] ; 0x2c 8002610: 015a lsls r2, r3, #5 8002612: 69fb ldr r3, [r7, #28] 8002614: 4413 add r3, r2 8002616: f503 6310 add.w r3, r3, #2304 ; 0x900 800261a: 681b ldr r3, [r3, #0] 800261c: 6afa ldr r2, [r7, #44] ; 0x2c 800261e: 0151 lsls r1, r2, #5 8002620: 69fa ldr r2, [r7, #28] 8002622: 440a add r2, r1 8002624: f502 6210 add.w r2, r2, #2304 ; 0x900 8002628: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 800262c: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 800262e: 6afb ldr r3, [r7, #44] ; 0x2c 8002630: 015a lsls r2, r3, #5 8002632: 69fb ldr r3, [r7, #28] 8002634: 4413 add r3, r2 8002636: f503 6330 add.w r3, r3, #2816 ; 0xb00 800263a: 461a mov r2, r3 800263c: f64f 337f movw r3, #64383 ; 0xfb7f 8002640: 6093 str r3, [r2, #8] USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8002642: 6afb ldr r3, [r7, #44] ; 0x2c 8002644: 015a lsls r2, r3, #5 8002646: 69fb ldr r3, [r7, #28] 8002648: 4413 add r3, r2 800264a: f503 6330 add.w r3, r3, #2816 ; 0xb00 800264e: 681b ldr r3, [r3, #0] 8002650: 6afa ldr r2, [r7, #44] ; 0x2c 8002652: 0151 lsls r1, r2, #5 8002654: 69fa ldr r2, [r7, #28] 8002656: 440a add r2, r1 8002658: f502 6230 add.w r2, r2, #2816 ; 0xb00 800265c: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 8002660: 6013 str r3, [r2, #0] USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8002662: 6afb ldr r3, [r7, #44] ; 0x2c 8002664: 015a lsls r2, r3, #5 8002666: 69fb ldr r3, [r7, #28] 8002668: 4413 add r3, r2 800266a: f503 6330 add.w r3, r3, #2816 ; 0xb00 800266e: 681b ldr r3, [r3, #0] 8002670: 6afa ldr r2, [r7, #44] ; 0x2c 8002672: 0151 lsls r1, r2, #5 8002674: 69fa ldr r2, [r7, #28] 8002676: 440a add r2, r1 8002678: f502 6230 add.w r2, r2, #2816 ; 0xb00 800267c: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8002680: 6013 str r3, [r2, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) 8002682: 6afb ldr r3, [r7, #44] ; 0x2c 8002684: 3301 adds r3, #1 8002686: 62fb str r3, [r7, #44] ; 0x2c 8002688: 687b ldr r3, [r7, #4] 800268a: 685b ldr r3, [r3, #4] 800268c: 6afa ldr r2, [r7, #44] ; 0x2c 800268e: 429a cmp r2, r3 8002690: d3a3 bcc.n 80025da } USBx_DEVICE->DAINTMSK |= 0x10001U; 8002692: 69fb ldr r3, [r7, #28] 8002694: f503 6300 add.w r3, r3, #2048 ; 0x800 8002698: 69db ldr r3, [r3, #28] 800269a: 69fa ldr r2, [r7, #28] 800269c: f502 6200 add.w r2, r2, #2048 ; 0x800 80026a0: f043 1301 orr.w r3, r3, #65537 ; 0x10001 80026a4: 61d3 str r3, [r2, #28] if (hpcd->Init.use_dedicated_ep1 != 0U) 80026a6: 687b ldr r3, [r7, #4] 80026a8: 6b1b ldr r3, [r3, #48] ; 0x30 80026aa: 2b00 cmp r3, #0 80026ac: d016 beq.n 80026dc { USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | 80026ae: 69fb ldr r3, [r7, #28] 80026b0: f503 6300 add.w r3, r3, #2048 ; 0x800 80026b4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80026b8: 69fa ldr r2, [r7, #28] 80026ba: f502 6200 add.w r2, r2, #2048 ; 0x800 80026be: f043 030b orr.w r3, r3, #11 80026c2: f8c2 3084 str.w r3, [r2, #132] ; 0x84 USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM; USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | 80026c6: 69fb ldr r3, [r7, #28] 80026c8: f503 6300 add.w r3, r3, #2048 ; 0x800 80026cc: 6c5b ldr r3, [r3, #68] ; 0x44 80026ce: 69fa ldr r2, [r7, #28] 80026d0: f502 6200 add.w r2, r2, #2048 ; 0x800 80026d4: f043 030b orr.w r3, r3, #11 80026d8: 6453 str r3, [r2, #68] ; 0x44 80026da: e015 b.n 8002708 USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } else { USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | 80026dc: 69fb ldr r3, [r7, #28] 80026de: f503 6300 add.w r3, r3, #2048 ; 0x800 80026e2: 695b ldr r3, [r3, #20] 80026e4: 69fa ldr r2, [r7, #28] 80026e6: f502 6200 add.w r2, r2, #2048 ; 0x800 80026ea: f443 5300 orr.w r3, r3, #8192 ; 0x2000 80026ee: f043 032b orr.w r3, r3, #43 ; 0x2b 80026f2: 6153 str r3, [r2, #20] USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM | USB_OTG_DOEPMSK_NAKM; USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | 80026f4: 69fb ldr r3, [r7, #28] 80026f6: f503 6300 add.w r3, r3, #2048 ; 0x800 80026fa: 691b ldr r3, [r3, #16] 80026fc: 69fa ldr r2, [r7, #28] 80026fe: f502 6200 add.w r2, r2, #2048 ; 0x800 8002702: f043 030b orr.w r3, r3, #11 8002706: 6113 str r3, [r2, #16] USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM; } /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; 8002708: 69fb ldr r3, [r7, #28] 800270a: f503 6300 add.w r3, r3, #2048 ; 0x800 800270e: 681b ldr r3, [r3, #0] 8002710: 69fa ldr r2, [r7, #28] 8002712: f502 6200 add.w r2, r2, #2048 ; 0x800 8002716: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 800271a: 6013 str r3, [r2, #0] /* setup EP0 to receive SETUP packets */ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 800271c: 687b ldr r3, [r7, #4] 800271e: 6818 ldr r0, [r3, #0] 8002720: 687b ldr r3, [r7, #4] 8002722: 691b ldr r3, [r3, #16] 8002724: b2d9 uxtb r1, r3 (uint8_t *)hpcd->Setup); 8002726: 687b ldr r3, [r7, #4] 8002728: f503 7371 add.w r3, r3, #964 ; 0x3c4 (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, 800272c: 461a mov r2, r3 800272e: f004 f94f bl 80069d0 __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); 8002732: 687b ldr r3, [r7, #4] 8002734: 681b ldr r3, [r3, #0] 8002736: 695a ldr r2, [r3, #20] 8002738: 687b ldr r3, [r7, #4] 800273a: 681b ldr r3, [r3, #0] 800273c: f402 5280 and.w r2, r2, #4096 ; 0x1000 8002740: 615a str r2, [r3, #20] } /* Handle Enumeration done Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) 8002742: 687b ldr r3, [r7, #4] 8002744: 681b ldr r3, [r3, #0] 8002746: 4618 mov r0, r3 8002748: f004 f87d bl 8006846 800274c: 4603 mov r3, r0 800274e: f403 5300 and.w r3, r3, #8192 ; 0x2000 8002752: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8002756: d124 bne.n 80027a2 { (void)USB_ActivateSetup(hpcd->Instance); 8002758: 687b ldr r3, [r7, #4] 800275a: 681b ldr r3, [r3, #0] 800275c: 4618 mov r0, r3 800275e: f004 f913 bl 8006988 hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); 8002762: 687b ldr r3, [r7, #4] 8002764: 681b ldr r3, [r3, #0] 8002766: 4618 mov r0, r3 8002768: f003 f97b bl 8005a62 800276c: 4603 mov r3, r0 800276e: 461a mov r2, r3 8002770: 687b ldr r3, [r7, #4] 8002772: 60da str r2, [r3, #12] /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, 8002774: 687b ldr r3, [r7, #4] 8002776: 681c ldr r4, [r3, #0] 8002778: f000 fe16 bl 80033a8 800277c: 4601 mov r1, r0 HAL_RCC_GetHCLKFreq(), (uint8_t)hpcd->Init.speed); 800277e: 687b ldr r3, [r7, #4] 8002780: 68db ldr r3, [r3, #12] (void)USB_SetTurnaroundTime(hpcd->Instance, 8002782: b2db uxtb r3, r3 8002784: 461a mov r2, r3 8002786: 4620 mov r0, r4 8002788: f002 fea0 bl 80054cc #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); 800278c: 6878 ldr r0, [r7, #4] 800278e: f006 f8f6 bl 800897e #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); 8002792: 687b ldr r3, [r7, #4] 8002794: 681b ldr r3, [r3, #0] 8002796: 695a ldr r2, [r3, #20] 8002798: 687b ldr r3, [r7, #4] 800279a: 681b ldr r3, [r3, #0] 800279c: f402 5200 and.w r2, r2, #8192 ; 0x2000 80027a0: 615a str r2, [r3, #20] } /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) 80027a2: 687b ldr r3, [r7, #4] 80027a4: 681b ldr r3, [r3, #0] 80027a6: 4618 mov r0, r3 80027a8: f004 f84d bl 8006846 80027ac: 4603 mov r3, r0 80027ae: f003 0308 and.w r3, r3, #8 80027b2: 2b08 cmp r3, #8 80027b4: d10a bne.n 80027cc { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); 80027b6: 6878 ldr r0, [r7, #4] 80027b8: f006 f8d3 bl 8008962 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); 80027bc: 687b ldr r3, [r7, #4] 80027be: 681b ldr r3, [r3, #0] 80027c0: 695a ldr r2, [r3, #20] 80027c2: 687b ldr r3, [r7, #4] 80027c4: 681b ldr r3, [r3, #0] 80027c6: f002 0208 and.w r2, r2, #8 80027ca: 615a str r2, [r3, #20] } /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) 80027cc: 687b ldr r3, [r7, #4] 80027ce: 681b ldr r3, [r3, #0] 80027d0: 4618 mov r0, r3 80027d2: f004 f838 bl 8006846 80027d6: 4603 mov r3, r0 80027d8: f403 1380 and.w r3, r3, #1048576 ; 0x100000 80027dc: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 80027e0: d10f bne.n 8002802 { /* Keep application checking the corresponding Iso IN endpoint causing the incomplete Interrupt */ epnum = 0U; 80027e2: 2300 movs r3, #0 80027e4: 627b str r3, [r7, #36] ; 0x24 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); 80027e6: 6a7b ldr r3, [r7, #36] ; 0x24 80027e8: b2db uxtb r3, r3 80027ea: 4619 mov r1, r3 80027ec: 6878 ldr r0, [r7, #4] 80027ee: f006 f935 bl 8008a5c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); 80027f2: 687b ldr r3, [r7, #4] 80027f4: 681b ldr r3, [r3, #0] 80027f6: 695a ldr r2, [r3, #20] 80027f8: 687b ldr r3, [r7, #4] 80027fa: 681b ldr r3, [r3, #0] 80027fc: f402 1280 and.w r2, r2, #1048576 ; 0x100000 8002800: 615a str r2, [r3, #20] } /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 8002802: 687b ldr r3, [r7, #4] 8002804: 681b ldr r3, [r3, #0] 8002806: 4618 mov r0, r3 8002808: f004 f81d bl 8006846 800280c: 4603 mov r3, r0 800280e: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8002812: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8002816: d10f bne.n 8002838 { /* Keep application checking the corresponding Iso OUT endpoint causing the incomplete Interrupt */ epnum = 0U; 8002818: 2300 movs r3, #0 800281a: 627b str r3, [r7, #36] ; 0x24 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); 800281c: 6a7b ldr r3, [r7, #36] ; 0x24 800281e: b2db uxtb r3, r3 8002820: 4619 mov r1, r3 8002822: 6878 ldr r0, [r7, #4] 8002824: f006 f908 bl 8008a38 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8002828: 687b ldr r3, [r7, #4] 800282a: 681b ldr r3, [r3, #0] 800282c: 695a ldr r2, [r3, #20] 800282e: 687b ldr r3, [r7, #4] 8002830: 681b ldr r3, [r3, #0] 8002832: f402 1200 and.w r2, r2, #2097152 ; 0x200000 8002836: 615a str r2, [r3, #20] } /* Handle Connection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) 8002838: 687b ldr r3, [r7, #4] 800283a: 681b ldr r3, [r3, #0] 800283c: 4618 mov r0, r3 800283e: f004 f802 bl 8006846 8002842: 4603 mov r3, r0 8002844: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8002848: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800284c: d10a bne.n 8002864 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ConnectCallback(hpcd); #else HAL_PCD_ConnectCallback(hpcd); 800284e: 6878 ldr r0, [r7, #4] 8002850: f006 f916 bl 8008a80 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); 8002854: 687b ldr r3, [r7, #4] 8002856: 681b ldr r3, [r3, #0] 8002858: 695a ldr r2, [r3, #20] 800285a: 687b ldr r3, [r7, #4] 800285c: 681b ldr r3, [r3, #0] 800285e: f002 4280 and.w r2, r2, #1073741824 ; 0x40000000 8002862: 615a str r2, [r3, #20] } /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) 8002864: 687b ldr r3, [r7, #4] 8002866: 681b ldr r3, [r3, #0] 8002868: 4618 mov r0, r3 800286a: f003 ffec bl 8006846 800286e: 4603 mov r3, r0 8002870: f003 0304 and.w r3, r3, #4 8002874: 2b04 cmp r3, #4 8002876: d115 bne.n 80028a4 { temp = hpcd->Instance->GOTGINT; 8002878: 687b ldr r3, [r7, #4] 800287a: 681b ldr r3, [r3, #0] 800287c: 685b ldr r3, [r3, #4] 800287e: 61bb str r3, [r7, #24] if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) 8002880: 69bb ldr r3, [r7, #24] 8002882: f003 0304 and.w r3, r3, #4 8002886: 2b00 cmp r3, #0 8002888: d002 beq.n 8002890 { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); #else HAL_PCD_DisconnectCallback(hpcd); 800288a: 6878 ldr r0, [r7, #4] 800288c: f006 f906 bl 8008a9c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= temp; 8002890: 687b ldr r3, [r7, #4] 8002892: 681b ldr r3, [r3, #0] 8002894: 6859 ldr r1, [r3, #4] 8002896: 687b ldr r3, [r7, #4] 8002898: 681b ldr r3, [r3, #0] 800289a: 69ba ldr r2, [r7, #24] 800289c: 430a orrs r2, r1 800289e: 605a str r2, [r3, #4] 80028a0: e000 b.n 80028a4 return; 80028a2: bf00 nop } } } 80028a4: 3734 adds r7, #52 ; 0x34 80028a6: 46bd mov sp, r7 80028a8: bd90 pop {r4, r7, pc} 080028aa : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { 80028aa: b580 push {r7, lr} 80028ac: b082 sub sp, #8 80028ae: af00 add r7, sp, #0 80028b0: 6078 str r0, [r7, #4] 80028b2: 460b mov r3, r1 80028b4: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); 80028b6: 687b ldr r3, [r7, #4] 80028b8: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 80028bc: 2b01 cmp r3, #1 80028be: d101 bne.n 80028c4 80028c0: 2302 movs r3, #2 80028c2: e013 b.n 80028ec 80028c4: 687b ldr r3, [r7, #4] 80028c6: 2201 movs r2, #1 80028c8: f883 23bc strb.w r2, [r3, #956] ; 0x3bc hpcd->USB_Address = address; 80028cc: 687b ldr r3, [r7, #4] 80028ce: 78fa ldrb r2, [r7, #3] 80028d0: f883 2038 strb.w r2, [r3, #56] ; 0x38 (void)USB_SetDevAddress(hpcd->Instance, address); 80028d4: 687b ldr r3, [r7, #4] 80028d6: 681b ldr r3, [r3, #0] 80028d8: 78fa ldrb r2, [r7, #3] 80028da: 4611 mov r1, r2 80028dc: 4618 mov r0, r3 80028de: f003 ff4a bl 8006776 __HAL_UNLOCK(hpcd); 80028e2: 687b ldr r3, [r7, #4] 80028e4: 2200 movs r2, #0 80028e6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 80028ea: 2300 movs r3, #0 } 80028ec: 4618 mov r0, r3 80028ee: 3708 adds r7, #8 80028f0: 46bd mov sp, r7 80028f2: bd80 pop {r7, pc} 080028f4 : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { 80028f4: b580 push {r7, lr} 80028f6: b084 sub sp, #16 80028f8: af00 add r7, sp, #0 80028fa: 6078 str r0, [r7, #4] 80028fc: 4608 mov r0, r1 80028fe: 4611 mov r1, r2 8002900: 461a mov r2, r3 8002902: 4603 mov r3, r0 8002904: 70fb strb r3, [r7, #3] 8002906: 460b mov r3, r1 8002908: 803b strh r3, [r7, #0] 800290a: 4613 mov r3, r2 800290c: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; 800290e: 2300 movs r3, #0 8002910: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 8002912: f997 3003 ldrsb.w r3, [r7, #3] 8002916: 2b00 cmp r3, #0 8002918: da0f bge.n 800293a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 800291a: 78fb ldrb r3, [r7, #3] 800291c: f003 020f and.w r2, r3, #15 8002920: 4613 mov r3, r2 8002922: 00db lsls r3, r3, #3 8002924: 1a9b subs r3, r3, r2 8002926: 009b lsls r3, r3, #2 8002928: 3338 adds r3, #56 ; 0x38 800292a: 687a ldr r2, [r7, #4] 800292c: 4413 add r3, r2 800292e: 3304 adds r3, #4 8002930: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002932: 68fb ldr r3, [r7, #12] 8002934: 2201 movs r2, #1 8002936: 705a strb r2, [r3, #1] 8002938: e00f b.n 800295a } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 800293a: 78fb ldrb r3, [r7, #3] 800293c: f003 020f and.w r2, r3, #15 8002940: 4613 mov r3, r2 8002942: 00db lsls r3, r3, #3 8002944: 1a9b subs r3, r3, r2 8002946: 009b lsls r3, r3, #2 8002948: f503 73fc add.w r3, r3, #504 ; 0x1f8 800294c: 687a ldr r2, [r7, #4] 800294e: 4413 add r3, r2 8002950: 3304 adds r3, #4 8002952: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002954: 68fb ldr r3, [r7, #12] 8002956: 2200 movs r2, #0 8002958: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 800295a: 78fb ldrb r3, [r7, #3] 800295c: f003 030f and.w r3, r3, #15 8002960: b2da uxtb r2, r3 8002962: 68fb ldr r3, [r7, #12] 8002964: 701a strb r2, [r3, #0] ep->maxpacket = ep_mps; 8002966: 883a ldrh r2, [r7, #0] 8002968: 68fb ldr r3, [r7, #12] 800296a: 609a str r2, [r3, #8] ep->type = ep_type; 800296c: 68fb ldr r3, [r7, #12] 800296e: 78ba ldrb r2, [r7, #2] 8002970: 70da strb r2, [r3, #3] if (ep->is_in != 0U) 8002972: 68fb ldr r3, [r7, #12] 8002974: 785b ldrb r3, [r3, #1] 8002976: 2b00 cmp r3, #0 8002978: d004 beq.n 8002984 { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; 800297a: 68fb ldr r3, [r7, #12] 800297c: 781b ldrb r3, [r3, #0] 800297e: b29a uxth r2, r3 8002980: 68fb ldr r3, [r7, #12] 8002982: 80da strh r2, [r3, #6] } /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) 8002984: 78bb ldrb r3, [r7, #2] 8002986: 2b02 cmp r3, #2 8002988: d102 bne.n 8002990 { ep->data_pid_start = 0U; 800298a: 68fb ldr r3, [r7, #12] 800298c: 2200 movs r2, #0 800298e: 711a strb r2, [r3, #4] } __HAL_LOCK(hpcd); 8002990: 687b ldr r3, [r7, #4] 8002992: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002996: 2b01 cmp r3, #1 8002998: d101 bne.n 800299e 800299a: 2302 movs r3, #2 800299c: e00e b.n 80029bc 800299e: 687b ldr r3, [r7, #4] 80029a0: 2201 movs r2, #1 80029a2: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_ActivateEndpoint(hpcd->Instance, ep); 80029a6: 687b ldr r3, [r7, #4] 80029a8: 681b ldr r3, [r3, #0] 80029aa: 68f9 ldr r1, [r7, #12] 80029ac: 4618 mov r0, r3 80029ae: f003 f87d bl 8005aac __HAL_UNLOCK(hpcd); 80029b2: 687b ldr r3, [r7, #4] 80029b4: 2200 movs r2, #0 80029b6: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return ret; 80029ba: 7afb ldrb r3, [r7, #11] } 80029bc: 4618 mov r0, r3 80029be: 3710 adds r7, #16 80029c0: 46bd mov sp, r7 80029c2: bd80 pop {r7, pc} 080029c4 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 80029c4: b580 push {r7, lr} 80029c6: b084 sub sp, #16 80029c8: af00 add r7, sp, #0 80029ca: 6078 str r0, [r7, #4] 80029cc: 460b mov r3, r1 80029ce: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) 80029d0: f997 3003 ldrsb.w r3, [r7, #3] 80029d4: 2b00 cmp r3, #0 80029d6: da0f bge.n 80029f8 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 80029d8: 78fb ldrb r3, [r7, #3] 80029da: f003 020f and.w r2, r3, #15 80029de: 4613 mov r3, r2 80029e0: 00db lsls r3, r3, #3 80029e2: 1a9b subs r3, r3, r2 80029e4: 009b lsls r3, r3, #2 80029e6: 3338 adds r3, #56 ; 0x38 80029e8: 687a ldr r2, [r7, #4] 80029ea: 4413 add r3, r2 80029ec: 3304 adds r3, #4 80029ee: 60fb str r3, [r7, #12] ep->is_in = 1U; 80029f0: 68fb ldr r3, [r7, #12] 80029f2: 2201 movs r2, #1 80029f4: 705a strb r2, [r3, #1] 80029f6: e00f b.n 8002a18 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 80029f8: 78fb ldrb r3, [r7, #3] 80029fa: f003 020f and.w r2, r3, #15 80029fe: 4613 mov r3, r2 8002a00: 00db lsls r3, r3, #3 8002a02: 1a9b subs r3, r3, r2 8002a04: 009b lsls r3, r3, #2 8002a06: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002a0a: 687a ldr r2, [r7, #4] 8002a0c: 4413 add r3, r2 8002a0e: 3304 adds r3, #4 8002a10: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002a12: 68fb ldr r3, [r7, #12] 8002a14: 2200 movs r2, #0 8002a16: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; 8002a18: 78fb ldrb r3, [r7, #3] 8002a1a: f003 030f and.w r3, r3, #15 8002a1e: b2da uxtb r2, r3 8002a20: 68fb ldr r3, [r7, #12] 8002a22: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8002a24: 687b ldr r3, [r7, #4] 8002a26: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002a2a: 2b01 cmp r3, #1 8002a2c: d101 bne.n 8002a32 8002a2e: 2302 movs r3, #2 8002a30: e00e b.n 8002a50 8002a32: 687b ldr r3, [r7, #4] 8002a34: 2201 movs r2, #1 8002a36: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_DeactivateEndpoint(hpcd->Instance, ep); 8002a3a: 687b ldr r3, [r7, #4] 8002a3c: 681b ldr r3, [r3, #0] 8002a3e: 68f9 ldr r1, [r7, #12] 8002a40: 4618 mov r0, r3 8002a42: f003 f8bb bl 8005bbc __HAL_UNLOCK(hpcd); 8002a46: 687b ldr r3, [r7, #4] 8002a48: 2200 movs r2, #0 8002a4a: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002a4e: 2300 movs r3, #0 } 8002a50: 4618 mov r0, r3 8002a52: 3710 adds r7, #16 8002a54: 46bd mov sp, r7 8002a56: bd80 pop {r7, pc} 08002a58 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8002a58: b580 push {r7, lr} 8002a5a: b086 sub sp, #24 8002a5c: af00 add r7, sp, #0 8002a5e: 60f8 str r0, [r7, #12] 8002a60: 607a str r2, [r7, #4] 8002a62: 603b str r3, [r7, #0] 8002a64: 460b mov r3, r1 8002a66: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8002a68: 7afb ldrb r3, [r7, #11] 8002a6a: f003 020f and.w r2, r3, #15 8002a6e: 4613 mov r3, r2 8002a70: 00db lsls r3, r3, #3 8002a72: 1a9b subs r3, r3, r2 8002a74: 009b lsls r3, r3, #2 8002a76: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002a7a: 68fa ldr r2, [r7, #12] 8002a7c: 4413 add r3, r2 8002a7e: 3304 adds r3, #4 8002a80: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8002a82: 697b ldr r3, [r7, #20] 8002a84: 687a ldr r2, [r7, #4] 8002a86: 60da str r2, [r3, #12] ep->xfer_len = len; 8002a88: 697b ldr r3, [r7, #20] 8002a8a: 683a ldr r2, [r7, #0] 8002a8c: 615a str r2, [r3, #20] ep->xfer_count = 0U; 8002a8e: 697b ldr r3, [r7, #20] 8002a90: 2200 movs r2, #0 8002a92: 619a str r2, [r3, #24] ep->is_in = 0U; 8002a94: 697b ldr r3, [r7, #20] 8002a96: 2200 movs r2, #0 8002a98: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8002a9a: 7afb ldrb r3, [r7, #11] 8002a9c: f003 030f and.w r3, r3, #15 8002aa0: b2da uxtb r2, r3 8002aa2: 697b ldr r3, [r7, #20] 8002aa4: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8002aa6: 68fb ldr r3, [r7, #12] 8002aa8: 691b ldr r3, [r3, #16] 8002aaa: 2b01 cmp r3, #1 8002aac: d102 bne.n 8002ab4 { ep->dma_addr = (uint32_t)pBuf; 8002aae: 687a ldr r2, [r7, #4] 8002ab0: 697b ldr r3, [r7, #20] 8002ab2: 611a str r2, [r3, #16] } if ((ep_addr & EP_ADDR_MSK) == 0U) 8002ab4: 7afb ldrb r3, [r7, #11] 8002ab6: f003 030f and.w r3, r3, #15 8002aba: 2b00 cmp r3, #0 8002abc: d109 bne.n 8002ad2 { (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8002abe: 68fb ldr r3, [r7, #12] 8002ac0: 6818 ldr r0, [r3, #0] 8002ac2: 68fb ldr r3, [r7, #12] 8002ac4: 691b ldr r3, [r3, #16] 8002ac6: b2db uxtb r3, r3 8002ac8: 461a mov r2, r3 8002aca: 6979 ldr r1, [r7, #20] 8002acc: f003 fb96 bl 80061fc 8002ad0: e008 b.n 8002ae4 } else { (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8002ad2: 68fb ldr r3, [r7, #12] 8002ad4: 6818 ldr r0, [r3, #0] 8002ad6: 68fb ldr r3, [r7, #12] 8002ad8: 691b ldr r3, [r3, #16] 8002ada: b2db uxtb r3, r3 8002adc: 461a mov r2, r3 8002ade: 6979 ldr r1, [r7, #20] 8002ae0: f003 f948 bl 8005d74 } return HAL_OK; 8002ae4: 2300 movs r3, #0 } 8002ae6: 4618 mov r0, r3 8002ae8: 3718 adds r7, #24 8002aea: 46bd mov sp, r7 8002aec: bd80 pop {r7, pc} 08002aee : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval Data Size */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8002aee: b480 push {r7} 8002af0: b083 sub sp, #12 8002af2: af00 add r7, sp, #0 8002af4: 6078 str r0, [r7, #4] 8002af6: 460b mov r3, r1 8002af8: 70fb strb r3, [r7, #3] return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; 8002afa: 78fb ldrb r3, [r7, #3] 8002afc: f003 020f and.w r2, r3, #15 8002b00: 6879 ldr r1, [r7, #4] 8002b02: 4613 mov r3, r2 8002b04: 00db lsls r3, r3, #3 8002b06: 1a9b subs r3, r3, r2 8002b08: 009b lsls r3, r3, #2 8002b0a: 440b add r3, r1 8002b0c: f503 7305 add.w r3, r3, #532 ; 0x214 8002b10: 681b ldr r3, [r3, #0] } 8002b12: 4618 mov r0, r3 8002b14: 370c adds r7, #12 8002b16: 46bd mov sp, r7 8002b18: f85d 7b04 ldr.w r7, [sp], #4 8002b1c: 4770 bx lr 08002b1e : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { 8002b1e: b580 push {r7, lr} 8002b20: b086 sub sp, #24 8002b22: af00 add r7, sp, #0 8002b24: 60f8 str r0, [r7, #12] 8002b26: 607a str r2, [r7, #4] 8002b28: 603b str r3, [r7, #0] 8002b2a: 460b mov r3, r1 8002b2c: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002b2e: 7afb ldrb r3, [r7, #11] 8002b30: f003 020f and.w r2, r3, #15 8002b34: 4613 mov r3, r2 8002b36: 00db lsls r3, r3, #3 8002b38: 1a9b subs r3, r3, r2 8002b3a: 009b lsls r3, r3, #2 8002b3c: 3338 adds r3, #56 ; 0x38 8002b3e: 68fa ldr r2, [r7, #12] 8002b40: 4413 add r3, r2 8002b42: 3304 adds r3, #4 8002b44: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; 8002b46: 697b ldr r3, [r7, #20] 8002b48: 687a ldr r2, [r7, #4] 8002b4a: 60da str r2, [r3, #12] ep->xfer_len = len; 8002b4c: 697b ldr r3, [r7, #20] 8002b4e: 683a ldr r2, [r7, #0] 8002b50: 615a str r2, [r3, #20] ep->xfer_count = 0U; 8002b52: 697b ldr r3, [r7, #20] 8002b54: 2200 movs r2, #0 8002b56: 619a str r2, [r3, #24] ep->is_in = 1U; 8002b58: 697b ldr r3, [r7, #20] 8002b5a: 2201 movs r2, #1 8002b5c: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; 8002b5e: 7afb ldrb r3, [r7, #11] 8002b60: f003 030f and.w r3, r3, #15 8002b64: b2da uxtb r2, r3 8002b66: 697b ldr r3, [r7, #20] 8002b68: 701a strb r2, [r3, #0] if (hpcd->Init.dma_enable == 1U) 8002b6a: 68fb ldr r3, [r7, #12] 8002b6c: 691b ldr r3, [r3, #16] 8002b6e: 2b01 cmp r3, #1 8002b70: d102 bne.n 8002b78 { ep->dma_addr = (uint32_t)pBuf; 8002b72: 687a ldr r2, [r7, #4] 8002b74: 697b ldr r3, [r7, #20] 8002b76: 611a str r2, [r3, #16] } if ((ep_addr & EP_ADDR_MSK) == 0U) 8002b78: 7afb ldrb r3, [r7, #11] 8002b7a: f003 030f and.w r3, r3, #15 8002b7e: 2b00 cmp r3, #0 8002b80: d109 bne.n 8002b96 { (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8002b82: 68fb ldr r3, [r7, #12] 8002b84: 6818 ldr r0, [r3, #0] 8002b86: 68fb ldr r3, [r7, #12] 8002b88: 691b ldr r3, [r3, #16] 8002b8a: b2db uxtb r3, r3 8002b8c: 461a mov r2, r3 8002b8e: 6979 ldr r1, [r7, #20] 8002b90: f003 fb34 bl 80061fc 8002b94: e008 b.n 8002ba8 } else { (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); 8002b96: 68fb ldr r3, [r7, #12] 8002b98: 6818 ldr r0, [r3, #0] 8002b9a: 68fb ldr r3, [r7, #12] 8002b9c: 691b ldr r3, [r3, #16] 8002b9e: b2db uxtb r3, r3 8002ba0: 461a mov r2, r3 8002ba2: 6979 ldr r1, [r7, #20] 8002ba4: f003 f8e6 bl 8005d74 } return HAL_OK; 8002ba8: 2300 movs r3, #0 } 8002baa: 4618 mov r0, r3 8002bac: 3718 adds r7, #24 8002bae: 46bd mov sp, r7 8002bb0: bd80 pop {r7, pc} 08002bb2 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8002bb2: b580 push {r7, lr} 8002bb4: b084 sub sp, #16 8002bb6: af00 add r7, sp, #0 8002bb8: 6078 str r0, [r7, #4] 8002bba: 460b mov r3, r1 8002bbc: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) 8002bbe: 78fb ldrb r3, [r7, #3] 8002bc0: f003 020f and.w r2, r3, #15 8002bc4: 687b ldr r3, [r7, #4] 8002bc6: 685b ldr r3, [r3, #4] 8002bc8: 429a cmp r2, r3 8002bca: d901 bls.n 8002bd0 { return HAL_ERROR; 8002bcc: 2301 movs r3, #1 8002bce: e050 b.n 8002c72 } if ((0x80U & ep_addr) == 0x80U) 8002bd0: f997 3003 ldrsb.w r3, [r7, #3] 8002bd4: 2b00 cmp r3, #0 8002bd6: da0f bge.n 8002bf8 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002bd8: 78fb ldrb r3, [r7, #3] 8002bda: f003 020f and.w r2, r3, #15 8002bde: 4613 mov r3, r2 8002be0: 00db lsls r3, r3, #3 8002be2: 1a9b subs r3, r3, r2 8002be4: 009b lsls r3, r3, #2 8002be6: 3338 adds r3, #56 ; 0x38 8002be8: 687a ldr r2, [r7, #4] 8002bea: 4413 add r3, r2 8002bec: 3304 adds r3, #4 8002bee: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002bf0: 68fb ldr r3, [r7, #12] 8002bf2: 2201 movs r2, #1 8002bf4: 705a strb r2, [r3, #1] 8002bf6: e00d b.n 8002c14 } else { ep = &hpcd->OUT_ep[ep_addr]; 8002bf8: 78fa ldrb r2, [r7, #3] 8002bfa: 4613 mov r3, r2 8002bfc: 00db lsls r3, r3, #3 8002bfe: 1a9b subs r3, r3, r2 8002c00: 009b lsls r3, r3, #2 8002c02: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002c06: 687a ldr r2, [r7, #4] 8002c08: 4413 add r3, r2 8002c0a: 3304 adds r3, #4 8002c0c: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002c0e: 68fb ldr r3, [r7, #12] 8002c10: 2200 movs r2, #0 8002c12: 705a strb r2, [r3, #1] } ep->is_stall = 1U; 8002c14: 68fb ldr r3, [r7, #12] 8002c16: 2201 movs r2, #1 8002c18: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8002c1a: 78fb ldrb r3, [r7, #3] 8002c1c: f003 030f and.w r3, r3, #15 8002c20: b2da uxtb r2, r3 8002c22: 68fb ldr r3, [r7, #12] 8002c24: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8002c26: 687b ldr r3, [r7, #4] 8002c28: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002c2c: 2b01 cmp r3, #1 8002c2e: d101 bne.n 8002c34 8002c30: 2302 movs r3, #2 8002c32: e01e b.n 8002c72 8002c34: 687b ldr r3, [r7, #4] 8002c36: 2201 movs r2, #1 8002c38: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_EPSetStall(hpcd->Instance, ep); 8002c3c: 687b ldr r3, [r7, #4] 8002c3e: 681b ldr r3, [r3, #0] 8002c40: 68f9 ldr r1, [r7, #12] 8002c42: 4618 mov r0, r3 8002c44: f003 fcc3 bl 80065ce if ((ep_addr & EP_ADDR_MSK) == 0U) 8002c48: 78fb ldrb r3, [r7, #3] 8002c4a: f003 030f and.w r3, r3, #15 8002c4e: 2b00 cmp r3, #0 8002c50: d10a bne.n 8002c68 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); 8002c52: 687b ldr r3, [r7, #4] 8002c54: 6818 ldr r0, [r3, #0] 8002c56: 687b ldr r3, [r7, #4] 8002c58: 691b ldr r3, [r3, #16] 8002c5a: b2d9 uxtb r1, r3 8002c5c: 687b ldr r3, [r7, #4] 8002c5e: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002c62: 461a mov r2, r3 8002c64: f003 feb4 bl 80069d0 } __HAL_UNLOCK(hpcd); 8002c68: 687b ldr r3, [r7, #4] 8002c6a: 2200 movs r2, #0 8002c6c: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002c70: 2300 movs r3, #0 } 8002c72: 4618 mov r0, r3 8002c74: 3710 adds r7, #16 8002c76: 46bd mov sp, r7 8002c78: bd80 pop {r7, pc} 08002c7a : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { 8002c7a: b580 push {r7, lr} 8002c7c: b084 sub sp, #16 8002c7e: af00 add r7, sp, #0 8002c80: 6078 str r0, [r7, #4] 8002c82: 460b mov r3, r1 8002c84: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) 8002c86: 78fb ldrb r3, [r7, #3] 8002c88: f003 020f and.w r2, r3, #15 8002c8c: 687b ldr r3, [r7, #4] 8002c8e: 685b ldr r3, [r3, #4] 8002c90: 429a cmp r2, r3 8002c92: d901 bls.n 8002c98 { return HAL_ERROR; 8002c94: 2301 movs r3, #1 8002c96: e042 b.n 8002d1e } if ((0x80U & ep_addr) == 0x80U) 8002c98: f997 3003 ldrsb.w r3, [r7, #3] 8002c9c: 2b00 cmp r3, #0 8002c9e: da0f bge.n 8002cc0 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; 8002ca0: 78fb ldrb r3, [r7, #3] 8002ca2: f003 020f and.w r2, r3, #15 8002ca6: 4613 mov r3, r2 8002ca8: 00db lsls r3, r3, #3 8002caa: 1a9b subs r3, r3, r2 8002cac: 009b lsls r3, r3, #2 8002cae: 3338 adds r3, #56 ; 0x38 8002cb0: 687a ldr r2, [r7, #4] 8002cb2: 4413 add r3, r2 8002cb4: 3304 adds r3, #4 8002cb6: 60fb str r3, [r7, #12] ep->is_in = 1U; 8002cb8: 68fb ldr r3, [r7, #12] 8002cba: 2201 movs r2, #1 8002cbc: 705a strb r2, [r3, #1] 8002cbe: e00f b.n 8002ce0 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; 8002cc0: 78fb ldrb r3, [r7, #3] 8002cc2: f003 020f and.w r2, r3, #15 8002cc6: 4613 mov r3, r2 8002cc8: 00db lsls r3, r3, #3 8002cca: 1a9b subs r3, r3, r2 8002ccc: 009b lsls r3, r3, #2 8002cce: f503 73fc add.w r3, r3, #504 ; 0x1f8 8002cd2: 687a ldr r2, [r7, #4] 8002cd4: 4413 add r3, r2 8002cd6: 3304 adds r3, #4 8002cd8: 60fb str r3, [r7, #12] ep->is_in = 0U; 8002cda: 68fb ldr r3, [r7, #12] 8002cdc: 2200 movs r2, #0 8002cde: 705a strb r2, [r3, #1] } ep->is_stall = 0U; 8002ce0: 68fb ldr r3, [r7, #12] 8002ce2: 2200 movs r2, #0 8002ce4: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; 8002ce6: 78fb ldrb r3, [r7, #3] 8002ce8: f003 030f and.w r3, r3, #15 8002cec: b2da uxtb r2, r3 8002cee: 68fb ldr r3, [r7, #12] 8002cf0: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); 8002cf2: 687b ldr r3, [r7, #4] 8002cf4: f893 33bc ldrb.w r3, [r3, #956] ; 0x3bc 8002cf8: 2b01 cmp r3, #1 8002cfa: d101 bne.n 8002d00 8002cfc: 2302 movs r3, #2 8002cfe: e00e b.n 8002d1e 8002d00: 687b ldr r3, [r7, #4] 8002d02: 2201 movs r2, #1 8002d04: f883 23bc strb.w r2, [r3, #956] ; 0x3bc (void)USB_EPClearStall(hpcd->Instance, ep); 8002d08: 687b ldr r3, [r7, #4] 8002d0a: 681b ldr r3, [r3, #0] 8002d0c: 68f9 ldr r1, [r7, #12] 8002d0e: 4618 mov r0, r3 8002d10: f003 fccb bl 80066aa __HAL_UNLOCK(hpcd); 8002d14: 687b ldr r3, [r7, #4] 8002d16: 2200 movs r2, #0 8002d18: f883 23bc strb.w r2, [r3, #956] ; 0x3bc return HAL_OK; 8002d1c: 2300 movs r3, #0 } 8002d1e: 4618 mov r0, r3 8002d20: 3710 adds r7, #16 8002d22: 46bd mov sp, r7 8002d24: bd80 pop {r7, pc} 08002d26 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002d26: b580 push {r7, lr} 8002d28: b08a sub sp, #40 ; 0x28 8002d2a: af02 add r7, sp, #8 8002d2c: 6078 str r0, [r7, #4] 8002d2e: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002d30: 687b ldr r3, [r7, #4] 8002d32: 681b ldr r3, [r3, #0] 8002d34: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002d36: 697b ldr r3, [r7, #20] 8002d38: 613b str r3, [r7, #16] USB_OTG_EPTypeDef *ep; uint32_t len; uint32_t len32b; uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; 8002d3a: 683a ldr r2, [r7, #0] 8002d3c: 4613 mov r3, r2 8002d3e: 00db lsls r3, r3, #3 8002d40: 1a9b subs r3, r3, r2 8002d42: 009b lsls r3, r3, #2 8002d44: 3338 adds r3, #56 ; 0x38 8002d46: 687a ldr r2, [r7, #4] 8002d48: 4413 add r3, r2 8002d4a: 3304 adds r3, #4 8002d4c: 60fb str r3, [r7, #12] if (ep->xfer_count > ep->xfer_len) 8002d4e: 68fb ldr r3, [r7, #12] 8002d50: 699a ldr r2, [r3, #24] 8002d52: 68fb ldr r3, [r7, #12] 8002d54: 695b ldr r3, [r3, #20] 8002d56: 429a cmp r2, r3 8002d58: d901 bls.n 8002d5e { return HAL_ERROR; 8002d5a: 2301 movs r3, #1 8002d5c: e06c b.n 8002e38 } len = ep->xfer_len - ep->xfer_count; 8002d5e: 68fb ldr r3, [r7, #12] 8002d60: 695a ldr r2, [r3, #20] 8002d62: 68fb ldr r3, [r7, #12] 8002d64: 699b ldr r3, [r3, #24] 8002d66: 1ad3 subs r3, r2, r3 8002d68: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8002d6a: 68fb ldr r3, [r7, #12] 8002d6c: 689b ldr r3, [r3, #8] 8002d6e: 69fa ldr r2, [r7, #28] 8002d70: 429a cmp r2, r3 8002d72: d902 bls.n 8002d7a { len = ep->maxpacket; 8002d74: 68fb ldr r3, [r7, #12] 8002d76: 689b ldr r3, [r3, #8] 8002d78: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8002d7a: 69fb ldr r3, [r7, #28] 8002d7c: 3303 adds r3, #3 8002d7e: 089b lsrs r3, r3, #2 8002d80: 61bb str r3, [r7, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002d82: e02b b.n 8002ddc (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; 8002d84: 68fb ldr r3, [r7, #12] 8002d86: 695a ldr r2, [r3, #20] 8002d88: 68fb ldr r3, [r7, #12] 8002d8a: 699b ldr r3, [r3, #24] 8002d8c: 1ad3 subs r3, r2, r3 8002d8e: 61fb str r3, [r7, #28] if (len > ep->maxpacket) 8002d90: 68fb ldr r3, [r7, #12] 8002d92: 689b ldr r3, [r3, #8] 8002d94: 69fa ldr r2, [r7, #28] 8002d96: 429a cmp r2, r3 8002d98: d902 bls.n 8002da0 { len = ep->maxpacket; 8002d9a: 68fb ldr r3, [r7, #12] 8002d9c: 689b ldr r3, [r3, #8] 8002d9e: 61fb str r3, [r7, #28] } len32b = (len + 3U) / 4U; 8002da0: 69fb ldr r3, [r7, #28] 8002da2: 3303 adds r3, #3 8002da4: 089b lsrs r3, r3, #2 8002da6: 61bb str r3, [r7, #24] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8002da8: 68fb ldr r3, [r7, #12] 8002daa: 68d9 ldr r1, [r3, #12] 8002dac: 683b ldr r3, [r7, #0] 8002dae: b2da uxtb r2, r3 8002db0: 69fb ldr r3, [r7, #28] 8002db2: b298 uxth r0, r3 (uint8_t)hpcd->Init.dma_enable); 8002db4: 687b ldr r3, [r7, #4] 8002db6: 691b ldr r3, [r3, #16] (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, 8002db8: b2db uxtb r3, r3 8002dba: 9300 str r3, [sp, #0] 8002dbc: 4603 mov r3, r0 8002dbe: 6978 ldr r0, [r7, #20] 8002dc0: f003 fb6f bl 80064a2 ep->xfer_buff += len; 8002dc4: 68fb ldr r3, [r7, #12] 8002dc6: 68da ldr r2, [r3, #12] 8002dc8: 69fb ldr r3, [r7, #28] 8002dca: 441a add r2, r3 8002dcc: 68fb ldr r3, [r7, #12] 8002dce: 60da str r2, [r3, #12] ep->xfer_count += len; 8002dd0: 68fb ldr r3, [r7, #12] 8002dd2: 699a ldr r2, [r3, #24] 8002dd4: 69fb ldr r3, [r7, #28] 8002dd6: 441a add r2, r3 8002dd8: 68fb ldr r3, [r7, #12] 8002dda: 619a str r2, [r3, #24] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002ddc: 683b ldr r3, [r7, #0] 8002dde: 015a lsls r2, r3, #5 8002de0: 693b ldr r3, [r7, #16] 8002de2: 4413 add r3, r2 8002de4: f503 6310 add.w r3, r3, #2304 ; 0x900 8002de8: 699b ldr r3, [r3, #24] 8002dea: b29b uxth r3, r3 8002dec: 69ba ldr r2, [r7, #24] 8002dee: 429a cmp r2, r3 8002df0: d809 bhi.n 8002e06 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8002df2: 68fb ldr r3, [r7, #12] 8002df4: 699a ldr r2, [r3, #24] 8002df6: 68fb ldr r3, [r7, #12] 8002df8: 695b ldr r3, [r3, #20] while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && 8002dfa: 429a cmp r2, r3 8002dfc: d203 bcs.n 8002e06 (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) 8002dfe: 68fb ldr r3, [r7, #12] 8002e00: 695b ldr r3, [r3, #20] 8002e02: 2b00 cmp r3, #0 8002e04: d1be bne.n 8002d84 } if (ep->xfer_len <= ep->xfer_count) 8002e06: 68fb ldr r3, [r7, #12] 8002e08: 695a ldr r2, [r3, #20] 8002e0a: 68fb ldr r3, [r7, #12] 8002e0c: 699b ldr r3, [r3, #24] 8002e0e: 429a cmp r2, r3 8002e10: d811 bhi.n 8002e36 { fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); 8002e12: 683b ldr r3, [r7, #0] 8002e14: f003 030f and.w r3, r3, #15 8002e18: 2201 movs r2, #1 8002e1a: fa02 f303 lsl.w r3, r2, r3 8002e1e: 60bb str r3, [r7, #8] USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; 8002e20: 693b ldr r3, [r7, #16] 8002e22: f503 6300 add.w r3, r3, #2048 ; 0x800 8002e26: 6b5a ldr r2, [r3, #52] ; 0x34 8002e28: 68bb ldr r3, [r7, #8] 8002e2a: 43db mvns r3, r3 8002e2c: 6939 ldr r1, [r7, #16] 8002e2e: f501 6100 add.w r1, r1, #2048 ; 0x800 8002e32: 4013 ands r3, r2 8002e34: 634b str r3, [r1, #52] ; 0x34 } return HAL_OK; 8002e36: 2300 movs r3, #0 } 8002e38: 4618 mov r0, r3 8002e3a: 3720 adds r7, #32 8002e3c: 46bd mov sp, r7 8002e3e: bd80 pop {r7, pc} 08002e40 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8002e40: b580 push {r7, lr} 8002e42: b086 sub sp, #24 8002e44: af00 add r7, sp, #0 8002e46: 6078 str r0, [r7, #4] 8002e48: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8002e4a: 687b ldr r3, [r7, #4] 8002e4c: 681b ldr r3, [r3, #0] 8002e4e: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002e50: 697b ldr r3, [r7, #20] 8002e52: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 8002e54: 697b ldr r3, [r7, #20] 8002e56: 333c adds r3, #60 ; 0x3c 8002e58: 3304 adds r3, #4 8002e5a: 681b ldr r3, [r3, #0] 8002e5c: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8002e5e: 683b ldr r3, [r7, #0] 8002e60: 015a lsls r2, r3, #5 8002e62: 693b ldr r3, [r7, #16] 8002e64: 4413 add r3, r2 8002e66: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002e6a: 689b ldr r3, [r3, #8] 8002e6c: 60bb str r3, [r7, #8] if (hpcd->Init.dma_enable == 1U) 8002e6e: 687b ldr r3, [r7, #4] 8002e70: 691b ldr r3, [r3, #16] 8002e72: 2b01 cmp r3, #1 8002e74: f040 80a0 bne.w 8002fb8 { if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ 8002e78: 68bb ldr r3, [r7, #8] 8002e7a: f003 0308 and.w r3, r3, #8 8002e7e: 2b00 cmp r3, #0 8002e80: d015 beq.n 8002eae { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002e82: 68fb ldr r3, [r7, #12] 8002e84: 4a72 ldr r2, [pc, #456] ; (8003050 ) 8002e86: 4293 cmp r3, r2 8002e88: f240 80dd bls.w 8003046 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002e8c: 68bb ldr r3, [r7, #8] 8002e8e: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002e92: 2b00 cmp r3, #0 8002e94: f000 80d7 beq.w 8003046 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002e98: 683b ldr r3, [r7, #0] 8002e9a: 015a lsls r2, r3, #5 8002e9c: 693b ldr r3, [r7, #16] 8002e9e: 4413 add r3, r2 8002ea0: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002ea4: 461a mov r2, r3 8002ea6: f44f 4300 mov.w r3, #32768 ; 0x8000 8002eaa: 6093 str r3, [r2, #8] 8002eac: e0cb b.n 8003046 } } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ 8002eae: 68bb ldr r3, [r7, #8] 8002eb0: f003 0320 and.w r3, r3, #32 8002eb4: 2b00 cmp r3, #0 8002eb6: d009 beq.n 8002ecc { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002eb8: 683b ldr r3, [r7, #0] 8002eba: 015a lsls r2, r3, #5 8002ebc: 693b ldr r3, [r7, #16] 8002ebe: 4413 add r3, r2 8002ec0: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002ec4: 461a mov r2, r3 8002ec6: 2320 movs r3, #32 8002ec8: 6093 str r3, [r2, #8] 8002eca: e0bc b.n 8003046 } else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) 8002ecc: 68bb ldr r3, [r7, #8] 8002ece: f003 0328 and.w r3, r3, #40 ; 0x28 8002ed2: 2b00 cmp r3, #0 8002ed4: f040 80b7 bne.w 8003046 { /* StupPktRcvd = 1 this is a setup packet */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002ed8: 68fb ldr r3, [r7, #12] 8002eda: 4a5d ldr r2, [pc, #372] ; (8003050 ) 8002edc: 4293 cmp r3, r2 8002ede: d90f bls.n 8002f00 ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 8002ee0: 68bb ldr r3, [r7, #8] 8002ee2: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8002ee6: 2b00 cmp r3, #0 8002ee8: d00a beq.n 8002f00 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002eea: 683b ldr r3, [r7, #0] 8002eec: 015a lsls r2, r3, #5 8002eee: 693b ldr r3, [r7, #16] 8002ef0: 4413 add r3, r2 8002ef2: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002ef6: 461a mov r2, r3 8002ef8: f44f 4300 mov.w r3, #32768 ; 0x8000 8002efc: 6093 str r3, [r2, #8] 8002efe: e0a2 b.n 8003046 } else { /* out data packet received over EP0 */ hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket - 8002f00: 6879 ldr r1, [r7, #4] 8002f02: 683a ldr r2, [r7, #0] 8002f04: 4613 mov r3, r2 8002f06: 00db lsls r3, r3, #3 8002f08: 1a9b subs r3, r3, r2 8002f0a: 009b lsls r3, r3, #2 8002f0c: 440b add r3, r1 8002f0e: f503 7301 add.w r3, r3, #516 ; 0x204 8002f12: 681a ldr r2, [r3, #0] (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 8002f14: 683b ldr r3, [r7, #0] 8002f16: 0159 lsls r1, r3, #5 8002f18: 693b ldr r3, [r7, #16] 8002f1a: 440b add r3, r1 8002f1c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002f20: 691b ldr r3, [r3, #16] 8002f22: f3c3 0312 ubfx r3, r3, #0, #19 hpcd->OUT_ep[epnum].maxpacket - 8002f26: 1ad1 subs r1, r2, r3 hpcd->OUT_ep[epnum].xfer_count = 8002f28: 6878 ldr r0, [r7, #4] 8002f2a: 683a ldr r2, [r7, #0] 8002f2c: 4613 mov r3, r2 8002f2e: 00db lsls r3, r3, #3 8002f30: 1a9b subs r3, r3, r2 8002f32: 009b lsls r3, r3, #2 8002f34: 4403 add r3, r0 8002f36: f503 7305 add.w r3, r3, #532 ; 0x214 8002f3a: 6019 str r1, [r3, #0] hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; 8002f3c: 6879 ldr r1, [r7, #4] 8002f3e: 683a ldr r2, [r7, #0] 8002f40: 4613 mov r3, r2 8002f42: 00db lsls r3, r3, #3 8002f44: 1a9b subs r3, r3, r2 8002f46: 009b lsls r3, r3, #2 8002f48: 440b add r3, r1 8002f4a: f503 7302 add.w r3, r3, #520 ; 0x208 8002f4e: 6819 ldr r1, [r3, #0] 8002f50: 6878 ldr r0, [r7, #4] 8002f52: 683a ldr r2, [r7, #0] 8002f54: 4613 mov r3, r2 8002f56: 00db lsls r3, r3, #3 8002f58: 1a9b subs r3, r3, r2 8002f5a: 009b lsls r3, r3, #2 8002f5c: 4403 add r3, r0 8002f5e: f503 7301 add.w r3, r3, #516 ; 0x204 8002f62: 681b ldr r3, [r3, #0] 8002f64: 4419 add r1, r3 8002f66: 6878 ldr r0, [r7, #4] 8002f68: 683a ldr r2, [r7, #0] 8002f6a: 4613 mov r3, r2 8002f6c: 00db lsls r3, r3, #3 8002f6e: 1a9b subs r3, r3, r2 8002f70: 009b lsls r3, r3, #2 8002f72: 4403 add r3, r0 8002f74: f503 7302 add.w r3, r3, #520 ; 0x208 8002f78: 6019 str r1, [r3, #0] if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 8002f7a: 683b ldr r3, [r7, #0] 8002f7c: 2b00 cmp r3, #0 8002f7e: d114 bne.n 8002faa 8002f80: 6879 ldr r1, [r7, #4] 8002f82: 683a ldr r2, [r7, #0] 8002f84: 4613 mov r3, r2 8002f86: 00db lsls r3, r3, #3 8002f88: 1a9b subs r3, r3, r2 8002f8a: 009b lsls r3, r3, #2 8002f8c: 440b add r3, r1 8002f8e: f503 7304 add.w r3, r3, #528 ; 0x210 8002f92: 681b ldr r3, [r3, #0] 8002f94: 2b00 cmp r3, #0 8002f96: d108 bne.n 8002faa { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 8002f98: 687b ldr r3, [r7, #4] 8002f9a: 6818 ldr r0, [r3, #0] 8002f9c: 687b ldr r3, [r7, #4] 8002f9e: f503 7371 add.w r3, r3, #964 ; 0x3c4 8002fa2: 461a mov r2, r3 8002fa4: 2101 movs r1, #1 8002fa6: f003 fd13 bl 80069d0 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002faa: 683b ldr r3, [r7, #0] 8002fac: b2db uxtb r3, r3 8002fae: 4619 mov r1, r3 8002fb0: 6878 ldr r0, [r7, #4] 8002fb2: f005 fca1 bl 80088f8 8002fb6: e046 b.n 8003046 /* ... */ } } else { if (gSNPSiD == USB_OTG_CORE_ID_310A) 8002fb8: 68fb ldr r3, [r7, #12] 8002fba: 4a26 ldr r2, [pc, #152] ; (8003054 ) 8002fbc: 4293 cmp r3, r2 8002fbe: d124 bne.n 800300a { /* StupPktRcvd = 1 this is a setup packet */ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) 8002fc0: 68bb ldr r3, [r7, #8] 8002fc2: f403 4300 and.w r3, r3, #32768 ; 0x8000 8002fc6: 2b00 cmp r3, #0 8002fc8: d00a beq.n 8002fe0 { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8002fca: 683b ldr r3, [r7, #0] 8002fcc: 015a lsls r2, r3, #5 8002fce: 693b ldr r3, [r7, #16] 8002fd0: 4413 add r3, r2 8002fd2: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002fd6: 461a mov r2, r3 8002fd8: f44f 4300 mov.w r3, #32768 ; 0x8000 8002fdc: 6093 str r3, [r2, #8] 8002fde: e032 b.n 8003046 } else { if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) 8002fe0: 68bb ldr r3, [r7, #8] 8002fe2: f003 0320 and.w r3, r3, #32 8002fe6: 2b00 cmp r3, #0 8002fe8: d008 beq.n 8002ffc { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); 8002fea: 683b ldr r3, [r7, #0] 8002fec: 015a lsls r2, r3, #5 8002fee: 693b ldr r3, [r7, #16] 8002ff0: 4413 add r3, r2 8002ff2: f503 6330 add.w r3, r3, #2816 ; 0xb00 8002ff6: 461a mov r2, r3 8002ff8: 2320 movs r3, #32 8002ffa: 6093 str r3, [r2, #8] } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 8002ffc: 683b ldr r3, [r7, #0] 8002ffe: b2db uxtb r3, r3 8003000: 4619 mov r1, r3 8003002: 6878 ldr r0, [r7, #4] 8003004: f005 fc78 bl 80088f8 8003008: e01d b.n 8003046 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else { if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) 800300a: 683b ldr r3, [r7, #0] 800300c: 2b00 cmp r3, #0 800300e: d114 bne.n 800303a 8003010: 6879 ldr r1, [r7, #4] 8003012: 683a ldr r2, [r7, #0] 8003014: 4613 mov r3, r2 8003016: 00db lsls r3, r3, #3 8003018: 1a9b subs r3, r3, r2 800301a: 009b lsls r3, r3, #2 800301c: 440b add r3, r1 800301e: f503 7304 add.w r3, r3, #528 ; 0x210 8003022: 681b ldr r3, [r3, #0] 8003024: 2b00 cmp r3, #0 8003026: d108 bne.n 800303a { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); 8003028: 687b ldr r3, [r7, #4] 800302a: 6818 ldr r0, [r3, #0] 800302c: 687b ldr r3, [r7, #4] 800302e: f503 7371 add.w r3, r3, #964 ; 0x3c4 8003032: 461a mov r2, r3 8003034: 2100 movs r1, #0 8003036: f003 fccb bl 80069d0 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); 800303a: 683b ldr r3, [r7, #0] 800303c: b2db uxtb r3, r3 800303e: 4619 mov r1, r3 8003040: 6878 ldr r0, [r7, #4] 8003042: f005 fc59 bl 80088f8 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } return HAL_OK; 8003046: 2300 movs r3, #0 } 8003048: 4618 mov r0, r3 800304a: 3718 adds r7, #24 800304c: 46bd mov sp, r7 800304e: bd80 pop {r7, pc} 8003050: 4f54300a .word 0x4f54300a 8003054: 4f54310a .word 0x4f54310a 08003058 : * @param hpcd PCD handle * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { 8003058: b580 push {r7, lr} 800305a: b086 sub sp, #24 800305c: af00 add r7, sp, #0 800305e: 6078 str r0, [r7, #4] 8003060: 6039 str r1, [r7, #0] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 8003062: 687b ldr r3, [r7, #4] 8003064: 681b ldr r3, [r3, #0] 8003066: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003068: 697b ldr r3, [r7, #20] 800306a: 613b str r3, [r7, #16] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 800306c: 697b ldr r3, [r7, #20] 800306e: 333c adds r3, #60 ; 0x3c 8003070: 3304 adds r3, #4 8003072: 681b ldr r3, [r3, #0] 8003074: 60fb str r3, [r7, #12] uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; 8003076: 683b ldr r3, [r7, #0] 8003078: 015a lsls r2, r3, #5 800307a: 693b ldr r3, [r7, #16] 800307c: 4413 add r3, r2 800307e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8003082: 689b ldr r3, [r3, #8] 8003084: 60bb str r3, [r7, #8] if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003086: 68fb ldr r3, [r7, #12] 8003088: 4a15 ldr r2, [pc, #84] ; (80030e0 ) 800308a: 4293 cmp r3, r2 800308c: d90e bls.n 80030ac ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) 800308e: 68bb ldr r3, [r7, #8] 8003090: f403 4300 and.w r3, r3, #32768 ; 0x8000 if ((gSNPSiD > USB_OTG_CORE_ID_300A) && 8003094: 2b00 cmp r3, #0 8003096: d009 beq.n 80030ac { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); 8003098: 683b ldr r3, [r7, #0] 800309a: 015a lsls r2, r3, #5 800309c: 693b ldr r3, [r7, #16] 800309e: 4413 add r3, r2 80030a0: f503 6330 add.w r3, r3, #2816 ; 0xb00 80030a4: 461a mov r2, r3 80030a6: f44f 4300 mov.w r3, #32768 ; 0x8000 80030aa: 6093 str r3, [r2, #8] /* Inform the upper layer that a setup packet is available */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); 80030ac: 6878 ldr r0, [r7, #4] 80030ae: f005 fc11 bl 80088d4 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) 80030b2: 68fb ldr r3, [r7, #12] 80030b4: 4a0a ldr r2, [pc, #40] ; (80030e0 ) 80030b6: 4293 cmp r3, r2 80030b8: d90c bls.n 80030d4 80030ba: 687b ldr r3, [r7, #4] 80030bc: 691b ldr r3, [r3, #16] 80030be: 2b01 cmp r3, #1 80030c0: d108 bne.n 80030d4 { (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); 80030c2: 687b ldr r3, [r7, #4] 80030c4: 6818 ldr r0, [r3, #0] 80030c6: 687b ldr r3, [r7, #4] 80030c8: f503 7371 add.w r3, r3, #964 ; 0x3c4 80030cc: 461a mov r2, r3 80030ce: 2101 movs r1, #1 80030d0: f003 fc7e bl 80069d0 } return HAL_OK; 80030d4: 2300 movs r3, #0 } 80030d6: 4618 mov r0, r3 80030d8: 3718 adds r7, #24 80030da: 46bd mov sp, r7 80030dc: bd80 pop {r7, pc} 80030de: bf00 nop 80030e0: 4f54300a .word 0x4f54300a 080030e4 : * @param fifo The number of Tx fifo * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { 80030e4: b480 push {r7} 80030e6: b085 sub sp, #20 80030e8: af00 add r7, sp, #0 80030ea: 6078 str r0, [r7, #4] 80030ec: 460b mov r3, r1 80030ee: 70fb strb r3, [r7, #3] 80030f0: 4613 mov r3, r2 80030f2: 803b strh r3, [r7, #0] --> Txn should be configured with the minimum space of 16 words The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ Tx_Offset = hpcd->Instance->GRXFSIZ; 80030f4: 687b ldr r3, [r7, #4] 80030f6: 681b ldr r3, [r3, #0] 80030f8: 6a5b ldr r3, [r3, #36] ; 0x24 80030fa: 60bb str r3, [r7, #8] if (fifo == 0U) 80030fc: 78fb ldrb r3, [r7, #3] 80030fe: 2b00 cmp r3, #0 8003100: d107 bne.n 8003112 { hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; 8003102: 883b ldrh r3, [r7, #0] 8003104: 0419 lsls r1, r3, #16 8003106: 687b ldr r3, [r7, #4] 8003108: 681b ldr r3, [r3, #0] 800310a: 68ba ldr r2, [r7, #8] 800310c: 430a orrs r2, r1 800310e: 629a str r2, [r3, #40] ; 0x28 8003110: e028 b.n 8003164 } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; 8003112: 687b ldr r3, [r7, #4] 8003114: 681b ldr r3, [r3, #0] 8003116: 6a9b ldr r3, [r3, #40] ; 0x28 8003118: 0c1b lsrs r3, r3, #16 800311a: 68ba ldr r2, [r7, #8] 800311c: 4413 add r3, r2 800311e: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 8003120: 2300 movs r3, #0 8003122: 73fb strb r3, [r7, #15] 8003124: e00d b.n 8003142 { Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); 8003126: 687b ldr r3, [r7, #4] 8003128: 681a ldr r2, [r3, #0] 800312a: 7bfb ldrb r3, [r7, #15] 800312c: 3340 adds r3, #64 ; 0x40 800312e: 009b lsls r3, r3, #2 8003130: 4413 add r3, r2 8003132: 685b ldr r3, [r3, #4] 8003134: 0c1b lsrs r3, r3, #16 8003136: 68ba ldr r2, [r7, #8] 8003138: 4413 add r3, r2 800313a: 60bb str r3, [r7, #8] for (i = 0U; i < (fifo - 1U); i++) 800313c: 7bfb ldrb r3, [r7, #15] 800313e: 3301 adds r3, #1 8003140: 73fb strb r3, [r7, #15] 8003142: 7bfa ldrb r2, [r7, #15] 8003144: 78fb ldrb r3, [r7, #3] 8003146: 3b01 subs r3, #1 8003148: 429a cmp r2, r3 800314a: d3ec bcc.n 8003126 } /* Multiply Tx_Size by 2 to get higher performance */ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; 800314c: 883b ldrh r3, [r7, #0] 800314e: 0418 lsls r0, r3, #16 8003150: 687b ldr r3, [r7, #4] 8003152: 6819 ldr r1, [r3, #0] 8003154: 78fb ldrb r3, [r7, #3] 8003156: 3b01 subs r3, #1 8003158: 68ba ldr r2, [r7, #8] 800315a: 4302 orrs r2, r0 800315c: 3340 adds r3, #64 ; 0x40 800315e: 009b lsls r3, r3, #2 8003160: 440b add r3, r1 8003162: 605a str r2, [r3, #4] } return HAL_OK; 8003164: 2300 movs r3, #0 } 8003166: 4618 mov r0, r3 8003168: 3714 adds r7, #20 800316a: 46bd mov sp, r7 800316c: f85d 7b04 ldr.w r7, [sp], #4 8003170: 4770 bx lr 08003172 : * @param hpcd PCD handle * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { 8003172: b480 push {r7} 8003174: b083 sub sp, #12 8003176: af00 add r7, sp, #0 8003178: 6078 str r0, [r7, #4] 800317a: 460b mov r3, r1 800317c: 807b strh r3, [r7, #2] hpcd->Instance->GRXFSIZ = size; 800317e: 687b ldr r3, [r7, #4] 8003180: 681b ldr r3, [r3, #0] 8003182: 887a ldrh r2, [r7, #2] 8003184: 625a str r2, [r3, #36] ; 0x24 return HAL_OK; 8003186: 2300 movs r3, #0 } 8003188: 4618 mov r0, r3 800318a: 370c adds r7, #12 800318c: 46bd mov sp, r7 800318e: f85d 7b04 ldr.w r7, [sp], #4 8003192: 4770 bx lr 08003194 : * @brief Activate LPM feature. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { 8003194: b480 push {r7} 8003196: b085 sub sp, #20 8003198: af00 add r7, sp, #0 800319a: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; 800319c: 687b ldr r3, [r7, #4] 800319e: 681b ldr r3, [r3, #0] 80031a0: 60fb str r3, [r7, #12] hpcd->lpm_active = 1U; 80031a2: 687b ldr r3, [r7, #4] 80031a4: 2201 movs r2, #1 80031a6: f8c3 23fc str.w r2, [r3, #1020] ; 0x3fc hpcd->LPM_State = LPM_L0; 80031aa: 687b ldr r3, [r7, #4] 80031ac: 2200 movs r2, #0 80031ae: f883 23f4 strb.w r2, [r3, #1012] ; 0x3f4 USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; 80031b2: 68fb ldr r3, [r7, #12] 80031b4: 699b ldr r3, [r3, #24] 80031b6: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000 80031ba: 68fb ldr r3, [r7, #12] 80031bc: 619a str r2, [r3, #24] USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); 80031be: 68fb ldr r3, [r7, #12] 80031c0: 6d5b ldr r3, [r3, #84] ; 0x54 80031c2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80031c6: f043 0303 orr.w r3, r3, #3 80031ca: 68fa ldr r2, [r7, #12] 80031cc: 6553 str r3, [r2, #84] ; 0x54 return HAL_OK; 80031ce: 2300 movs r3, #0 } 80031d0: 4618 mov r0, r3 80031d2: 3714 adds r7, #20 80031d4: 46bd mov sp, r7 80031d6: f85d 7b04 ldr.w r7, [sp], #4 80031da: 4770 bx lr 080031dc : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80031dc: b580 push {r7, lr} 80031de: b084 sub sp, #16 80031e0: af00 add r7, sp, #0 80031e2: 6078 str r0, [r7, #4] 80031e4: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 80031e6: 687b ldr r3, [r7, #4] 80031e8: 2b00 cmp r3, #0 80031ea: d101 bne.n 80031f0 { return HAL_ERROR; 80031ec: 2301 movs r3, #1 80031ee: e0cc b.n 800338a /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 80031f0: 4b68 ldr r3, [pc, #416] ; (8003394 ) 80031f2: 681b ldr r3, [r3, #0] 80031f4: f003 030f and.w r3, r3, #15 80031f8: 683a ldr r2, [r7, #0] 80031fa: 429a cmp r2, r3 80031fc: d90c bls.n 8003218 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80031fe: 4b65 ldr r3, [pc, #404] ; (8003394 ) 8003200: 683a ldr r2, [r7, #0] 8003202: b2d2 uxtb r2, r2 8003204: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8003206: 4b63 ldr r3, [pc, #396] ; (8003394 ) 8003208: 681b ldr r3, [r3, #0] 800320a: f003 030f and.w r3, r3, #15 800320e: 683a ldr r2, [r7, #0] 8003210: 429a cmp r2, r3 8003212: d001 beq.n 8003218 { return HAL_ERROR; 8003214: 2301 movs r3, #1 8003216: e0b8 b.n 800338a } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003218: 687b ldr r3, [r7, #4] 800321a: 681b ldr r3, [r3, #0] 800321c: f003 0302 and.w r3, r3, #2 8003220: 2b00 cmp r3, #0 8003222: d020 beq.n 8003266 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003224: 687b ldr r3, [r7, #4] 8003226: 681b ldr r3, [r3, #0] 8003228: f003 0304 and.w r3, r3, #4 800322c: 2b00 cmp r3, #0 800322e: d005 beq.n 800323c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003230: 4b59 ldr r3, [pc, #356] ; (8003398 ) 8003232: 689b ldr r3, [r3, #8] 8003234: 4a58 ldr r2, [pc, #352] ; (8003398 ) 8003236: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 800323a: 6093 str r3, [r2, #8] } if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800323c: 687b ldr r3, [r7, #4] 800323e: 681b ldr r3, [r3, #0] 8003240: f003 0308 and.w r3, r3, #8 8003244: 2b00 cmp r3, #0 8003246: d005 beq.n 8003254 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8003248: 4b53 ldr r3, [pc, #332] ; (8003398 ) 800324a: 689b ldr r3, [r3, #8] 800324c: 4a52 ldr r2, [pc, #328] ; (8003398 ) 800324e: f443 4360 orr.w r3, r3, #57344 ; 0xe000 8003252: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003254: 4b50 ldr r3, [pc, #320] ; (8003398 ) 8003256: 689b ldr r3, [r3, #8] 8003258: f023 02f0 bic.w r2, r3, #240 ; 0xf0 800325c: 687b ldr r3, [r7, #4] 800325e: 689b ldr r3, [r3, #8] 8003260: 494d ldr r1, [pc, #308] ; (8003398 ) 8003262: 4313 orrs r3, r2 8003264: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003266: 687b ldr r3, [r7, #4] 8003268: 681b ldr r3, [r3, #0] 800326a: f003 0301 and.w r3, r3, #1 800326e: 2b00 cmp r3, #0 8003270: d044 beq.n 80032fc { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003272: 687b ldr r3, [r7, #4] 8003274: 685b ldr r3, [r3, #4] 8003276: 2b01 cmp r3, #1 8003278: d107 bne.n 800328a { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800327a: 4b47 ldr r3, [pc, #284] ; (8003398 ) 800327c: 681b ldr r3, [r3, #0] 800327e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003282: 2b00 cmp r3, #0 8003284: d119 bne.n 80032ba { return HAL_ERROR; 8003286: 2301 movs r3, #1 8003288: e07f b.n 800338a } } /* PLL is selected as System Clock Source */ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 800328a: 687b ldr r3, [r7, #4] 800328c: 685b ldr r3, [r3, #4] 800328e: 2b02 cmp r3, #2 8003290: d003 beq.n 800329a (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8003292: 687b ldr r3, [r7, #4] 8003294: 685b ldr r3, [r3, #4] else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8003296: 2b03 cmp r3, #3 8003298: d107 bne.n 80032aa { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800329a: 4b3f ldr r3, [pc, #252] ; (8003398 ) 800329c: 681b ldr r3, [r3, #0] 800329e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80032a2: 2b00 cmp r3, #0 80032a4: d109 bne.n 80032ba { return HAL_ERROR; 80032a6: 2301 movs r3, #1 80032a8: e06f b.n 800338a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80032aa: 4b3b ldr r3, [pc, #236] ; (8003398 ) 80032ac: 681b ldr r3, [r3, #0] 80032ae: f003 0302 and.w r3, r3, #2 80032b2: 2b00 cmp r3, #0 80032b4: d101 bne.n 80032ba { return HAL_ERROR; 80032b6: 2301 movs r3, #1 80032b8: e067 b.n 800338a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80032ba: 4b37 ldr r3, [pc, #220] ; (8003398 ) 80032bc: 689b ldr r3, [r3, #8] 80032be: f023 0203 bic.w r2, r3, #3 80032c2: 687b ldr r3, [r7, #4] 80032c4: 685b ldr r3, [r3, #4] 80032c6: 4934 ldr r1, [pc, #208] ; (8003398 ) 80032c8: 4313 orrs r3, r2 80032ca: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 80032cc: f7fd ffe6 bl 800129c 80032d0: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80032d2: e00a b.n 80032ea { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80032d4: f7fd ffe2 bl 800129c 80032d8: 4602 mov r2, r0 80032da: 68fb ldr r3, [r7, #12] 80032dc: 1ad3 subs r3, r2, r3 80032de: f241 3288 movw r2, #5000 ; 0x1388 80032e2: 4293 cmp r3, r2 80032e4: d901 bls.n 80032ea { return HAL_TIMEOUT; 80032e6: 2303 movs r3, #3 80032e8: e04f b.n 800338a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80032ea: 4b2b ldr r3, [pc, #172] ; (8003398 ) 80032ec: 689b ldr r3, [r3, #8] 80032ee: f003 020c and.w r2, r3, #12 80032f2: 687b ldr r3, [r7, #4] 80032f4: 685b ldr r3, [r3, #4] 80032f6: 009b lsls r3, r3, #2 80032f8: 429a cmp r2, r3 80032fa: d1eb bne.n 80032d4 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 80032fc: 4b25 ldr r3, [pc, #148] ; (8003394 ) 80032fe: 681b ldr r3, [r3, #0] 8003300: f003 030f and.w r3, r3, #15 8003304: 683a ldr r2, [r7, #0] 8003306: 429a cmp r2, r3 8003308: d20c bcs.n 8003324 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800330a: 4b22 ldr r3, [pc, #136] ; (8003394 ) 800330c: 683a ldr r2, [r7, #0] 800330e: b2d2 uxtb r2, r2 8003310: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8003312: 4b20 ldr r3, [pc, #128] ; (8003394 ) 8003314: 681b ldr r3, [r3, #0] 8003316: f003 030f and.w r3, r3, #15 800331a: 683a ldr r2, [r7, #0] 800331c: 429a cmp r2, r3 800331e: d001 beq.n 8003324 { return HAL_ERROR; 8003320: 2301 movs r3, #1 8003322: e032 b.n 800338a } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003324: 687b ldr r3, [r7, #4] 8003326: 681b ldr r3, [r3, #0] 8003328: f003 0304 and.w r3, r3, #4 800332c: 2b00 cmp r3, #0 800332e: d008 beq.n 8003342 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8003330: 4b19 ldr r3, [pc, #100] ; (8003398 ) 8003332: 689b ldr r3, [r3, #8] 8003334: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 8003338: 687b ldr r3, [r7, #4] 800333a: 68db ldr r3, [r3, #12] 800333c: 4916 ldr r1, [pc, #88] ; (8003398 ) 800333e: 4313 orrs r3, r2 8003340: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003342: 687b ldr r3, [r7, #4] 8003344: 681b ldr r3, [r3, #0] 8003346: f003 0308 and.w r3, r3, #8 800334a: 2b00 cmp r3, #0 800334c: d009 beq.n 8003362 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 800334e: 4b12 ldr r3, [pc, #72] ; (8003398 ) 8003350: 689b ldr r3, [r3, #8] 8003352: f423 4260 bic.w r2, r3, #57344 ; 0xe000 8003356: 687b ldr r3, [r7, #4] 8003358: 691b ldr r3, [r3, #16] 800335a: 00db lsls r3, r3, #3 800335c: 490e ldr r1, [pc, #56] ; (8003398 ) 800335e: 4313 orrs r3, r2 8003360: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; 8003362: f000 fb7f bl 8003a64 8003366: 4602 mov r2, r0 8003368: 4b0b ldr r3, [pc, #44] ; (8003398 ) 800336a: 689b ldr r3, [r3, #8] 800336c: 091b lsrs r3, r3, #4 800336e: f003 030f and.w r3, r3, #15 8003372: 490a ldr r1, [pc, #40] ; (800339c ) 8003374: 5ccb ldrb r3, [r1, r3] 8003376: fa22 f303 lsr.w r3, r2, r3 800337a: 4a09 ldr r2, [pc, #36] ; (80033a0 ) 800337c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick (uwTickPrio); 800337e: 4b09 ldr r3, [pc, #36] ; (80033a4 ) 8003380: 681b ldr r3, [r3, #0] 8003382: 4618 mov r0, r3 8003384: f7fd ff46 bl 8001214 return HAL_OK; 8003388: 2300 movs r3, #0 } 800338a: 4618 mov r0, r3 800338c: 3710 adds r7, #16 800338e: 46bd mov sp, r7 8003390: bd80 pop {r7, pc} 8003392: bf00 nop 8003394: 40023c00 .word 0x40023c00 8003398: 40023800 .word 0x40023800 800339c: 08008fa8 .word 0x08008fa8 80033a0: 20000000 .word 0x20000000 80033a4: 20000004 .word 0x20000004 080033a8 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80033a8: b480 push {r7} 80033aa: af00 add r7, sp, #0 return SystemCoreClock; 80033ac: 4b03 ldr r3, [pc, #12] ; (80033bc ) 80033ae: 681b ldr r3, [r3, #0] } 80033b0: 4618 mov r0, r3 80033b2: 46bd mov sp, r7 80033b4: f85d 7b04 ldr.w r7, [sp], #4 80033b8: 4770 bx lr 80033ba: bf00 nop 80033bc: 20000000 .word 0x20000000 080033c0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80033c0: b580 push {r7, lr} 80033c2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); 80033c4: f7ff fff0 bl 80033a8 80033c8: 4602 mov r2, r0 80033ca: 4b05 ldr r3, [pc, #20] ; (80033e0 ) 80033cc: 689b ldr r3, [r3, #8] 80033ce: 0a9b lsrs r3, r3, #10 80033d0: f003 0307 and.w r3, r3, #7 80033d4: 4903 ldr r1, [pc, #12] ; (80033e4 ) 80033d6: 5ccb ldrb r3, [r1, r3] 80033d8: fa22 f303 lsr.w r3, r2, r3 } 80033dc: 4618 mov r0, r3 80033de: bd80 pop {r7, pc} 80033e0: 40023800 .word 0x40023800 80033e4: 08008fb8 .word 0x08008fb8 080033e8 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80033e8: b580 push {r7, lr} 80033ea: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); 80033ec: f7ff ffdc bl 80033a8 80033f0: 4602 mov r2, r0 80033f2: 4b05 ldr r3, [pc, #20] ; (8003408 ) 80033f4: 689b ldr r3, [r3, #8] 80033f6: 0b5b lsrs r3, r3, #13 80033f8: f003 0307 and.w r3, r3, #7 80033fc: 4903 ldr r1, [pc, #12] ; (800340c ) 80033fe: 5ccb ldrb r3, [r1, r3] 8003400: fa22 f303 lsr.w r3, r2, r3 } 8003404: 4618 mov r0, r3 8003406: bd80 pop {r7, pc} 8003408: 40023800 .word 0x40023800 800340c: 08008fb8 .word 0x08008fb8 08003410 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003410: b580 push {r7, lr} 8003412: b08c sub sp, #48 ; 0x30 8003414: af00 add r7, sp, #0 8003416: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8003418: 2300 movs r3, #0 800341a: 627b str r3, [r7, #36] ; 0x24 uint32_t tmpreg1 = 0U; 800341c: 2300 movs r3, #0 800341e: 623b str r3, [r7, #32] uint32_t plli2sp = 0U; 8003420: 2300 movs r3, #0 8003422: 61fb str r3, [r7, #28] uint32_t plli2sq = 0U; 8003424: 2300 movs r3, #0 8003426: 61bb str r3, [r7, #24] uint32_t plli2sr = 0U; 8003428: 2300 movs r3, #0 800342a: 617b str r3, [r7, #20] uint32_t pllsaip = 0U; 800342c: 2300 movs r3, #0 800342e: 613b str r3, [r7, #16] uint32_t pllsaiq = 0U; 8003430: 2300 movs r3, #0 8003432: 60fb str r3, [r7, #12] uint32_t plli2sused = 0U; 8003434: 2300 movs r3, #0 8003436: 62fb str r3, [r7, #44] ; 0x2c uint32_t pllsaiused = 0U; 8003438: 2300 movs r3, #0 800343a: 62bb str r3, [r7, #40] ; 0x28 /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------ I2S APB1 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) 800343c: 687b ldr r3, [r7, #4] 800343e: 681b ldr r3, [r3, #0] 8003440: f003 0301 and.w r3, r3, #1 8003444: 2b00 cmp r3, #0 8003446: d010 beq.n 800346a { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); 8003448: 4b6f ldr r3, [pc, #444] ; (8003608 ) 800344a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 800344e: f023 62c0 bic.w r2, r3, #100663296 ; 0x6000000 8003452: 687b ldr r3, [r7, #4] 8003454: 6b9b ldr r3, [r3, #56] ; 0x38 8003456: 496c ldr r1, [pc, #432] ; (8003608 ) 8003458: 4313 orrs r3, r2 800345a: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) 800345e: 687b ldr r3, [r7, #4] 8003460: 6b9b ldr r3, [r3, #56] ; 0x38 8003462: 2b00 cmp r3, #0 8003464: d101 bne.n 800346a { plli2sused = 1U; 8003466: 2301 movs r3, #1 8003468: 62fb str r3, [r7, #44] ; 0x2c } } /*--------------------------------------------------------------------------*/ /*---------------------------- I2S APB2 configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) 800346a: 687b ldr r3, [r7, #4] 800346c: 681b ldr r3, [r3, #0] 800346e: f003 0302 and.w r3, r3, #2 8003472: 2b00 cmp r3, #0 8003474: d010 beq.n 8003498 { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); 8003476: 4b64 ldr r3, [pc, #400] ; (8003608 ) 8003478: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 800347c: f023 52c0 bic.w r2, r3, #402653184 ; 0x18000000 8003480: 687b ldr r3, [r7, #4] 8003482: 6bdb ldr r3, [r3, #60] ; 0x3c 8003484: 4960 ldr r1, [pc, #384] ; (8003608 ) 8003486: 4313 orrs r3, r2 8003488: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) 800348c: 687b ldr r3, [r7, #4] 800348e: 6bdb ldr r3, [r3, #60] ; 0x3c 8003490: 2b00 cmp r3, #0 8003492: d101 bne.n 8003498 { plli2sused = 1U; 8003494: 2301 movs r3, #1 8003496: 62fb str r3, [r7, #44] ; 0x2c } } /*--------------------------------------------------------------------------*/ /*--------------------------- SAI1 configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) 8003498: 687b ldr r3, [r7, #4] 800349a: 681b ldr r3, [r3, #0] 800349c: f003 0304 and.w r3, r3, #4 80034a0: 2b00 cmp r3, #0 80034a2: d017 beq.n 80034d4 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80034a4: 4b58 ldr r3, [pc, #352] ; (8003608 ) 80034a6: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80034aa: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 80034ae: 687b ldr r3, [r7, #4] 80034b0: 6b1b ldr r3, [r3, #48] ; 0x30 80034b2: 4955 ldr r1, [pc, #340] ; (8003608 ) 80034b4: 4313 orrs r3, r2 80034b6: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) 80034ba: 687b ldr r3, [r7, #4] 80034bc: 6b1b ldr r3, [r3, #48] ; 0x30 80034be: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 80034c2: d101 bne.n 80034c8 { plli2sused = 1U; 80034c4: 2301 movs r3, #1 80034c6: 62fb str r3, [r7, #44] ; 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) 80034c8: 687b ldr r3, [r7, #4] 80034ca: 6b1b ldr r3, [r3, #48] ; 0x30 80034cc: 2b00 cmp r3, #0 80034ce: d101 bne.n 80034d4 { pllsaiused = 1U; 80034d0: 2301 movs r3, #1 80034d2: 62bb str r3, [r7, #40] ; 0x28 } } /*--------------------------------------------------------------------------*/ /*-------------------------- SAI2 configuration ----------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) 80034d4: 687b ldr r3, [r7, #4] 80034d6: 681b ldr r3, [r3, #0] 80034d8: f003 0308 and.w r3, r3, #8 80034dc: 2b00 cmp r3, #0 80034de: d017 beq.n 8003510 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 80034e0: 4b49 ldr r3, [pc, #292] ; (8003608 ) 80034e2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80034e6: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 80034ea: 687b ldr r3, [r7, #4] 80034ec: 6b5b ldr r3, [r3, #52] ; 0x34 80034ee: 4946 ldr r1, [pc, #280] ; (8003608 ) 80034f0: 4313 orrs r3, r2 80034f2: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) 80034f6: 687b ldr r3, [r7, #4] 80034f8: 6b5b ldr r3, [r3, #52] ; 0x34 80034fa: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 80034fe: d101 bne.n 8003504 { plli2sused = 1U; 8003500: 2301 movs r3, #1 8003502: 62fb str r3, [r7, #44] ; 0x2c } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) 8003504: 687b ldr r3, [r7, #4] 8003506: 6b5b ldr r3, [r3, #52] ; 0x34 8003508: 2b00 cmp r3, #0 800350a: d101 bne.n 8003510 { pllsaiused = 1U; 800350c: 2301 movs r3, #1 800350e: 62bb str r3, [r7, #40] ; 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- RTC configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 8003510: 687b ldr r3, [r7, #4] 8003512: 681b ldr r3, [r3, #0] 8003514: f003 0320 and.w r3, r3, #32 8003518: 2b00 cmp r3, #0 800351a: f000 808a beq.w 8003632 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 800351e: 2300 movs r3, #0 8003520: 60bb str r3, [r7, #8] 8003522: 4b39 ldr r3, [pc, #228] ; (8003608 ) 8003524: 6c1b ldr r3, [r3, #64] ; 0x40 8003526: 4a38 ldr r2, [pc, #224] ; (8003608 ) 8003528: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800352c: 6413 str r3, [r2, #64] ; 0x40 800352e: 4b36 ldr r3, [pc, #216] ; (8003608 ) 8003530: 6c1b ldr r3, [r3, #64] ; 0x40 8003532: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003536: 60bb str r3, [r7, #8] 8003538: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 800353a: 4b34 ldr r3, [pc, #208] ; (800360c ) 800353c: 681b ldr r3, [r3, #0] 800353e: 4a33 ldr r2, [pc, #204] ; (800360c ) 8003540: f443 7380 orr.w r3, r3, #256 ; 0x100 8003544: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 8003546: f7fd fea9 bl 800129c 800354a: 6278 str r0, [r7, #36] ; 0x24 while((PWR->CR & PWR_CR_DBP) == RESET) 800354c: e008 b.n 8003560 { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) 800354e: f7fd fea5 bl 800129c 8003552: 4602 mov r2, r0 8003554: 6a7b ldr r3, [r7, #36] ; 0x24 8003556: 1ad3 subs r3, r2, r3 8003558: 2b02 cmp r3, #2 800355a: d901 bls.n 8003560 { return HAL_TIMEOUT; 800355c: 2303 movs r3, #3 800355e: e278 b.n 8003a52 while((PWR->CR & PWR_CR_DBP) == RESET) 8003560: 4b2a ldr r3, [pc, #168] ; (800360c ) 8003562: 681b ldr r3, [r3, #0] 8003564: f403 7380 and.w r3, r3, #256 ; 0x100 8003568: 2b00 cmp r3, #0 800356a: d0f0 beq.n 800354e } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 800356c: 4b26 ldr r3, [pc, #152] ; (8003608 ) 800356e: 6f1b ldr r3, [r3, #112] ; 0x70 8003570: f403 7340 and.w r3, r3, #768 ; 0x300 8003574: 623b str r3, [r7, #32] if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8003576: 6a3b ldr r3, [r7, #32] 8003578: 2b00 cmp r3, #0 800357a: d02f beq.n 80035dc 800357c: 687b ldr r3, [r7, #4] 800357e: 6c1b ldr r3, [r3, #64] ; 0x40 8003580: f403 7340 and.w r3, r3, #768 ; 0x300 8003584: 6a3a ldr r2, [r7, #32] 8003586: 429a cmp r2, r3 8003588: d028 beq.n 80035dc { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800358a: 4b1f ldr r3, [pc, #124] ; (8003608 ) 800358c: 6f1b ldr r3, [r3, #112] ; 0x70 800358e: f423 7340 bic.w r3, r3, #768 ; 0x300 8003592: 623b str r3, [r7, #32] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8003594: 4b1e ldr r3, [pc, #120] ; (8003610 ) 8003596: 2201 movs r2, #1 8003598: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 800359a: 4b1d ldr r3, [pc, #116] ; (8003610 ) 800359c: 2200 movs r2, #0 800359e: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 80035a0: 4a19 ldr r2, [pc, #100] ; (8003608 ) 80035a2: 6a3b ldr r3, [r7, #32] 80035a4: 6713 str r3, [r2, #112] ; 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 80035a6: 4b18 ldr r3, [pc, #96] ; (8003608 ) 80035a8: 6f1b ldr r3, [r3, #112] ; 0x70 80035aa: f003 0301 and.w r3, r3, #1 80035ae: 2b01 cmp r3, #1 80035b0: d114 bne.n 80035dc { /* Get tick */ tickstart = HAL_GetTick(); 80035b2: f7fd fe73 bl 800129c 80035b6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80035b8: e00a b.n 80035d0 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80035ba: f7fd fe6f bl 800129c 80035be: 4602 mov r2, r0 80035c0: 6a7b ldr r3, [r7, #36] ; 0x24 80035c2: 1ad3 subs r3, r2, r3 80035c4: f241 3288 movw r2, #5000 ; 0x1388 80035c8: 4293 cmp r3, r2 80035ca: d901 bls.n 80035d0 { return HAL_TIMEOUT; 80035cc: 2303 movs r3, #3 80035ce: e240 b.n 8003a52 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80035d0: 4b0d ldr r3, [pc, #52] ; (8003608 ) 80035d2: 6f1b ldr r3, [r3, #112] ; 0x70 80035d4: f003 0302 and.w r3, r3, #2 80035d8: 2b00 cmp r3, #0 80035da: d0ee beq.n 80035ba } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80035dc: 687b ldr r3, [r7, #4] 80035de: 6c1b ldr r3, [r3, #64] ; 0x40 80035e0: f403 7340 and.w r3, r3, #768 ; 0x300 80035e4: f5b3 7f40 cmp.w r3, #768 ; 0x300 80035e8: d114 bne.n 8003614 80035ea: 4b07 ldr r3, [pc, #28] ; (8003608 ) 80035ec: 689b ldr r3, [r3, #8] 80035ee: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 80035f2: 687b ldr r3, [r7, #4] 80035f4: 6c1b ldr r3, [r3, #64] ; 0x40 80035f6: f023 4370 bic.w r3, r3, #4026531840 ; 0xf0000000 80035fa: f423 7340 bic.w r3, r3, #768 ; 0x300 80035fe: 4902 ldr r1, [pc, #8] ; (8003608 ) 8003600: 4313 orrs r3, r2 8003602: 608b str r3, [r1, #8] 8003604: e00c b.n 8003620 8003606: bf00 nop 8003608: 40023800 .word 0x40023800 800360c: 40007000 .word 0x40007000 8003610: 42470e40 .word 0x42470e40 8003614: 4b4a ldr r3, [pc, #296] ; (8003740 ) 8003616: 689b ldr r3, [r3, #8] 8003618: 4a49 ldr r2, [pc, #292] ; (8003740 ) 800361a: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 800361e: 6093 str r3, [r2, #8] 8003620: 4b47 ldr r3, [pc, #284] ; (8003740 ) 8003622: 6f1a ldr r2, [r3, #112] ; 0x70 8003624: 687b ldr r3, [r7, #4] 8003626: 6c1b ldr r3, [r3, #64] ; 0x40 8003628: f3c3 030b ubfx r3, r3, #0, #12 800362c: 4944 ldr r1, [pc, #272] ; (8003740 ) 800362e: 4313 orrs r3, r2 8003630: 670b str r3, [r1, #112] ; 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8003632: 687b ldr r3, [r7, #4] 8003634: 681b ldr r3, [r3, #0] 8003636: f003 0310 and.w r3, r3, #16 800363a: 2b00 cmp r3, #0 800363c: d004 beq.n 8003648 { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800363e: 687b ldr r3, [r7, #4] 8003640: f893 2058 ldrb.w r2, [r3, #88] ; 0x58 8003644: 4b3f ldr r3, [pc, #252] ; (8003744 ) 8003646: 601a str r2, [r3, #0] } /*--------------------------------------------------------------------------*/ /*---------------------------- FMPI2C1 Configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) 8003648: 687b ldr r3, [r7, #4] 800364a: 681b ldr r3, [r3, #0] 800364c: f003 0380 and.w r3, r3, #128 ; 0x80 8003650: 2b00 cmp r3, #0 8003652: d00a beq.n 800366a { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); 8003654: 4b3a ldr r3, [pc, #232] ; (8003740 ) 8003656: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 800365a: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 800365e: 687b ldr r3, [r7, #4] 8003660: 6cdb ldr r3, [r3, #76] ; 0x4c 8003662: 4937 ldr r1, [pc, #220] ; (8003740 ) 8003664: 4313 orrs r3, r2 8003666: f8c1 3094 str.w r3, [r1, #148] ; 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ CEC Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800366a: 687b ldr r3, [r7, #4] 800366c: 681b ldr r3, [r3, #0] 800366e: f003 0340 and.w r3, r3, #64 ; 0x40 8003672: 2b00 cmp r3, #0 8003674: d00a beq.n 800368c { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8003676: 4b32 ldr r3, [pc, #200] ; (8003740 ) 8003678: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 800367c: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 8003680: 687b ldr r3, [r7, #4] 8003682: 6c9b ldr r3, [r3, #72] ; 0x48 8003684: 492e ldr r1, [pc, #184] ; (8003740 ) 8003686: 4313 orrs r3, r2 8003688: f8c1 3094 str.w r3, [r1, #148] ; 0x94 } /*--------------------------------------------------------------------------*/ /*----------------------------- CLK48 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) 800368c: 687b ldr r3, [r7, #4] 800368e: 681b ldr r3, [r3, #0] 8003690: f403 7380 and.w r3, r3, #256 ; 0x100 8003694: 2b00 cmp r3, #0 8003696: d011 beq.n 80036bc { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); 8003698: 4b29 ldr r3, [pc, #164] ; (8003740 ) 800369a: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 800369e: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 80036a2: 687b ldr r3, [r7, #4] 80036a4: 6d5b ldr r3, [r3, #84] ; 0x54 80036a6: 4926 ldr r1, [pc, #152] ; (8003740 ) 80036a8: 4313 orrs r3, r2 80036aa: f8c1 3094 str.w r3, [r1, #148] ; 0x94 /* Enable the PLLSAI when it's used as clock source for CLK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) 80036ae: 687b ldr r3, [r7, #4] 80036b0: 6d5b ldr r3, [r3, #84] ; 0x54 80036b2: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80036b6: d101 bne.n 80036bc { pllsaiused = 1U; 80036b8: 2301 movs r3, #1 80036ba: 62bb str r3, [r7, #40] ; 0x28 } } /*--------------------------------------------------------------------------*/ /*----------------------------- SDIO Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) 80036bc: 687b ldr r3, [r7, #4] 80036be: 681b ldr r3, [r3, #0] 80036c0: f403 7300 and.w r3, r3, #512 ; 0x200 80036c4: 2b00 cmp r3, #0 80036c6: d00a beq.n 80036de { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); 80036c8: 4b1d ldr r3, [pc, #116] ; (8003740 ) 80036ca: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 80036ce: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 80036d2: 687b ldr r3, [r7, #4] 80036d4: 6c5b ldr r3, [r3, #68] ; 0x44 80036d6: 491a ldr r1, [pc, #104] ; (8003740 ) 80036d8: 4313 orrs r3, r2 80036da: f8c1 3094 str.w r3, [r1, #148] ; 0x94 } /*--------------------------------------------------------------------------*/ /*------------------------------ SPDIFRX Configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80036de: 687b ldr r3, [r7, #4] 80036e0: 681b ldr r3, [r3, #0] 80036e2: f403 6380 and.w r3, r3, #1024 ; 0x400 80036e6: 2b00 cmp r3, #0 80036e8: d011 beq.n 800370e { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); 80036ea: 4b15 ldr r3, [pc, #84] ; (8003740 ) 80036ec: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 80036f0: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 80036f4: 687b ldr r3, [r7, #4] 80036f6: 6d1b ldr r3, [r3, #80] ; 0x50 80036f8: 4911 ldr r1, [pc, #68] ; (8003740 ) 80036fa: 4313 orrs r3, r2 80036fc: f8c1 3094 str.w r3, [r1, #148] ; 0x94 /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) 8003700: 687b ldr r3, [r7, #4] 8003702: 6d1b ldr r3, [r3, #80] ; 0x50 8003704: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8003708: d101 bne.n 800370e { plli2sused = 1U; 800370a: 2301 movs r3, #1 800370c: 62fb str r3, [r7, #44] ; 0x2c /*--------------------------------------------------------------------------*/ /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) 800370e: 6afb ldr r3, [r7, #44] ; 0x2c 8003710: 2b01 cmp r3, #1 8003712: d005 beq.n 8003720 8003714: 687b ldr r3, [r7, #4] 8003716: 681b ldr r3, [r3, #0] 8003718: f5b3 6f00 cmp.w r3, #2048 ; 0x800 800371c: f040 80ff bne.w 800391e { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8003720: 4b09 ldr r3, [pc, #36] ; (8003748 ) 8003722: 2200 movs r2, #0 8003724: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8003726: f7fd fdb9 bl 800129c 800372a: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 800372c: e00e b.n 800374c { if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) 800372e: f7fd fdb5 bl 800129c 8003732: 4602 mov r2, r0 8003734: 6a7b ldr r3, [r7, #36] ; 0x24 8003736: 1ad3 subs r3, r2, r3 8003738: 2b02 cmp r3, #2 800373a: d907 bls.n 800374c { /* return in case of Timeout detected */ return HAL_TIMEOUT; 800373c: 2303 movs r3, #3 800373e: e188 b.n 8003a52 8003740: 40023800 .word 0x40023800 8003744: 424711e0 .word 0x424711e0 8003748: 42470068 .word 0x42470068 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 800374c: 4b7e ldr r3, [pc, #504] ; (8003948 ) 800374e: 681b ldr r3, [r3, #0] 8003750: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8003754: 2b00 cmp r3, #0 8003756: d1ea bne.n 800372e /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8003758: 687b ldr r3, [r7, #4] 800375a: 681b ldr r3, [r3, #0] 800375c: f003 0301 and.w r3, r3, #1 8003760: 2b00 cmp r3, #0 8003762: d003 beq.n 800376c 8003764: 687b ldr r3, [r7, #4] 8003766: 6b9b ldr r3, [r3, #56] ; 0x38 8003768: 2b00 cmp r3, #0 800376a: d009 beq.n 8003780 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 800376c: 687b ldr r3, [r7, #4] 800376e: 681b ldr r3, [r3, #0] 8003770: f003 0302 and.w r3, r3, #2 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || 8003774: 2b00 cmp r3, #0 8003776: d028 beq.n 80037ca ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) 8003778: 687b ldr r3, [r7, #4] 800377a: 6bdb ldr r3, [r3, #60] ; 0x3c 800377c: 2b00 cmp r3, #0 800377e: d124 bne.n 80037ca { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 8003780: 4b71 ldr r3, [pc, #452] ; (8003948 ) 8003782: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8003786: 0c1b lsrs r3, r3, #16 8003788: f003 0303 and.w r3, r3, #3 800378c: 3301 adds r3, #1 800378e: 005b lsls r3, r3, #1 8003790: 61fb str r3, [r7, #28] plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); 8003792: 4b6d ldr r3, [pc, #436] ; (8003948 ) 8003794: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8003798: 0e1b lsrs r3, r3, #24 800379a: f003 030f and.w r3, r3, #15 800379e: 61bb str r3, [r7, #24] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); 80037a0: 687b ldr r3, [r7, #4] 80037a2: 685a ldr r2, [r3, #4] 80037a4: 687b ldr r3, [r7, #4] 80037a6: 689b ldr r3, [r3, #8] 80037a8: 019b lsls r3, r3, #6 80037aa: 431a orrs r2, r3 80037ac: 69fb ldr r3, [r7, #28] 80037ae: 085b lsrs r3, r3, #1 80037b0: 3b01 subs r3, #1 80037b2: 041b lsls r3, r3, #16 80037b4: 431a orrs r2, r3 80037b6: 69bb ldr r3, [r7, #24] 80037b8: 061b lsls r3, r3, #24 80037ba: 431a orrs r2, r3 80037bc: 687b ldr r3, [r7, #4] 80037be: 695b ldr r3, [r3, #20] 80037c0: 071b lsls r3, r3, #28 80037c2: 4961 ldr r1, [pc, #388] ; (8003948 ) 80037c4: 4313 orrs r3, r2 80037c6: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80037ca: 687b ldr r3, [r7, #4] 80037cc: 681b ldr r3, [r3, #0] 80037ce: f003 0304 and.w r3, r3, #4 80037d2: 2b00 cmp r3, #0 80037d4: d004 beq.n 80037e0 80037d6: 687b ldr r3, [r7, #4] 80037d8: 6b1b ldr r3, [r3, #48] ; 0x30 80037da: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 80037de: d00a beq.n 80037f6 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80037e0: 687b ldr r3, [r7, #4] 80037e2: 681b ldr r3, [r3, #0] 80037e4: f003 0308 and.w r3, r3, #8 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || 80037e8: 2b00 cmp r3, #0 80037ea: d035 beq.n 8003858 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) 80037ec: 687b ldr r3, [r7, #4] 80037ee: 6b5b ldr r3, [r3, #52] ; 0x34 80037f0: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 80037f4: d130 bne.n 8003858 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 80037f6: 4b54 ldr r3, [pc, #336] ; (8003948 ) 80037f8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80037fc: 0c1b lsrs r3, r3, #16 80037fe: f003 0303 and.w r3, r3, #3 8003802: 3301 adds r3, #1 8003804: 005b lsls r3, r3, #1 8003806: 61fb str r3, [r7, #28] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8003808: 4b4f ldr r3, [pc, #316] ; (8003948 ) 800380a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 800380e: 0f1b lsrs r3, r3, #28 8003810: f003 0307 and.w r3, r3, #7 8003814: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); 8003816: 687b ldr r3, [r7, #4] 8003818: 685a ldr r2, [r3, #4] 800381a: 687b ldr r3, [r7, #4] 800381c: 689b ldr r3, [r3, #8] 800381e: 019b lsls r3, r3, #6 8003820: 431a orrs r2, r3 8003822: 69fb ldr r3, [r7, #28] 8003824: 085b lsrs r3, r3, #1 8003826: 3b01 subs r3, #1 8003828: 041b lsls r3, r3, #16 800382a: 431a orrs r2, r3 800382c: 687b ldr r3, [r7, #4] 800382e: 691b ldr r3, [r3, #16] 8003830: 061b lsls r3, r3, #24 8003832: 431a orrs r2, r3 8003834: 697b ldr r3, [r7, #20] 8003836: 071b lsls r3, r3, #28 8003838: 4943 ldr r1, [pc, #268] ; (8003948 ) 800383a: 4313 orrs r3, r2 800383c: f8c1 3084 str.w r3, [r1, #132] ; 0x84 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8003840: 4b41 ldr r3, [pc, #260] ; (8003948 ) 8003842: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8003846: f023 021f bic.w r2, r3, #31 800384a: 687b ldr r3, [r7, #4] 800384c: 6a9b ldr r3, [r3, #40] ; 0x28 800384e: 3b01 subs r3, #1 8003850: 493d ldr r1, [pc, #244] ; (8003948 ) 8003852: 4313 orrs r3, r2 8003854: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 8003858: 687b ldr r3, [r7, #4] 800385a: 681b ldr r3, [r3, #0] 800385c: f403 6380 and.w r3, r3, #1024 ; 0x400 8003860: 2b00 cmp r3, #0 8003862: d029 beq.n 80038b8 8003864: 687b ldr r3, [r7, #4] 8003866: 6d1b ldr r3, [r3, #80] ; 0x50 8003868: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 800386c: d124 bne.n 80038b8 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); 800386e: 4b36 ldr r3, [pc, #216] ; (8003948 ) 8003870: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8003874: 0c1b lsrs r3, r3, #16 8003876: f003 0303 and.w r3, r3, #3 800387a: 3301 adds r3, #1 800387c: 005b lsls r3, r3, #1 800387e: 61bb str r3, [r7, #24] plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8003880: 4b31 ldr r3, [pc, #196] ; (8003948 ) 8003882: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8003886: 0f1b lsrs r3, r3, #28 8003888: f003 0307 and.w r3, r3, #7 800388c: 617b str r3, [r7, #20] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr); 800388e: 687b ldr r3, [r7, #4] 8003890: 685a ldr r2, [r3, #4] 8003892: 687b ldr r3, [r7, #4] 8003894: 689b ldr r3, [r3, #8] 8003896: 019b lsls r3, r3, #6 8003898: 431a orrs r2, r3 800389a: 687b ldr r3, [r7, #4] 800389c: 68db ldr r3, [r3, #12] 800389e: 085b lsrs r3, r3, #1 80038a0: 3b01 subs r3, #1 80038a2: 041b lsls r3, r3, #16 80038a4: 431a orrs r2, r3 80038a6: 69bb ldr r3, [r7, #24] 80038a8: 061b lsls r3, r3, #24 80038aa: 431a orrs r2, r3 80038ac: 697b ldr r3, [r7, #20] 80038ae: 071b lsls r3, r3, #28 80038b0: 4925 ldr r1, [pc, #148] ; (8003948 ) 80038b2: 4313 orrs r3, r2 80038b4: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 80038b8: 687b ldr r3, [r7, #4] 80038ba: 681b ldr r3, [r3, #0] 80038bc: f403 6300 and.w r3, r3, #2048 ; 0x800 80038c0: 2b00 cmp r3, #0 80038c2: d016 beq.n 80038f2 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); 80038c4: 687b ldr r3, [r7, #4] 80038c6: 685a ldr r2, [r3, #4] 80038c8: 687b ldr r3, [r7, #4] 80038ca: 689b ldr r3, [r3, #8] 80038cc: 019b lsls r3, r3, #6 80038ce: 431a orrs r2, r3 80038d0: 687b ldr r3, [r7, #4] 80038d2: 68db ldr r3, [r3, #12] 80038d4: 085b lsrs r3, r3, #1 80038d6: 3b01 subs r3, #1 80038d8: 041b lsls r3, r3, #16 80038da: 431a orrs r2, r3 80038dc: 687b ldr r3, [r7, #4] 80038de: 691b ldr r3, [r3, #16] 80038e0: 061b lsls r3, r3, #24 80038e2: 431a orrs r2, r3 80038e4: 687b ldr r3, [r7, #4] 80038e6: 695b ldr r3, [r3, #20] 80038e8: 071b lsls r3, r3, #28 80038ea: 4917 ldr r1, [pc, #92] ; (8003948 ) 80038ec: 4313 orrs r3, r2 80038ee: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 80038f2: 4b16 ldr r3, [pc, #88] ; (800394c ) 80038f4: 2201 movs r2, #1 80038f6: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80038f8: f7fd fcd0 bl 800129c 80038fc: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 80038fe: e008 b.n 8003912 { if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) 8003900: f7fd fccc bl 800129c 8003904: 4602 mov r2, r0 8003906: 6a7b ldr r3, [r7, #36] ; 0x24 8003908: 1ad3 subs r3, r2, r3 800390a: 2b02 cmp r3, #2 800390c: d901 bls.n 8003912 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 800390e: 2303 movs r3, #3 8003910: e09f b.n 8003a52 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8003912: 4b0d ldr r3, [pc, #52] ; (8003948 ) 8003914: 681b ldr r3, [r3, #0] 8003916: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 800391a: 2b00 cmp r3, #0 800391c: d0f0 beq.n 8003900 } /*--------------------------------------------------------------------------*/ /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if(pllsaiused == 1U) 800391e: 6abb ldr r3, [r7, #40] ; 0x28 8003920: 2b01 cmp r3, #1 8003922: f040 8095 bne.w 8003a50 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 8003926: 4b0a ldr r3, [pc, #40] ; (8003950 ) 8003928: 2200 movs r2, #0 800392a: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800392c: f7fd fcb6 bl 800129c 8003930: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8003932: e00f b.n 8003954 { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) 8003934: f7fd fcb2 bl 800129c 8003938: 4602 mov r2, r0 800393a: 6a7b ldr r3, [r7, #36] ; 0x24 800393c: 1ad3 subs r3, r2, r3 800393e: 2b02 cmp r3, #2 8003940: d908 bls.n 8003954 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8003942: 2303 movs r3, #3 8003944: e085 b.n 8003a52 8003946: bf00 nop 8003948: 40023800 .word 0x40023800 800394c: 42470068 .word 0x42470068 8003950: 42470070 .word 0x42470070 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8003954: 4b41 ldr r3, [pc, #260] ; (8003a5c ) 8003956: 681b ldr r3, [r3, #0] 8003958: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800395c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8003960: d0e8 beq.n 8003934 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 8003962: 687b ldr r3, [r7, #4] 8003964: 681b ldr r3, [r3, #0] 8003966: f003 0304 and.w r3, r3, #4 800396a: 2b00 cmp r3, #0 800396c: d003 beq.n 8003976 800396e: 687b ldr r3, [r7, #4] 8003970: 6b1b ldr r3, [r3, #48] ; 0x30 8003972: 2b00 cmp r3, #0 8003974: d009 beq.n 800398a ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8003976: 687b ldr r3, [r7, #4] 8003978: 681b ldr r3, [r3, #0] 800397a: f003 0308 and.w r3, r3, #8 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || 800397e: 2b00 cmp r3, #0 8003980: d02b beq.n 80039da ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) 8003982: 687b ldr r3, [r7, #4] 8003984: 6b5b ldr r3, [r3, #52] ; 0x34 8003986: 2b00 cmp r3, #0 8003988: d127 bne.n 80039da assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); 800398a: 4b34 ldr r3, [pc, #208] ; (8003a5c ) 800398c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8003990: 0c1b lsrs r3, r3, #16 8003992: f003 0303 and.w r3, r3, #3 8003996: 3301 adds r3, #1 8003998: 005b lsls r3, r3, #1 800399a: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U); 800399c: 687b ldr r3, [r7, #4] 800399e: 699a ldr r2, [r3, #24] 80039a0: 687b ldr r3, [r7, #4] 80039a2: 69db ldr r3, [r3, #28] 80039a4: 019b lsls r3, r3, #6 80039a6: 431a orrs r2, r3 80039a8: 693b ldr r3, [r7, #16] 80039aa: 085b lsrs r3, r3, #1 80039ac: 3b01 subs r3, #1 80039ae: 041b lsls r3, r3, #16 80039b0: 431a orrs r2, r3 80039b2: 687b ldr r3, [r7, #4] 80039b4: 6a5b ldr r3, [r3, #36] ; 0x24 80039b6: 061b lsls r3, r3, #24 80039b8: 4928 ldr r1, [pc, #160] ; (8003a5c ) 80039ba: 4313 orrs r3, r2 80039bc: f8c1 3088 str.w r3, [r1, #136] ; 0x88 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 80039c0: 4b26 ldr r3, [pc, #152] ; (8003a5c ) 80039c2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 80039c6: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 80039ca: 687b ldr r3, [r7, #4] 80039cc: 6adb ldr r3, [r3, #44] ; 0x2c 80039ce: 3b01 subs r3, #1 80039d0: 021b lsls r3, r3, #8 80039d2: 4922 ldr r1, [pc, #136] ; (8003a5c ) 80039d4: 4313 orrs r3, r2 80039d6: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ /* In Case of PLLI2S is selected as source clock for CLK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) 80039da: 687b ldr r3, [r7, #4] 80039dc: 681b ldr r3, [r3, #0] 80039de: f403 7380 and.w r3, r3, #256 ; 0x100 80039e2: 2b00 cmp r3, #0 80039e4: d01d beq.n 8003a22 80039e6: 687b ldr r3, [r7, #4] 80039e8: 6d5b ldr r3, [r3, #84] ; 0x54 80039ea: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80039ee: d118 bne.n 8003a22 { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 80039f0: 4b1a ldr r3, [pc, #104] ; (8003a5c ) 80039f2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80039f6: 0e1b lsrs r3, r3, #24 80039f8: f003 030f and.w r3, r3, #15 80039fc: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U); 80039fe: 687b ldr r3, [r7, #4] 8003a00: 699a ldr r2, [r3, #24] 8003a02: 687b ldr r3, [r7, #4] 8003a04: 69db ldr r3, [r3, #28] 8003a06: 019b lsls r3, r3, #6 8003a08: 431a orrs r2, r3 8003a0a: 687b ldr r3, [r7, #4] 8003a0c: 6a1b ldr r3, [r3, #32] 8003a0e: 085b lsrs r3, r3, #1 8003a10: 3b01 subs r3, #1 8003a12: 041b lsls r3, r3, #16 8003a14: 431a orrs r2, r3 8003a16: 68fb ldr r3, [r7, #12] 8003a18: 061b lsls r3, r3, #24 8003a1a: 4910 ldr r1, [pc, #64] ; (8003a5c ) 8003a1c: 4313 orrs r3, r2 8003a1e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 8003a22: 4b0f ldr r3, [pc, #60] ; (8003a60 ) 8003a24: 2201 movs r2, #1 8003a26: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8003a28: f7fd fc38 bl 800129c 8003a2c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLLSAI is ready */ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8003a2e: e008 b.n 8003a42 { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) 8003a30: f7fd fc34 bl 800129c 8003a34: 4602 mov r2, r0 8003a36: 6a7b ldr r3, [r7, #36] ; 0x24 8003a38: 1ad3 subs r3, r2, r3 8003a3a: 2b02 cmp r3, #2 8003a3c: d901 bls.n 8003a42 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8003a3e: 2303 movs r3, #3 8003a40: e007 b.n 8003a52 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 8003a42: 4b06 ldr r3, [pc, #24] ; (8003a5c ) 8003a44: 681b ldr r3, [r3, #0] 8003a46: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8003a4a: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8003a4e: d1ef bne.n 8003a30 } } } return HAL_OK; 8003a50: 2300 movs r3, #0 } 8003a52: 4618 mov r0, r3 8003a54: 3730 adds r7, #48 ; 0x30 8003a56: 46bd mov sp, r7 8003a58: bd80 pop {r7, pc} 8003a5a: bf00 nop 8003a5c: 40023800 .word 0x40023800 8003a60: 42470070 .word 0x42470070 08003a64 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003a64: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8003a68: b088 sub sp, #32 8003a6a: af00 add r7, sp, #0 uint32_t pllm = 0U; 8003a6c: 2300 movs r3, #0 8003a6e: 617b str r3, [r7, #20] uint32_t pllvco = 0U; 8003a70: 2300 movs r3, #0 8003a72: 61fb str r3, [r7, #28] uint32_t pllp = 0U; 8003a74: 2300 movs r3, #0 8003a76: 613b str r3, [r7, #16] uint32_t pllr = 0U; 8003a78: 2300 movs r3, #0 8003a7a: 60fb str r3, [r7, #12] uint32_t sysclockfreq = 0U; 8003a7c: 2300 movs r3, #0 8003a7e: 61bb str r3, [r7, #24] /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8003a80: 4bce ldr r3, [pc, #824] ; (8003dbc ) 8003a82: 689b ldr r3, [r3, #8] 8003a84: f003 030c and.w r3, r3, #12 8003a88: 2b0c cmp r3, #12 8003a8a: f200 818d bhi.w 8003da8 8003a8e: a201 add r2, pc, #4 ; (adr r2, 8003a94 ) 8003a90: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003a94: 08003ac9 .word 0x08003ac9 8003a98: 08003da9 .word 0x08003da9 8003a9c: 08003da9 .word 0x08003da9 8003aa0: 08003da9 .word 0x08003da9 8003aa4: 08003acf .word 0x08003acf 8003aa8: 08003da9 .word 0x08003da9 8003aac: 08003da9 .word 0x08003da9 8003ab0: 08003da9 .word 0x08003da9 8003ab4: 08003ad5 .word 0x08003ad5 8003ab8: 08003da9 .word 0x08003da9 8003abc: 08003da9 .word 0x08003da9 8003ac0: 08003da9 .word 0x08003da9 8003ac4: 08003c49 .word 0x08003c49 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8003ac8: 4bbd ldr r3, [pc, #756] ; (8003dc0 ) 8003aca: 61bb str r3, [r7, #24] break; 8003acc: e16f b.n 8003dae } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8003ace: 4bbd ldr r3, [pc, #756] ; (8003dc4 ) 8003ad0: 61bb str r3, [r7, #24] break; 8003ad2: e16c b.n 8003dae } case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8003ad4: 4bb9 ldr r3, [pc, #740] ; (8003dbc ) 8003ad6: 685b ldr r3, [r3, #4] 8003ad8: f003 033f and.w r3, r3, #63 ; 0x3f 8003adc: 617b str r3, [r7, #20] if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8003ade: 4bb7 ldr r3, [pc, #732] ; (8003dbc ) 8003ae0: 685b ldr r3, [r3, #4] 8003ae2: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8003ae6: 2b00 cmp r3, #0 8003ae8: d053 beq.n 8003b92 { /* HSE used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8003aea: 4bb4 ldr r3, [pc, #720] ; (8003dbc ) 8003aec: 685b ldr r3, [r3, #4] 8003aee: 099b lsrs r3, r3, #6 8003af0: 461a mov r2, r3 8003af2: f04f 0300 mov.w r3, #0 8003af6: f240 10ff movw r0, #511 ; 0x1ff 8003afa: f04f 0100 mov.w r1, #0 8003afe: ea02 0400 and.w r4, r2, r0 8003b02: 603c str r4, [r7, #0] 8003b04: 400b ands r3, r1 8003b06: 607b str r3, [r7, #4] 8003b08: e9d7 4500 ldrd r4, r5, [r7] 8003b0c: 4620 mov r0, r4 8003b0e: 4629 mov r1, r5 8003b10: f04f 0200 mov.w r2, #0 8003b14: f04f 0300 mov.w r3, #0 8003b18: 014b lsls r3, r1, #5 8003b1a: ea43 63d0 orr.w r3, r3, r0, lsr #27 8003b1e: 0142 lsls r2, r0, #5 8003b20: 4610 mov r0, r2 8003b22: 4619 mov r1, r3 8003b24: 4623 mov r3, r4 8003b26: 1ac0 subs r0, r0, r3 8003b28: 462b mov r3, r5 8003b2a: eb61 0103 sbc.w r1, r1, r3 8003b2e: f04f 0200 mov.w r2, #0 8003b32: f04f 0300 mov.w r3, #0 8003b36: 018b lsls r3, r1, #6 8003b38: ea43 6390 orr.w r3, r3, r0, lsr #26 8003b3c: 0182 lsls r2, r0, #6 8003b3e: 1a12 subs r2, r2, r0 8003b40: eb63 0301 sbc.w r3, r3, r1 8003b44: f04f 0000 mov.w r0, #0 8003b48: f04f 0100 mov.w r1, #0 8003b4c: 00d9 lsls r1, r3, #3 8003b4e: ea41 7152 orr.w r1, r1, r2, lsr #29 8003b52: 00d0 lsls r0, r2, #3 8003b54: 4602 mov r2, r0 8003b56: 460b mov r3, r1 8003b58: 4621 mov r1, r4 8003b5a: 1852 adds r2, r2, r1 8003b5c: 4629 mov r1, r5 8003b5e: eb43 0101 adc.w r1, r3, r1 8003b62: 460b mov r3, r1 8003b64: f04f 0000 mov.w r0, #0 8003b68: f04f 0100 mov.w r1, #0 8003b6c: 0259 lsls r1, r3, #9 8003b6e: ea41 51d2 orr.w r1, r1, r2, lsr #23 8003b72: 0250 lsls r0, r2, #9 8003b74: 4602 mov r2, r0 8003b76: 460b mov r3, r1 8003b78: 4610 mov r0, r2 8003b7a: 4619 mov r1, r3 8003b7c: 697b ldr r3, [r7, #20] 8003b7e: 461a mov r2, r3 8003b80: f04f 0300 mov.w r3, #0 8003b84: f7fc fb3e bl 8000204 <__aeabi_uldivmod> 8003b88: 4602 mov r2, r0 8003b8a: 460b mov r3, r1 8003b8c: 4613 mov r3, r2 8003b8e: 61fb str r3, [r7, #28] 8003b90: e04c b.n 8003c2c } else { /* HSI used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8003b92: 4b8a ldr r3, [pc, #552] ; (8003dbc ) 8003b94: 685b ldr r3, [r3, #4] 8003b96: 099b lsrs r3, r3, #6 8003b98: 461a mov r2, r3 8003b9a: f04f 0300 mov.w r3, #0 8003b9e: f240 10ff movw r0, #511 ; 0x1ff 8003ba2: f04f 0100 mov.w r1, #0 8003ba6: ea02 0a00 and.w sl, r2, r0 8003baa: ea03 0b01 and.w fp, r3, r1 8003bae: 4650 mov r0, sl 8003bb0: 4659 mov r1, fp 8003bb2: f04f 0200 mov.w r2, #0 8003bb6: f04f 0300 mov.w r3, #0 8003bba: 014b lsls r3, r1, #5 8003bbc: ea43 63d0 orr.w r3, r3, r0, lsr #27 8003bc0: 0142 lsls r2, r0, #5 8003bc2: 4610 mov r0, r2 8003bc4: 4619 mov r1, r3 8003bc6: ebb0 000a subs.w r0, r0, sl 8003bca: eb61 010b sbc.w r1, r1, fp 8003bce: f04f 0200 mov.w r2, #0 8003bd2: f04f 0300 mov.w r3, #0 8003bd6: 018b lsls r3, r1, #6 8003bd8: ea43 6390 orr.w r3, r3, r0, lsr #26 8003bdc: 0182 lsls r2, r0, #6 8003bde: 1a12 subs r2, r2, r0 8003be0: eb63 0301 sbc.w r3, r3, r1 8003be4: f04f 0000 mov.w r0, #0 8003be8: f04f 0100 mov.w r1, #0 8003bec: 00d9 lsls r1, r3, #3 8003bee: ea41 7152 orr.w r1, r1, r2, lsr #29 8003bf2: 00d0 lsls r0, r2, #3 8003bf4: 4602 mov r2, r0 8003bf6: 460b mov r3, r1 8003bf8: eb12 020a adds.w r2, r2, sl 8003bfc: eb43 030b adc.w r3, r3, fp 8003c00: f04f 0000 mov.w r0, #0 8003c04: f04f 0100 mov.w r1, #0 8003c08: 0299 lsls r1, r3, #10 8003c0a: ea41 5192 orr.w r1, r1, r2, lsr #22 8003c0e: 0290 lsls r0, r2, #10 8003c10: 4602 mov r2, r0 8003c12: 460b mov r3, r1 8003c14: 4610 mov r0, r2 8003c16: 4619 mov r1, r3 8003c18: 697b ldr r3, [r7, #20] 8003c1a: 461a mov r2, r3 8003c1c: f04f 0300 mov.w r3, #0 8003c20: f7fc faf0 bl 8000204 <__aeabi_uldivmod> 8003c24: 4602 mov r2, r0 8003c26: 460b mov r3, r1 8003c28: 4613 mov r3, r2 8003c2a: 61fb str r3, [r7, #28] } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); 8003c2c: 4b63 ldr r3, [pc, #396] ; (8003dbc ) 8003c2e: 685b ldr r3, [r3, #4] 8003c30: 0c1b lsrs r3, r3, #16 8003c32: f003 0303 and.w r3, r3, #3 8003c36: 3301 adds r3, #1 8003c38: 005b lsls r3, r3, #1 8003c3a: 613b str r3, [r7, #16] sysclockfreq = pllvco/pllp; 8003c3c: 69fa ldr r2, [r7, #28] 8003c3e: 693b ldr r3, [r7, #16] 8003c40: fbb2 f3f3 udiv r3, r2, r3 8003c44: 61bb str r3, [r7, #24] break; 8003c46: e0b2 b.n 8003dae } case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8003c48: 4b5c ldr r3, [pc, #368] ; (8003dbc ) 8003c4a: 685b ldr r3, [r3, #4] 8003c4c: f003 033f and.w r3, r3, #63 ; 0x3f 8003c50: 617b str r3, [r7, #20] if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8003c52: 4b5a ldr r3, [pc, #360] ; (8003dbc ) 8003c54: 685b ldr r3, [r3, #4] 8003c56: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8003c5a: 2b00 cmp r3, #0 8003c5c: d04d beq.n 8003cfa { /* HSE used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8003c5e: 4b57 ldr r3, [pc, #348] ; (8003dbc ) 8003c60: 685b ldr r3, [r3, #4] 8003c62: 099b lsrs r3, r3, #6 8003c64: 461a mov r2, r3 8003c66: f04f 0300 mov.w r3, #0 8003c6a: f240 10ff movw r0, #511 ; 0x1ff 8003c6e: f04f 0100 mov.w r1, #0 8003c72: ea02 0800 and.w r8, r2, r0 8003c76: ea03 0901 and.w r9, r3, r1 8003c7a: 4640 mov r0, r8 8003c7c: 4649 mov r1, r9 8003c7e: f04f 0200 mov.w r2, #0 8003c82: f04f 0300 mov.w r3, #0 8003c86: 014b lsls r3, r1, #5 8003c88: ea43 63d0 orr.w r3, r3, r0, lsr #27 8003c8c: 0142 lsls r2, r0, #5 8003c8e: 4610 mov r0, r2 8003c90: 4619 mov r1, r3 8003c92: ebb0 0008 subs.w r0, r0, r8 8003c96: eb61 0109 sbc.w r1, r1, r9 8003c9a: f04f 0200 mov.w r2, #0 8003c9e: f04f 0300 mov.w r3, #0 8003ca2: 018b lsls r3, r1, #6 8003ca4: ea43 6390 orr.w r3, r3, r0, lsr #26 8003ca8: 0182 lsls r2, r0, #6 8003caa: 1a12 subs r2, r2, r0 8003cac: eb63 0301 sbc.w r3, r3, r1 8003cb0: f04f 0000 mov.w r0, #0 8003cb4: f04f 0100 mov.w r1, #0 8003cb8: 00d9 lsls r1, r3, #3 8003cba: ea41 7152 orr.w r1, r1, r2, lsr #29 8003cbe: 00d0 lsls r0, r2, #3 8003cc0: 4602 mov r2, r0 8003cc2: 460b mov r3, r1 8003cc4: eb12 0208 adds.w r2, r2, r8 8003cc8: eb43 0309 adc.w r3, r3, r9 8003ccc: f04f 0000 mov.w r0, #0 8003cd0: f04f 0100 mov.w r1, #0 8003cd4: 0259 lsls r1, r3, #9 8003cd6: ea41 51d2 orr.w r1, r1, r2, lsr #23 8003cda: 0250 lsls r0, r2, #9 8003cdc: 4602 mov r2, r0 8003cde: 460b mov r3, r1 8003ce0: 4610 mov r0, r2 8003ce2: 4619 mov r1, r3 8003ce4: 697b ldr r3, [r7, #20] 8003ce6: 461a mov r2, r3 8003ce8: f04f 0300 mov.w r3, #0 8003cec: f7fc fa8a bl 8000204 <__aeabi_uldivmod> 8003cf0: 4602 mov r2, r0 8003cf2: 460b mov r3, r1 8003cf4: 4613 mov r3, r2 8003cf6: 61fb str r3, [r7, #28] 8003cf8: e04a b.n 8003d90 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8003cfa: 4b30 ldr r3, [pc, #192] ; (8003dbc ) 8003cfc: 685b ldr r3, [r3, #4] 8003cfe: 099b lsrs r3, r3, #6 8003d00: 461a mov r2, r3 8003d02: f04f 0300 mov.w r3, #0 8003d06: f240 10ff movw r0, #511 ; 0x1ff 8003d0a: f04f 0100 mov.w r1, #0 8003d0e: ea02 0400 and.w r4, r2, r0 8003d12: ea03 0501 and.w r5, r3, r1 8003d16: 4620 mov r0, r4 8003d18: 4629 mov r1, r5 8003d1a: f04f 0200 mov.w r2, #0 8003d1e: f04f 0300 mov.w r3, #0 8003d22: 014b lsls r3, r1, #5 8003d24: ea43 63d0 orr.w r3, r3, r0, lsr #27 8003d28: 0142 lsls r2, r0, #5 8003d2a: 4610 mov r0, r2 8003d2c: 4619 mov r1, r3 8003d2e: 1b00 subs r0, r0, r4 8003d30: eb61 0105 sbc.w r1, r1, r5 8003d34: f04f 0200 mov.w r2, #0 8003d38: f04f 0300 mov.w r3, #0 8003d3c: 018b lsls r3, r1, #6 8003d3e: ea43 6390 orr.w r3, r3, r0, lsr #26 8003d42: 0182 lsls r2, r0, #6 8003d44: 1a12 subs r2, r2, r0 8003d46: eb63 0301 sbc.w r3, r3, r1 8003d4a: f04f 0000 mov.w r0, #0 8003d4e: f04f 0100 mov.w r1, #0 8003d52: 00d9 lsls r1, r3, #3 8003d54: ea41 7152 orr.w r1, r1, r2, lsr #29 8003d58: 00d0 lsls r0, r2, #3 8003d5a: 4602 mov r2, r0 8003d5c: 460b mov r3, r1 8003d5e: 1912 adds r2, r2, r4 8003d60: eb45 0303 adc.w r3, r5, r3 8003d64: f04f 0000 mov.w r0, #0 8003d68: f04f 0100 mov.w r1, #0 8003d6c: 0299 lsls r1, r3, #10 8003d6e: ea41 5192 orr.w r1, r1, r2, lsr #22 8003d72: 0290 lsls r0, r2, #10 8003d74: 4602 mov r2, r0 8003d76: 460b mov r3, r1 8003d78: 4610 mov r0, r2 8003d7a: 4619 mov r1, r3 8003d7c: 697b ldr r3, [r7, #20] 8003d7e: 461a mov r2, r3 8003d80: f04f 0300 mov.w r3, #0 8003d84: f7fc fa3e bl 8000204 <__aeabi_uldivmod> 8003d88: 4602 mov r2, r0 8003d8a: 460b mov r3, r1 8003d8c: 4613 mov r3, r2 8003d8e: 61fb str r3, [r7, #28] } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); 8003d90: 4b0a ldr r3, [pc, #40] ; (8003dbc ) 8003d92: 685b ldr r3, [r3, #4] 8003d94: 0f1b lsrs r3, r3, #28 8003d96: f003 0307 and.w r3, r3, #7 8003d9a: 60fb str r3, [r7, #12] sysclockfreq = pllvco/pllr; 8003d9c: 69fa ldr r2, [r7, #28] 8003d9e: 68fb ldr r3, [r7, #12] 8003da0: fbb2 f3f3 udiv r3, r2, r3 8003da4: 61bb str r3, [r7, #24] break; 8003da6: e002 b.n 8003dae } default: { sysclockfreq = HSI_VALUE; 8003da8: 4b05 ldr r3, [pc, #20] ; (8003dc0 ) 8003daa: 61bb str r3, [r7, #24] break; 8003dac: bf00 nop } } return sysclockfreq; 8003dae: 69bb ldr r3, [r7, #24] } 8003db0: 4618 mov r0, r3 8003db2: 3720 adds r7, #32 8003db4: 46bd mov sp, r7 8003db6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8003dba: bf00 nop 8003dbc: 40023800 .word 0x40023800 8003dc0: 00f42400 .word 0x00f42400 8003dc4: 007a1200 .word 0x007a1200 08003dc8 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003dc8: b580 push {r7, lr} 8003dca: b086 sub sp, #24 8003dcc: af00 add r7, sp, #0 8003dce: 6078 str r0, [r7, #4] uint32_t tickstart, pll_config; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 8003dd0: 687b ldr r3, [r7, #4] 8003dd2: 2b00 cmp r3, #0 8003dd4: d101 bne.n 8003dda { return HAL_ERROR; 8003dd6: 2301 movs r3, #1 8003dd8: e28d b.n 80042f6 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8003dda: 687b ldr r3, [r7, #4] 8003ddc: 681b ldr r3, [r3, #0] 8003dde: f003 0301 and.w r3, r3, #1 8003de2: 2b00 cmp r3, #0 8003de4: f000 8083 beq.w 8003eee { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ #if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ 8003de8: 4b94 ldr r3, [pc, #592] ; (800403c ) 8003dea: 689b ldr r3, [r3, #8] 8003dec: f003 030c and.w r3, r3, #12 8003df0: 2b04 cmp r3, #4 8003df2: d019 beq.n 8003e28 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\ 8003df4: 4b91 ldr r3, [pc, #580] ; (800403c ) 8003df6: 689b ldr r3, [r3, #8] 8003df8: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ 8003dfc: 2b08 cmp r3, #8 8003dfe: d106 bne.n 8003e0e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\ 8003e00: 4b8e ldr r3, [pc, #568] ; (800403c ) 8003e02: 685b ldr r3, [r3, #4] 8003e04: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8003e08: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8003e0c: d00c beq.n 8003e28 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8003e0e: 4b8b ldr r3, [pc, #556] ; (800403c ) 8003e10: 689b ldr r3, [r3, #8] 8003e12: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\ 8003e16: 2b0c cmp r3, #12 8003e18: d112 bne.n 8003e40 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8003e1a: 4b88 ldr r3, [pc, #544] ; (800403c ) 8003e1c: 685b ldr r3, [r3, #4] 8003e1e: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8003e22: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8003e26: d10b bne.n 8003e40 #else if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #endif /* STM32F446xx */ { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003e28: 4b84 ldr r3, [pc, #528] ; (800403c ) 8003e2a: 681b ldr r3, [r3, #0] 8003e2c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003e30: 2b00 cmp r3, #0 8003e32: d05b beq.n 8003eec 8003e34: 687b ldr r3, [r7, #4] 8003e36: 685b ldr r3, [r3, #4] 8003e38: 2b00 cmp r3, #0 8003e3a: d157 bne.n 8003eec { return HAL_ERROR; 8003e3c: 2301 movs r3, #1 8003e3e: e25a b.n 80042f6 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8003e40: 687b ldr r3, [r7, #4] 8003e42: 685b ldr r3, [r3, #4] 8003e44: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003e48: d106 bne.n 8003e58 8003e4a: 4b7c ldr r3, [pc, #496] ; (800403c ) 8003e4c: 681b ldr r3, [r3, #0] 8003e4e: 4a7b ldr r2, [pc, #492] ; (800403c ) 8003e50: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003e54: 6013 str r3, [r2, #0] 8003e56: e01d b.n 8003e94 8003e58: 687b ldr r3, [r7, #4] 8003e5a: 685b ldr r3, [r3, #4] 8003e5c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003e60: d10c bne.n 8003e7c 8003e62: 4b76 ldr r3, [pc, #472] ; (800403c ) 8003e64: 681b ldr r3, [r3, #0] 8003e66: 4a75 ldr r2, [pc, #468] ; (800403c ) 8003e68: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8003e6c: 6013 str r3, [r2, #0] 8003e6e: 4b73 ldr r3, [pc, #460] ; (800403c ) 8003e70: 681b ldr r3, [r3, #0] 8003e72: 4a72 ldr r2, [pc, #456] ; (800403c ) 8003e74: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003e78: 6013 str r3, [r2, #0] 8003e7a: e00b b.n 8003e94 8003e7c: 4b6f ldr r3, [pc, #444] ; (800403c ) 8003e7e: 681b ldr r3, [r3, #0] 8003e80: 4a6e ldr r2, [pc, #440] ; (800403c ) 8003e82: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003e86: 6013 str r3, [r2, #0] 8003e88: 4b6c ldr r3, [pc, #432] ; (800403c ) 8003e8a: 681b ldr r3, [r3, #0] 8003e8c: 4a6b ldr r2, [pc, #428] ; (800403c ) 8003e8e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003e92: 6013 str r3, [r2, #0] /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8003e94: 687b ldr r3, [r7, #4] 8003e96: 685b ldr r3, [r3, #4] 8003e98: 2b00 cmp r3, #0 8003e9a: d013 beq.n 8003ec4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003e9c: f7fd f9fe bl 800129c 8003ea0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003ea2: e008 b.n 8003eb6 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8003ea4: f7fd f9fa bl 800129c 8003ea8: 4602 mov r2, r0 8003eaa: 693b ldr r3, [r7, #16] 8003eac: 1ad3 subs r3, r2, r3 8003eae: 2b64 cmp r3, #100 ; 0x64 8003eb0: d901 bls.n 8003eb6 { return HAL_TIMEOUT; 8003eb2: 2303 movs r3, #3 8003eb4: e21f b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003eb6: 4b61 ldr r3, [pc, #388] ; (800403c ) 8003eb8: 681b ldr r3, [r3, #0] 8003eba: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003ebe: 2b00 cmp r3, #0 8003ec0: d0f0 beq.n 8003ea4 8003ec2: e014 b.n 8003eee } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ec4: f7fd f9ea bl 800129c 8003ec8: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8003eca: e008 b.n 8003ede { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8003ecc: f7fd f9e6 bl 800129c 8003ed0: 4602 mov r2, r0 8003ed2: 693b ldr r3, [r7, #16] 8003ed4: 1ad3 subs r3, r2, r3 8003ed6: 2b64 cmp r3, #100 ; 0x64 8003ed8: d901 bls.n 8003ede { return HAL_TIMEOUT; 8003eda: 2303 movs r3, #3 8003edc: e20b b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8003ede: 4b57 ldr r3, [pc, #348] ; (800403c ) 8003ee0: 681b ldr r3, [r3, #0] 8003ee2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003ee6: 2b00 cmp r3, #0 8003ee8: d1f0 bne.n 8003ecc 8003eea: e000 b.n 8003eee if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003eec: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003eee: 687b ldr r3, [r7, #4] 8003ef0: 681b ldr r3, [r3, #0] 8003ef2: f003 0302 and.w r3, r3, #2 8003ef6: 2b00 cmp r3, #0 8003ef8: d06f beq.n 8003fda assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ 8003efa: 4b50 ldr r3, [pc, #320] ; (800403c ) 8003efc: 689b ldr r3, [r3, #8] 8003efe: f003 030c and.w r3, r3, #12 8003f02: 2b00 cmp r3, #0 8003f04: d017 beq.n 8003f36 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\ 8003f06: 4b4d ldr r3, [pc, #308] ; (800403c ) 8003f08: 689b ldr r3, [r3, #8] 8003f0a: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ 8003f0e: 2b08 cmp r3, #8 8003f10: d105 bne.n 8003f1e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\ 8003f12: 4b4a ldr r3, [pc, #296] ; (800403c ) 8003f14: 685b ldr r3, [r3, #4] 8003f16: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8003f1a: 2b00 cmp r3, #0 8003f1c: d00b beq.n 8003f36 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8003f1e: 4b47 ldr r3, [pc, #284] ; (800403c ) 8003f20: 689b ldr r3, [r3, #8] 8003f22: f003 030c and.w r3, r3, #12 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\ 8003f26: 2b0c cmp r3, #12 8003f28: d11c bne.n 8003f64 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8003f2a: 4b44 ldr r3, [pc, #272] ; (800403c ) 8003f2c: 685b ldr r3, [r3, #4] 8003f2e: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8003f32: 2b00 cmp r3, #0 8003f34: d116 bne.n 8003f64 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8003f36: 4b41 ldr r3, [pc, #260] ; (800403c ) 8003f38: 681b ldr r3, [r3, #0] 8003f3a: f003 0302 and.w r3, r3, #2 8003f3e: 2b00 cmp r3, #0 8003f40: d005 beq.n 8003f4e 8003f42: 687b ldr r3, [r7, #4] 8003f44: 68db ldr r3, [r3, #12] 8003f46: 2b01 cmp r3, #1 8003f48: d001 beq.n 8003f4e { return HAL_ERROR; 8003f4a: 2301 movs r3, #1 8003f4c: e1d3 b.n 80042f6 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003f4e: 4b3b ldr r3, [pc, #236] ; (800403c ) 8003f50: 681b ldr r3, [r3, #0] 8003f52: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8003f56: 687b ldr r3, [r7, #4] 8003f58: 691b ldr r3, [r3, #16] 8003f5a: 00db lsls r3, r3, #3 8003f5c: 4937 ldr r1, [pc, #220] ; (800403c ) 8003f5e: 4313 orrs r3, r2 8003f60: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8003f62: e03a b.n 8003fda } } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 8003f64: 687b ldr r3, [r7, #4] 8003f66: 68db ldr r3, [r3, #12] 8003f68: 2b00 cmp r3, #0 8003f6a: d020 beq.n 8003fae { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8003f6c: 4b34 ldr r3, [pc, #208] ; (8004040 ) 8003f6e: 2201 movs r2, #1 8003f70: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003f72: f7fd f993 bl 800129c 8003f76: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003f78: e008 b.n 8003f8c { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8003f7a: f7fd f98f bl 800129c 8003f7e: 4602 mov r2, r0 8003f80: 693b ldr r3, [r7, #16] 8003f82: 1ad3 subs r3, r2, r3 8003f84: 2b02 cmp r3, #2 8003f86: d901 bls.n 8003f8c { return HAL_TIMEOUT; 8003f88: 2303 movs r3, #3 8003f8a: e1b4 b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003f8c: 4b2b ldr r3, [pc, #172] ; (800403c ) 8003f8e: 681b ldr r3, [r3, #0] 8003f90: f003 0302 and.w r3, r3, #2 8003f94: 2b00 cmp r3, #0 8003f96: d0f0 beq.n 8003f7a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003f98: 4b28 ldr r3, [pc, #160] ; (800403c ) 8003f9a: 681b ldr r3, [r3, #0] 8003f9c: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8003fa0: 687b ldr r3, [r7, #4] 8003fa2: 691b ldr r3, [r3, #16] 8003fa4: 00db lsls r3, r3, #3 8003fa6: 4925 ldr r1, [pc, #148] ; (800403c ) 8003fa8: 4313 orrs r3, r2 8003faa: 600b str r3, [r1, #0] 8003fac: e015 b.n 8003fda } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003fae: 4b24 ldr r3, [pc, #144] ; (8004040 ) 8003fb0: 2200 movs r2, #0 8003fb2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003fb4: f7fd f972 bl 800129c 8003fb8: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003fba: e008 b.n 8003fce { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8003fbc: f7fd f96e bl 800129c 8003fc0: 4602 mov r2, r0 8003fc2: 693b ldr r3, [r7, #16] 8003fc4: 1ad3 subs r3, r2, r3 8003fc6: 2b02 cmp r3, #2 8003fc8: d901 bls.n 8003fce { return HAL_TIMEOUT; 8003fca: 2303 movs r3, #3 8003fcc: e193 b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003fce: 4b1b ldr r3, [pc, #108] ; (800403c ) 8003fd0: 681b ldr r3, [r3, #0] 8003fd2: f003 0302 and.w r3, r3, #2 8003fd6: 2b00 cmp r3, #0 8003fd8: d1f0 bne.n 8003fbc } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003fda: 687b ldr r3, [r7, #4] 8003fdc: 681b ldr r3, [r3, #0] 8003fde: f003 0308 and.w r3, r3, #8 8003fe2: 2b00 cmp r3, #0 8003fe4: d036 beq.n 8004054 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 8003fe6: 687b ldr r3, [r7, #4] 8003fe8: 695b ldr r3, [r3, #20] 8003fea: 2b00 cmp r3, #0 8003fec: d016 beq.n 800401c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003fee: 4b15 ldr r3, [pc, #84] ; (8004044 ) 8003ff0: 2201 movs r2, #1 8003ff2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ff4: f7fd f952 bl 800129c 8003ff8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8003ffa: e008 b.n 800400e { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8003ffc: f7fd f94e bl 800129c 8004000: 4602 mov r2, r0 8004002: 693b ldr r3, [r7, #16] 8004004: 1ad3 subs r3, r2, r3 8004006: 2b02 cmp r3, #2 8004008: d901 bls.n 800400e { return HAL_TIMEOUT; 800400a: 2303 movs r3, #3 800400c: e173 b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800400e: 4b0b ldr r3, [pc, #44] ; (800403c ) 8004010: 6f5b ldr r3, [r3, #116] ; 0x74 8004012: f003 0302 and.w r3, r3, #2 8004016: 2b00 cmp r3, #0 8004018: d0f0 beq.n 8003ffc 800401a: e01b b.n 8004054 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800401c: 4b09 ldr r3, [pc, #36] ; (8004044 ) 800401e: 2200 movs r2, #0 8004020: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004022: f7fd f93b bl 800129c 8004026: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004028: e00e b.n 8004048 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 800402a: f7fd f937 bl 800129c 800402e: 4602 mov r2, r0 8004030: 693b ldr r3, [r7, #16] 8004032: 1ad3 subs r3, r2, r3 8004034: 2b02 cmp r3, #2 8004036: d907 bls.n 8004048 { return HAL_TIMEOUT; 8004038: 2303 movs r3, #3 800403a: e15c b.n 80042f6 800403c: 40023800 .word 0x40023800 8004040: 42470000 .word 0x42470000 8004044: 42470e80 .word 0x42470e80 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004048: 4b8a ldr r3, [pc, #552] ; (8004274 ) 800404a: 6f5b ldr r3, [r3, #116] ; 0x74 800404c: f003 0302 and.w r3, r3, #2 8004050: 2b00 cmp r3, #0 8004052: d1ea bne.n 800402a } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004054: 687b ldr r3, [r7, #4] 8004056: 681b ldr r3, [r3, #0] 8004058: f003 0304 and.w r3, r3, #4 800405c: 2b00 cmp r3, #0 800405e: f000 8097 beq.w 8004190 { FlagStatus pwrclkchanged = RESET; 8004062: 2300 movs r3, #0 8004064: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004066: 4b83 ldr r3, [pc, #524] ; (8004274 ) 8004068: 6c1b ldr r3, [r3, #64] ; 0x40 800406a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800406e: 2b00 cmp r3, #0 8004070: d10f bne.n 8004092 { __HAL_RCC_PWR_CLK_ENABLE(); 8004072: 2300 movs r3, #0 8004074: 60bb str r3, [r7, #8] 8004076: 4b7f ldr r3, [pc, #508] ; (8004274 ) 8004078: 6c1b ldr r3, [r3, #64] ; 0x40 800407a: 4a7e ldr r2, [pc, #504] ; (8004274 ) 800407c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8004080: 6413 str r3, [r2, #64] ; 0x40 8004082: 4b7c ldr r3, [pc, #496] ; (8004274 ) 8004084: 6c1b ldr r3, [r3, #64] ; 0x40 8004086: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800408a: 60bb str r3, [r7, #8] 800408c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800408e: 2301 movs r3, #1 8004090: 75fb strb r3, [r7, #23] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004092: 4b79 ldr r3, [pc, #484] ; (8004278 ) 8004094: 681b ldr r3, [r3, #0] 8004096: f403 7380 and.w r3, r3, #256 ; 0x100 800409a: 2b00 cmp r3, #0 800409c: d118 bne.n 80040d0 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800409e: 4b76 ldr r3, [pc, #472] ; (8004278 ) 80040a0: 681b ldr r3, [r3, #0] 80040a2: 4a75 ldr r2, [pc, #468] ; (8004278 ) 80040a4: f443 7380 orr.w r3, r3, #256 ; 0x100 80040a8: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80040aa: f7fd f8f7 bl 800129c 80040ae: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80040b0: e008 b.n 80040c4 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80040b2: f7fd f8f3 bl 800129c 80040b6: 4602 mov r2, r0 80040b8: 693b ldr r3, [r7, #16] 80040ba: 1ad3 subs r3, r2, r3 80040bc: 2b02 cmp r3, #2 80040be: d901 bls.n 80040c4 { return HAL_TIMEOUT; 80040c0: 2303 movs r3, #3 80040c2: e118 b.n 80042f6 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80040c4: 4b6c ldr r3, [pc, #432] ; (8004278 ) 80040c6: 681b ldr r3, [r3, #0] 80040c8: f403 7380 and.w r3, r3, #256 ; 0x100 80040cc: 2b00 cmp r3, #0 80040ce: d0f0 beq.n 80040b2 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80040d0: 687b ldr r3, [r7, #4] 80040d2: 689b ldr r3, [r3, #8] 80040d4: 2b01 cmp r3, #1 80040d6: d106 bne.n 80040e6 80040d8: 4b66 ldr r3, [pc, #408] ; (8004274 ) 80040da: 6f1b ldr r3, [r3, #112] ; 0x70 80040dc: 4a65 ldr r2, [pc, #404] ; (8004274 ) 80040de: f043 0301 orr.w r3, r3, #1 80040e2: 6713 str r3, [r2, #112] ; 0x70 80040e4: e01c b.n 8004120 80040e6: 687b ldr r3, [r7, #4] 80040e8: 689b ldr r3, [r3, #8] 80040ea: 2b05 cmp r3, #5 80040ec: d10c bne.n 8004108 80040ee: 4b61 ldr r3, [pc, #388] ; (8004274 ) 80040f0: 6f1b ldr r3, [r3, #112] ; 0x70 80040f2: 4a60 ldr r2, [pc, #384] ; (8004274 ) 80040f4: f043 0304 orr.w r3, r3, #4 80040f8: 6713 str r3, [r2, #112] ; 0x70 80040fa: 4b5e ldr r3, [pc, #376] ; (8004274 ) 80040fc: 6f1b ldr r3, [r3, #112] ; 0x70 80040fe: 4a5d ldr r2, [pc, #372] ; (8004274 ) 8004100: f043 0301 orr.w r3, r3, #1 8004104: 6713 str r3, [r2, #112] ; 0x70 8004106: e00b b.n 8004120 8004108: 4b5a ldr r3, [pc, #360] ; (8004274 ) 800410a: 6f1b ldr r3, [r3, #112] ; 0x70 800410c: 4a59 ldr r2, [pc, #356] ; (8004274 ) 800410e: f023 0301 bic.w r3, r3, #1 8004112: 6713 str r3, [r2, #112] ; 0x70 8004114: 4b57 ldr r3, [pc, #348] ; (8004274 ) 8004116: 6f1b ldr r3, [r3, #112] ; 0x70 8004118: 4a56 ldr r2, [pc, #344] ; (8004274 ) 800411a: f023 0304 bic.w r3, r3, #4 800411e: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8004120: 687b ldr r3, [r7, #4] 8004122: 689b ldr r3, [r3, #8] 8004124: 2b00 cmp r3, #0 8004126: d015 beq.n 8004154 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004128: f7fd f8b8 bl 800129c 800412c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800412e: e00a b.n 8004146 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8004130: f7fd f8b4 bl 800129c 8004134: 4602 mov r2, r0 8004136: 693b ldr r3, [r7, #16] 8004138: 1ad3 subs r3, r2, r3 800413a: f241 3288 movw r2, #5000 ; 0x1388 800413e: 4293 cmp r3, r2 8004140: d901 bls.n 8004146 { return HAL_TIMEOUT; 8004142: 2303 movs r3, #3 8004144: e0d7 b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004146: 4b4b ldr r3, [pc, #300] ; (8004274 ) 8004148: 6f1b ldr r3, [r3, #112] ; 0x70 800414a: f003 0302 and.w r3, r3, #2 800414e: 2b00 cmp r3, #0 8004150: d0ee beq.n 8004130 8004152: e014 b.n 800417e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004154: f7fd f8a2 bl 800129c 8004158: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800415a: e00a b.n 8004172 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 800415c: f7fd f89e bl 800129c 8004160: 4602 mov r2, r0 8004162: 693b ldr r3, [r7, #16] 8004164: 1ad3 subs r3, r2, r3 8004166: f241 3288 movw r2, #5000 ; 0x1388 800416a: 4293 cmp r3, r2 800416c: d901 bls.n 8004172 { return HAL_TIMEOUT; 800416e: 2303 movs r3, #3 8004170: e0c1 b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004172: 4b40 ldr r3, [pc, #256] ; (8004274 ) 8004174: 6f1b ldr r3, [r3, #112] ; 0x70 8004176: f003 0302 and.w r3, r3, #2 800417a: 2b00 cmp r3, #0 800417c: d1ee bne.n 800415c } } } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 800417e: 7dfb ldrb r3, [r7, #23] 8004180: 2b01 cmp r3, #1 8004182: d105 bne.n 8004190 { __HAL_RCC_PWR_CLK_DISABLE(); 8004184: 4b3b ldr r3, [pc, #236] ; (8004274 ) 8004186: 6c1b ldr r3, [r3, #64] ; 0x40 8004188: 4a3a ldr r2, [pc, #232] ; (8004274 ) 800418a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800418e: 6413 str r3, [r2, #64] ; 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8004190: 687b ldr r3, [r7, #4] 8004192: 699b ldr r3, [r3, #24] 8004194: 2b00 cmp r3, #0 8004196: f000 80ad beq.w 80042f4 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 800419a: 4b36 ldr r3, [pc, #216] ; (8004274 ) 800419c: 689b ldr r3, [r3, #8] 800419e: f003 030c and.w r3, r3, #12 80041a2: 2b08 cmp r3, #8 80041a4: d060 beq.n 8004268 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80041a6: 687b ldr r3, [r7, #4] 80041a8: 699b ldr r3, [r3, #24] 80041aa: 2b02 cmp r3, #2 80041ac: d145 bne.n 800423a assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80041ae: 4b33 ldr r3, [pc, #204] ; (800427c ) 80041b0: 2200 movs r2, #0 80041b2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80041b4: f7fd f872 bl 800129c 80041b8: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80041ba: e008 b.n 80041ce { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80041bc: f7fd f86e bl 800129c 80041c0: 4602 mov r2, r0 80041c2: 693b ldr r3, [r7, #16] 80041c4: 1ad3 subs r3, r2, r3 80041c6: 2b02 cmp r3, #2 80041c8: d901 bls.n 80041ce { return HAL_TIMEOUT; 80041ca: 2303 movs r3, #3 80041cc: e093 b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80041ce: 4b29 ldr r3, [pc, #164] ; (8004274 ) 80041d0: 681b ldr r3, [r3, #0] 80041d2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80041d6: 2b00 cmp r3, #0 80041d8: d1f0 bne.n 80041bc } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 80041da: 687b ldr r3, [r7, #4] 80041dc: 69da ldr r2, [r3, #28] 80041de: 687b ldr r3, [r7, #4] 80041e0: 6a1b ldr r3, [r3, #32] 80041e2: 431a orrs r2, r3 80041e4: 687b ldr r3, [r7, #4] 80041e6: 6a5b ldr r3, [r3, #36] ; 0x24 80041e8: 019b lsls r3, r3, #6 80041ea: 431a orrs r2, r3 80041ec: 687b ldr r3, [r7, #4] 80041ee: 6a9b ldr r3, [r3, #40] ; 0x28 80041f0: 085b lsrs r3, r3, #1 80041f2: 3b01 subs r3, #1 80041f4: 041b lsls r3, r3, #16 80041f6: 431a orrs r2, r3 80041f8: 687b ldr r3, [r7, #4] 80041fa: 6adb ldr r3, [r3, #44] ; 0x2c 80041fc: 061b lsls r3, r3, #24 80041fe: 431a orrs r2, r3 8004200: 687b ldr r3, [r7, #4] 8004202: 6b1b ldr r3, [r3, #48] ; 0x30 8004204: 071b lsls r3, r3, #28 8004206: 491b ldr r1, [pc, #108] ; (8004274 ) 8004208: 4313 orrs r3, r2 800420a: 604b str r3, [r1, #4] (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800420c: 4b1b ldr r3, [pc, #108] ; (800427c ) 800420e: 2201 movs r2, #1 8004210: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004212: f7fd f843 bl 800129c 8004216: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004218: e008 b.n 800422c { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800421a: f7fd f83f bl 800129c 800421e: 4602 mov r2, r0 8004220: 693b ldr r3, [r7, #16] 8004222: 1ad3 subs r3, r2, r3 8004224: 2b02 cmp r3, #2 8004226: d901 bls.n 800422c { return HAL_TIMEOUT; 8004228: 2303 movs r3, #3 800422a: e064 b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800422c: 4b11 ldr r3, [pc, #68] ; (8004274 ) 800422e: 681b ldr r3, [r3, #0] 8004230: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004234: 2b00 cmp r3, #0 8004236: d0f0 beq.n 800421a 8004238: e05c b.n 80042f4 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800423a: 4b10 ldr r3, [pc, #64] ; (800427c ) 800423c: 2200 movs r2, #0 800423e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004240: f7fd f82c bl 800129c 8004244: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004246: e008 b.n 800425a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8004248: f7fd f828 bl 800129c 800424c: 4602 mov r2, r0 800424e: 693b ldr r3, [r7, #16] 8004250: 1ad3 subs r3, r2, r3 8004252: 2b02 cmp r3, #2 8004254: d901 bls.n 800425a { return HAL_TIMEOUT; 8004256: 2303 movs r3, #3 8004258: e04d b.n 80042f6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800425a: 4b06 ldr r3, [pc, #24] ; (8004274 ) 800425c: 681b ldr r3, [r3, #0] 800425e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004262: 2b00 cmp r3, #0 8004264: d1f0 bne.n 8004248 8004266: e045 b.n 80042f4 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8004268: 687b ldr r3, [r7, #4] 800426a: 699b ldr r3, [r3, #24] 800426c: 2b01 cmp r3, #1 800426e: d107 bne.n 8004280 { return HAL_ERROR; 8004270: 2301 movs r3, #1 8004272: e040 b.n 80042f6 8004274: 40023800 .word 0x40023800 8004278: 40007000 .word 0x40007000 800427c: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 8004280: 4b1f ldr r3, [pc, #124] ; (8004300 ) 8004282: 685b ldr r3, [r3, #4] 8004284: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8004286: 687b ldr r3, [r7, #4] 8004288: 699b ldr r3, [r3, #24] 800428a: 2b01 cmp r3, #1 800428c: d030 beq.n 80042f0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800428e: 68fb ldr r3, [r7, #12] 8004290: f403 0280 and.w r2, r3, #4194304 ; 0x400000 8004294: 687b ldr r3, [r7, #4] 8004296: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8004298: 429a cmp r2, r3 800429a: d129 bne.n 80042f0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 800429c: 68fb ldr r3, [r7, #12] 800429e: f003 023f and.w r2, r3, #63 ; 0x3f 80042a2: 687b ldr r3, [r7, #4] 80042a4: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80042a6: 429a cmp r2, r3 80042a8: d122 bne.n 80042f0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80042aa: 68fa ldr r2, [r7, #12] 80042ac: f647 73c0 movw r3, #32704 ; 0x7fc0 80042b0: 4013 ands r3, r2 80042b2: 687a ldr r2, [r7, #4] 80042b4: 6a52 ldr r2, [r2, #36] ; 0x24 80042b6: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80042b8: 4293 cmp r3, r2 80042ba: d119 bne.n 80042f0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80042bc: 68fb ldr r3, [r7, #12] 80042be: f403 3240 and.w r2, r3, #196608 ; 0x30000 80042c2: 687b ldr r3, [r7, #4] 80042c4: 6a9b ldr r3, [r3, #40] ; 0x28 80042c6: 085b lsrs r3, r3, #1 80042c8: 3b01 subs r3, #1 80042ca: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80042cc: 429a cmp r2, r3 80042ce: d10f bne.n 80042f0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80042d0: 68fb ldr r3, [r7, #12] 80042d2: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 80042d6: 687b ldr r3, [r7, #4] 80042d8: 6adb ldr r3, [r3, #44] ; 0x2c 80042da: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80042dc: 429a cmp r2, r3 80042de: d107 bne.n 80042f0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) 80042e0: 68fb ldr r3, [r7, #12] 80042e2: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 80042e6: 687b ldr r3, [r7, #4] 80042e8: 6b1b ldr r3, [r3, #48] ; 0x30 80042ea: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || 80042ec: 429a cmp r2, r3 80042ee: d001 beq.n 80042f4 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif { return HAL_ERROR; 80042f0: 2301 movs r3, #1 80042f2: e000 b.n 80042f6 } } } } return HAL_OK; 80042f4: 2300 movs r3, #0 } 80042f6: 4618 mov r0, r3 80042f8: 3718 adds r7, #24 80042fa: 46bd mov sp, r7 80042fc: bd80 pop {r7, pc} 80042fe: bf00 nop 8004300: 40023800 .word 0x40023800 08004304 : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { 8004304: b580 push {r7, lr} 8004306: b082 sub sp, #8 8004308: af00 add r7, sp, #0 800430a: 6078 str r0, [r7, #4] /* Check the RTC peripheral state */ if(hrtc == NULL) 800430c: 687b ldr r3, [r7, #4] 800430e: 2b00 cmp r3, #0 8004310: d101 bne.n 8004316 { return HAL_ERROR; 8004312: 2301 movs r3, #1 8004314: e083 b.n 800441e { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else if(hrtc->State == HAL_RTC_STATE_RESET) 8004316: 687b ldr r3, [r7, #4] 8004318: 7f5b ldrb r3, [r3, #29] 800431a: b2db uxtb r3, r3 800431c: 2b00 cmp r3, #0 800431e: d105 bne.n 800432c { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; 8004320: 687b ldr r3, [r7, #4] 8004322: 2200 movs r2, #0 8004324: 771a strb r2, [r3, #28] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); 8004326: 6878 ldr r0, [r7, #4] 8004328: f7fc fdae bl 8000e88 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; 800432c: 687b ldr r3, [r7, #4] 800432e: 2202 movs r2, #2 8004330: 775a strb r2, [r3, #29] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 8004332: 687b ldr r3, [r7, #4] 8004334: 681b ldr r3, [r3, #0] 8004336: 22ca movs r2, #202 ; 0xca 8004338: 625a str r2, [r3, #36] ; 0x24 800433a: 687b ldr r3, [r7, #4] 800433c: 681b ldr r3, [r3, #0] 800433e: 2253 movs r2, #83 ; 0x53 8004340: 625a str r2, [r3, #36] ; 0x24 /* Set Initialization mode */ if(RTC_EnterInitMode(hrtc) != HAL_OK) 8004342: 6878 ldr r0, [r7, #4] 8004344: f000 f9fb bl 800473e 8004348: 4603 mov r3, r0 800434a: 2b00 cmp r3, #0 800434c: d008 beq.n 8004360 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800434e: 687b ldr r3, [r7, #4] 8004350: 681b ldr r3, [r3, #0] 8004352: 22ff movs r2, #255 ; 0xff 8004354: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 8004356: 687b ldr r3, [r7, #4] 8004358: 2204 movs r2, #4 800435a: 775a strb r2, [r3, #29] return HAL_ERROR; 800435c: 2301 movs r3, #1 800435e: e05e b.n 800441e } else { /* Clear RTC_CR FMT, OSEL and POL Bits */ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); 8004360: 687b ldr r3, [r7, #4] 8004362: 681b ldr r3, [r3, #0] 8004364: 689b ldr r3, [r3, #8] 8004366: 687a ldr r2, [r7, #4] 8004368: 6812 ldr r2, [r2, #0] 800436a: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 800436e: f023 0340 bic.w r3, r3, #64 ; 0x40 8004372: 6093 str r3, [r2, #8] /* Set RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); 8004374: 687b ldr r3, [r7, #4] 8004376: 681b ldr r3, [r3, #0] 8004378: 6899 ldr r1, [r3, #8] 800437a: 687b ldr r3, [r7, #4] 800437c: 685a ldr r2, [r3, #4] 800437e: 687b ldr r3, [r7, #4] 8004380: 691b ldr r3, [r3, #16] 8004382: 431a orrs r2, r3 8004384: 687b ldr r3, [r7, #4] 8004386: 695b ldr r3, [r3, #20] 8004388: 431a orrs r2, r3 800438a: 687b ldr r3, [r7, #4] 800438c: 681b ldr r3, [r3, #0] 800438e: 430a orrs r2, r1 8004390: 609a str r2, [r3, #8] /* Configure the RTC PRER */ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); 8004392: 687b ldr r3, [r7, #4] 8004394: 681b ldr r3, [r3, #0] 8004396: 687a ldr r2, [r7, #4] 8004398: 68d2 ldr r2, [r2, #12] 800439a: 611a str r2, [r3, #16] hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); 800439c: 687b ldr r3, [r7, #4] 800439e: 681b ldr r3, [r3, #0] 80043a0: 6919 ldr r1, [r3, #16] 80043a2: 687b ldr r3, [r7, #4] 80043a4: 689b ldr r3, [r3, #8] 80043a6: 041a lsls r2, r3, #16 80043a8: 687b ldr r3, [r7, #4] 80043aa: 681b ldr r3, [r3, #0] 80043ac: 430a orrs r2, r1 80043ae: 611a str r2, [r3, #16] /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 80043b0: 687b ldr r3, [r7, #4] 80043b2: 681b ldr r3, [r3, #0] 80043b4: 68da ldr r2, [r3, #12] 80043b6: 687b ldr r3, [r7, #4] 80043b8: 681b ldr r3, [r3, #0] 80043ba: f022 0280 bic.w r2, r2, #128 ; 0x80 80043be: 60da str r2, [r3, #12] /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) 80043c0: 687b ldr r3, [r7, #4] 80043c2: 681b ldr r3, [r3, #0] 80043c4: 689b ldr r3, [r3, #8] 80043c6: f003 0320 and.w r3, r3, #32 80043ca: 2b00 cmp r3, #0 80043cc: d10e bne.n 80043ec { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 80043ce: 6878 ldr r0, [r7, #4] 80043d0: f000 f98d bl 80046ee 80043d4: 4603 mov r3, r0 80043d6: 2b00 cmp r3, #0 80043d8: d008 beq.n 80043ec { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80043da: 687b ldr r3, [r7, #4] 80043dc: 681b ldr r3, [r3, #0] 80043de: 22ff movs r2, #255 ; 0xff 80043e0: 625a str r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_ERROR; 80043e2: 687b ldr r3, [r7, #4] 80043e4: 2204 movs r2, #4 80043e6: 775a strb r2, [r3, #29] return HAL_ERROR; 80043e8: 2301 movs r3, #1 80043ea: e018 b.n 800441e } } hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; 80043ec: 687b ldr r3, [r7, #4] 80043ee: 681b ldr r3, [r3, #0] 80043f0: 6c1a ldr r2, [r3, #64] ; 0x40 80043f2: 687b ldr r3, [r7, #4] 80043f4: 681b ldr r3, [r3, #0] 80043f6: f422 2280 bic.w r2, r2, #262144 ; 0x40000 80043fa: 641a str r2, [r3, #64] ; 0x40 hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); 80043fc: 687b ldr r3, [r7, #4] 80043fe: 681b ldr r3, [r3, #0] 8004400: 6c19 ldr r1, [r3, #64] ; 0x40 8004402: 687b ldr r3, [r7, #4] 8004404: 699a ldr r2, [r3, #24] 8004406: 687b ldr r3, [r7, #4] 8004408: 681b ldr r3, [r3, #0] 800440a: 430a orrs r2, r1 800440c: 641a str r2, [r3, #64] ; 0x40 /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800440e: 687b ldr r3, [r7, #4] 8004410: 681b ldr r3, [r3, #0] 8004412: 22ff movs r2, #255 ; 0xff 8004414: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; 8004416: 687b ldr r3, [r7, #4] 8004418: 2201 movs r2, #1 800441a: 775a strb r2, [r3, #29] return HAL_OK; 800441c: 2300 movs r3, #0 } } 800441e: 4618 mov r0, r3 8004420: 3708 adds r7, #8 8004422: 46bd mov sp, r7 8004424: bd80 pop {r7, pc} 08004426 : * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { 8004426: b590 push {r4, r7, lr} 8004428: b087 sub sp, #28 800442a: af00 add r7, sp, #0 800442c: 60f8 str r0, [r7, #12] 800442e: 60b9 str r1, [r7, #8] 8004430: 607a str r2, [r7, #4] uint32_t tmpreg = 0U; 8004432: 2300 movs r3, #0 8004434: 617b str r3, [r7, #20] assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); /* Process Locked */ __HAL_LOCK(hrtc); 8004436: 68fb ldr r3, [r7, #12] 8004438: 7f1b ldrb r3, [r3, #28] 800443a: 2b01 cmp r3, #1 800443c: d101 bne.n 8004442 800443e: 2302 movs r3, #2 8004440: e0aa b.n 8004598 8004442: 68fb ldr r3, [r7, #12] 8004444: 2201 movs r2, #1 8004446: 771a strb r2, [r3, #28] hrtc->State = HAL_RTC_STATE_BUSY; 8004448: 68fb ldr r3, [r7, #12] 800444a: 2202 movs r2, #2 800444c: 775a strb r2, [r3, #29] if(Format == RTC_FORMAT_BIN) 800444e: 687b ldr r3, [r7, #4] 8004450: 2b00 cmp r3, #0 8004452: d126 bne.n 80044a2 { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) 8004454: 68fb ldr r3, [r7, #12] 8004456: 681b ldr r3, [r3, #0] 8004458: 689b ldr r3, [r3, #8] 800445a: f003 0340 and.w r3, r3, #64 ; 0x40 800445e: 2b00 cmp r3, #0 8004460: d102 bne.n 8004468 assert_param(IS_RTC_HOUR12(sTime->Hours)); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); } else { sTime->TimeFormat = 0x00U; 8004462: 68bb ldr r3, [r7, #8] 8004464: 2200 movs r2, #0 8004466: 70da strb r2, [r3, #3] assert_param(IS_RTC_HOUR24(sTime->Hours)); } assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ 8004468: 68bb ldr r3, [r7, #8] 800446a: 781b ldrb r3, [r3, #0] 800446c: 4618 mov r0, r3 800446e: f000 f992 bl 8004796 8004472: 4603 mov r3, r0 8004474: 041c lsls r4, r3, #16 ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ 8004476: 68bb ldr r3, [r7, #8] 8004478: 785b ldrb r3, [r3, #1] 800447a: 4618 mov r0, r3 800447c: f000 f98b bl 8004796 8004480: 4603 mov r3, r0 8004482: 021b lsls r3, r3, #8 tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ 8004484: 431c orrs r4, r3 ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ 8004486: 68bb ldr r3, [r7, #8] 8004488: 789b ldrb r3, [r3, #2] 800448a: 4618 mov r0, r3 800448c: f000 f983 bl 8004796 8004490: 4603 mov r3, r0 ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ 8004492: ea44 0203 orr.w r2, r4, r3 (((uint32_t)sTime->TimeFormat) << 16U)); 8004496: 68bb ldr r3, [r7, #8] 8004498: 78db ldrb r3, [r3, #3] 800449a: 041b lsls r3, r3, #16 tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ 800449c: 4313 orrs r3, r2 800449e: 617b str r3, [r7, #20] 80044a0: e018 b.n 80044d4 } else { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) 80044a2: 68fb ldr r3, [r7, #12] 80044a4: 681b ldr r3, [r3, #0] 80044a6: 689b ldr r3, [r3, #8] 80044a8: f003 0340 and.w r3, r3, #64 ; 0x40 80044ac: 2b00 cmp r3, #0 80044ae: d102 bne.n 80044b6 assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); } else { sTime->TimeFormat = 0x00U; 80044b0: 68bb ldr r3, [r7, #8] 80044b2: 2200 movs r2, #0 80044b4: 70da strb r2, [r3, #3] assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ 80044b6: 68bb ldr r3, [r7, #8] 80044b8: 781b ldrb r3, [r3, #0] 80044ba: 041a lsls r2, r3, #16 ((uint32_t)(sTime->Minutes) << 8U) | \ 80044bc: 68bb ldr r3, [r7, #8] 80044be: 785b ldrb r3, [r3, #1] 80044c0: 021b lsls r3, r3, #8 tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ 80044c2: 4313 orrs r3, r2 ((uint32_t)sTime->Seconds) | \ 80044c4: 68ba ldr r2, [r7, #8] 80044c6: 7892 ldrb r2, [r2, #2] ((uint32_t)(sTime->Minutes) << 8U) | \ 80044c8: 431a orrs r2, r3 ((uint32_t)(sTime->TimeFormat) << 16U)); 80044ca: 68bb ldr r3, [r7, #8] 80044cc: 78db ldrb r3, [r3, #3] 80044ce: 041b lsls r3, r3, #16 tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ 80044d0: 4313 orrs r3, r2 80044d2: 617b str r3, [r7, #20] } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 80044d4: 68fb ldr r3, [r7, #12] 80044d6: 681b ldr r3, [r3, #0] 80044d8: 22ca movs r2, #202 ; 0xca 80044da: 625a str r2, [r3, #36] ; 0x24 80044dc: 68fb ldr r3, [r7, #12] 80044de: 681b ldr r3, [r3, #0] 80044e0: 2253 movs r2, #83 ; 0x53 80044e2: 625a str r2, [r3, #36] ; 0x24 /* Set Initialization mode */ if(RTC_EnterInitMode(hrtc) != HAL_OK) 80044e4: 68f8 ldr r0, [r7, #12] 80044e6: f000 f92a bl 800473e 80044ea: 4603 mov r3, r0 80044ec: 2b00 cmp r3, #0 80044ee: d00b beq.n 8004508 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80044f0: 68fb ldr r3, [r7, #12] 80044f2: 681b ldr r3, [r3, #0] 80044f4: 22ff movs r2, #255 ; 0xff 80044f6: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; 80044f8: 68fb ldr r3, [r7, #12] 80044fa: 2204 movs r2, #4 80044fc: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); 80044fe: 68fb ldr r3, [r7, #12] 8004500: 2200 movs r2, #0 8004502: 771a strb r2, [r3, #28] return HAL_ERROR; 8004504: 2301 movs r3, #1 8004506: e047 b.n 8004598 } else { /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); 8004508: 68fb ldr r3, [r7, #12] 800450a: 681a ldr r2, [r3, #0] 800450c: 697b ldr r3, [r7, #20] 800450e: f003 337f and.w r3, r3, #2139062143 ; 0x7f7f7f7f 8004512: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 8004516: 6013 str r3, [r2, #0] /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; 8004518: 68fb ldr r3, [r7, #12] 800451a: 681b ldr r3, [r3, #0] 800451c: 689a ldr r2, [r3, #8] 800451e: 68fb ldr r3, [r7, #12] 8004520: 681b ldr r3, [r3, #0] 8004522: f422 2280 bic.w r2, r2, #262144 ; 0x40000 8004526: 609a str r2, [r3, #8] /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); 8004528: 68fb ldr r3, [r7, #12] 800452a: 681b ldr r3, [r3, #0] 800452c: 6899 ldr r1, [r3, #8] 800452e: 68bb ldr r3, [r7, #8] 8004530: 68da ldr r2, [r3, #12] 8004532: 68bb ldr r3, [r7, #8] 8004534: 691b ldr r3, [r3, #16] 8004536: 431a orrs r2, r3 8004538: 68fb ldr r3, [r7, #12] 800453a: 681b ldr r3, [r3, #0] 800453c: 430a orrs r2, r1 800453e: 609a str r2, [r3, #8] /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 8004540: 68fb ldr r3, [r7, #12] 8004542: 681b ldr r3, [r3, #0] 8004544: 68da ldr r2, [r3, #12] 8004546: 68fb ldr r3, [r7, #12] 8004548: 681b ldr r3, [r3, #0] 800454a: f022 0280 bic.w r2, r2, #128 ; 0x80 800454e: 60da str r2, [r3, #12] /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) 8004550: 68fb ldr r3, [r7, #12] 8004552: 681b ldr r3, [r3, #0] 8004554: 689b ldr r3, [r3, #8] 8004556: f003 0320 and.w r3, r3, #32 800455a: 2b00 cmp r3, #0 800455c: d111 bne.n 8004582 { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 800455e: 68f8 ldr r0, [r7, #12] 8004560: f000 f8c5 bl 80046ee 8004564: 4603 mov r3, r0 8004566: 2b00 cmp r3, #0 8004568: d00b beq.n 8004582 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 800456a: 68fb ldr r3, [r7, #12] 800456c: 681b ldr r3, [r3, #0] 800456e: 22ff movs r2, #255 ; 0xff 8004570: 625a str r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_ERROR; 8004572: 68fb ldr r3, [r7, #12] 8004574: 2204 movs r2, #4 8004576: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); 8004578: 68fb ldr r3, [r7, #12] 800457a: 2200 movs r2, #0 800457c: 771a strb r2, [r3, #28] return HAL_ERROR; 800457e: 2301 movs r3, #1 8004580: e00a b.n 8004598 } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8004582: 68fb ldr r3, [r7, #12] 8004584: 681b ldr r3, [r3, #0] 8004586: 22ff movs r2, #255 ; 0xff 8004588: 625a str r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_READY; 800458a: 68fb ldr r3, [r7, #12] 800458c: 2201 movs r2, #1 800458e: 775a strb r2, [r3, #29] __HAL_UNLOCK(hrtc); 8004590: 68fb ldr r3, [r7, #12] 8004592: 2200 movs r2, #0 8004594: 771a strb r2, [r3, #28] return HAL_OK; 8004596: 2300 movs r3, #0 } } 8004598: 4618 mov r0, r3 800459a: 371c adds r7, #28 800459c: 46bd mov sp, r7 800459e: bd90 pop {r4, r7, pc} 080045a0 : * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { 80045a0: b590 push {r4, r7, lr} 80045a2: b087 sub sp, #28 80045a4: af00 add r7, sp, #0 80045a6: 60f8 str r0, [r7, #12] 80045a8: 60b9 str r1, [r7, #8] 80045aa: 607a str r2, [r7, #4] uint32_t datetmpreg = 0U; 80045ac: 2300 movs r3, #0 80045ae: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); /* Process Locked */ __HAL_LOCK(hrtc); 80045b0: 68fb ldr r3, [r7, #12] 80045b2: 7f1b ldrb r3, [r3, #28] 80045b4: 2b01 cmp r3, #1 80045b6: d101 bne.n 80045bc 80045b8: 2302 movs r3, #2 80045ba: e094 b.n 80046e6 80045bc: 68fb ldr r3, [r7, #12] 80045be: 2201 movs r2, #1 80045c0: 771a strb r2, [r3, #28] hrtc->State = HAL_RTC_STATE_BUSY; 80045c2: 68fb ldr r3, [r7, #12] 80045c4: 2202 movs r2, #2 80045c6: 775a strb r2, [r3, #29] if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) 80045c8: 687b ldr r3, [r7, #4] 80045ca: 2b00 cmp r3, #0 80045cc: d10e bne.n 80045ec 80045ce: 68bb ldr r3, [r7, #8] 80045d0: 785b ldrb r3, [r3, #1] 80045d2: f003 0310 and.w r3, r3, #16 80045d6: 2b00 cmp r3, #0 80045d8: d008 beq.n 80045ec { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); 80045da: 68bb ldr r3, [r7, #8] 80045dc: 785b ldrb r3, [r3, #1] 80045de: f023 0310 bic.w r3, r3, #16 80045e2: b2db uxtb r3, r3 80045e4: 330a adds r3, #10 80045e6: b2da uxtb r2, r3 80045e8: 68bb ldr r3, [r7, #8] 80045ea: 705a strb r2, [r3, #1] } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); if(Format == RTC_FORMAT_BIN) 80045ec: 687b ldr r3, [r7, #4] 80045ee: 2b00 cmp r3, #0 80045f0: d11c bne.n 800462c { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ 80045f2: 68bb ldr r3, [r7, #8] 80045f4: 78db ldrb r3, [r3, #3] 80045f6: 4618 mov r0, r3 80045f8: f000 f8cd bl 8004796 80045fc: 4603 mov r3, r0 80045fe: 041c lsls r4, r3, #16 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ 8004600: 68bb ldr r3, [r7, #8] 8004602: 785b ldrb r3, [r3, #1] 8004604: 4618 mov r0, r3 8004606: f000 f8c6 bl 8004796 800460a: 4603 mov r3, r0 800460c: 021b lsls r3, r3, #8 datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ 800460e: 431c orrs r4, r3 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ 8004610: 68bb ldr r3, [r7, #8] 8004612: 789b ldrb r3, [r3, #2] 8004614: 4618 mov r0, r3 8004616: f000 f8be bl 8004796 800461a: 4603 mov r3, r0 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ 800461c: ea44 0203 orr.w r2, r4, r3 ((uint32_t)sDate->WeekDay << 13U)); 8004620: 68bb ldr r3, [r7, #8] 8004622: 781b ldrb r3, [r3, #0] 8004624: 035b lsls r3, r3, #13 datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ 8004626: 4313 orrs r3, r2 8004628: 617b str r3, [r7, #20] 800462a: e00e b.n 800464a { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ 800462c: 68bb ldr r3, [r7, #8] 800462e: 78db ldrb r3, [r3, #3] 8004630: 041a lsls r2, r3, #16 (((uint32_t)sDate->Month) << 8U) | \ 8004632: 68bb ldr r3, [r7, #8] 8004634: 785b ldrb r3, [r3, #1] 8004636: 021b lsls r3, r3, #8 datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ 8004638: 4313 orrs r3, r2 ((uint32_t)sDate->Date) | \ 800463a: 68ba ldr r2, [r7, #8] 800463c: 7892 ldrb r2, [r2, #2] (((uint32_t)sDate->Month) << 8U) | \ 800463e: 431a orrs r2, r3 (((uint32_t)sDate->WeekDay) << 13U)); 8004640: 68bb ldr r3, [r7, #8] 8004642: 781b ldrb r3, [r3, #0] 8004644: 035b lsls r3, r3, #13 datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ 8004646: 4313 orrs r3, r2 8004648: 617b str r3, [r7, #20] } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); 800464a: 68fb ldr r3, [r7, #12] 800464c: 681b ldr r3, [r3, #0] 800464e: 22ca movs r2, #202 ; 0xca 8004650: 625a str r2, [r3, #36] ; 0x24 8004652: 68fb ldr r3, [r7, #12] 8004654: 681b ldr r3, [r3, #0] 8004656: 2253 movs r2, #83 ; 0x53 8004658: 625a str r2, [r3, #36] ; 0x24 /* Set Initialization mode */ if(RTC_EnterInitMode(hrtc) != HAL_OK) 800465a: 68f8 ldr r0, [r7, #12] 800465c: f000 f86f bl 800473e 8004660: 4603 mov r3, r0 8004662: 2b00 cmp r3, #0 8004664: d00b beq.n 800467e { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 8004666: 68fb ldr r3, [r7, #12] 8004668: 681b ldr r3, [r3, #0] 800466a: 22ff movs r2, #255 ; 0xff 800466c: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state*/ hrtc->State = HAL_RTC_STATE_ERROR; 800466e: 68fb ldr r3, [r7, #12] 8004670: 2204 movs r2, #4 8004672: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); 8004674: 68fb ldr r3, [r7, #12] 8004676: 2200 movs r2, #0 8004678: 771a strb r2, [r3, #28] return HAL_ERROR; 800467a: 2301 movs r3, #1 800467c: e033 b.n 80046e6 } else { /* Set the RTC_DR register */ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); 800467e: 68fb ldr r3, [r7, #12] 8004680: 681a ldr r2, [r3, #0] 8004682: 697b ldr r3, [r7, #20] 8004684: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 8004688: f023 03c0 bic.w r3, r3, #192 ; 0xc0 800468c: 6053 str r3, [r2, #4] /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 800468e: 68fb ldr r3, [r7, #12] 8004690: 681b ldr r3, [r3, #0] 8004692: 68da ldr r2, [r3, #12] 8004694: 68fb ldr r3, [r7, #12] 8004696: 681b ldr r3, [r3, #0] 8004698: f022 0280 bic.w r2, r2, #128 ; 0x80 800469c: 60da str r2, [r3, #12] /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) 800469e: 68fb ldr r3, [r7, #12] 80046a0: 681b ldr r3, [r3, #0] 80046a2: 689b ldr r3, [r3, #8] 80046a4: f003 0320 and.w r3, r3, #32 80046a8: 2b00 cmp r3, #0 80046aa: d111 bne.n 80046d0 { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) 80046ac: 68f8 ldr r0, [r7, #12] 80046ae: f000 f81e bl 80046ee 80046b2: 4603 mov r3, r0 80046b4: 2b00 cmp r3, #0 80046b6: d00b beq.n 80046d0 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80046b8: 68fb ldr r3, [r7, #12] 80046ba: 681b ldr r3, [r3, #0] 80046bc: 22ff movs r2, #255 ; 0xff 80046be: 625a str r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_ERROR; 80046c0: 68fb ldr r3, [r7, #12] 80046c2: 2204 movs r2, #4 80046c4: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); 80046c6: 68fb ldr r3, [r7, #12] 80046c8: 2200 movs r2, #0 80046ca: 771a strb r2, [r3, #28] return HAL_ERROR; 80046cc: 2301 movs r3, #1 80046ce: e00a b.n 80046e6 } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 80046d0: 68fb ldr r3, [r7, #12] 80046d2: 681b ldr r3, [r3, #0] 80046d4: 22ff movs r2, #255 ; 0xff 80046d6: 625a str r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_READY ; 80046d8: 68fb ldr r3, [r7, #12] 80046da: 2201 movs r2, #1 80046dc: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); 80046de: 68fb ldr r3, [r7, #12] 80046e0: 2200 movs r2, #0 80046e2: 771a strb r2, [r3, #28] return HAL_OK; 80046e4: 2300 movs r3, #0 } } 80046e6: 4618 mov r0, r3 80046e8: 371c adds r7, #28 80046ea: 46bd mov sp, r7 80046ec: bd90 pop {r4, r7, pc} 080046ee : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { 80046ee: b580 push {r7, lr} 80046f0: b084 sub sp, #16 80046f2: af00 add r7, sp, #0 80046f4: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80046f6: 2300 movs r3, #0 80046f8: 60fb str r3, [r7, #12] /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; 80046fa: 687b ldr r3, [r7, #4] 80046fc: 681b ldr r3, [r3, #0] 80046fe: 68da ldr r2, [r3, #12] 8004700: 687b ldr r3, [r7, #4] 8004702: 681b ldr r3, [r3, #0] 8004704: f022 02a0 bic.w r2, r2, #160 ; 0xa0 8004708: 60da str r2, [r3, #12] /* Get tick */ tickstart = HAL_GetTick(); 800470a: f7fc fdc7 bl 800129c 800470e: 60f8 str r0, [r7, #12] /* Wait the registers to be synchronised */ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) 8004710: e009 b.n 8004726 { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) 8004712: f7fc fdc3 bl 800129c 8004716: 4602 mov r2, r0 8004718: 68fb ldr r3, [r7, #12] 800471a: 1ad3 subs r3, r2, r3 800471c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8004720: d901 bls.n 8004726 { return HAL_TIMEOUT; 8004722: 2303 movs r3, #3 8004724: e007 b.n 8004736 while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) 8004726: 687b ldr r3, [r7, #4] 8004728: 681b ldr r3, [r3, #0] 800472a: 68db ldr r3, [r3, #12] 800472c: f003 0320 and.w r3, r3, #32 8004730: 2b00 cmp r3, #0 8004732: d0ee beq.n 8004712 } } return HAL_OK; 8004734: 2300 movs r3, #0 } 8004736: 4618 mov r0, r3 8004738: 3710 adds r7, #16 800473a: 46bd mov sp, r7 800473c: bd80 pop {r7, pc} 0800473e : * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { 800473e: b580 push {r7, lr} 8004740: b084 sub sp, #16 8004742: af00 add r7, sp, #0 8004744: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8004746: 2300 movs r3, #0 8004748: 60fb str r3, [r7, #12] /* Check if the Initialization mode is set */ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) 800474a: 687b ldr r3, [r7, #4] 800474c: 681b ldr r3, [r3, #0] 800474e: 68db ldr r3, [r3, #12] 8004750: f003 0340 and.w r3, r3, #64 ; 0x40 8004754: 2b00 cmp r3, #0 8004756: d119 bne.n 800478c { /* Set the Initialization mode */ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; 8004758: 687b ldr r3, [r7, #4] 800475a: 681b ldr r3, [r3, #0] 800475c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 8004760: 60da str r2, [r3, #12] /* Get tick */ tickstart = HAL_GetTick(); 8004762: f7fc fd9b bl 800129c 8004766: 60f8 str r0, [r7, #12] /* Wait till RTC is in INIT state and if Time out is reached exit */ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) 8004768: e009 b.n 800477e { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) 800476a: f7fc fd97 bl 800129c 800476e: 4602 mov r2, r0 8004770: 68fb ldr r3, [r7, #12] 8004772: 1ad3 subs r3, r2, r3 8004774: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 8004778: d901 bls.n 800477e { return HAL_TIMEOUT; 800477a: 2303 movs r3, #3 800477c: e007 b.n 800478e while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) 800477e: 687b ldr r3, [r7, #4] 8004780: 681b ldr r3, [r3, #0] 8004782: 68db ldr r3, [r3, #12] 8004784: f003 0340 and.w r3, r3, #64 ; 0x40 8004788: 2b00 cmp r3, #0 800478a: d0ee beq.n 800476a } } } return HAL_OK; 800478c: 2300 movs r3, #0 } 800478e: 4618 mov r0, r3 8004790: 3710 adds r7, #16 8004792: 46bd mov sp, r7 8004794: bd80 pop {r7, pc} 08004796 : * @brief Converts a 2 digit decimal to BCD format. * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) { 8004796: b480 push {r7} 8004798: b085 sub sp, #20 800479a: af00 add r7, sp, #0 800479c: 4603 mov r3, r0 800479e: 71fb strb r3, [r7, #7] uint32_t bcdhigh = 0U; 80047a0: 2300 movs r3, #0 80047a2: 60fb str r3, [r7, #12] while(Value >= 10U) 80047a4: e005 b.n 80047b2 { bcdhigh++; 80047a6: 68fb ldr r3, [r7, #12] 80047a8: 3301 adds r3, #1 80047aa: 60fb str r3, [r7, #12] Value -= 10U; 80047ac: 79fb ldrb r3, [r7, #7] 80047ae: 3b0a subs r3, #10 80047b0: 71fb strb r3, [r7, #7] while(Value >= 10U) 80047b2: 79fb ldrb r3, [r7, #7] 80047b4: 2b09 cmp r3, #9 80047b6: d8f6 bhi.n 80047a6 } return ((uint8_t)(bcdhigh << 4U) | Value); 80047b8: 68fb ldr r3, [r7, #12] 80047ba: b2db uxtb r3, r3 80047bc: 011b lsls r3, r3, #4 80047be: b2da uxtb r2, r3 80047c0: 79fb ldrb r3, [r7, #7] 80047c2: 4313 orrs r3, r2 80047c4: b2db uxtb r3, r3 } 80047c6: 4618 mov r0, r3 80047c8: 3714 adds r7, #20 80047ca: 46bd mov sp, r7 80047cc: f85d 7b04 ldr.w r7, [sp], #4 80047d0: 4770 bx lr ... 080047d4 : * @param hsmbus pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) { 80047d4: b580 push {r7, lr} 80047d6: b084 sub sp, #16 80047d8: af00 add r7, sp, #0 80047da: 6078 str r0, [r7, #4] uint32_t freqrange = 0U; 80047dc: 2300 movs r3, #0 80047de: 60fb str r3, [r7, #12] uint32_t pclk1 = 0U; 80047e0: 2300 movs r3, #0 80047e2: 60bb str r3, [r7, #8] /* Check the SMBUS handle allocation */ if (hsmbus == NULL) 80047e4: 687b ldr r3, [r7, #4] 80047e6: 2b00 cmp r3, #0 80047e8: d101 bne.n 80047ee { return HAL_ERROR; 80047ea: 2301 movs r3, #1 80047ec: e0aa b.n 8004944 assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); if (hsmbus->State == HAL_SMBUS_STATE_RESET) 80047ee: 687b ldr r3, [r7, #4] 80047f0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 80047f4: b2db uxtb r3, r3 80047f6: 2b00 cmp r3, #0 80047f8: d106 bne.n 8004808 { /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; 80047fa: 687b ldr r3, [r7, #4] 80047fc: 2200 movs r2, #0 80047fe: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hsmbus->MspInitCallback(hsmbus); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); 8004802: 6878 ldr r0, [r7, #4] 8004804: f7fc faf8 bl 8000df8 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } hsmbus->State = HAL_SMBUS_STATE_BUSY; 8004808: 687b ldr r3, [r7, #4] 800480a: 2224 movs r2, #36 ; 0x24 800480c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); 8004810: 687b ldr r3, [r7, #4] 8004812: 681b ldr r3, [r3, #0] 8004814: 681a ldr r2, [r3, #0] 8004816: 687b ldr r3, [r7, #4] 8004818: 681b ldr r3, [r3, #0] 800481a: f022 0201 bic.w r2, r2, #1 800481e: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8004820: f7fe fdce bl 80033c0 8004824: 60b8 str r0, [r7, #8] /* Calculate frequency range */ freqrange = SMBUS_FREQRANGE(pclk1); 8004826: 68bb ldr r3, [r7, #8] 8004828: 4a48 ldr r2, [pc, #288] ; (800494c ) 800482a: fba2 2303 umull r2, r3, r2, r3 800482e: 0c9b lsrs r3, r3, #18 8004830: 60fb str r3, [r7, #12] /*---------------------------- SMBUSx CR2 Configuration ----------------------*/ /* Configure SMBUSx: Frequency range */ MODIFY_REG(hsmbus->Instance->CR2, I2C_CR2_FREQ, freqrange); 8004832: 687b ldr r3, [r7, #4] 8004834: 681b ldr r3, [r3, #0] 8004836: 685b ldr r3, [r3, #4] 8004838: f023 013f bic.w r1, r3, #63 ; 0x3f 800483c: 687b ldr r3, [r7, #4] 800483e: 681b ldr r3, [r3, #0] 8004840: 68fa ldr r2, [r7, #12] 8004842: 430a orrs r2, r1 8004844: 605a str r2, [r3, #4] /*---------------------------- SMBUSx TRISE Configuration --------------------*/ /* Configure SMBUSx: Rise Time */ MODIFY_REG(hsmbus->Instance->TRISE, I2C_TRISE_TRISE, SMBUS_RISE_TIME(freqrange)); 8004846: 687b ldr r3, [r7, #4] 8004848: 681b ldr r3, [r3, #0] 800484a: 6a1b ldr r3, [r3, #32] 800484c: f023 013f bic.w r1, r3, #63 ; 0x3f 8004850: 68fb ldr r3, [r7, #12] 8004852: 1c5a adds r2, r3, #1 8004854: 687b ldr r3, [r7, #4] 8004856: 681b ldr r3, [r3, #0] 8004858: 430a orrs r2, r1 800485a: 621a str r2, [r3, #32] /*---------------------------- SMBUSx CCR Configuration ----------------------*/ /* Configure SMBUSx: Speed */ MODIFY_REG(hsmbus->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), SMBUS_SPEED_STANDARD(pclk1, hsmbus->Init.ClockSpeed)); 800485c: 687b ldr r3, [r7, #4] 800485e: 681b ldr r3, [r3, #0] 8004860: 69db ldr r3, [r3, #28] 8004862: f423 434f bic.w r3, r3, #52992 ; 0xcf00 8004866: f023 03ff bic.w r3, r3, #255 ; 0xff 800486a: 687a ldr r2, [r7, #4] 800486c: 6852 ldr r2, [r2, #4] 800486e: 0052 lsls r2, r2, #1 8004870: 68b9 ldr r1, [r7, #8] 8004872: fbb1 f1f2 udiv r1, r1, r2 8004876: f640 72fc movw r2, #4092 ; 0xffc 800487a: 400a ands r2, r1 800487c: 2a00 cmp r2, #0 800487e: d006 beq.n 800488e 8004880: 687a ldr r2, [r7, #4] 8004882: 6852 ldr r2, [r2, #4] 8004884: 0052 lsls r2, r2, #1 8004886: 68b9 ldr r1, [r7, #8] 8004888: fbb1 f2f2 udiv r2, r1, r2 800488c: e000 b.n 8004890 800488e: 2204 movs r2, #4 8004890: 6879 ldr r1, [r7, #4] 8004892: 6809 ldr r1, [r1, #0] 8004894: 4313 orrs r3, r2 8004896: 61cb str r3, [r1, #28] /*---------------------------- SMBUSx CR1 Configuration ----------------------*/ /* Configure SMBUSx: Generalcall , PEC , Peripheral mode and NoStretch mode */ MODIFY_REG(hsmbus->Instance->CR1, (I2C_CR1_NOSTRETCH | I2C_CR1_ENGC | I2C_CR1_ENPEC | I2C_CR1_ENARP | I2C_CR1_SMBTYPE | I2C_CR1_SMBUS), (hsmbus->Init.NoStretchMode | hsmbus->Init.GeneralCallMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode)); 8004898: 687b ldr r3, [r7, #4] 800489a: 681b ldr r3, [r3, #0] 800489c: 681b ldr r3, [r3, #0] 800489e: f023 01fa bic.w r1, r3, #250 ; 0xfa 80048a2: 687b ldr r3, [r7, #4] 80048a4: 6a1a ldr r2, [r3, #32] 80048a6: 687b ldr r3, [r7, #4] 80048a8: 69db ldr r3, [r3, #28] 80048aa: 431a orrs r2, r3 80048ac: 687b ldr r3, [r7, #4] 80048ae: 6a5b ldr r3, [r3, #36] ; 0x24 80048b0: 431a orrs r2, r3 80048b2: 687b ldr r3, [r7, #4] 80048b4: 6a9b ldr r3, [r3, #40] ; 0x28 80048b6: 431a orrs r2, r3 80048b8: 687b ldr r3, [r7, #4] 80048ba: 681b ldr r3, [r3, #0] 80048bc: 430a orrs r2, r1 80048be: 601a str r2, [r3, #0] /*---------------------------- SMBUSx OAR1 Configuration ---------------------*/ /* Configure SMBUSx: Own Address1 and addressing mode */ MODIFY_REG(hsmbus->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hsmbus->Init.AddressingMode | hsmbus->Init.OwnAddress1)); 80048c0: 687b ldr r3, [r7, #4] 80048c2: 681b ldr r3, [r3, #0] 80048c4: 689b ldr r3, [r3, #8] 80048c6: f423 4303 bic.w r3, r3, #33536 ; 0x8300 80048ca: f023 03ff bic.w r3, r3, #255 ; 0xff 80048ce: 687a ldr r2, [r7, #4] 80048d0: 6911 ldr r1, [r2, #16] 80048d2: 687a ldr r2, [r7, #4] 80048d4: 68d2 ldr r2, [r2, #12] 80048d6: 4311 orrs r1, r2 80048d8: 687a ldr r2, [r7, #4] 80048da: 6812 ldr r2, [r2, #0] 80048dc: 430b orrs r3, r1 80048de: 6093 str r3, [r2, #8] /*---------------------------- SMBUSx OAR2 Configuration ---------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ MODIFY_REG(hsmbus->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2)); 80048e0: 687b ldr r3, [r7, #4] 80048e2: 681b ldr r3, [r3, #0] 80048e4: 68db ldr r3, [r3, #12] 80048e6: f023 01ff bic.w r1, r3, #255 ; 0xff 80048ea: 687b ldr r3, [r7, #4] 80048ec: 695a ldr r2, [r3, #20] 80048ee: 687b ldr r3, [r7, #4] 80048f0: 699b ldr r3, [r3, #24] 80048f2: 431a orrs r2, r3 80048f4: 687b ldr r3, [r7, #4] 80048f6: 681b ldr r3, [r3, #0] 80048f8: 430a orrs r2, r1 80048fa: 60da str r2, [r3, #12] #if defined(I2C_FLTR_ANOFF) /*---------------------------- SMBUSx FLTR Configuration ------------------------*/ /* Configure SMBUSx: Analog noise filter */ SET_BIT(hsmbus->Instance->FLTR, hsmbus->Init.AnalogFilter); 80048fc: 687b ldr r3, [r7, #4] 80048fe: 681b ldr r3, [r3, #0] 8004900: 6a59 ldr r1, [r3, #36] ; 0x24 8004902: 687b ldr r3, [r7, #4] 8004904: 689a ldr r2, [r3, #8] 8004906: 687b ldr r3, [r7, #4] 8004908: 681b ldr r3, [r3, #0] 800490a: 430a orrs r2, r1 800490c: 625a str r2, [r3, #36] ; 0x24 #endif /* Enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); 800490e: 687b ldr r3, [r7, #4] 8004910: 681b ldr r3, [r3, #0] 8004912: 681a ldr r2, [r3, #0] 8004914: 687b ldr r3, [r7, #4] 8004916: 681b ldr r3, [r3, #0] 8004918: f042 0201 orr.w r2, r2, #1 800491c: 601a str r2, [r3, #0] hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; 800491e: 687b ldr r3, [r7, #4] 8004920: 2200 movs r2, #0 8004922: 641a str r2, [r3, #64] ; 0x40 hsmbus->State = HAL_SMBUS_STATE_READY; 8004924: 687b ldr r3, [r7, #4] 8004926: 2220 movs r2, #32 8004928: f883 203d strb.w r2, [r3, #61] ; 0x3d hsmbus->PreviousState = SMBUS_STATE_NONE; 800492c: 687b ldr r3, [r7, #4] 800492e: 2200 movs r2, #0 8004930: 639a str r2, [r3, #56] ; 0x38 hsmbus->Mode = HAL_SMBUS_MODE_NONE; 8004932: 687b ldr r3, [r7, #4] 8004934: 2200 movs r2, #0 8004936: f883 203e strb.w r2, [r3, #62] ; 0x3e hsmbus->XferPEC = 0x00; 800493a: 687b ldr r3, [r7, #4] 800493c: 2200 movs r2, #0 800493e: f883 204c strb.w r2, [r3, #76] ; 0x4c return HAL_OK; 8004942: 2300 movs r3, #0 } 8004944: 4618 mov r0, r3 8004946: 3710 adds r7, #16 8004948: 46bd mov sp, r7 800494a: bd80 pop {r7, pc} 800494c: 431bde83 .word 0x431bde83 08004950 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 8004950: b580 push {r7, lr} 8004952: b082 sub sp, #8 8004954: af00 add r7, sp, #0 8004956: 6078 str r0, [r7, #4] /* Check the SPI handle allocation */ if (hspi == NULL) 8004958: 687b ldr r3, [r7, #4] 800495a: 2b00 cmp r3, #0 800495c: d101 bne.n 8004962 { return HAL_ERROR; 800495e: 2301 movs r3, #1 8004960: e07b b.n 8004a5a assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 8004962: 687b ldr r3, [r7, #4] 8004964: 6a5b ldr r3, [r3, #36] ; 0x24 8004966: 2b00 cmp r3, #0 8004968: d108 bne.n 800497c { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 800496a: 687b ldr r3, [r7, #4] 800496c: 685b ldr r3, [r3, #4] 800496e: f5b3 7f82 cmp.w r3, #260 ; 0x104 8004972: d009 beq.n 8004988 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8004974: 687b ldr r3, [r7, #4] 8004976: 2200 movs r2, #0 8004978: 61da str r2, [r3, #28] 800497a: e005 b.n 8004988 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 800497c: 687b ldr r3, [r7, #4] 800497e: 2200 movs r2, #0 8004980: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 8004982: 687b ldr r3, [r7, #4] 8004984: 2200 movs r2, #0 8004986: 615a str r2, [r3, #20] if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8004988: 687b ldr r3, [r7, #4] 800498a: 2200 movs r2, #0 800498c: 629a str r2, [r3, #40] ; 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 800498e: 687b ldr r3, [r7, #4] 8004990: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 8004994: b2db uxtb r3, r3 8004996: 2b00 cmp r3, #0 8004998: d106 bne.n 80049a8 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 800499a: 687b ldr r3, [r7, #4] 800499c: 2200 movs r2, #0 800499e: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 80049a2: 6878 ldr r0, [r7, #4] 80049a4: f7fc fa9a bl 8000edc #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 80049a8: 687b ldr r3, [r7, #4] 80049aa: 2202 movs r2, #2 80049ac: f883 2051 strb.w r2, [r3, #81] ; 0x51 /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 80049b0: 687b ldr r3, [r7, #4] 80049b2: 681b ldr r3, [r3, #0] 80049b4: 681a ldr r2, [r3, #0] 80049b6: 687b ldr r3, [r7, #4] 80049b8: 681b ldr r3, [r3, #0] 80049ba: f022 0240 bic.w r2, r2, #64 ; 0x40 80049be: 601a str r2, [r3, #0] /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 80049c0: 687b ldr r3, [r7, #4] 80049c2: 685b ldr r3, [r3, #4] 80049c4: f403 7282 and.w r2, r3, #260 ; 0x104 80049c8: 687b ldr r3, [r7, #4] 80049ca: 689b ldr r3, [r3, #8] 80049cc: f403 4304 and.w r3, r3, #33792 ; 0x8400 80049d0: 431a orrs r2, r3 80049d2: 687b ldr r3, [r7, #4] 80049d4: 68db ldr r3, [r3, #12] 80049d6: f403 6300 and.w r3, r3, #2048 ; 0x800 80049da: 431a orrs r2, r3 80049dc: 687b ldr r3, [r7, #4] 80049de: 691b ldr r3, [r3, #16] 80049e0: f003 0302 and.w r3, r3, #2 80049e4: 431a orrs r2, r3 80049e6: 687b ldr r3, [r7, #4] 80049e8: 695b ldr r3, [r3, #20] 80049ea: f003 0301 and.w r3, r3, #1 80049ee: 431a orrs r2, r3 80049f0: 687b ldr r3, [r7, #4] 80049f2: 699b ldr r3, [r3, #24] 80049f4: f403 7300 and.w r3, r3, #512 ; 0x200 80049f8: 431a orrs r2, r3 80049fa: 687b ldr r3, [r7, #4] 80049fc: 69db ldr r3, [r3, #28] 80049fe: f003 0338 and.w r3, r3, #56 ; 0x38 8004a02: 431a orrs r2, r3 8004a04: 687b ldr r3, [r7, #4] 8004a06: 6a1b ldr r3, [r3, #32] 8004a08: f003 0380 and.w r3, r3, #128 ; 0x80 8004a0c: ea42 0103 orr.w r1, r2, r3 8004a10: 687b ldr r3, [r7, #4] 8004a12: 6a9b ldr r3, [r3, #40] ; 0x28 8004a14: f403 5200 and.w r2, r3, #8192 ; 0x2000 8004a18: 687b ldr r3, [r7, #4] 8004a1a: 681b ldr r3, [r3, #0] 8004a1c: 430a orrs r2, r1 8004a1e: 601a str r2, [r3, #0] (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); /* Configure : NSS management, TI Mode */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); 8004a20: 687b ldr r3, [r7, #4] 8004a22: 699b ldr r3, [r3, #24] 8004a24: 0c1b lsrs r3, r3, #16 8004a26: f003 0104 and.w r1, r3, #4 8004a2a: 687b ldr r3, [r7, #4] 8004a2c: 6a5b ldr r3, [r3, #36] ; 0x24 8004a2e: f003 0210 and.w r2, r3, #16 8004a32: 687b ldr r3, [r7, #4] 8004a34: 681b ldr r3, [r3, #0] 8004a36: 430a orrs r2, r1 8004a38: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 8004a3a: 687b ldr r3, [r7, #4] 8004a3c: 681b ldr r3, [r3, #0] 8004a3e: 69da ldr r2, [r3, #28] 8004a40: 687b ldr r3, [r7, #4] 8004a42: 681b ldr r3, [r3, #0] 8004a44: f422 6200 bic.w r2, r2, #2048 ; 0x800 8004a48: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8004a4a: 687b ldr r3, [r7, #4] 8004a4c: 2200 movs r2, #0 8004a4e: 655a str r2, [r3, #84] ; 0x54 hspi->State = HAL_SPI_STATE_READY; 8004a50: 687b ldr r3, [r7, #4] 8004a52: 2201 movs r2, #1 8004a54: f883 2051 strb.w r2, [r3, #81] ; 0x51 return HAL_OK; 8004a58: 2300 movs r3, #0 } 8004a5a: 4618 mov r0, r3 8004a5c: 3708 adds r7, #8 8004a5e: 46bd mov sp, r7 8004a60: bd80 pop {r7, pc} 08004a62 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8004a62: b580 push {r7, lr} 8004a64: b082 sub sp, #8 8004a66: af00 add r7, sp, #0 8004a68: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8004a6a: 687b ldr r3, [r7, #4] 8004a6c: 2b00 cmp r3, #0 8004a6e: d101 bne.n 8004a74 { return HAL_ERROR; 8004a70: 2301 movs r3, #1 8004a72: e041 b.n 8004af8 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8004a74: 687b ldr r3, [r7, #4] 8004a76: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8004a7a: b2db uxtb r3, r3 8004a7c: 2b00 cmp r3, #0 8004a7e: d106 bne.n 8004a8e { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8004a80: 687b ldr r3, [r7, #4] 8004a82: 2200 movs r2, #0 8004a84: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8004a88: 6878 ldr r0, [r7, #4] 8004a8a: f7fc faa3 bl 8000fd4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8004a8e: 687b ldr r3, [r7, #4] 8004a90: 2202 movs r2, #2 8004a92: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8004a96: 687b ldr r3, [r7, #4] 8004a98: 681a ldr r2, [r3, #0] 8004a9a: 687b ldr r3, [r7, #4] 8004a9c: 3304 adds r3, #4 8004a9e: 4619 mov r1, r3 8004aa0: 4610 mov r0, r2 8004aa2: f000 f86f bl 8004b84 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8004aa6: 687b ldr r3, [r7, #4] 8004aa8: 2201 movs r2, #1 8004aaa: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004aae: 687b ldr r3, [r7, #4] 8004ab0: 2201 movs r2, #1 8004ab2: f883 203e strb.w r2, [r3, #62] ; 0x3e 8004ab6: 687b ldr r3, [r7, #4] 8004ab8: 2201 movs r2, #1 8004aba: f883 203f strb.w r2, [r3, #63] ; 0x3f 8004abe: 687b ldr r3, [r7, #4] 8004ac0: 2201 movs r2, #1 8004ac2: f883 2040 strb.w r2, [r3, #64] ; 0x40 8004ac6: 687b ldr r3, [r7, #4] 8004ac8: 2201 movs r2, #1 8004aca: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004ace: 687b ldr r3, [r7, #4] 8004ad0: 2201 movs r2, #1 8004ad2: f883 2042 strb.w r2, [r3, #66] ; 0x42 8004ad6: 687b ldr r3, [r7, #4] 8004ad8: 2201 movs r2, #1 8004ada: f883 2043 strb.w r2, [r3, #67] ; 0x43 8004ade: 687b ldr r3, [r7, #4] 8004ae0: 2201 movs r2, #1 8004ae2: f883 2044 strb.w r2, [r3, #68] ; 0x44 8004ae6: 687b ldr r3, [r7, #4] 8004ae8: 2201 movs r2, #1 8004aea: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8004aee: 687b ldr r3, [r7, #4] 8004af0: 2201 movs r2, #1 8004af2: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8004af6: 2300 movs r3, #0 } 8004af8: 4618 mov r0, r3 8004afa: 3708 adds r7, #8 8004afc: 46bd mov sp, r7 8004afe: bd80 pop {r7, pc} 08004b00 : * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { 8004b00: b580 push {r7, lr} 8004b02: b082 sub sp, #8 8004b04: af00 add r7, sp, #0 8004b06: 6078 str r0, [r7, #4] 8004b08: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); 8004b0a: 687b ldr r3, [r7, #4] 8004b0c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8004b10: 2b01 cmp r3, #1 8004b12: d101 bne.n 8004b18 8004b14: 2302 movs r3, #2 8004b16: e031 b.n 8004b7c 8004b18: 687b ldr r3, [r7, #4] 8004b1a: 2201 movs r2, #1 8004b1c: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 8004b20: 687b ldr r3, [r7, #4] 8004b22: 2202 movs r2, #2 8004b24: f883 203d strb.w r2, [r3, #61] ; 0x3d if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) 8004b28: 6839 ldr r1, [r7, #0] 8004b2a: 6878 ldr r0, [r7, #4] 8004b2c: f000 f8ca bl 8004cc4 8004b30: 4603 mov r3, r0 8004b32: 2b00 cmp r3, #0 8004b34: d009 beq.n 8004b4a { htim->State = HAL_TIM_STATE_READY; 8004b36: 687b ldr r3, [r7, #4] 8004b38: 2201 movs r2, #1 8004b3a: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8004b3e: 687b ldr r3, [r7, #4] 8004b40: 2200 movs r2, #0 8004b42: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_ERROR; 8004b46: 2301 movs r3, #1 8004b48: e018 b.n 8004b7c } /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); 8004b4a: 687b ldr r3, [r7, #4] 8004b4c: 681b ldr r3, [r3, #0] 8004b4e: 68da ldr r2, [r3, #12] 8004b50: 687b ldr r3, [r7, #4] 8004b52: 681b ldr r3, [r3, #0] 8004b54: f022 0240 bic.w r2, r2, #64 ; 0x40 8004b58: 60da str r2, [r3, #12] /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); 8004b5a: 687b ldr r3, [r7, #4] 8004b5c: 681b ldr r3, [r3, #0] 8004b5e: 68da ldr r2, [r3, #12] 8004b60: 687b ldr r3, [r7, #4] 8004b62: 681b ldr r3, [r3, #0] 8004b64: f422 4280 bic.w r2, r2, #16384 ; 0x4000 8004b68: 60da str r2, [r3, #12] htim->State = HAL_TIM_STATE_READY; 8004b6a: 687b ldr r3, [r7, #4] 8004b6c: 2201 movs r2, #1 8004b6e: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8004b72: 687b ldr r3, [r7, #4] 8004b74: 2200 movs r2, #0 8004b76: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8004b7a: 2300 movs r3, #0 } 8004b7c: 4618 mov r0, r3 8004b7e: 3708 adds r7, #8 8004b80: 46bd mov sp, r7 8004b82: bd80 pop {r7, pc} 08004b84 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 8004b84: b480 push {r7} 8004b86: b085 sub sp, #20 8004b88: af00 add r7, sp, #0 8004b8a: 6078 str r0, [r7, #4] 8004b8c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8004b8e: 687b ldr r3, [r7, #4] 8004b90: 681b ldr r3, [r3, #0] 8004b92: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8004b94: 687b ldr r3, [r7, #4] 8004b96: 4a40 ldr r2, [pc, #256] ; (8004c98 ) 8004b98: 4293 cmp r3, r2 8004b9a: d013 beq.n 8004bc4 8004b9c: 687b ldr r3, [r7, #4] 8004b9e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004ba2: d00f beq.n 8004bc4 8004ba4: 687b ldr r3, [r7, #4] 8004ba6: 4a3d ldr r2, [pc, #244] ; (8004c9c ) 8004ba8: 4293 cmp r3, r2 8004baa: d00b beq.n 8004bc4 8004bac: 687b ldr r3, [r7, #4] 8004bae: 4a3c ldr r2, [pc, #240] ; (8004ca0 ) 8004bb0: 4293 cmp r3, r2 8004bb2: d007 beq.n 8004bc4 8004bb4: 687b ldr r3, [r7, #4] 8004bb6: 4a3b ldr r2, [pc, #236] ; (8004ca4 ) 8004bb8: 4293 cmp r3, r2 8004bba: d003 beq.n 8004bc4 8004bbc: 687b ldr r3, [r7, #4] 8004bbe: 4a3a ldr r2, [pc, #232] ; (8004ca8 ) 8004bc0: 4293 cmp r3, r2 8004bc2: d108 bne.n 8004bd6 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8004bc4: 68fb ldr r3, [r7, #12] 8004bc6: f023 0370 bic.w r3, r3, #112 ; 0x70 8004bca: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8004bcc: 683b ldr r3, [r7, #0] 8004bce: 685b ldr r3, [r3, #4] 8004bd0: 68fa ldr r2, [r7, #12] 8004bd2: 4313 orrs r3, r2 8004bd4: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8004bd6: 687b ldr r3, [r7, #4] 8004bd8: 4a2f ldr r2, [pc, #188] ; (8004c98 ) 8004bda: 4293 cmp r3, r2 8004bdc: d02b beq.n 8004c36 8004bde: 687b ldr r3, [r7, #4] 8004be0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004be4: d027 beq.n 8004c36 8004be6: 687b ldr r3, [r7, #4] 8004be8: 4a2c ldr r2, [pc, #176] ; (8004c9c ) 8004bea: 4293 cmp r3, r2 8004bec: d023 beq.n 8004c36 8004bee: 687b ldr r3, [r7, #4] 8004bf0: 4a2b ldr r2, [pc, #172] ; (8004ca0 ) 8004bf2: 4293 cmp r3, r2 8004bf4: d01f beq.n 8004c36 8004bf6: 687b ldr r3, [r7, #4] 8004bf8: 4a2a ldr r2, [pc, #168] ; (8004ca4 ) 8004bfa: 4293 cmp r3, r2 8004bfc: d01b beq.n 8004c36 8004bfe: 687b ldr r3, [r7, #4] 8004c00: 4a29 ldr r2, [pc, #164] ; (8004ca8 ) 8004c02: 4293 cmp r3, r2 8004c04: d017 beq.n 8004c36 8004c06: 687b ldr r3, [r7, #4] 8004c08: 4a28 ldr r2, [pc, #160] ; (8004cac ) 8004c0a: 4293 cmp r3, r2 8004c0c: d013 beq.n 8004c36 8004c0e: 687b ldr r3, [r7, #4] 8004c10: 4a27 ldr r2, [pc, #156] ; (8004cb0 ) 8004c12: 4293 cmp r3, r2 8004c14: d00f beq.n 8004c36 8004c16: 687b ldr r3, [r7, #4] 8004c18: 4a26 ldr r2, [pc, #152] ; (8004cb4 ) 8004c1a: 4293 cmp r3, r2 8004c1c: d00b beq.n 8004c36 8004c1e: 687b ldr r3, [r7, #4] 8004c20: 4a25 ldr r2, [pc, #148] ; (8004cb8 ) 8004c22: 4293 cmp r3, r2 8004c24: d007 beq.n 8004c36 8004c26: 687b ldr r3, [r7, #4] 8004c28: 4a24 ldr r2, [pc, #144] ; (8004cbc ) 8004c2a: 4293 cmp r3, r2 8004c2c: d003 beq.n 8004c36 8004c2e: 687b ldr r3, [r7, #4] 8004c30: 4a23 ldr r2, [pc, #140] ; (8004cc0 ) 8004c32: 4293 cmp r3, r2 8004c34: d108 bne.n 8004c48 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8004c36: 68fb ldr r3, [r7, #12] 8004c38: f423 7340 bic.w r3, r3, #768 ; 0x300 8004c3c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004c3e: 683b ldr r3, [r7, #0] 8004c40: 68db ldr r3, [r3, #12] 8004c42: 68fa ldr r2, [r7, #12] 8004c44: 4313 orrs r3, r2 8004c46: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004c48: 68fb ldr r3, [r7, #12] 8004c4a: f023 0280 bic.w r2, r3, #128 ; 0x80 8004c4e: 683b ldr r3, [r7, #0] 8004c50: 695b ldr r3, [r3, #20] 8004c52: 4313 orrs r3, r2 8004c54: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8004c56: 687b ldr r3, [r7, #4] 8004c58: 68fa ldr r2, [r7, #12] 8004c5a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8004c5c: 683b ldr r3, [r7, #0] 8004c5e: 689a ldr r2, [r3, #8] 8004c60: 687b ldr r3, [r7, #4] 8004c62: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8004c64: 683b ldr r3, [r7, #0] 8004c66: 681a ldr r2, [r3, #0] 8004c68: 687b ldr r3, [r7, #4] 8004c6a: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8004c6c: 687b ldr r3, [r7, #4] 8004c6e: 4a0a ldr r2, [pc, #40] ; (8004c98 ) 8004c70: 4293 cmp r3, r2 8004c72: d003 beq.n 8004c7c 8004c74: 687b ldr r3, [r7, #4] 8004c76: 4a0c ldr r2, [pc, #48] ; (8004ca8 ) 8004c78: 4293 cmp r3, r2 8004c7a: d103 bne.n 8004c84 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8004c7c: 683b ldr r3, [r7, #0] 8004c7e: 691a ldr r2, [r3, #16] 8004c80: 687b ldr r3, [r7, #4] 8004c82: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8004c84: 687b ldr r3, [r7, #4] 8004c86: 2201 movs r2, #1 8004c88: 615a str r2, [r3, #20] } 8004c8a: bf00 nop 8004c8c: 3714 adds r7, #20 8004c8e: 46bd mov sp, r7 8004c90: f85d 7b04 ldr.w r7, [sp], #4 8004c94: 4770 bx lr 8004c96: bf00 nop 8004c98: 40010000 .word 0x40010000 8004c9c: 40000400 .word 0x40000400 8004ca0: 40000800 .word 0x40000800 8004ca4: 40000c00 .word 0x40000c00 8004ca8: 40010400 .word 0x40010400 8004cac: 40014000 .word 0x40014000 8004cb0: 40014400 .word 0x40014400 8004cb4: 40014800 .word 0x40014800 8004cb8: 40001800 .word 0x40001800 8004cbc: 40001c00 .word 0x40001c00 8004cc0: 40002000 .word 0x40002000 08004cc4 : * @param sSlaveConfig Slave timer configuration * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { 8004cc4: b580 push {r7, lr} 8004cc6: b086 sub sp, #24 8004cc8: af00 add r7, sp, #0 8004cca: 6078 str r0, [r7, #4] 8004ccc: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8004cce: 2300 movs r3, #0 8004cd0: 75fb strb r3, [r7, #23] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8004cd2: 687b ldr r3, [r7, #4] 8004cd4: 681b ldr r3, [r3, #0] 8004cd6: 689b ldr r3, [r3, #8] 8004cd8: 613b str r3, [r7, #16] /* Reset the Trigger Selection Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8004cda: 693b ldr r3, [r7, #16] 8004cdc: f023 0370 bic.w r3, r3, #112 ; 0x70 8004ce0: 613b str r3, [r7, #16] /* Set the Input Trigger source */ tmpsmcr |= sSlaveConfig->InputTrigger; 8004ce2: 683b ldr r3, [r7, #0] 8004ce4: 685b ldr r3, [r3, #4] 8004ce6: 693a ldr r2, [r7, #16] 8004ce8: 4313 orrs r3, r2 8004cea: 613b str r3, [r7, #16] /* Reset the slave mode Bits */ tmpsmcr &= ~TIM_SMCR_SMS; 8004cec: 693b ldr r3, [r7, #16] 8004cee: f023 0307 bic.w r3, r3, #7 8004cf2: 613b str r3, [r7, #16] /* Set the slave mode */ tmpsmcr |= sSlaveConfig->SlaveMode; 8004cf4: 683b ldr r3, [r7, #0] 8004cf6: 681b ldr r3, [r3, #0] 8004cf8: 693a ldr r2, [r7, #16] 8004cfa: 4313 orrs r3, r2 8004cfc: 613b str r3, [r7, #16] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8004cfe: 687b ldr r3, [r7, #4] 8004d00: 681b ldr r3, [r3, #0] 8004d02: 693a ldr r2, [r7, #16] 8004d04: 609a str r2, [r3, #8] /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) 8004d06: 683b ldr r3, [r7, #0] 8004d08: 685b ldr r3, [r3, #4] 8004d0a: 2b70 cmp r3, #112 ; 0x70 8004d0c: d01a beq.n 8004d44 8004d0e: 2b70 cmp r3, #112 ; 0x70 8004d10: d860 bhi.n 8004dd4 8004d12: 2b60 cmp r3, #96 ; 0x60 8004d14: d054 beq.n 8004dc0 8004d16: 2b60 cmp r3, #96 ; 0x60 8004d18: d85c bhi.n 8004dd4 8004d1a: 2b50 cmp r3, #80 ; 0x50 8004d1c: d046 beq.n 8004dac 8004d1e: 2b50 cmp r3, #80 ; 0x50 8004d20: d858 bhi.n 8004dd4 8004d22: 2b40 cmp r3, #64 ; 0x40 8004d24: d019 beq.n 8004d5a 8004d26: 2b40 cmp r3, #64 ; 0x40 8004d28: d854 bhi.n 8004dd4 8004d2a: 2b30 cmp r3, #48 ; 0x30 8004d2c: d055 beq.n 8004dda 8004d2e: 2b30 cmp r3, #48 ; 0x30 8004d30: d850 bhi.n 8004dd4 8004d32: 2b20 cmp r3, #32 8004d34: d051 beq.n 8004dda 8004d36: 2b20 cmp r3, #32 8004d38: d84c bhi.n 8004dd4 8004d3a: 2b00 cmp r3, #0 8004d3c: d04d beq.n 8004dda 8004d3e: 2b10 cmp r3, #16 8004d40: d04b beq.n 8004dda 8004d42: e047 b.n 8004dd4 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ TIM_ETR_SetConfig(htim->Instance, 8004d44: 687b ldr r3, [r7, #4] 8004d46: 6818 ldr r0, [r3, #0] 8004d48: 683b ldr r3, [r7, #0] 8004d4a: 68d9 ldr r1, [r3, #12] 8004d4c: 683b ldr r3, [r7, #0] 8004d4e: 689a ldr r2, [r3, #8] 8004d50: 683b ldr r3, [r7, #0] 8004d52: 691b ldr r3, [r3, #16] 8004d54: f000 f8a6 bl 8004ea4 sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; 8004d58: e040 b.n 8004ddc { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) 8004d5a: 683b ldr r3, [r7, #0] 8004d5c: 681b ldr r3, [r3, #0] 8004d5e: 2b05 cmp r3, #5 8004d60: d101 bne.n 8004d66 { return HAL_ERROR; 8004d62: 2301 movs r3, #1 8004d64: e03b b.n 8004dde } /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; 8004d66: 687b ldr r3, [r7, #4] 8004d68: 681b ldr r3, [r3, #0] 8004d6a: 6a1b ldr r3, [r3, #32] 8004d6c: 60fb str r3, [r7, #12] htim->Instance->CCER &= ~TIM_CCER_CC1E; 8004d6e: 687b ldr r3, [r7, #4] 8004d70: 681b ldr r3, [r3, #0] 8004d72: 6a1a ldr r2, [r3, #32] 8004d74: 687b ldr r3, [r7, #4] 8004d76: 681b ldr r3, [r3, #0] 8004d78: f022 0201 bic.w r2, r2, #1 8004d7c: 621a str r2, [r3, #32] tmpccmr1 = htim->Instance->CCMR1; 8004d7e: 687b ldr r3, [r7, #4] 8004d80: 681b ldr r3, [r3, #0] 8004d82: 699b ldr r3, [r3, #24] 8004d84: 60bb str r3, [r7, #8] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8004d86: 68bb ldr r3, [r7, #8] 8004d88: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8004d8c: 60bb str r3, [r7, #8] tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); 8004d8e: 683b ldr r3, [r7, #0] 8004d90: 691b ldr r3, [r3, #16] 8004d92: 011b lsls r3, r3, #4 8004d94: 68ba ldr r2, [r7, #8] 8004d96: 4313 orrs r3, r2 8004d98: 60bb str r3, [r7, #8] /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; 8004d9a: 687b ldr r3, [r7, #4] 8004d9c: 681b ldr r3, [r3, #0] 8004d9e: 68ba ldr r2, [r7, #8] 8004da0: 619a str r2, [r3, #24] htim->Instance->CCER = tmpccer; 8004da2: 687b ldr r3, [r7, #4] 8004da4: 681b ldr r3, [r3, #0] 8004da6: 68fa ldr r2, [r7, #12] 8004da8: 621a str r2, [r3, #32] break; 8004daa: e017 b.n 8004ddc assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, 8004dac: 687b ldr r3, [r7, #4] 8004dae: 6818 ldr r0, [r3, #0] 8004db0: 683b ldr r3, [r7, #0] 8004db2: 6899 ldr r1, [r3, #8] 8004db4: 683b ldr r3, [r7, #0] 8004db6: 691b ldr r3, [r3, #16] 8004db8: 461a mov r2, r3 8004dba: f000 f814 bl 8004de6 sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; 8004dbe: e00d b.n 8004ddc assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, 8004dc0: 687b ldr r3, [r7, #4] 8004dc2: 6818 ldr r0, [r3, #0] 8004dc4: 683b ldr r3, [r7, #0] 8004dc6: 6899 ldr r1, [r3, #8] 8004dc8: 683b ldr r3, [r7, #0] 8004dca: 691b ldr r3, [r3, #16] 8004dcc: 461a mov r2, r3 8004dce: f000 f839 bl 8004e44 sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; 8004dd2: e003 b.n 8004ddc assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); break; } default: status = HAL_ERROR; 8004dd4: 2301 movs r3, #1 8004dd6: 75fb strb r3, [r7, #23] break; 8004dd8: e000 b.n 8004ddc break; 8004dda: bf00 nop } return status; 8004ddc: 7dfb ldrb r3, [r7, #23] } 8004dde: 4618 mov r0, r3 8004de0: 3718 adds r7, #24 8004de2: 46bd mov sp, r7 8004de4: bd80 pop {r7, pc} 08004de6 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8004de6: b480 push {r7} 8004de8: b087 sub sp, #28 8004dea: af00 add r7, sp, #0 8004dec: 60f8 str r0, [r7, #12] 8004dee: 60b9 str r1, [r7, #8] 8004df0: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8004df2: 68fb ldr r3, [r7, #12] 8004df4: 6a1b ldr r3, [r3, #32] 8004df6: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8004df8: 68fb ldr r3, [r7, #12] 8004dfa: 6a1b ldr r3, [r3, #32] 8004dfc: f023 0201 bic.w r2, r3, #1 8004e00: 68fb ldr r3, [r7, #12] 8004e02: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8004e04: 68fb ldr r3, [r7, #12] 8004e06: 699b ldr r3, [r3, #24] 8004e08: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8004e0a: 693b ldr r3, [r7, #16] 8004e0c: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8004e10: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8004e12: 687b ldr r3, [r7, #4] 8004e14: 011b lsls r3, r3, #4 8004e16: 693a ldr r2, [r7, #16] 8004e18: 4313 orrs r3, r2 8004e1a: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8004e1c: 697b ldr r3, [r7, #20] 8004e1e: f023 030a bic.w r3, r3, #10 8004e22: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8004e24: 697a ldr r2, [r7, #20] 8004e26: 68bb ldr r3, [r7, #8] 8004e28: 4313 orrs r3, r2 8004e2a: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8004e2c: 68fb ldr r3, [r7, #12] 8004e2e: 693a ldr r2, [r7, #16] 8004e30: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8004e32: 68fb ldr r3, [r7, #12] 8004e34: 697a ldr r2, [r7, #20] 8004e36: 621a str r2, [r3, #32] } 8004e38: bf00 nop 8004e3a: 371c adds r7, #28 8004e3c: 46bd mov sp, r7 8004e3e: f85d 7b04 ldr.w r7, [sp], #4 8004e42: 4770 bx lr 08004e44 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8004e44: b480 push {r7} 8004e46: b087 sub sp, #28 8004e48: af00 add r7, sp, #0 8004e4a: 60f8 str r0, [r7, #12] 8004e4c: 60b9 str r1, [r7, #8] 8004e4e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8004e50: 68fb ldr r3, [r7, #12] 8004e52: 6a1b ldr r3, [r3, #32] 8004e54: f023 0210 bic.w r2, r3, #16 8004e58: 68fb ldr r3, [r7, #12] 8004e5a: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8004e5c: 68fb ldr r3, [r7, #12] 8004e5e: 699b ldr r3, [r3, #24] 8004e60: 617b str r3, [r7, #20] tmpccer = TIMx->CCER; 8004e62: 68fb ldr r3, [r7, #12] 8004e64: 6a1b ldr r3, [r3, #32] 8004e66: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8004e68: 697b ldr r3, [r7, #20] 8004e6a: f423 4370 bic.w r3, r3, #61440 ; 0xf000 8004e6e: 617b str r3, [r7, #20] tmpccmr1 |= (TIM_ICFilter << 12U); 8004e70: 687b ldr r3, [r7, #4] 8004e72: 031b lsls r3, r3, #12 8004e74: 697a ldr r2, [r7, #20] 8004e76: 4313 orrs r3, r2 8004e78: 617b str r3, [r7, #20] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8004e7a: 693b ldr r3, [r7, #16] 8004e7c: f023 03a0 bic.w r3, r3, #160 ; 0xa0 8004e80: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity << 4U); 8004e82: 68bb ldr r3, [r7, #8] 8004e84: 011b lsls r3, r3, #4 8004e86: 693a ldr r2, [r7, #16] 8004e88: 4313 orrs r3, r2 8004e8a: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8004e8c: 68fb ldr r3, [r7, #12] 8004e8e: 697a ldr r2, [r7, #20] 8004e90: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8004e92: 68fb ldr r3, [r7, #12] 8004e94: 693a ldr r2, [r7, #16] 8004e96: 621a str r2, [r3, #32] } 8004e98: bf00 nop 8004e9a: 371c adds r7, #28 8004e9c: 46bd mov sp, r7 8004e9e: f85d 7b04 ldr.w r7, [sp], #4 8004ea2: 4770 bx lr 08004ea4 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8004ea4: b480 push {r7} 8004ea6: b087 sub sp, #28 8004ea8: af00 add r7, sp, #0 8004eaa: 60f8 str r0, [r7, #12] 8004eac: 60b9 str r1, [r7, #8] 8004eae: 607a str r2, [r7, #4] 8004eb0: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8004eb2: 68fb ldr r3, [r7, #12] 8004eb4: 689b ldr r3, [r3, #8] 8004eb6: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8004eb8: 697b ldr r3, [r7, #20] 8004eba: f423 437f bic.w r3, r3, #65280 ; 0xff00 8004ebe: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8004ec0: 683b ldr r3, [r7, #0] 8004ec2: 021a lsls r2, r3, #8 8004ec4: 687b ldr r3, [r7, #4] 8004ec6: 431a orrs r2, r3 8004ec8: 68bb ldr r3, [r7, #8] 8004eca: 4313 orrs r3, r2 8004ecc: 697a ldr r2, [r7, #20] 8004ece: 4313 orrs r3, r2 8004ed0: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8004ed2: 68fb ldr r3, [r7, #12] 8004ed4: 697a ldr r2, [r7, #20] 8004ed6: 609a str r2, [r3, #8] } 8004ed8: bf00 nop 8004eda: 371c adds r7, #28 8004edc: 46bd mov sp, r7 8004ede: f85d 7b04 ldr.w r7, [sp], #4 8004ee2: 4770 bx lr 08004ee4 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 8004ee4: b480 push {r7} 8004ee6: b085 sub sp, #20 8004ee8: af00 add r7, sp, #0 8004eea: 6078 str r0, [r7, #4] 8004eec: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8004eee: 687b ldr r3, [r7, #4] 8004ef0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8004ef4: 2b01 cmp r3, #1 8004ef6: d101 bne.n 8004efc 8004ef8: 2302 movs r3, #2 8004efa: e05a b.n 8004fb2 8004efc: 687b ldr r3, [r7, #4] 8004efe: 2201 movs r2, #1 8004f00: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8004f04: 687b ldr r3, [r7, #4] 8004f06: 2202 movs r2, #2 8004f08: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8004f0c: 687b ldr r3, [r7, #4] 8004f0e: 681b ldr r3, [r3, #0] 8004f10: 685b ldr r3, [r3, #4] 8004f12: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8004f14: 687b ldr r3, [r7, #4] 8004f16: 681b ldr r3, [r3, #0] 8004f18: 689b ldr r3, [r3, #8] 8004f1a: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8004f1c: 68fb ldr r3, [r7, #12] 8004f1e: f023 0370 bic.w r3, r3, #112 ; 0x70 8004f22: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8004f24: 683b ldr r3, [r7, #0] 8004f26: 681b ldr r3, [r3, #0] 8004f28: 68fa ldr r2, [r7, #12] 8004f2a: 4313 orrs r3, r2 8004f2c: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8004f2e: 687b ldr r3, [r7, #4] 8004f30: 681b ldr r3, [r3, #0] 8004f32: 68fa ldr r2, [r7, #12] 8004f34: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8004f36: 687b ldr r3, [r7, #4] 8004f38: 681b ldr r3, [r3, #0] 8004f3a: 4a21 ldr r2, [pc, #132] ; (8004fc0 ) 8004f3c: 4293 cmp r3, r2 8004f3e: d022 beq.n 8004f86 8004f40: 687b ldr r3, [r7, #4] 8004f42: 681b ldr r3, [r3, #0] 8004f44: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004f48: d01d beq.n 8004f86 8004f4a: 687b ldr r3, [r7, #4] 8004f4c: 681b ldr r3, [r3, #0] 8004f4e: 4a1d ldr r2, [pc, #116] ; (8004fc4 ) 8004f50: 4293 cmp r3, r2 8004f52: d018 beq.n 8004f86 8004f54: 687b ldr r3, [r7, #4] 8004f56: 681b ldr r3, [r3, #0] 8004f58: 4a1b ldr r2, [pc, #108] ; (8004fc8 ) 8004f5a: 4293 cmp r3, r2 8004f5c: d013 beq.n 8004f86 8004f5e: 687b ldr r3, [r7, #4] 8004f60: 681b ldr r3, [r3, #0] 8004f62: 4a1a ldr r2, [pc, #104] ; (8004fcc ) 8004f64: 4293 cmp r3, r2 8004f66: d00e beq.n 8004f86 8004f68: 687b ldr r3, [r7, #4] 8004f6a: 681b ldr r3, [r3, #0] 8004f6c: 4a18 ldr r2, [pc, #96] ; (8004fd0 ) 8004f6e: 4293 cmp r3, r2 8004f70: d009 beq.n 8004f86 8004f72: 687b ldr r3, [r7, #4] 8004f74: 681b ldr r3, [r3, #0] 8004f76: 4a17 ldr r2, [pc, #92] ; (8004fd4 ) 8004f78: 4293 cmp r3, r2 8004f7a: d004 beq.n 8004f86 8004f7c: 687b ldr r3, [r7, #4] 8004f7e: 681b ldr r3, [r3, #0] 8004f80: 4a15 ldr r2, [pc, #84] ; (8004fd8 ) 8004f82: 4293 cmp r3, r2 8004f84: d10c bne.n 8004fa0 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8004f86: 68bb ldr r3, [r7, #8] 8004f88: f023 0380 bic.w r3, r3, #128 ; 0x80 8004f8c: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8004f8e: 683b ldr r3, [r7, #0] 8004f90: 685b ldr r3, [r3, #4] 8004f92: 68ba ldr r2, [r7, #8] 8004f94: 4313 orrs r3, r2 8004f96: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8004f98: 687b ldr r3, [r7, #4] 8004f9a: 681b ldr r3, [r3, #0] 8004f9c: 68ba ldr r2, [r7, #8] 8004f9e: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8004fa0: 687b ldr r3, [r7, #4] 8004fa2: 2201 movs r2, #1 8004fa4: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8004fa8: 687b ldr r3, [r7, #4] 8004faa: 2200 movs r2, #0 8004fac: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8004fb0: 2300 movs r3, #0 } 8004fb2: 4618 mov r0, r3 8004fb4: 3714 adds r7, #20 8004fb6: 46bd mov sp, r7 8004fb8: f85d 7b04 ldr.w r7, [sp], #4 8004fbc: 4770 bx lr 8004fbe: bf00 nop 8004fc0: 40010000 .word 0x40010000 8004fc4: 40000400 .word 0x40000400 8004fc8: 40000800 .word 0x40000800 8004fcc: 40000c00 .word 0x40000c00 8004fd0: 40010400 .word 0x40010400 8004fd4: 40014000 .word 0x40014000 8004fd8: 40001800 .word 0x40001800 08004fdc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8004fdc: b580 push {r7, lr} 8004fde: b082 sub sp, #8 8004fe0: af00 add r7, sp, #0 8004fe2: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8004fe4: 687b ldr r3, [r7, #4] 8004fe6: 2b00 cmp r3, #0 8004fe8: d101 bne.n 8004fee { return HAL_ERROR; 8004fea: 2301 movs r3, #1 8004fec: e03f b.n 800506e assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8004fee: 687b ldr r3, [r7, #4] 8004ff0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8004ff4: b2db uxtb r3, r3 8004ff6: 2b00 cmp r3, #0 8004ff8: d106 bne.n 8005008 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8004ffa: 687b ldr r3, [r7, #4] 8004ffc: 2200 movs r2, #0 8004ffe: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005002: 6878 ldr r0, [r7, #4] 8005004: f7fc f82c bl 8001060 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005008: 687b ldr r3, [r7, #4] 800500a: 2224 movs r2, #36 ; 0x24 800500c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005010: 687b ldr r3, [r7, #4] 8005012: 681b ldr r3, [r3, #0] 8005014: 68da ldr r2, [r3, #12] 8005016: 687b ldr r3, [r7, #4] 8005018: 681b ldr r3, [r3, #0] 800501a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 800501e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005020: 6878 ldr r0, [r7, #4] 8005022: f000 f829 bl 8005078 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005026: 687b ldr r3, [r7, #4] 8005028: 681b ldr r3, [r3, #0] 800502a: 691a ldr r2, [r3, #16] 800502c: 687b ldr r3, [r7, #4] 800502e: 681b ldr r3, [r3, #0] 8005030: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8005034: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005036: 687b ldr r3, [r7, #4] 8005038: 681b ldr r3, [r3, #0] 800503a: 695a ldr r2, [r3, #20] 800503c: 687b ldr r3, [r7, #4] 800503e: 681b ldr r3, [r3, #0] 8005040: f022 022a bic.w r2, r2, #42 ; 0x2a 8005044: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005046: 687b ldr r3, [r7, #4] 8005048: 681b ldr r3, [r3, #0] 800504a: 68da ldr r2, [r3, #12] 800504c: 687b ldr r3, [r7, #4] 800504e: 681b ldr r3, [r3, #0] 8005050: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8005054: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005056: 687b ldr r3, [r7, #4] 8005058: 2200 movs r2, #0 800505a: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_READY; 800505c: 687b ldr r3, [r7, #4] 800505e: 2220 movs r2, #32 8005060: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8005064: 687b ldr r3, [r7, #4] 8005066: 2220 movs r2, #32 8005068: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 800506c: 2300 movs r3, #0 } 800506e: 4618 mov r0, r3 8005070: 3708 adds r7, #8 8005072: 46bd mov sp, r7 8005074: bd80 pop {r7, pc} ... 08005078 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8005078: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800507c: b09f sub sp, #124 ; 0x7c 800507e: af00 add r7, sp, #0 8005080: 66f8 str r0, [r7, #108] ; 0x6c assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005082: 6efb ldr r3, [r7, #108] ; 0x6c 8005084: 681b ldr r3, [r3, #0] 8005086: 691b ldr r3, [r3, #16] 8005088: f423 5040 bic.w r0, r3, #12288 ; 0x3000 800508c: 6efb ldr r3, [r7, #108] ; 0x6c 800508e: 68d9 ldr r1, [r3, #12] 8005090: 6efb ldr r3, [r7, #108] ; 0x6c 8005092: 681a ldr r2, [r3, #0] 8005094: ea40 0301 orr.w r3, r0, r1 8005098: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 800509a: 6efb ldr r3, [r7, #108] ; 0x6c 800509c: 689a ldr r2, [r3, #8] 800509e: 6efb ldr r3, [r7, #108] ; 0x6c 80050a0: 691b ldr r3, [r3, #16] 80050a2: 431a orrs r2, r3 80050a4: 6efb ldr r3, [r7, #108] ; 0x6c 80050a6: 695b ldr r3, [r3, #20] 80050a8: 431a orrs r2, r3 80050aa: 6efb ldr r3, [r7, #108] ; 0x6c 80050ac: 69db ldr r3, [r3, #28] 80050ae: 4313 orrs r3, r2 80050b0: 673b str r3, [r7, #112] ; 0x70 MODIFY_REG(huart->Instance->CR1, 80050b2: 6efb ldr r3, [r7, #108] ; 0x6c 80050b4: 681b ldr r3, [r3, #0] 80050b6: 68db ldr r3, [r3, #12] 80050b8: f423 4116 bic.w r1, r3, #38400 ; 0x9600 80050bc: f021 010c bic.w r1, r1, #12 80050c0: 6efb ldr r3, [r7, #108] ; 0x6c 80050c2: 681a ldr r2, [r3, #0] 80050c4: 6f3b ldr r3, [r7, #112] ; 0x70 80050c6: 430b orrs r3, r1 80050c8: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80050ca: 6efb ldr r3, [r7, #108] ; 0x6c 80050cc: 681b ldr r3, [r3, #0] 80050ce: 695b ldr r3, [r3, #20] 80050d0: f423 7040 bic.w r0, r3, #768 ; 0x300 80050d4: 6efb ldr r3, [r7, #108] ; 0x6c 80050d6: 6999 ldr r1, [r3, #24] 80050d8: 6efb ldr r3, [r7, #108] ; 0x6c 80050da: 681a ldr r2, [r3, #0] 80050dc: ea40 0301 orr.w r3, r0, r1 80050e0: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 80050e2: 6efb ldr r3, [r7, #108] ; 0x6c 80050e4: 681a ldr r2, [r3, #0] 80050e6: 4bc5 ldr r3, [pc, #788] ; (80053fc ) 80050e8: 429a cmp r2, r3 80050ea: d004 beq.n 80050f6 80050ec: 6efb ldr r3, [r7, #108] ; 0x6c 80050ee: 681a ldr r2, [r3, #0] 80050f0: 4bc3 ldr r3, [pc, #780] ; (8005400 ) 80050f2: 429a cmp r2, r3 80050f4: d103 bne.n 80050fe { pclk = HAL_RCC_GetPCLK2Freq(); 80050f6: f7fe f977 bl 80033e8 80050fa: 6778 str r0, [r7, #116] ; 0x74 80050fc: e002 b.n 8005104 pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 80050fe: f7fe f95f bl 80033c0 8005102: 6778 str r0, [r7, #116] ; 0x74 } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8005104: 6efb ldr r3, [r7, #108] ; 0x6c 8005106: 69db ldr r3, [r3, #28] 8005108: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 800510c: f040 80b6 bne.w 800527c { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8005110: 6f7b ldr r3, [r7, #116] ; 0x74 8005112: 461c mov r4, r3 8005114: f04f 0500 mov.w r5, #0 8005118: 4622 mov r2, r4 800511a: 462b mov r3, r5 800511c: 1891 adds r1, r2, r2 800511e: 6439 str r1, [r7, #64] ; 0x40 8005120: 415b adcs r3, r3 8005122: 647b str r3, [r7, #68] ; 0x44 8005124: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40 8005128: 1912 adds r2, r2, r4 800512a: eb45 0303 adc.w r3, r5, r3 800512e: f04f 0000 mov.w r0, #0 8005132: f04f 0100 mov.w r1, #0 8005136: 00d9 lsls r1, r3, #3 8005138: ea41 7152 orr.w r1, r1, r2, lsr #29 800513c: 00d0 lsls r0, r2, #3 800513e: 4602 mov r2, r0 8005140: 460b mov r3, r1 8005142: 1911 adds r1, r2, r4 8005144: 6639 str r1, [r7, #96] ; 0x60 8005146: 416b adcs r3, r5 8005148: 667b str r3, [r7, #100] ; 0x64 800514a: 6efb ldr r3, [r7, #108] ; 0x6c 800514c: 685b ldr r3, [r3, #4] 800514e: 461a mov r2, r3 8005150: f04f 0300 mov.w r3, #0 8005154: 1891 adds r1, r2, r2 8005156: 63b9 str r1, [r7, #56] ; 0x38 8005158: 415b adcs r3, r3 800515a: 63fb str r3, [r7, #60] ; 0x3c 800515c: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 8005160: e9d7 0118 ldrd r0, r1, [r7, #96] ; 0x60 8005164: f7fb f84e bl 8000204 <__aeabi_uldivmod> 8005168: 4602 mov r2, r0 800516a: 460b mov r3, r1 800516c: 4ba5 ldr r3, [pc, #660] ; (8005404 ) 800516e: fba3 2302 umull r2, r3, r3, r2 8005172: 095b lsrs r3, r3, #5 8005174: 011e lsls r6, r3, #4 8005176: 6f7b ldr r3, [r7, #116] ; 0x74 8005178: 461c mov r4, r3 800517a: f04f 0500 mov.w r5, #0 800517e: 4622 mov r2, r4 8005180: 462b mov r3, r5 8005182: 1891 adds r1, r2, r2 8005184: 6339 str r1, [r7, #48] ; 0x30 8005186: 415b adcs r3, r3 8005188: 637b str r3, [r7, #52] ; 0x34 800518a: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30 800518e: 1912 adds r2, r2, r4 8005190: eb45 0303 adc.w r3, r5, r3 8005194: f04f 0000 mov.w r0, #0 8005198: f04f 0100 mov.w r1, #0 800519c: 00d9 lsls r1, r3, #3 800519e: ea41 7152 orr.w r1, r1, r2, lsr #29 80051a2: 00d0 lsls r0, r2, #3 80051a4: 4602 mov r2, r0 80051a6: 460b mov r3, r1 80051a8: 1911 adds r1, r2, r4 80051aa: 65b9 str r1, [r7, #88] ; 0x58 80051ac: 416b adcs r3, r5 80051ae: 65fb str r3, [r7, #92] ; 0x5c 80051b0: 6efb ldr r3, [r7, #108] ; 0x6c 80051b2: 685b ldr r3, [r3, #4] 80051b4: 461a mov r2, r3 80051b6: f04f 0300 mov.w r3, #0 80051ba: 1891 adds r1, r2, r2 80051bc: 62b9 str r1, [r7, #40] ; 0x28 80051be: 415b adcs r3, r3 80051c0: 62fb str r3, [r7, #44] ; 0x2c 80051c2: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 80051c6: e9d7 0116 ldrd r0, r1, [r7, #88] ; 0x58 80051ca: f7fb f81b bl 8000204 <__aeabi_uldivmod> 80051ce: 4602 mov r2, r0 80051d0: 460b mov r3, r1 80051d2: 4b8c ldr r3, [pc, #560] ; (8005404 ) 80051d4: fba3 1302 umull r1, r3, r3, r2 80051d8: 095b lsrs r3, r3, #5 80051da: 2164 movs r1, #100 ; 0x64 80051dc: fb01 f303 mul.w r3, r1, r3 80051e0: 1ad3 subs r3, r2, r3 80051e2: 00db lsls r3, r3, #3 80051e4: 3332 adds r3, #50 ; 0x32 80051e6: 4a87 ldr r2, [pc, #540] ; (8005404 ) 80051e8: fba2 2303 umull r2, r3, r2, r3 80051ec: 095b lsrs r3, r3, #5 80051ee: 005b lsls r3, r3, #1 80051f0: f403 73f8 and.w r3, r3, #496 ; 0x1f0 80051f4: 441e add r6, r3 80051f6: 6f7b ldr r3, [r7, #116] ; 0x74 80051f8: 4618 mov r0, r3 80051fa: f04f 0100 mov.w r1, #0 80051fe: 4602 mov r2, r0 8005200: 460b mov r3, r1 8005202: 1894 adds r4, r2, r2 8005204: 623c str r4, [r7, #32] 8005206: 415b adcs r3, r3 8005208: 627b str r3, [r7, #36] ; 0x24 800520a: e9d7 2308 ldrd r2, r3, [r7, #32] 800520e: 1812 adds r2, r2, r0 8005210: eb41 0303 adc.w r3, r1, r3 8005214: f04f 0400 mov.w r4, #0 8005218: f04f 0500 mov.w r5, #0 800521c: 00dd lsls r5, r3, #3 800521e: ea45 7552 orr.w r5, r5, r2, lsr #29 8005222: 00d4 lsls r4, r2, #3 8005224: 4622 mov r2, r4 8005226: 462b mov r3, r5 8005228: 1814 adds r4, r2, r0 800522a: 653c str r4, [r7, #80] ; 0x50 800522c: 414b adcs r3, r1 800522e: 657b str r3, [r7, #84] ; 0x54 8005230: 6efb ldr r3, [r7, #108] ; 0x6c 8005232: 685b ldr r3, [r3, #4] 8005234: 461a mov r2, r3 8005236: f04f 0300 mov.w r3, #0 800523a: 1891 adds r1, r2, r2 800523c: 61b9 str r1, [r7, #24] 800523e: 415b adcs r3, r3 8005240: 61fb str r3, [r7, #28] 8005242: e9d7 2306 ldrd r2, r3, [r7, #24] 8005246: e9d7 0114 ldrd r0, r1, [r7, #80] ; 0x50 800524a: f7fa ffdb bl 8000204 <__aeabi_uldivmod> 800524e: 4602 mov r2, r0 8005250: 460b mov r3, r1 8005252: 4b6c ldr r3, [pc, #432] ; (8005404 ) 8005254: fba3 1302 umull r1, r3, r3, r2 8005258: 095b lsrs r3, r3, #5 800525a: 2164 movs r1, #100 ; 0x64 800525c: fb01 f303 mul.w r3, r1, r3 8005260: 1ad3 subs r3, r2, r3 8005262: 00db lsls r3, r3, #3 8005264: 3332 adds r3, #50 ; 0x32 8005266: 4a67 ldr r2, [pc, #412] ; (8005404 ) 8005268: fba2 2303 umull r2, r3, r2, r3 800526c: 095b lsrs r3, r3, #5 800526e: f003 0207 and.w r2, r3, #7 8005272: 6efb ldr r3, [r7, #108] ; 0x6c 8005274: 681b ldr r3, [r3, #0] 8005276: 4432 add r2, r6 8005278: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 800527a: e0b9 b.n 80053f0 huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 800527c: 6f7b ldr r3, [r7, #116] ; 0x74 800527e: 461c mov r4, r3 8005280: f04f 0500 mov.w r5, #0 8005284: 4622 mov r2, r4 8005286: 462b mov r3, r5 8005288: 1891 adds r1, r2, r2 800528a: 6139 str r1, [r7, #16] 800528c: 415b adcs r3, r3 800528e: 617b str r3, [r7, #20] 8005290: e9d7 2304 ldrd r2, r3, [r7, #16] 8005294: 1912 adds r2, r2, r4 8005296: eb45 0303 adc.w r3, r5, r3 800529a: f04f 0000 mov.w r0, #0 800529e: f04f 0100 mov.w r1, #0 80052a2: 00d9 lsls r1, r3, #3 80052a4: ea41 7152 orr.w r1, r1, r2, lsr #29 80052a8: 00d0 lsls r0, r2, #3 80052aa: 4602 mov r2, r0 80052ac: 460b mov r3, r1 80052ae: eb12 0804 adds.w r8, r2, r4 80052b2: eb43 0905 adc.w r9, r3, r5 80052b6: 6efb ldr r3, [r7, #108] ; 0x6c 80052b8: 685b ldr r3, [r3, #4] 80052ba: 4618 mov r0, r3 80052bc: f04f 0100 mov.w r1, #0 80052c0: f04f 0200 mov.w r2, #0 80052c4: f04f 0300 mov.w r3, #0 80052c8: 008b lsls r3, r1, #2 80052ca: ea43 7390 orr.w r3, r3, r0, lsr #30 80052ce: 0082 lsls r2, r0, #2 80052d0: 4640 mov r0, r8 80052d2: 4649 mov r1, r9 80052d4: f7fa ff96 bl 8000204 <__aeabi_uldivmod> 80052d8: 4602 mov r2, r0 80052da: 460b mov r3, r1 80052dc: 4b49 ldr r3, [pc, #292] ; (8005404 ) 80052de: fba3 2302 umull r2, r3, r3, r2 80052e2: 095b lsrs r3, r3, #5 80052e4: 011e lsls r6, r3, #4 80052e6: 6f7b ldr r3, [r7, #116] ; 0x74 80052e8: 4618 mov r0, r3 80052ea: f04f 0100 mov.w r1, #0 80052ee: 4602 mov r2, r0 80052f0: 460b mov r3, r1 80052f2: 1894 adds r4, r2, r2 80052f4: 60bc str r4, [r7, #8] 80052f6: 415b adcs r3, r3 80052f8: 60fb str r3, [r7, #12] 80052fa: e9d7 2302 ldrd r2, r3, [r7, #8] 80052fe: 1812 adds r2, r2, r0 8005300: eb41 0303 adc.w r3, r1, r3 8005304: f04f 0400 mov.w r4, #0 8005308: f04f 0500 mov.w r5, #0 800530c: 00dd lsls r5, r3, #3 800530e: ea45 7552 orr.w r5, r5, r2, lsr #29 8005312: 00d4 lsls r4, r2, #3 8005314: 4622 mov r2, r4 8005316: 462b mov r3, r5 8005318: 1814 adds r4, r2, r0 800531a: 64bc str r4, [r7, #72] ; 0x48 800531c: 414b adcs r3, r1 800531e: 64fb str r3, [r7, #76] ; 0x4c 8005320: 6efb ldr r3, [r7, #108] ; 0x6c 8005322: 685b ldr r3, [r3, #4] 8005324: 4618 mov r0, r3 8005326: f04f 0100 mov.w r1, #0 800532a: f04f 0200 mov.w r2, #0 800532e: f04f 0300 mov.w r3, #0 8005332: 008b lsls r3, r1, #2 8005334: ea43 7390 orr.w r3, r3, r0, lsr #30 8005338: 0082 lsls r2, r0, #2 800533a: e9d7 0112 ldrd r0, r1, [r7, #72] ; 0x48 800533e: f7fa ff61 bl 8000204 <__aeabi_uldivmod> 8005342: 4602 mov r2, r0 8005344: 460b mov r3, r1 8005346: 4b2f ldr r3, [pc, #188] ; (8005404 ) 8005348: fba3 1302 umull r1, r3, r3, r2 800534c: 095b lsrs r3, r3, #5 800534e: 2164 movs r1, #100 ; 0x64 8005350: fb01 f303 mul.w r3, r1, r3 8005354: 1ad3 subs r3, r2, r3 8005356: 011b lsls r3, r3, #4 8005358: 3332 adds r3, #50 ; 0x32 800535a: 4a2a ldr r2, [pc, #168] ; (8005404 ) 800535c: fba2 2303 umull r2, r3, r2, r3 8005360: 095b lsrs r3, r3, #5 8005362: f003 03f0 and.w r3, r3, #240 ; 0xf0 8005366: 441e add r6, r3 8005368: 6f7b ldr r3, [r7, #116] ; 0x74 800536a: 4618 mov r0, r3 800536c: f04f 0100 mov.w r1, #0 8005370: 4602 mov r2, r0 8005372: 460b mov r3, r1 8005374: 1894 adds r4, r2, r2 8005376: 603c str r4, [r7, #0] 8005378: 415b adcs r3, r3 800537a: 607b str r3, [r7, #4] 800537c: e9d7 2300 ldrd r2, r3, [r7] 8005380: 1812 adds r2, r2, r0 8005382: eb41 0303 adc.w r3, r1, r3 8005386: f04f 0400 mov.w r4, #0 800538a: f04f 0500 mov.w r5, #0 800538e: 00dd lsls r5, r3, #3 8005390: ea45 7552 orr.w r5, r5, r2, lsr #29 8005394: 00d4 lsls r4, r2, #3 8005396: 4622 mov r2, r4 8005398: 462b mov r3, r5 800539a: eb12 0a00 adds.w sl, r2, r0 800539e: eb43 0b01 adc.w fp, r3, r1 80053a2: 6efb ldr r3, [r7, #108] ; 0x6c 80053a4: 685b ldr r3, [r3, #4] 80053a6: 4618 mov r0, r3 80053a8: f04f 0100 mov.w r1, #0 80053ac: f04f 0200 mov.w r2, #0 80053b0: f04f 0300 mov.w r3, #0 80053b4: 008b lsls r3, r1, #2 80053b6: ea43 7390 orr.w r3, r3, r0, lsr #30 80053ba: 0082 lsls r2, r0, #2 80053bc: 4650 mov r0, sl 80053be: 4659 mov r1, fp 80053c0: f7fa ff20 bl 8000204 <__aeabi_uldivmod> 80053c4: 4602 mov r2, r0 80053c6: 460b mov r3, r1 80053c8: 4b0e ldr r3, [pc, #56] ; (8005404 ) 80053ca: fba3 1302 umull r1, r3, r3, r2 80053ce: 095b lsrs r3, r3, #5 80053d0: 2164 movs r1, #100 ; 0x64 80053d2: fb01 f303 mul.w r3, r1, r3 80053d6: 1ad3 subs r3, r2, r3 80053d8: 011b lsls r3, r3, #4 80053da: 3332 adds r3, #50 ; 0x32 80053dc: 4a09 ldr r2, [pc, #36] ; (8005404 ) 80053de: fba2 2303 umull r2, r3, r2, r3 80053e2: 095b lsrs r3, r3, #5 80053e4: f003 020f and.w r2, r3, #15 80053e8: 6efb ldr r3, [r7, #108] ; 0x6c 80053ea: 681b ldr r3, [r3, #0] 80053ec: 4432 add r2, r6 80053ee: 609a str r2, [r3, #8] } 80053f0: bf00 nop 80053f2: 377c adds r7, #124 ; 0x7c 80053f4: 46bd mov sp, r7 80053f6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80053fa: bf00 nop 80053fc: 40011000 .word 0x40011000 8005400: 40011400 .word 0x40011400 8005404: 51eb851f .word 0x51eb851f 08005408 : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 8005408: b084 sub sp, #16 800540a: b580 push {r7, lr} 800540c: b084 sub sp, #16 800540e: af00 add r7, sp, #0 8005410: 6078 str r0, [r7, #4] 8005412: f107 001c add.w r0, r7, #28 8005416: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret; if (cfg.phy_itface == USB_OTG_ULPI_PHY) 800541a: 6b3b ldr r3, [r7, #48] ; 0x30 800541c: 2b01 cmp r3, #1 800541e: d122 bne.n 8005466 { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8005420: 687b ldr r3, [r7, #4] 8005422: 6b9b ldr r3, [r3, #56] ; 0x38 8005424: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8005428: 687b ldr r3, [r7, #4] 800542a: 639a str r2, [r3, #56] ; 0x38 /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); 800542c: 687b ldr r3, [r7, #4] 800542e: 68db ldr r3, [r3, #12] 8005430: f423 0384 bic.w r3, r3, #4325376 ; 0x420000 8005434: f023 0340 bic.w r3, r3, #64 ; 0x40 8005438: 687a ldr r2, [r7, #4] 800543a: 60d3 str r3, [r2, #12] /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); 800543c: 687b ldr r3, [r7, #4] 800543e: 68db ldr r3, [r3, #12] 8005440: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 8005444: 687b ldr r3, [r7, #4] 8005446: 60da str r2, [r3, #12] if (cfg.use_external_vbus == 1U) 8005448: 6cfb ldr r3, [r7, #76] ; 0x4c 800544a: 2b01 cmp r3, #1 800544c: d105 bne.n 800545a { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; 800544e: 687b ldr r3, [r7, #4] 8005450: 68db ldr r3, [r3, #12] 8005452: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8005456: 687b ldr r3, [r7, #4] 8005458: 60da str r2, [r3, #12] } /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 800545a: 6878 ldr r0, [r7, #4] 800545c: f001 fb16 bl 8006a8c 8005460: 4603 mov r3, r0 8005462: 73fb strb r3, [r7, #15] 8005464: e01a b.n 800549c } else /* FS interface (embedded Phy) */ { /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 8005466: 687b ldr r3, [r7, #4] 8005468: 68db ldr r3, [r3, #12] 800546a: f043 0240 orr.w r2, r3, #64 ; 0x40 800546e: 687b ldr r3, [r7, #4] 8005470: 60da str r2, [r3, #12] /* Reset after a PHY select */ ret = USB_CoreReset(USBx); 8005472: 6878 ldr r0, [r7, #4] 8005474: f001 fb0a bl 8006a8c 8005478: 4603 mov r3, r0 800547a: 73fb strb r3, [r7, #15] if (cfg.battery_charging_enable == 0U) 800547c: 6c3b ldr r3, [r7, #64] ; 0x40 800547e: 2b00 cmp r3, #0 8005480: d106 bne.n 8005490 { /* Activate the USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; 8005482: 687b ldr r3, [r7, #4] 8005484: 6b9b ldr r3, [r3, #56] ; 0x38 8005486: f443 3280 orr.w r2, r3, #65536 ; 0x10000 800548a: 687b ldr r3, [r7, #4] 800548c: 639a str r2, [r3, #56] ; 0x38 800548e: e005 b.n 800549c } else { /* Deactivate the USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); 8005490: 687b ldr r3, [r7, #4] 8005492: 6b9b ldr r3, [r3, #56] ; 0x38 8005494: f423 3280 bic.w r2, r3, #65536 ; 0x10000 8005498: 687b ldr r3, [r7, #4] 800549a: 639a str r2, [r3, #56] ; 0x38 } } if (cfg.dma_enable == 1U) 800549c: 6abb ldr r3, [r7, #40] ; 0x28 800549e: 2b01 cmp r3, #1 80054a0: d10b bne.n 80054ba { USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; 80054a2: 687b ldr r3, [r7, #4] 80054a4: 689b ldr r3, [r3, #8] 80054a6: f043 0206 orr.w r2, r3, #6 80054aa: 687b ldr r3, [r7, #4] 80054ac: 609a str r2, [r3, #8] USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; 80054ae: 687b ldr r3, [r7, #4] 80054b0: 689b ldr r3, [r3, #8] 80054b2: f043 0220 orr.w r2, r3, #32 80054b6: 687b ldr r3, [r7, #4] 80054b8: 609a str r2, [r3, #8] } return ret; 80054ba: 7bfb ldrb r3, [r7, #15] } 80054bc: 4618 mov r0, r3 80054be: 3710 adds r7, #16 80054c0: 46bd mov sp, r7 80054c2: e8bd 4080 ldmia.w sp!, {r7, lr} 80054c6: b004 add sp, #16 80054c8: 4770 bx lr ... 080054cc : * @param hclk: AHB clock frequency * @retval USB turnaround time In PHY Clocks number */ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed) { 80054cc: b480 push {r7} 80054ce: b087 sub sp, #28 80054d0: af00 add r7, sp, #0 80054d2: 60f8 str r0, [r7, #12] 80054d4: 60b9 str r1, [r7, #8] 80054d6: 4613 mov r3, r2 80054d8: 71fb strb r3, [r7, #7] /* The USBTRD is configured according to the tables below, depending on AHB frequency used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ if (speed == USBD_FS_SPEED) 80054da: 79fb ldrb r3, [r7, #7] 80054dc: 2b02 cmp r3, #2 80054de: d165 bne.n 80055ac { if ((hclk >= 14200000U) && (hclk < 15000000U)) 80054e0: 68bb ldr r3, [r7, #8] 80054e2: 4a41 ldr r2, [pc, #260] ; (80055e8 ) 80054e4: 4293 cmp r3, r2 80054e6: d906 bls.n 80054f6 80054e8: 68bb ldr r3, [r7, #8] 80054ea: 4a40 ldr r2, [pc, #256] ; (80055ec ) 80054ec: 4293 cmp r3, r2 80054ee: d202 bcs.n 80054f6 { /* hclk Clock Range between 14.2-15 MHz */ UsbTrd = 0xFU; 80054f0: 230f movs r3, #15 80054f2: 617b str r3, [r7, #20] 80054f4: e062 b.n 80055bc } else if ((hclk >= 15000000U) && (hclk < 16000000U)) 80054f6: 68bb ldr r3, [r7, #8] 80054f8: 4a3c ldr r2, [pc, #240] ; (80055ec ) 80054fa: 4293 cmp r3, r2 80054fc: d306 bcc.n 800550c 80054fe: 68bb ldr r3, [r7, #8] 8005500: 4a3b ldr r2, [pc, #236] ; (80055f0 ) 8005502: 4293 cmp r3, r2 8005504: d202 bcs.n 800550c { /* hclk Clock Range between 15-16 MHz */ UsbTrd = 0xEU; 8005506: 230e movs r3, #14 8005508: 617b str r3, [r7, #20] 800550a: e057 b.n 80055bc } else if ((hclk >= 16000000U) && (hclk < 17200000U)) 800550c: 68bb ldr r3, [r7, #8] 800550e: 4a38 ldr r2, [pc, #224] ; (80055f0 ) 8005510: 4293 cmp r3, r2 8005512: d306 bcc.n 8005522 8005514: 68bb ldr r3, [r7, #8] 8005516: 4a37 ldr r2, [pc, #220] ; (80055f4 ) 8005518: 4293 cmp r3, r2 800551a: d202 bcs.n 8005522 { /* hclk Clock Range between 16-17.2 MHz */ UsbTrd = 0xDU; 800551c: 230d movs r3, #13 800551e: 617b str r3, [r7, #20] 8005520: e04c b.n 80055bc } else if ((hclk >= 17200000U) && (hclk < 18500000U)) 8005522: 68bb ldr r3, [r7, #8] 8005524: 4a33 ldr r2, [pc, #204] ; (80055f4 ) 8005526: 4293 cmp r3, r2 8005528: d306 bcc.n 8005538 800552a: 68bb ldr r3, [r7, #8] 800552c: 4a32 ldr r2, [pc, #200] ; (80055f8 ) 800552e: 4293 cmp r3, r2 8005530: d802 bhi.n 8005538 { /* hclk Clock Range between 17.2-18.5 MHz */ UsbTrd = 0xCU; 8005532: 230c movs r3, #12 8005534: 617b str r3, [r7, #20] 8005536: e041 b.n 80055bc } else if ((hclk >= 18500000U) && (hclk < 20000000U)) 8005538: 68bb ldr r3, [r7, #8] 800553a: 4a2f ldr r2, [pc, #188] ; (80055f8 ) 800553c: 4293 cmp r3, r2 800553e: d906 bls.n 800554e 8005540: 68bb ldr r3, [r7, #8] 8005542: 4a2e ldr r2, [pc, #184] ; (80055fc ) 8005544: 4293 cmp r3, r2 8005546: d802 bhi.n 800554e { /* hclk Clock Range between 18.5-20 MHz */ UsbTrd = 0xBU; 8005548: 230b movs r3, #11 800554a: 617b str r3, [r7, #20] 800554c: e036 b.n 80055bc } else if ((hclk >= 20000000U) && (hclk < 21800000U)) 800554e: 68bb ldr r3, [r7, #8] 8005550: 4a2a ldr r2, [pc, #168] ; (80055fc ) 8005552: 4293 cmp r3, r2 8005554: d906 bls.n 8005564 8005556: 68bb ldr r3, [r7, #8] 8005558: 4a29 ldr r2, [pc, #164] ; (8005600 ) 800555a: 4293 cmp r3, r2 800555c: d802 bhi.n 8005564 { /* hclk Clock Range between 20-21.8 MHz */ UsbTrd = 0xAU; 800555e: 230a movs r3, #10 8005560: 617b str r3, [r7, #20] 8005562: e02b b.n 80055bc } else if ((hclk >= 21800000U) && (hclk < 24000000U)) 8005564: 68bb ldr r3, [r7, #8] 8005566: 4a26 ldr r2, [pc, #152] ; (8005600 ) 8005568: 4293 cmp r3, r2 800556a: d906 bls.n 800557a 800556c: 68bb ldr r3, [r7, #8] 800556e: 4a25 ldr r2, [pc, #148] ; (8005604 ) 8005570: 4293 cmp r3, r2 8005572: d202 bcs.n 800557a { /* hclk Clock Range between 21.8-24 MHz */ UsbTrd = 0x9U; 8005574: 2309 movs r3, #9 8005576: 617b str r3, [r7, #20] 8005578: e020 b.n 80055bc } else if ((hclk >= 24000000U) && (hclk < 27700000U)) 800557a: 68bb ldr r3, [r7, #8] 800557c: 4a21 ldr r2, [pc, #132] ; (8005604 ) 800557e: 4293 cmp r3, r2 8005580: d306 bcc.n 8005590 8005582: 68bb ldr r3, [r7, #8] 8005584: 4a20 ldr r2, [pc, #128] ; (8005608 ) 8005586: 4293 cmp r3, r2 8005588: d802 bhi.n 8005590 { /* hclk Clock Range between 24-27.7 MHz */ UsbTrd = 0x8U; 800558a: 2308 movs r3, #8 800558c: 617b str r3, [r7, #20] 800558e: e015 b.n 80055bc } else if ((hclk >= 27700000U) && (hclk < 32000000U)) 8005590: 68bb ldr r3, [r7, #8] 8005592: 4a1d ldr r2, [pc, #116] ; (8005608 ) 8005594: 4293 cmp r3, r2 8005596: d906 bls.n 80055a6 8005598: 68bb ldr r3, [r7, #8] 800559a: 4a1c ldr r2, [pc, #112] ; (800560c ) 800559c: 4293 cmp r3, r2 800559e: d202 bcs.n 80055a6 { /* hclk Clock Range between 27.7-32 MHz */ UsbTrd = 0x7U; 80055a0: 2307 movs r3, #7 80055a2: 617b str r3, [r7, #20] 80055a4: e00a b.n 80055bc } else /* if(hclk >= 32000000) */ { /* hclk Clock Range between 32-200 MHz */ UsbTrd = 0x6U; 80055a6: 2306 movs r3, #6 80055a8: 617b str r3, [r7, #20] 80055aa: e007 b.n 80055bc } } else if (speed == USBD_HS_SPEED) 80055ac: 79fb ldrb r3, [r7, #7] 80055ae: 2b00 cmp r3, #0 80055b0: d102 bne.n 80055b8 { UsbTrd = USBD_HS_TRDT_VALUE; 80055b2: 2309 movs r3, #9 80055b4: 617b str r3, [r7, #20] 80055b6: e001 b.n 80055bc } else { UsbTrd = USBD_DEFAULT_TRDT_VALUE; 80055b8: 2309 movs r3, #9 80055ba: 617b str r3, [r7, #20] } USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; 80055bc: 68fb ldr r3, [r7, #12] 80055be: 68db ldr r3, [r3, #12] 80055c0: f423 5270 bic.w r2, r3, #15360 ; 0x3c00 80055c4: 68fb ldr r3, [r7, #12] 80055c6: 60da str r2, [r3, #12] USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); 80055c8: 68fb ldr r3, [r7, #12] 80055ca: 68da ldr r2, [r3, #12] 80055cc: 697b ldr r3, [r7, #20] 80055ce: 029b lsls r3, r3, #10 80055d0: f403 5370 and.w r3, r3, #15360 ; 0x3c00 80055d4: 431a orrs r2, r3 80055d6: 68fb ldr r3, [r7, #12] 80055d8: 60da str r2, [r3, #12] return HAL_OK; 80055da: 2300 movs r3, #0 } 80055dc: 4618 mov r0, r3 80055de: 371c adds r7, #28 80055e0: 46bd mov sp, r7 80055e2: f85d 7b04 ldr.w r7, [sp], #4 80055e6: 4770 bx lr 80055e8: 00d8acbf .word 0x00d8acbf 80055ec: 00e4e1c0 .word 0x00e4e1c0 80055f0: 00f42400 .word 0x00f42400 80055f4: 01067380 .word 0x01067380 80055f8: 011a499f .word 0x011a499f 80055fc: 01312cff .word 0x01312cff 8005600: 014ca43f .word 0x014ca43f 8005604: 016e3600 .word 0x016e3600 8005608: 01a6ab1f .word 0x01a6ab1f 800560c: 01e84800 .word 0x01e84800 08005610 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8005610: b480 push {r7} 8005612: b083 sub sp, #12 8005614: af00 add r7, sp, #0 8005616: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8005618: 687b ldr r3, [r7, #4] 800561a: 689b ldr r3, [r3, #8] 800561c: f043 0201 orr.w r2, r3, #1 8005620: 687b ldr r3, [r7, #4] 8005622: 609a str r2, [r3, #8] return HAL_OK; 8005624: 2300 movs r3, #0 } 8005626: 4618 mov r0, r3 8005628: 370c adds r7, #12 800562a: 46bd mov sp, r7 800562c: f85d 7b04 ldr.w r7, [sp], #4 8005630: 4770 bx lr 08005632 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 8005632: b480 push {r7} 8005634: b083 sub sp, #12 8005636: af00 add r7, sp, #0 8005638: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 800563a: 687b ldr r3, [r7, #4] 800563c: 689b ldr r3, [r3, #8] 800563e: f023 0201 bic.w r2, r3, #1 8005642: 687b ldr r3, [r7, #4] 8005644: 609a str r2, [r3, #8] return HAL_OK; 8005646: 2300 movs r3, #0 } 8005648: 4618 mov r0, r3 800564a: 370c adds r7, #12 800564c: 46bd mov sp, r7 800564e: f85d 7b04 ldr.w r7, [sp], #4 8005652: 4770 bx lr 08005654 : * @arg USB_DEVICE_MODE Peripheral mode * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { 8005654: b580 push {r7, lr} 8005656: b084 sub sp, #16 8005658: af00 add r7, sp, #0 800565a: 6078 str r0, [r7, #4] 800565c: 460b mov r3, r1 800565e: 70fb strb r3, [r7, #3] uint32_t ms = 0U; 8005660: 2300 movs r3, #0 8005662: 60fb str r3, [r7, #12] USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 8005664: 687b ldr r3, [r7, #4] 8005666: 68db ldr r3, [r3, #12] 8005668: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000 800566c: 687b ldr r3, [r7, #4] 800566e: 60da str r2, [r3, #12] if (mode == USB_HOST_MODE) 8005670: 78fb ldrb r3, [r7, #3] 8005672: 2b01 cmp r3, #1 8005674: d115 bne.n 80056a2 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 8005676: 687b ldr r3, [r7, #4] 8005678: 68db ldr r3, [r3, #12] 800567a: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 800567e: 687b ldr r3, [r7, #4] 8005680: 60da str r2, [r3, #12] do { HAL_Delay(1U); 8005682: 2001 movs r0, #1 8005684: f7fb fe16 bl 80012b4 ms++; 8005688: 68fb ldr r3, [r7, #12] 800568a: 3301 adds r3, #1 800568c: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); 800568e: 6878 ldr r0, [r7, #4] 8005690: f001 f96c bl 800696c 8005694: 4603 mov r3, r0 8005696: 2b01 cmp r3, #1 8005698: d01e beq.n 80056d8 800569a: 68fb ldr r3, [r7, #12] 800569c: 2b31 cmp r3, #49 ; 0x31 800569e: d9f0 bls.n 8005682 80056a0: e01a b.n 80056d8 } else if (mode == USB_DEVICE_MODE) 80056a2: 78fb ldrb r3, [r7, #3] 80056a4: 2b00 cmp r3, #0 80056a6: d115 bne.n 80056d4 { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 80056a8: 687b ldr r3, [r7, #4] 80056aa: 68db ldr r3, [r3, #12] 80056ac: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 80056b0: 687b ldr r3, [r7, #4] 80056b2: 60da str r2, [r3, #12] do { HAL_Delay(1U); 80056b4: 2001 movs r0, #1 80056b6: f7fb fdfd bl 80012b4 ms++; 80056ba: 68fb ldr r3, [r7, #12] 80056bc: 3301 adds r3, #1 80056be: 60fb str r3, [r7, #12] } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); 80056c0: 6878 ldr r0, [r7, #4] 80056c2: f001 f953 bl 800696c 80056c6: 4603 mov r3, r0 80056c8: 2b00 cmp r3, #0 80056ca: d005 beq.n 80056d8 80056cc: 68fb ldr r3, [r7, #12] 80056ce: 2b31 cmp r3, #49 ; 0x31 80056d0: d9f0 bls.n 80056b4 80056d2: e001 b.n 80056d8 } else { return HAL_ERROR; 80056d4: 2301 movs r3, #1 80056d6: e005 b.n 80056e4 } if (ms == 50U) 80056d8: 68fb ldr r3, [r7, #12] 80056da: 2b32 cmp r3, #50 ; 0x32 80056dc: d101 bne.n 80056e2 { return HAL_ERROR; 80056de: 2301 movs r3, #1 80056e0: e000 b.n 80056e4 } return HAL_OK; 80056e2: 2300 movs r3, #0 } 80056e4: 4618 mov r0, r3 80056e6: 3710 adds r7, #16 80056e8: 46bd mov sp, r7 80056ea: bd80 pop {r7, pc} 080056ec : * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { 80056ec: b084 sub sp, #16 80056ee: b580 push {r7, lr} 80056f0: b086 sub sp, #24 80056f2: af00 add r7, sp, #0 80056f4: 6078 str r0, [r7, #4] 80056f6: f107 0024 add.w r0, r7, #36 ; 0x24 80056fa: e880 000e stmia.w r0, {r1, r2, r3} HAL_StatusTypeDef ret = HAL_OK; 80056fe: 2300 movs r3, #0 8005700: 75fb strb r3, [r7, #23] uint32_t USBx_BASE = (uint32_t)USBx; 8005702: 687b ldr r3, [r7, #4] 8005704: 60fb str r3, [r7, #12] uint32_t i; for (i = 0U; i < 15U; i++) 8005706: 2300 movs r3, #0 8005708: 613b str r3, [r7, #16] 800570a: e009 b.n 8005720 { USBx->DIEPTXF[i] = 0U; 800570c: 687a ldr r2, [r7, #4] 800570e: 693b ldr r3, [r7, #16] 8005710: 3340 adds r3, #64 ; 0x40 8005712: 009b lsls r3, r3, #2 8005714: 4413 add r3, r2 8005716: 2200 movs r2, #0 8005718: 605a str r2, [r3, #4] for (i = 0U; i < 15U; i++) 800571a: 693b ldr r3, [r7, #16] 800571c: 3301 adds r3, #1 800571e: 613b str r3, [r7, #16] 8005720: 693b ldr r3, [r7, #16] 8005722: 2b0e cmp r3, #14 8005724: d9f2 bls.n 800570c } #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) 8005726: 6cfb ldr r3, [r7, #76] ; 0x4c 8005728: 2b00 cmp r3, #0 800572a: d11c bne.n 8005766 { USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 800572c: 68fb ldr r3, [r7, #12] 800572e: f503 6300 add.w r3, r3, #2048 ; 0x800 8005732: 685b ldr r3, [r3, #4] 8005734: 68fa ldr r2, [r7, #12] 8005736: f502 6200 add.w r2, r2, #2048 ; 0x800 800573a: f043 0302 orr.w r3, r3, #2 800573e: 6053 str r3, [r2, #4] /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; 8005740: 687b ldr r3, [r7, #4] 8005742: 6b9b ldr r3, [r3, #56] ; 0x38 8005744: f423 1200 bic.w r2, r3, #2097152 ; 0x200000 8005748: 687b ldr r3, [r7, #4] 800574a: 639a str r2, [r3, #56] ; 0x38 /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 800574c: 687b ldr r3, [r7, #4] 800574e: 681b ldr r3, [r3, #0] 8005750: f043 0240 orr.w r2, r3, #64 ; 0x40 8005754: 687b ldr r3, [r7, #4] 8005756: 601a str r2, [r3, #0] USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 8005758: 687b ldr r3, [r7, #4] 800575a: 681b ldr r3, [r3, #0] 800575c: f043 0280 orr.w r2, r3, #128 ; 0x80 8005760: 687b ldr r3, [r7, #4] 8005762: 601a str r2, [r3, #0] 8005764: e005 b.n 8005772 } else { /* Enable HW VBUS sensing */ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 8005766: 687b ldr r3, [r7, #4] 8005768: 6b9b ldr r3, [r3, #56] ; 0x38 800576a: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 800576e: 687b ldr r3, [r7, #4] 8005770: 639a str r2, [r3, #56] ; 0x38 USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; 8005772: 68fb ldr r3, [r7, #12] 8005774: f503 6360 add.w r3, r3, #3584 ; 0xe00 8005778: 461a mov r2, r3 800577a: 2300 movs r3, #0 800577c: 6013 str r3, [r2, #0] /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; 800577e: 68fb ldr r3, [r7, #12] 8005780: f503 6300 add.w r3, r3, #2048 ; 0x800 8005784: 4619 mov r1, r3 8005786: 68fb ldr r3, [r7, #12] 8005788: f503 6300 add.w r3, r3, #2048 ; 0x800 800578c: 461a mov r2, r3 800578e: 680b ldr r3, [r1, #0] 8005790: 6013 str r3, [r2, #0] if (cfg.phy_itface == USB_OTG_ULPI_PHY) 8005792: 6bbb ldr r3, [r7, #56] ; 0x38 8005794: 2b01 cmp r3, #1 8005796: d10c bne.n 80057b2 { if (cfg.speed == USBD_HS_SPEED) 8005798: 6afb ldr r3, [r7, #44] ; 0x2c 800579a: 2b00 cmp r3, #0 800579c: d104 bne.n 80057a8 { /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); 800579e: 2100 movs r1, #0 80057a0: 6878 ldr r0, [r7, #4] 80057a2: f000 f945 bl 8005a30 80057a6: e008 b.n 80057ba } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); 80057a8: 2101 movs r1, #1 80057aa: 6878 ldr r0, [r7, #4] 80057ac: f000 f940 bl 8005a30 80057b0: e003 b.n 80057ba } } else { /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); 80057b2: 2103 movs r1, #3 80057b4: 6878 ldr r0, [r7, #4] 80057b6: f000 f93b bl 8005a30 } /* Flush the FIFOs */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 80057ba: 2110 movs r1, #16 80057bc: 6878 ldr r0, [r7, #4] 80057be: f000 f8f3 bl 80059a8 80057c2: 4603 mov r3, r0 80057c4: 2b00 cmp r3, #0 80057c6: d001 beq.n 80057cc { ret = HAL_ERROR; 80057c8: 2301 movs r3, #1 80057ca: 75fb strb r3, [r7, #23] } if (USB_FlushRxFifo(USBx) != HAL_OK) 80057cc: 6878 ldr r0, [r7, #4] 80057ce: f000 f90f bl 80059f0 80057d2: 4603 mov r3, r0 80057d4: 2b00 cmp r3, #0 80057d6: d001 beq.n 80057dc { ret = HAL_ERROR; 80057d8: 2301 movs r3, #1 80057da: 75fb strb r3, [r7, #23] } /* Clear all pending Device Interrupts */ USBx_DEVICE->DIEPMSK = 0U; 80057dc: 68fb ldr r3, [r7, #12] 80057de: f503 6300 add.w r3, r3, #2048 ; 0x800 80057e2: 461a mov r2, r3 80057e4: 2300 movs r3, #0 80057e6: 6113 str r3, [r2, #16] USBx_DEVICE->DOEPMSK = 0U; 80057e8: 68fb ldr r3, [r7, #12] 80057ea: f503 6300 add.w r3, r3, #2048 ; 0x800 80057ee: 461a mov r2, r3 80057f0: 2300 movs r3, #0 80057f2: 6153 str r3, [r2, #20] USBx_DEVICE->DAINTMSK = 0U; 80057f4: 68fb ldr r3, [r7, #12] 80057f6: f503 6300 add.w r3, r3, #2048 ; 0x800 80057fa: 461a mov r2, r3 80057fc: 2300 movs r3, #0 80057fe: 61d3 str r3, [r2, #28] for (i = 0U; i < cfg.dev_endpoints; i++) 8005800: 2300 movs r3, #0 8005802: 613b str r3, [r7, #16] 8005804: e043 b.n 800588e { if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8005806: 693b ldr r3, [r7, #16] 8005808: 015a lsls r2, r3, #5 800580a: 68fb ldr r3, [r7, #12] 800580c: 4413 add r3, r2 800580e: f503 6310 add.w r3, r3, #2304 ; 0x900 8005812: 681b ldr r3, [r3, #0] 8005814: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8005818: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 800581c: d118 bne.n 8005850 { if (i == 0U) 800581e: 693b ldr r3, [r7, #16] 8005820: 2b00 cmp r3, #0 8005822: d10a bne.n 800583a { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; 8005824: 693b ldr r3, [r7, #16] 8005826: 015a lsls r2, r3, #5 8005828: 68fb ldr r3, [r7, #12] 800582a: 4413 add r3, r2 800582c: f503 6310 add.w r3, r3, #2304 ; 0x900 8005830: 461a mov r2, r3 8005832: f04f 6300 mov.w r3, #134217728 ; 0x8000000 8005836: 6013 str r3, [r2, #0] 8005838: e013 b.n 8005862 } else { USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; 800583a: 693b ldr r3, [r7, #16] 800583c: 015a lsls r2, r3, #5 800583e: 68fb ldr r3, [r7, #12] 8005840: 4413 add r3, r2 8005842: f503 6310 add.w r3, r3, #2304 ; 0x900 8005846: 461a mov r2, r3 8005848: f04f 4390 mov.w r3, #1207959552 ; 0x48000000 800584c: 6013 str r3, [r2, #0] 800584e: e008 b.n 8005862 } } else { USBx_INEP(i)->DIEPCTL = 0U; 8005850: 693b ldr r3, [r7, #16] 8005852: 015a lsls r2, r3, #5 8005854: 68fb ldr r3, [r7, #12] 8005856: 4413 add r3, r2 8005858: f503 6310 add.w r3, r3, #2304 ; 0x900 800585c: 461a mov r2, r3 800585e: 2300 movs r3, #0 8005860: 6013 str r3, [r2, #0] } USBx_INEP(i)->DIEPTSIZ = 0U; 8005862: 693b ldr r3, [r7, #16] 8005864: 015a lsls r2, r3, #5 8005866: 68fb ldr r3, [r7, #12] 8005868: 4413 add r3, r2 800586a: f503 6310 add.w r3, r3, #2304 ; 0x900 800586e: 461a mov r2, r3 8005870: 2300 movs r3, #0 8005872: 6113 str r3, [r2, #16] USBx_INEP(i)->DIEPINT = 0xFB7FU; 8005874: 693b ldr r3, [r7, #16] 8005876: 015a lsls r2, r3, #5 8005878: 68fb ldr r3, [r7, #12] 800587a: 4413 add r3, r2 800587c: f503 6310 add.w r3, r3, #2304 ; 0x900 8005880: 461a mov r2, r3 8005882: f64f 337f movw r3, #64383 ; 0xfb7f 8005886: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 8005888: 693b ldr r3, [r7, #16] 800588a: 3301 adds r3, #1 800588c: 613b str r3, [r7, #16] 800588e: 6a7b ldr r3, [r7, #36] ; 0x24 8005890: 693a ldr r2, [r7, #16] 8005892: 429a cmp r2, r3 8005894: d3b7 bcc.n 8005806 } for (i = 0U; i < cfg.dev_endpoints; i++) 8005896: 2300 movs r3, #0 8005898: 613b str r3, [r7, #16] 800589a: e043 b.n 8005924 { if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 800589c: 693b ldr r3, [r7, #16] 800589e: 015a lsls r2, r3, #5 80058a0: 68fb ldr r3, [r7, #12] 80058a2: 4413 add r3, r2 80058a4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80058a8: 681b ldr r3, [r3, #0] 80058aa: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 80058ae: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 80058b2: d118 bne.n 80058e6 { if (i == 0U) 80058b4: 693b ldr r3, [r7, #16] 80058b6: 2b00 cmp r3, #0 80058b8: d10a bne.n 80058d0 { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; 80058ba: 693b ldr r3, [r7, #16] 80058bc: 015a lsls r2, r3, #5 80058be: 68fb ldr r3, [r7, #12] 80058c0: 4413 add r3, r2 80058c2: f503 6330 add.w r3, r3, #2816 ; 0xb00 80058c6: 461a mov r2, r3 80058c8: f04f 6300 mov.w r3, #134217728 ; 0x8000000 80058cc: 6013 str r3, [r2, #0] 80058ce: e013 b.n 80058f8 } else { USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; 80058d0: 693b ldr r3, [r7, #16] 80058d2: 015a lsls r2, r3, #5 80058d4: 68fb ldr r3, [r7, #12] 80058d6: 4413 add r3, r2 80058d8: f503 6330 add.w r3, r3, #2816 ; 0xb00 80058dc: 461a mov r2, r3 80058de: f04f 4390 mov.w r3, #1207959552 ; 0x48000000 80058e2: 6013 str r3, [r2, #0] 80058e4: e008 b.n 80058f8 } } else { USBx_OUTEP(i)->DOEPCTL = 0U; 80058e6: 693b ldr r3, [r7, #16] 80058e8: 015a lsls r2, r3, #5 80058ea: 68fb ldr r3, [r7, #12] 80058ec: 4413 add r3, r2 80058ee: f503 6330 add.w r3, r3, #2816 ; 0xb00 80058f2: 461a mov r2, r3 80058f4: 2300 movs r3, #0 80058f6: 6013 str r3, [r2, #0] } USBx_OUTEP(i)->DOEPTSIZ = 0U; 80058f8: 693b ldr r3, [r7, #16] 80058fa: 015a lsls r2, r3, #5 80058fc: 68fb ldr r3, [r7, #12] 80058fe: 4413 add r3, r2 8005900: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005904: 461a mov r2, r3 8005906: 2300 movs r3, #0 8005908: 6113 str r3, [r2, #16] USBx_OUTEP(i)->DOEPINT = 0xFB7FU; 800590a: 693b ldr r3, [r7, #16] 800590c: 015a lsls r2, r3, #5 800590e: 68fb ldr r3, [r7, #12] 8005910: 4413 add r3, r2 8005912: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005916: 461a mov r2, r3 8005918: f64f 337f movw r3, #64383 ; 0xfb7f 800591c: 6093 str r3, [r2, #8] for (i = 0U; i < cfg.dev_endpoints; i++) 800591e: 693b ldr r3, [r7, #16] 8005920: 3301 adds r3, #1 8005922: 613b str r3, [r7, #16] 8005924: 6a7b ldr r3, [r7, #36] ; 0x24 8005926: 693a ldr r2, [r7, #16] 8005928: 429a cmp r2, r3 800592a: d3b7 bcc.n 800589c } USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 800592c: 68fb ldr r3, [r7, #12] 800592e: f503 6300 add.w r3, r3, #2048 ; 0x800 8005932: 691b ldr r3, [r3, #16] 8005934: 68fa ldr r2, [r7, #12] 8005936: f502 6200 add.w r2, r2, #2048 ; 0x800 800593a: f423 7380 bic.w r3, r3, #256 ; 0x100 800593e: 6113 str r3, [r2, #16] /* Disable all interrupts. */ USBx->GINTMSK = 0U; 8005940: 687b ldr r3, [r7, #4] 8005942: 2200 movs r2, #0 8005944: 619a str r2, [r3, #24] /* Clear any pending interrupts */ USBx->GINTSTS = 0xBFFFFFFFU; 8005946: 687b ldr r3, [r7, #4] 8005948: f06f 4280 mvn.w r2, #1073741824 ; 0x40000000 800594c: 615a str r2, [r3, #20] /* Enable the common interrupts */ if (cfg.dma_enable == 0U) 800594e: 6b3b ldr r3, [r7, #48] ; 0x30 8005950: 2b00 cmp r3, #0 8005952: d105 bne.n 8005960 { USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 8005954: 687b ldr r3, [r7, #4] 8005956: 699b ldr r3, [r3, #24] 8005958: f043 0210 orr.w r2, r3, #16 800595c: 687b ldr r3, [r7, #4] 800595e: 619a str r2, [r3, #24] } /* Enable interrupts matching to the Device mode ONLY */ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | 8005960: 687b ldr r3, [r7, #4] 8005962: 699a ldr r2, [r3, #24] 8005964: 4b0f ldr r3, [pc, #60] ; (80059a4 ) 8005966: 4313 orrs r3, r2 8005968: 687a ldr r2, [r7, #4] 800596a: 6193 str r3, [r2, #24] USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; if (cfg.Sof_enable != 0U) 800596c: 6bfb ldr r3, [r7, #60] ; 0x3c 800596e: 2b00 cmp r3, #0 8005970: d005 beq.n 800597e { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 8005972: 687b ldr r3, [r7, #4] 8005974: 699b ldr r3, [r3, #24] 8005976: f043 0208 orr.w r2, r3, #8 800597a: 687b ldr r3, [r7, #4] 800597c: 619a str r2, [r3, #24] } if (cfg.vbus_sensing_enable == 1U) 800597e: 6cfb ldr r3, [r7, #76] ; 0x4c 8005980: 2b01 cmp r3, #1 8005982: d107 bne.n 8005994 { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 8005984: 687b ldr r3, [r7, #4] 8005986: 699b ldr r3, [r3, #24] 8005988: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 800598c: f043 0304 orr.w r3, r3, #4 8005990: 687a ldr r2, [r7, #4] 8005992: 6193 str r3, [r2, #24] } return ret; 8005994: 7dfb ldrb r3, [r7, #23] } 8005996: 4618 mov r0, r3 8005998: 3718 adds r7, #24 800599a: 46bd mov sp, r7 800599c: e8bd 4080 ldmia.w sp!, {r7, lr} 80059a0: b004 add sp, #16 80059a2: 4770 bx lr 80059a4: 803c3800 .word 0x803c3800 080059a8 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 80059a8: b480 push {r7} 80059aa: b085 sub sp, #20 80059ac: af00 add r7, sp, #0 80059ae: 6078 str r0, [r7, #4] 80059b0: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 80059b2: 2300 movs r3, #0 80059b4: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 80059b6: 683b ldr r3, [r7, #0] 80059b8: 019b lsls r3, r3, #6 80059ba: f043 0220 orr.w r2, r3, #32 80059be: 687b ldr r3, [r7, #4] 80059c0: 611a str r2, [r3, #16] do { if (++count > 200000U) 80059c2: 68fb ldr r3, [r7, #12] 80059c4: 3301 adds r3, #1 80059c6: 60fb str r3, [r7, #12] 80059c8: 4a08 ldr r2, [pc, #32] ; (80059ec ) 80059ca: 4293 cmp r3, r2 80059cc: d901 bls.n 80059d2 { return HAL_TIMEOUT; 80059ce: 2303 movs r3, #3 80059d0: e006 b.n 80059e0 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 80059d2: 687b ldr r3, [r7, #4] 80059d4: 691b ldr r3, [r3, #16] 80059d6: f003 0320 and.w r3, r3, #32 80059da: 2b20 cmp r3, #32 80059dc: d0f1 beq.n 80059c2 return HAL_OK; 80059de: 2300 movs r3, #0 } 80059e0: 4618 mov r0, r3 80059e2: 3714 adds r7, #20 80059e4: 46bd mov sp, r7 80059e6: f85d 7b04 ldr.w r7, [sp], #4 80059ea: 4770 bx lr 80059ec: 00030d40 .word 0x00030d40 080059f0 : * @brief USB_FlushRxFifo : Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 80059f0: b480 push {r7} 80059f2: b085 sub sp, #20 80059f4: af00 add r7, sp, #0 80059f6: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80059f8: 2300 movs r3, #0 80059fa: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 80059fc: 687b ldr r3, [r7, #4] 80059fe: 2210 movs r2, #16 8005a00: 611a str r2, [r3, #16] do { if (++count > 200000U) 8005a02: 68fb ldr r3, [r7, #12] 8005a04: 3301 adds r3, #1 8005a06: 60fb str r3, [r7, #12] 8005a08: 4a08 ldr r2, [pc, #32] ; (8005a2c ) 8005a0a: 4293 cmp r3, r2 8005a0c: d901 bls.n 8005a12 { return HAL_TIMEOUT; 8005a0e: 2303 movs r3, #3 8005a10: e006 b.n 8005a20 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 8005a12: 687b ldr r3, [r7, #4] 8005a14: 691b ldr r3, [r3, #16] 8005a16: f003 0310 and.w r3, r3, #16 8005a1a: 2b10 cmp r3, #16 8005a1c: d0f1 beq.n 8005a02 return HAL_OK; 8005a1e: 2300 movs r3, #0 } 8005a20: 4618 mov r0, r3 8005a22: 3714 adds r7, #20 8005a24: 46bd mov sp, r7 8005a26: f85d 7b04 ldr.w r7, [sp], #4 8005a2a: 4770 bx lr 8005a2c: 00030d40 .word 0x00030d40 08005a30 : * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { 8005a30: b480 push {r7} 8005a32: b085 sub sp, #20 8005a34: af00 add r7, sp, #0 8005a36: 6078 str r0, [r7, #4] 8005a38: 460b mov r3, r1 8005a3a: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG |= speed; 8005a40: 68fb ldr r3, [r7, #12] 8005a42: f503 6300 add.w r3, r3, #2048 ; 0x800 8005a46: 681a ldr r2, [r3, #0] 8005a48: 78fb ldrb r3, [r7, #3] 8005a4a: 68f9 ldr r1, [r7, #12] 8005a4c: f501 6100 add.w r1, r1, #2048 ; 0x800 8005a50: 4313 orrs r3, r2 8005a52: 600b str r3, [r1, #0] return HAL_OK; 8005a54: 2300 movs r3, #0 } 8005a56: 4618 mov r0, r3 8005a58: 3714 adds r7, #20 8005a5a: 46bd mov sp, r7 8005a5c: f85d 7b04 ldr.w r7, [sp], #4 8005a60: 4770 bx lr 08005a62 : * This parameter can be one of these values: * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { 8005a62: b480 push {r7} 8005a64: b087 sub sp, #28 8005a66: af00 add r7, sp, #0 8005a68: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8005a6a: 687b ldr r3, [r7, #4] 8005a6c: 613b str r3, [r7, #16] uint8_t speed; uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; 8005a6e: 693b ldr r3, [r7, #16] 8005a70: f503 6300 add.w r3, r3, #2048 ; 0x800 8005a74: 689b ldr r3, [r3, #8] 8005a76: f003 0306 and.w r3, r3, #6 8005a7a: 60fb str r3, [r7, #12] if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 8005a7c: 68fb ldr r3, [r7, #12] 8005a7e: 2b00 cmp r3, #0 8005a80: d102 bne.n 8005a88 { speed = USBD_HS_SPEED; 8005a82: 2300 movs r3, #0 8005a84: 75fb strb r3, [r7, #23] 8005a86: e00a b.n 8005a9e } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || 8005a88: 68fb ldr r3, [r7, #12] 8005a8a: 2b02 cmp r3, #2 8005a8c: d002 beq.n 8005a94 8005a8e: 68fb ldr r3, [r7, #12] 8005a90: 2b06 cmp r3, #6 8005a92: d102 bne.n 8005a9a (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { speed = USBD_FS_SPEED; 8005a94: 2302 movs r3, #2 8005a96: 75fb strb r3, [r7, #23] 8005a98: e001 b.n 8005a9e } else { speed = 0xFU; 8005a9a: 230f movs r3, #15 8005a9c: 75fb strb r3, [r7, #23] } return speed; 8005a9e: 7dfb ldrb r3, [r7, #23] } 8005aa0: 4618 mov r0, r3 8005aa2: 371c adds r7, #28 8005aa4: 46bd mov sp, r7 8005aa6: f85d 7b04 ldr.w r7, [sp], #4 8005aaa: 4770 bx lr 08005aac : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8005aac: b480 push {r7} 8005aae: b085 sub sp, #20 8005ab0: af00 add r7, sp, #0 8005ab2: 6078 str r0, [r7, #4] 8005ab4: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8005ab6: 687b ldr r3, [r7, #4] 8005ab8: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8005aba: 683b ldr r3, [r7, #0] 8005abc: 781b ldrb r3, [r3, #0] 8005abe: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 8005ac0: 683b ldr r3, [r7, #0] 8005ac2: 785b ldrb r3, [r3, #1] 8005ac4: 2b01 cmp r3, #1 8005ac6: d13a bne.n 8005b3e { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); 8005ac8: 68fb ldr r3, [r7, #12] 8005aca: f503 6300 add.w r3, r3, #2048 ; 0x800 8005ace: 69da ldr r2, [r3, #28] 8005ad0: 683b ldr r3, [r7, #0] 8005ad2: 781b ldrb r3, [r3, #0] 8005ad4: f003 030f and.w r3, r3, #15 8005ad8: 2101 movs r1, #1 8005ada: fa01 f303 lsl.w r3, r1, r3 8005ade: b29b uxth r3, r3 8005ae0: 68f9 ldr r1, [r7, #12] 8005ae2: f501 6100 add.w r1, r1, #2048 ; 0x800 8005ae6: 4313 orrs r3, r2 8005ae8: 61cb str r3, [r1, #28] if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) 8005aea: 68bb ldr r3, [r7, #8] 8005aec: 015a lsls r2, r3, #5 8005aee: 68fb ldr r3, [r7, #12] 8005af0: 4413 add r3, r2 8005af2: f503 6310 add.w r3, r3, #2304 ; 0x900 8005af6: 681b ldr r3, [r3, #0] 8005af8: f403 4300 and.w r3, r3, #32768 ; 0x8000 8005afc: 2b00 cmp r3, #0 8005afe: d155 bne.n 8005bac { USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8005b00: 68bb ldr r3, [r7, #8] 8005b02: 015a lsls r2, r3, #5 8005b04: 68fb ldr r3, [r7, #12] 8005b06: 4413 add r3, r2 8005b08: f503 6310 add.w r3, r3, #2304 ; 0x900 8005b0c: 681a ldr r2, [r3, #0] 8005b0e: 683b ldr r3, [r7, #0] 8005b10: 689b ldr r3, [r3, #8] 8005b12: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | (epnum << 22) | 8005b16: 683b ldr r3, [r7, #0] 8005b18: 78db ldrb r3, [r3, #3] 8005b1a: 049b lsls r3, r3, #18 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8005b1c: 4319 orrs r1, r3 ((uint32_t)ep->type << 18) | (epnum << 22) | 8005b1e: 68bb ldr r3, [r7, #8] 8005b20: 059b lsls r3, r3, #22 8005b22: 430b orrs r3, r1 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | 8005b24: 4313 orrs r3, r2 8005b26: 68ba ldr r2, [r7, #8] 8005b28: 0151 lsls r1, r2, #5 8005b2a: 68fa ldr r2, [r7, #12] 8005b2c: 440a add r2, r1 8005b2e: f502 6210 add.w r2, r2, #2304 ; 0x900 8005b32: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005b36: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8005b3a: 6013 str r3, [r2, #0] 8005b3c: e036 b.n 8005bac USB_OTG_DIEPCTL_USBAEP; } } else { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); 8005b3e: 68fb ldr r3, [r7, #12] 8005b40: f503 6300 add.w r3, r3, #2048 ; 0x800 8005b44: 69da ldr r2, [r3, #28] 8005b46: 683b ldr r3, [r7, #0] 8005b48: 781b ldrb r3, [r3, #0] 8005b4a: f003 030f and.w r3, r3, #15 8005b4e: 2101 movs r1, #1 8005b50: fa01 f303 lsl.w r3, r1, r3 8005b54: 041b lsls r3, r3, #16 8005b56: 68f9 ldr r1, [r7, #12] 8005b58: f501 6100 add.w r1, r1, #2048 ; 0x800 8005b5c: 4313 orrs r3, r2 8005b5e: 61cb str r3, [r1, #28] if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) 8005b60: 68bb ldr r3, [r7, #8] 8005b62: 015a lsls r2, r3, #5 8005b64: 68fb ldr r3, [r7, #12] 8005b66: 4413 add r3, r2 8005b68: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005b6c: 681b ldr r3, [r3, #0] 8005b6e: f403 4300 and.w r3, r3, #32768 ; 0x8000 8005b72: 2b00 cmp r3, #0 8005b74: d11a bne.n 8005bac { USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 8005b76: 68bb ldr r3, [r7, #8] 8005b78: 015a lsls r2, r3, #5 8005b7a: 68fb ldr r3, [r7, #12] 8005b7c: 4413 add r3, r2 8005b7e: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005b82: 681a ldr r2, [r3, #0] 8005b84: 683b ldr r3, [r7, #0] 8005b86: 689b ldr r3, [r3, #8] 8005b88: f3c3 010a ubfx r1, r3, #0, #11 ((uint32_t)ep->type << 18) | 8005b8c: 683b ldr r3, [r7, #0] 8005b8e: 78db ldrb r3, [r3, #3] 8005b90: 049b lsls r3, r3, #18 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | 8005b92: 430b orrs r3, r1 8005b94: 4313 orrs r3, r2 8005b96: 68ba ldr r2, [r7, #8] 8005b98: 0151 lsls r1, r2, #5 8005b9a: 68fa ldr r2, [r7, #12] 8005b9c: 440a add r2, r1 8005b9e: f502 6230 add.w r2, r2, #2816 ; 0xb00 8005ba2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005ba6: f443 4300 orr.w r3, r3, #32768 ; 0x8000 8005baa: 6013 str r3, [r2, #0] USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_USBAEP; } } return HAL_OK; 8005bac: 2300 movs r3, #0 } 8005bae: 4618 mov r0, r3 8005bb0: 3714 adds r7, #20 8005bb2: 46bd mov sp, r7 8005bb4: f85d 7b04 ldr.w r7, [sp], #4 8005bb8: 4770 bx lr ... 08005bbc : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 8005bbc: b480 push {r7} 8005bbe: b085 sub sp, #20 8005bc0: af00 add r7, sp, #0 8005bc2: 6078 str r0, [r7, #4] 8005bc4: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 8005bc6: 687b ldr r3, [r7, #4] 8005bc8: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 8005bca: 683b ldr r3, [r7, #0] 8005bcc: 781b ldrb r3, [r3, #0] 8005bce: 60bb str r3, [r7, #8] /* Read DEPCTLn register */ if (ep->is_in == 1U) 8005bd0: 683b ldr r3, [r7, #0] 8005bd2: 785b ldrb r3, [r3, #1] 8005bd4: 2b01 cmp r3, #1 8005bd6: d161 bne.n 8005c9c { if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 8005bd8: 68bb ldr r3, [r7, #8] 8005bda: 015a lsls r2, r3, #5 8005bdc: 68fb ldr r3, [r7, #12] 8005bde: 4413 add r3, r2 8005be0: f503 6310 add.w r3, r3, #2304 ; 0x900 8005be4: 681b ldr r3, [r3, #0] 8005be6: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8005bea: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8005bee: d11f bne.n 8005c30 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; 8005bf0: 68bb ldr r3, [r7, #8] 8005bf2: 015a lsls r2, r3, #5 8005bf4: 68fb ldr r3, [r7, #12] 8005bf6: 4413 add r3, r2 8005bf8: f503 6310 add.w r3, r3, #2304 ; 0x900 8005bfc: 681b ldr r3, [r3, #0] 8005bfe: 68ba ldr r2, [r7, #8] 8005c00: 0151 lsls r1, r2, #5 8005c02: 68fa ldr r2, [r7, #12] 8005c04: 440a add r2, r1 8005c06: f502 6210 add.w r2, r2, #2304 ; 0x900 8005c0a: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8005c0e: 6013 str r3, [r2, #0] USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; 8005c10: 68bb ldr r3, [r7, #8] 8005c12: 015a lsls r2, r3, #5 8005c14: 68fb ldr r3, [r7, #12] 8005c16: 4413 add r3, r2 8005c18: f503 6310 add.w r3, r3, #2304 ; 0x900 8005c1c: 681b ldr r3, [r3, #0] 8005c1e: 68ba ldr r2, [r7, #8] 8005c20: 0151 lsls r1, r2, #5 8005c22: 68fa ldr r2, [r7, #12] 8005c24: 440a add r2, r1 8005c26: f502 6210 add.w r2, r2, #2304 ; 0x900 8005c2a: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8005c2e: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8005c30: 68fb ldr r3, [r7, #12] 8005c32: f503 6300 add.w r3, r3, #2048 ; 0x800 8005c36: 6bda ldr r2, [r3, #60] ; 0x3c 8005c38: 683b ldr r3, [r7, #0] 8005c3a: 781b ldrb r3, [r3, #0] 8005c3c: f003 030f and.w r3, r3, #15 8005c40: 2101 movs r1, #1 8005c42: fa01 f303 lsl.w r3, r1, r3 8005c46: b29b uxth r3, r3 8005c48: 43db mvns r3, r3 8005c4a: 68f9 ldr r1, [r7, #12] 8005c4c: f501 6100 add.w r1, r1, #2048 ; 0x800 8005c50: 4013 ands r3, r2 8005c52: 63cb str r3, [r1, #60] ; 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); 8005c54: 68fb ldr r3, [r7, #12] 8005c56: f503 6300 add.w r3, r3, #2048 ; 0x800 8005c5a: 69da ldr r2, [r3, #28] 8005c5c: 683b ldr r3, [r7, #0] 8005c5e: 781b ldrb r3, [r3, #0] 8005c60: f003 030f and.w r3, r3, #15 8005c64: 2101 movs r1, #1 8005c66: fa01 f303 lsl.w r3, r1, r3 8005c6a: b29b uxth r3, r3 8005c6c: 43db mvns r3, r3 8005c6e: 68f9 ldr r1, [r7, #12] 8005c70: f501 6100 add.w r1, r1, #2048 ; 0x800 8005c74: 4013 ands r3, r2 8005c76: 61cb str r3, [r1, #28] USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | 8005c78: 68bb ldr r3, [r7, #8] 8005c7a: 015a lsls r2, r3, #5 8005c7c: 68fb ldr r3, [r7, #12] 8005c7e: 4413 add r3, r2 8005c80: f503 6310 add.w r3, r3, #2304 ; 0x900 8005c84: 681a ldr r2, [r3, #0] 8005c86: 68bb ldr r3, [r7, #8] 8005c88: 0159 lsls r1, r3, #5 8005c8a: 68fb ldr r3, [r7, #12] 8005c8c: 440b add r3, r1 8005c8e: f503 6310 add.w r3, r3, #2304 ; 0x900 8005c92: 4619 mov r1, r3 8005c94: 4b35 ldr r3, [pc, #212] ; (8005d6c ) 8005c96: 4013 ands r3, r2 8005c98: 600b str r3, [r1, #0] 8005c9a: e060 b.n 8005d5e USB_OTG_DIEPCTL_SD0PID_SEVNFRM | USB_OTG_DIEPCTL_EPTYP); } else { if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 8005c9c: 68bb ldr r3, [r7, #8] 8005c9e: 015a lsls r2, r3, #5 8005ca0: 68fb ldr r3, [r7, #12] 8005ca2: 4413 add r3, r2 8005ca4: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005ca8: 681b ldr r3, [r3, #0] 8005caa: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8005cae: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8005cb2: d11f bne.n 8005cf4 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; 8005cb4: 68bb ldr r3, [r7, #8] 8005cb6: 015a lsls r2, r3, #5 8005cb8: 68fb ldr r3, [r7, #12] 8005cba: 4413 add r3, r2 8005cbc: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005cc0: 681b ldr r3, [r3, #0] 8005cc2: 68ba ldr r2, [r7, #8] 8005cc4: 0151 lsls r1, r2, #5 8005cc6: 68fa ldr r2, [r7, #12] 8005cc8: 440a add r2, r1 8005cca: f502 6230 add.w r2, r2, #2816 ; 0xb00 8005cce: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 8005cd2: 6013 str r3, [r2, #0] USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; 8005cd4: 68bb ldr r3, [r7, #8] 8005cd6: 015a lsls r2, r3, #5 8005cd8: 68fb ldr r3, [r7, #12] 8005cda: 4413 add r3, r2 8005cdc: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005ce0: 681b ldr r3, [r3, #0] 8005ce2: 68ba ldr r2, [r7, #8] 8005ce4: 0151 lsls r1, r2, #5 8005ce6: 68fa ldr r2, [r7, #12] 8005ce8: 440a add r2, r1 8005cea: f502 6230 add.w r2, r2, #2816 ; 0xb00 8005cee: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8005cf2: 6013 str r3, [r2, #0] } USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8005cf4: 68fb ldr r3, [r7, #12] 8005cf6: f503 6300 add.w r3, r3, #2048 ; 0x800 8005cfa: 6bda ldr r2, [r3, #60] ; 0x3c 8005cfc: 683b ldr r3, [r7, #0] 8005cfe: 781b ldrb r3, [r3, #0] 8005d00: f003 030f and.w r3, r3, #15 8005d04: 2101 movs r1, #1 8005d06: fa01 f303 lsl.w r3, r1, r3 8005d0a: 041b lsls r3, r3, #16 8005d0c: 43db mvns r3, r3 8005d0e: 68f9 ldr r1, [r7, #12] 8005d10: f501 6100 add.w r1, r1, #2048 ; 0x800 8005d14: 4013 ands r3, r2 8005d16: 63cb str r3, [r1, #60] ; 0x3c USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); 8005d18: 68fb ldr r3, [r7, #12] 8005d1a: f503 6300 add.w r3, r3, #2048 ; 0x800 8005d1e: 69da ldr r2, [r3, #28] 8005d20: 683b ldr r3, [r7, #0] 8005d22: 781b ldrb r3, [r3, #0] 8005d24: f003 030f and.w r3, r3, #15 8005d28: 2101 movs r1, #1 8005d2a: fa01 f303 lsl.w r3, r1, r3 8005d2e: 041b lsls r3, r3, #16 8005d30: 43db mvns r3, r3 8005d32: 68f9 ldr r1, [r7, #12] 8005d34: f501 6100 add.w r1, r1, #2048 ; 0x800 8005d38: 4013 ands r3, r2 8005d3a: 61cb str r3, [r1, #28] USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | 8005d3c: 68bb ldr r3, [r7, #8] 8005d3e: 015a lsls r2, r3, #5 8005d40: 68fb ldr r3, [r7, #12] 8005d42: 4413 add r3, r2 8005d44: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005d48: 681a ldr r2, [r3, #0] 8005d4a: 68bb ldr r3, [r7, #8] 8005d4c: 0159 lsls r1, r3, #5 8005d4e: 68fb ldr r3, [r7, #12] 8005d50: 440b add r3, r1 8005d52: f503 6330 add.w r3, r3, #2816 ; 0xb00 8005d56: 4619 mov r1, r3 8005d58: 4b05 ldr r3, [pc, #20] ; (8005d70 ) 8005d5a: 4013 ands r3, r2 8005d5c: 600b str r3, [r1, #0] USB_OTG_DOEPCTL_MPSIZ | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | USB_OTG_DOEPCTL_EPTYP); } return HAL_OK; 8005d5e: 2300 movs r3, #0 } 8005d60: 4618 mov r0, r3 8005d62: 3714 adds r7, #20 8005d64: 46bd mov sp, r7 8005d66: f85d 7b04 ldr.w r7, [sp], #4 8005d6a: 4770 bx lr 8005d6c: ec337800 .word 0xec337800 8005d70: eff37800 .word 0xeff37800 08005d74 : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 8005d74: b580 push {r7, lr} 8005d76: b08a sub sp, #40 ; 0x28 8005d78: af02 add r7, sp, #8 8005d7a: 60f8 str r0, [r7, #12] 8005d7c: 60b9 str r1, [r7, #8] 8005d7e: 4613 mov r3, r2 8005d80: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 8005d82: 68fb ldr r3, [r7, #12] 8005d84: 61fb str r3, [r7, #28] uint32_t epnum = (uint32_t)ep->num; 8005d86: 68bb ldr r3, [r7, #8] 8005d88: 781b ldrb r3, [r3, #0] 8005d8a: 61bb str r3, [r7, #24] uint16_t pktcnt; /* IN endpoint */ if (ep->is_in == 1U) 8005d8c: 68bb ldr r3, [r7, #8] 8005d8e: 785b ldrb r3, [r3, #1] 8005d90: 2b01 cmp r3, #1 8005d92: f040 815c bne.w 800604e { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 8005d96: 68bb ldr r3, [r7, #8] 8005d98: 695b ldr r3, [r3, #20] 8005d9a: 2b00 cmp r3, #0 8005d9c: d132 bne.n 8005e04 { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8005d9e: 69bb ldr r3, [r7, #24] 8005da0: 015a lsls r2, r3, #5 8005da2: 69fb ldr r3, [r7, #28] 8005da4: 4413 add r3, r2 8005da6: f503 6310 add.w r3, r3, #2304 ; 0x900 8005daa: 691b ldr r3, [r3, #16] 8005dac: 69ba ldr r2, [r7, #24] 8005dae: 0151 lsls r1, r2, #5 8005db0: 69fa ldr r2, [r7, #28] 8005db2: 440a add r2, r1 8005db4: f502 6210 add.w r2, r2, #2304 ; 0x900 8005db8: f023 53ff bic.w r3, r3, #534773760 ; 0x1fe00000 8005dbc: f423 13c0 bic.w r3, r3, #1572864 ; 0x180000 8005dc0: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 8005dc2: 69bb ldr r3, [r7, #24] 8005dc4: 015a lsls r2, r3, #5 8005dc6: 69fb ldr r3, [r7, #28] 8005dc8: 4413 add r3, r2 8005dca: f503 6310 add.w r3, r3, #2304 ; 0x900 8005dce: 691b ldr r3, [r3, #16] 8005dd0: 69ba ldr r2, [r7, #24] 8005dd2: 0151 lsls r1, r2, #5 8005dd4: 69fa ldr r2, [r7, #28] 8005dd6: 440a add r2, r1 8005dd8: f502 6210 add.w r2, r2, #2304 ; 0x900 8005ddc: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8005de0: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8005de2: 69bb ldr r3, [r7, #24] 8005de4: 015a lsls r2, r3, #5 8005de6: 69fb ldr r3, [r7, #28] 8005de8: 4413 add r3, r2 8005dea: f503 6310 add.w r3, r3, #2304 ; 0x900 8005dee: 691b ldr r3, [r3, #16] 8005df0: 69ba ldr r2, [r7, #24] 8005df2: 0151 lsls r1, r2, #5 8005df4: 69fa ldr r2, [r7, #28] 8005df6: 440a add r2, r1 8005df8: f502 6210 add.w r2, r2, #2304 ; 0x900 8005dfc: 0cdb lsrs r3, r3, #19 8005dfe: 04db lsls r3, r3, #19 8005e00: 6113 str r3, [r2, #16] 8005e02: e074 b.n 8005eee /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 8005e04: 69bb ldr r3, [r7, #24] 8005e06: 015a lsls r2, r3, #5 8005e08: 69fb ldr r3, [r7, #28] 8005e0a: 4413 add r3, r2 8005e0c: f503 6310 add.w r3, r3, #2304 ; 0x900 8005e10: 691b ldr r3, [r3, #16] 8005e12: 69ba ldr r2, [r7, #24] 8005e14: 0151 lsls r1, r2, #5 8005e16: 69fa ldr r2, [r7, #28] 8005e18: 440a add r2, r1 8005e1a: f502 6210 add.w r2, r2, #2304 ; 0x900 8005e1e: 0cdb lsrs r3, r3, #19 8005e20: 04db lsls r3, r3, #19 8005e22: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8005e24: 69bb ldr r3, [r7, #24] 8005e26: 015a lsls r2, r3, #5 8005e28: 69fb ldr r3, [r7, #28] 8005e2a: 4413 add r3, r2 8005e2c: f503 6310 add.w r3, r3, #2304 ; 0x900 8005e30: 691b ldr r3, [r3, #16] 8005e32: 69ba ldr r2, [r7, #24] 8005e34: 0151 lsls r1, r2, #5 8005e36: 69fa ldr r2, [r7, #28] 8005e38: 440a add r2, r1 8005e3a: f502 6210 add.w r2, r2, #2304 ; 0x900 8005e3e: f023 53ff bic.w r3, r3, #534773760 ; 0x1fe00000 8005e42: f423 13c0 bic.w r3, r3, #1572864 ; 0x180000 8005e46: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & 8005e48: 69bb ldr r3, [r7, #24] 8005e4a: 015a lsls r2, r3, #5 8005e4c: 69fb ldr r3, [r7, #28] 8005e4e: 4413 add r3, r2 8005e50: f503 6310 add.w r3, r3, #2304 ; 0x900 8005e54: 691a ldr r2, [r3, #16] (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); 8005e56: 68bb ldr r3, [r7, #8] 8005e58: 6959 ldr r1, [r3, #20] 8005e5a: 68bb ldr r3, [r7, #8] 8005e5c: 689b ldr r3, [r3, #8] 8005e5e: 440b add r3, r1 8005e60: 1e59 subs r1, r3, #1 8005e62: 68bb ldr r3, [r7, #8] 8005e64: 689b ldr r3, [r3, #8] 8005e66: fbb1 f3f3 udiv r3, r1, r3 8005e6a: 04d9 lsls r1, r3, #19 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & 8005e6c: 4b9d ldr r3, [pc, #628] ; (80060e4 ) 8005e6e: 400b ands r3, r1 8005e70: 69b9 ldr r1, [r7, #24] 8005e72: 0148 lsls r0, r1, #5 8005e74: 69f9 ldr r1, [r7, #28] 8005e76: 4401 add r1, r0 8005e78: f501 6110 add.w r1, r1, #2304 ; 0x900 8005e7c: 4313 orrs r3, r2 8005e7e: 610b str r3, [r1, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8005e80: 69bb ldr r3, [r7, #24] 8005e82: 015a lsls r2, r3, #5 8005e84: 69fb ldr r3, [r7, #28] 8005e86: 4413 add r3, r2 8005e88: f503 6310 add.w r3, r3, #2304 ; 0x900 8005e8c: 691a ldr r2, [r3, #16] 8005e8e: 68bb ldr r3, [r7, #8] 8005e90: 695b ldr r3, [r3, #20] 8005e92: f3c3 0312 ubfx r3, r3, #0, #19 8005e96: 69b9 ldr r1, [r7, #24] 8005e98: 0148 lsls r0, r1, #5 8005e9a: 69f9 ldr r1, [r7, #28] 8005e9c: 4401 add r1, r0 8005e9e: f501 6110 add.w r1, r1, #2304 ; 0x900 8005ea2: 4313 orrs r3, r2 8005ea4: 610b str r3, [r1, #16] if (ep->type == EP_TYPE_ISOC) 8005ea6: 68bb ldr r3, [r7, #8] 8005ea8: 78db ldrb r3, [r3, #3] 8005eaa: 2b01 cmp r3, #1 8005eac: d11f bne.n 8005eee { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 8005eae: 69bb ldr r3, [r7, #24] 8005eb0: 015a lsls r2, r3, #5 8005eb2: 69fb ldr r3, [r7, #28] 8005eb4: 4413 add r3, r2 8005eb6: f503 6310 add.w r3, r3, #2304 ; 0x900 8005eba: 691b ldr r3, [r3, #16] 8005ebc: 69ba ldr r2, [r7, #24] 8005ebe: 0151 lsls r1, r2, #5 8005ec0: 69fa ldr r2, [r7, #28] 8005ec2: 440a add r2, r1 8005ec4: f502 6210 add.w r2, r2, #2304 ; 0x900 8005ec8: f023 43c0 bic.w r3, r3, #1610612736 ; 0x60000000 8005ecc: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); 8005ece: 69bb ldr r3, [r7, #24] 8005ed0: 015a lsls r2, r3, #5 8005ed2: 69fb ldr r3, [r7, #28] 8005ed4: 4413 add r3, r2 8005ed6: f503 6310 add.w r3, r3, #2304 ; 0x900 8005eda: 691b ldr r3, [r3, #16] 8005edc: 69ba ldr r2, [r7, #24] 8005ede: 0151 lsls r1, r2, #5 8005ee0: 69fa ldr r2, [r7, #28] 8005ee2: 440a add r2, r1 8005ee4: f502 6210 add.w r2, r2, #2304 ; 0x900 8005ee8: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8005eec: 6113 str r3, [r2, #16] } } if (dma == 1U) 8005eee: 79fb ldrb r3, [r7, #7] 8005ef0: 2b01 cmp r3, #1 8005ef2: d14b bne.n 8005f8c { if ((uint32_t)ep->dma_addr != 0U) 8005ef4: 68bb ldr r3, [r7, #8] 8005ef6: 691b ldr r3, [r3, #16] 8005ef8: 2b00 cmp r3, #0 8005efa: d009 beq.n 8005f10 { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8005efc: 69bb ldr r3, [r7, #24] 8005efe: 015a lsls r2, r3, #5 8005f00: 69fb ldr r3, [r7, #28] 8005f02: 4413 add r3, r2 8005f04: f503 6310 add.w r3, r3, #2304 ; 0x900 8005f08: 461a mov r2, r3 8005f0a: 68bb ldr r3, [r7, #8] 8005f0c: 691b ldr r3, [r3, #16] 8005f0e: 6153 str r3, [r2, #20] } if (ep->type == EP_TYPE_ISOC) 8005f10: 68bb ldr r3, [r7, #8] 8005f12: 78db ldrb r3, [r3, #3] 8005f14: 2b01 cmp r3, #1 8005f16: d128 bne.n 8005f6a { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8005f18: 69fb ldr r3, [r7, #28] 8005f1a: f503 6300 add.w r3, r3, #2048 ; 0x800 8005f1e: 689b ldr r3, [r3, #8] 8005f20: f403 7380 and.w r3, r3, #256 ; 0x100 8005f24: 2b00 cmp r3, #0 8005f26: d110 bne.n 8005f4a { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8005f28: 69bb ldr r3, [r7, #24] 8005f2a: 015a lsls r2, r3, #5 8005f2c: 69fb ldr r3, [r7, #28] 8005f2e: 4413 add r3, r2 8005f30: f503 6310 add.w r3, r3, #2304 ; 0x900 8005f34: 681b ldr r3, [r3, #0] 8005f36: 69ba ldr r2, [r7, #24] 8005f38: 0151 lsls r1, r2, #5 8005f3a: 69fa ldr r2, [r7, #28] 8005f3c: 440a add r2, r1 8005f3e: f502 6210 add.w r2, r2, #2304 ; 0x900 8005f42: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 8005f46: 6013 str r3, [r2, #0] 8005f48: e00f b.n 8005f6a } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8005f4a: 69bb ldr r3, [r7, #24] 8005f4c: 015a lsls r2, r3, #5 8005f4e: 69fb ldr r3, [r7, #28] 8005f50: 4413 add r3, r2 8005f52: f503 6310 add.w r3, r3, #2304 ; 0x900 8005f56: 681b ldr r3, [r3, #0] 8005f58: 69ba ldr r2, [r7, #24] 8005f5a: 0151 lsls r1, r2, #5 8005f5c: 69fa ldr r2, [r7, #28] 8005f5e: 440a add r2, r1 8005f60: f502 6210 add.w r2, r2, #2304 ; 0x900 8005f64: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005f68: 6013 str r3, [r2, #0] } } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8005f6a: 69bb ldr r3, [r7, #24] 8005f6c: 015a lsls r2, r3, #5 8005f6e: 69fb ldr r3, [r7, #28] 8005f70: 4413 add r3, r2 8005f72: f503 6310 add.w r3, r3, #2304 ; 0x900 8005f76: 681b ldr r3, [r3, #0] 8005f78: 69ba ldr r2, [r7, #24] 8005f7a: 0151 lsls r1, r2, #5 8005f7c: 69fa ldr r2, [r7, #28] 8005f7e: 440a add r2, r1 8005f80: f502 6210 add.w r2, r2, #2304 ; 0x900 8005f84: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8005f88: 6013 str r3, [r2, #0] 8005f8a: e12f b.n 80061ec } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 8005f8c: 69bb ldr r3, [r7, #24] 8005f8e: 015a lsls r2, r3, #5 8005f90: 69fb ldr r3, [r7, #28] 8005f92: 4413 add r3, r2 8005f94: f503 6310 add.w r3, r3, #2304 ; 0x900 8005f98: 681b ldr r3, [r3, #0] 8005f9a: 69ba ldr r2, [r7, #24] 8005f9c: 0151 lsls r1, r2, #5 8005f9e: 69fa ldr r2, [r7, #28] 8005fa0: 440a add r2, r1 8005fa2: f502 6210 add.w r2, r2, #2304 ; 0x900 8005fa6: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8005faa: 6013 str r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) 8005fac: 68bb ldr r3, [r7, #8] 8005fae: 78db ldrb r3, [r3, #3] 8005fb0: 2b01 cmp r3, #1 8005fb2: d015 beq.n 8005fe0 { /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 8005fb4: 68bb ldr r3, [r7, #8] 8005fb6: 695b ldr r3, [r3, #20] 8005fb8: 2b00 cmp r3, #0 8005fba: f000 8117 beq.w 80061ec { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8005fbe: 69fb ldr r3, [r7, #28] 8005fc0: f503 6300 add.w r3, r3, #2048 ; 0x800 8005fc4: 6b5a ldr r2, [r3, #52] ; 0x34 8005fc6: 68bb ldr r3, [r7, #8] 8005fc8: 781b ldrb r3, [r3, #0] 8005fca: f003 030f and.w r3, r3, #15 8005fce: 2101 movs r1, #1 8005fd0: fa01 f303 lsl.w r3, r1, r3 8005fd4: 69f9 ldr r1, [r7, #28] 8005fd6: f501 6100 add.w r1, r1, #2048 ; 0x800 8005fda: 4313 orrs r3, r2 8005fdc: 634b str r3, [r1, #52] ; 0x34 8005fde: e105 b.n 80061ec } } else { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 8005fe0: 69fb ldr r3, [r7, #28] 8005fe2: f503 6300 add.w r3, r3, #2048 ; 0x800 8005fe6: 689b ldr r3, [r3, #8] 8005fe8: f403 7380 and.w r3, r3, #256 ; 0x100 8005fec: 2b00 cmp r3, #0 8005fee: d110 bne.n 8006012 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 8005ff0: 69bb ldr r3, [r7, #24] 8005ff2: 015a lsls r2, r3, #5 8005ff4: 69fb ldr r3, [r7, #28] 8005ff6: 4413 add r3, r2 8005ff8: f503 6310 add.w r3, r3, #2304 ; 0x900 8005ffc: 681b ldr r3, [r3, #0] 8005ffe: 69ba ldr r2, [r7, #24] 8006000: 0151 lsls r1, r2, #5 8006002: 69fa ldr r2, [r7, #28] 8006004: 440a add r2, r1 8006006: f502 6210 add.w r2, r2, #2304 ; 0x900 800600a: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 800600e: 6013 str r3, [r2, #0] 8006010: e00f b.n 8006032 } else { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 8006012: 69bb ldr r3, [r7, #24] 8006014: 015a lsls r2, r3, #5 8006016: 69fb ldr r3, [r7, #28] 8006018: 4413 add r3, r2 800601a: f503 6310 add.w r3, r3, #2304 ; 0x900 800601e: 681b ldr r3, [r3, #0] 8006020: 69ba ldr r2, [r7, #24] 8006022: 0151 lsls r1, r2, #5 8006024: 69fa ldr r2, [r7, #28] 8006026: 440a add r2, r1 8006028: f502 6210 add.w r2, r2, #2304 ; 0x900 800602c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8006030: 6013 str r3, [r2, #0] } (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); 8006032: 68bb ldr r3, [r7, #8] 8006034: 68d9 ldr r1, [r3, #12] 8006036: 68bb ldr r3, [r7, #8] 8006038: 781a ldrb r2, [r3, #0] 800603a: 68bb ldr r3, [r7, #8] 800603c: 695b ldr r3, [r3, #20] 800603e: b298 uxth r0, r3 8006040: 79fb ldrb r3, [r7, #7] 8006042: 9300 str r3, [sp, #0] 8006044: 4603 mov r3, r0 8006046: 68f8 ldr r0, [r7, #12] 8006048: f000 fa2b bl 80064a2 800604c: e0ce b.n 80061ec { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 800604e: 69bb ldr r3, [r7, #24] 8006050: 015a lsls r2, r3, #5 8006052: 69fb ldr r3, [r7, #28] 8006054: 4413 add r3, r2 8006056: f503 6330 add.w r3, r3, #2816 ; 0xb00 800605a: 691b ldr r3, [r3, #16] 800605c: 69ba ldr r2, [r7, #24] 800605e: 0151 lsls r1, r2, #5 8006060: 69fa ldr r2, [r7, #28] 8006062: 440a add r2, r1 8006064: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006068: 0cdb lsrs r3, r3, #19 800606a: 04db lsls r3, r3, #19 800606c: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 800606e: 69bb ldr r3, [r7, #24] 8006070: 015a lsls r2, r3, #5 8006072: 69fb ldr r3, [r7, #28] 8006074: 4413 add r3, r2 8006076: f503 6330 add.w r3, r3, #2816 ; 0xb00 800607a: 691b ldr r3, [r3, #16] 800607c: 69ba ldr r2, [r7, #24] 800607e: 0151 lsls r1, r2, #5 8006080: 69fa ldr r2, [r7, #28] 8006082: 440a add r2, r1 8006084: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006088: f023 53ff bic.w r3, r3, #534773760 ; 0x1fe00000 800608c: f423 13c0 bic.w r3, r3, #1572864 ; 0x180000 8006090: 6113 str r3, [r2, #16] if (ep->xfer_len == 0U) 8006092: 68bb ldr r3, [r7, #8] 8006094: 695b ldr r3, [r3, #20] 8006096: 2b00 cmp r3, #0 8006098: d126 bne.n 80060e8 { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 800609a: 69bb ldr r3, [r7, #24] 800609c: 015a lsls r2, r3, #5 800609e: 69fb ldr r3, [r7, #28] 80060a0: 4413 add r3, r2 80060a2: f503 6330 add.w r3, r3, #2816 ; 0xb00 80060a6: 691a ldr r2, [r3, #16] 80060a8: 68bb ldr r3, [r7, #8] 80060aa: 689b ldr r3, [r3, #8] 80060ac: f3c3 0312 ubfx r3, r3, #0, #19 80060b0: 69b9 ldr r1, [r7, #24] 80060b2: 0148 lsls r0, r1, #5 80060b4: 69f9 ldr r1, [r7, #28] 80060b6: 4401 add r1, r0 80060b8: f501 6130 add.w r1, r1, #2816 ; 0xb00 80060bc: 4313 orrs r3, r2 80060be: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 80060c0: 69bb ldr r3, [r7, #24] 80060c2: 015a lsls r2, r3, #5 80060c4: 69fb ldr r3, [r7, #28] 80060c6: 4413 add r3, r2 80060c8: f503 6330 add.w r3, r3, #2816 ; 0xb00 80060cc: 691b ldr r3, [r3, #16] 80060ce: 69ba ldr r2, [r7, #24] 80060d0: 0151 lsls r1, r2, #5 80060d2: 69fa ldr r2, [r7, #28] 80060d4: 440a add r2, r1 80060d6: f502 6230 add.w r2, r2, #2816 ; 0xb00 80060da: f443 2300 orr.w r3, r3, #524288 ; 0x80000 80060de: 6113 str r3, [r2, #16] 80060e0: e036 b.n 8006150 80060e2: bf00 nop 80060e4: 1ff80000 .word 0x1ff80000 } else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); 80060e8: 68bb ldr r3, [r7, #8] 80060ea: 695a ldr r2, [r3, #20] 80060ec: 68bb ldr r3, [r7, #8] 80060ee: 689b ldr r3, [r3, #8] 80060f0: 4413 add r3, r2 80060f2: 1e5a subs r2, r3, #1 80060f4: 68bb ldr r3, [r7, #8] 80060f6: 689b ldr r3, [r3, #8] 80060f8: fbb2 f3f3 udiv r3, r2, r3 80060fc: 82fb strh r3, [r7, #22] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); 80060fe: 69bb ldr r3, [r7, #24] 8006100: 015a lsls r2, r3, #5 8006102: 69fb ldr r3, [r7, #28] 8006104: 4413 add r3, r2 8006106: f503 6330 add.w r3, r3, #2816 ; 0xb00 800610a: 691a ldr r2, [r3, #16] 800610c: 8afb ldrh r3, [r7, #22] 800610e: 04d9 lsls r1, r3, #19 8006110: 4b39 ldr r3, [pc, #228] ; (80061f8 ) 8006112: 400b ands r3, r1 8006114: 69b9 ldr r1, [r7, #24] 8006116: 0148 lsls r0, r1, #5 8006118: 69f9 ldr r1, [r7, #28] 800611a: 4401 add r1, r0 800611c: f501 6130 add.w r1, r1, #2816 ; 0xb00 8006120: 4313 orrs r3, r2 8006122: 610b str r3, [r1, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); 8006124: 69bb ldr r3, [r7, #24] 8006126: 015a lsls r2, r3, #5 8006128: 69fb ldr r3, [r7, #28] 800612a: 4413 add r3, r2 800612c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006130: 691a ldr r2, [r3, #16] 8006132: 68bb ldr r3, [r7, #8] 8006134: 689b ldr r3, [r3, #8] 8006136: 8af9 ldrh r1, [r7, #22] 8006138: fb01 f303 mul.w r3, r1, r3 800613c: f3c3 0312 ubfx r3, r3, #0, #19 8006140: 69b9 ldr r1, [r7, #24] 8006142: 0148 lsls r0, r1, #5 8006144: 69f9 ldr r1, [r7, #28] 8006146: 4401 add r1, r0 8006148: f501 6130 add.w r1, r1, #2816 ; 0xb00 800614c: 4313 orrs r3, r2 800614e: 610b str r3, [r1, #16] } if (dma == 1U) 8006150: 79fb ldrb r3, [r7, #7] 8006152: 2b01 cmp r3, #1 8006154: d10d bne.n 8006172 { if ((uint32_t)ep->xfer_buff != 0U) 8006156: 68bb ldr r3, [r7, #8] 8006158: 68db ldr r3, [r3, #12] 800615a: 2b00 cmp r3, #0 800615c: d009 beq.n 8006172 { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 800615e: 68bb ldr r3, [r7, #8] 8006160: 68d9 ldr r1, [r3, #12] 8006162: 69bb ldr r3, [r7, #24] 8006164: 015a lsls r2, r3, #5 8006166: 69fb ldr r3, [r7, #28] 8006168: 4413 add r3, r2 800616a: f503 6330 add.w r3, r3, #2816 ; 0xb00 800616e: 460a mov r2, r1 8006170: 615a str r2, [r3, #20] } } if (ep->type == EP_TYPE_ISOC) 8006172: 68bb ldr r3, [r7, #8] 8006174: 78db ldrb r3, [r3, #3] 8006176: 2b01 cmp r3, #1 8006178: d128 bne.n 80061cc { if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) 800617a: 69fb ldr r3, [r7, #28] 800617c: f503 6300 add.w r3, r3, #2048 ; 0x800 8006180: 689b ldr r3, [r3, #8] 8006182: f403 7380 and.w r3, r3, #256 ; 0x100 8006186: 2b00 cmp r3, #0 8006188: d110 bne.n 80061ac { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 800618a: 69bb ldr r3, [r7, #24] 800618c: 015a lsls r2, r3, #5 800618e: 69fb ldr r3, [r7, #28] 8006190: 4413 add r3, r2 8006192: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006196: 681b ldr r3, [r3, #0] 8006198: 69ba ldr r2, [r7, #24] 800619a: 0151 lsls r1, r2, #5 800619c: 69fa ldr r2, [r7, #28] 800619e: 440a add r2, r1 80061a0: f502 6230 add.w r2, r2, #2816 ; 0xb00 80061a4: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 80061a8: 6013 str r3, [r2, #0] 80061aa: e00f b.n 80061cc } else { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 80061ac: 69bb ldr r3, [r7, #24] 80061ae: 015a lsls r2, r3, #5 80061b0: 69fb ldr r3, [r7, #28] 80061b2: 4413 add r3, r2 80061b4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80061b8: 681b ldr r3, [r3, #0] 80061ba: 69ba ldr r2, [r7, #24] 80061bc: 0151 lsls r1, r2, #5 80061be: 69fa ldr r2, [r7, #28] 80061c0: 440a add r2, r1 80061c2: f502 6230 add.w r2, r2, #2816 ; 0xb00 80061c6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80061ca: 6013 str r3, [r2, #0] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 80061cc: 69bb ldr r3, [r7, #24] 80061ce: 015a lsls r2, r3, #5 80061d0: 69fb ldr r3, [r7, #28] 80061d2: 4413 add r3, r2 80061d4: f503 6330 add.w r3, r3, #2816 ; 0xb00 80061d8: 681b ldr r3, [r3, #0] 80061da: 69ba ldr r2, [r7, #24] 80061dc: 0151 lsls r1, r2, #5 80061de: 69fa ldr r2, [r7, #28] 80061e0: 440a add r2, r1 80061e2: f502 6230 add.w r2, r2, #2816 ; 0xb00 80061e6: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 80061ea: 6013 str r3, [r2, #0] } return HAL_OK; 80061ec: 2300 movs r3, #0 } 80061ee: 4618 mov r0, r3 80061f0: 3720 adds r7, #32 80061f2: 46bd mov sp, r7 80061f4: bd80 pop {r7, pc} 80061f6: bf00 nop 80061f8: 1ff80000 .word 0x1ff80000 080061fc : * 0 : DMA feature not used * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) { 80061fc: b480 push {r7} 80061fe: b087 sub sp, #28 8006200: af00 add r7, sp, #0 8006202: 60f8 str r0, [r7, #12] 8006204: 60b9 str r1, [r7, #8] 8006206: 4613 mov r3, r2 8006208: 71fb strb r3, [r7, #7] uint32_t USBx_BASE = (uint32_t)USBx; 800620a: 68fb ldr r3, [r7, #12] 800620c: 617b str r3, [r7, #20] uint32_t epnum = (uint32_t)ep->num; 800620e: 68bb ldr r3, [r7, #8] 8006210: 781b ldrb r3, [r3, #0] 8006212: 613b str r3, [r7, #16] /* IN endpoint */ if (ep->is_in == 1U) 8006214: 68bb ldr r3, [r7, #8] 8006216: 785b ldrb r3, [r3, #1] 8006218: 2b01 cmp r3, #1 800621a: f040 80cd bne.w 80063b8 { /* Zero Length Packet? */ if (ep->xfer_len == 0U) 800621e: 68bb ldr r3, [r7, #8] 8006220: 695b ldr r3, [r3, #20] 8006222: 2b00 cmp r3, #0 8006224: d132 bne.n 800628c { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 8006226: 693b ldr r3, [r7, #16] 8006228: 015a lsls r2, r3, #5 800622a: 697b ldr r3, [r7, #20] 800622c: 4413 add r3, r2 800622e: f503 6310 add.w r3, r3, #2304 ; 0x900 8006232: 691b ldr r3, [r3, #16] 8006234: 693a ldr r2, [r7, #16] 8006236: 0151 lsls r1, r2, #5 8006238: 697a ldr r2, [r7, #20] 800623a: 440a add r2, r1 800623c: f502 6210 add.w r2, r2, #2304 ; 0x900 8006240: f023 53ff bic.w r3, r3, #534773760 ; 0x1fe00000 8006244: f423 13c0 bic.w r3, r3, #1572864 ; 0x180000 8006248: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 800624a: 693b ldr r3, [r7, #16] 800624c: 015a lsls r2, r3, #5 800624e: 697b ldr r3, [r7, #20] 8006250: 4413 add r3, r2 8006252: f503 6310 add.w r3, r3, #2304 ; 0x900 8006256: 691b ldr r3, [r3, #16] 8006258: 693a ldr r2, [r7, #16] 800625a: 0151 lsls r1, r2, #5 800625c: 697a ldr r2, [r7, #20] 800625e: 440a add r2, r1 8006260: f502 6210 add.w r2, r2, #2304 ; 0x900 8006264: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006268: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800626a: 693b ldr r3, [r7, #16] 800626c: 015a lsls r2, r3, #5 800626e: 697b ldr r3, [r7, #20] 8006270: 4413 add r3, r2 8006272: f503 6310 add.w r3, r3, #2304 ; 0x900 8006276: 691b ldr r3, [r3, #16] 8006278: 693a ldr r2, [r7, #16] 800627a: 0151 lsls r1, r2, #5 800627c: 697a ldr r2, [r7, #20] 800627e: 440a add r2, r1 8006280: f502 6210 add.w r2, r2, #2304 ; 0x900 8006284: 0cdb lsrs r3, r3, #19 8006286: 04db lsls r3, r3, #19 8006288: 6113 str r3, [r2, #16] 800628a: e04e b.n 800632a /* Program the transfer size and packet count * as follows: xfersize = N * maxpacket + * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 800628c: 693b ldr r3, [r7, #16] 800628e: 015a lsls r2, r3, #5 8006290: 697b ldr r3, [r7, #20] 8006292: 4413 add r3, r2 8006294: f503 6310 add.w r3, r3, #2304 ; 0x900 8006298: 691b ldr r3, [r3, #16] 800629a: 693a ldr r2, [r7, #16] 800629c: 0151 lsls r1, r2, #5 800629e: 697a ldr r2, [r7, #20] 80062a0: 440a add r2, r1 80062a2: f502 6210 add.w r2, r2, #2304 ; 0x900 80062a6: 0cdb lsrs r3, r3, #19 80062a8: 04db lsls r3, r3, #19 80062aa: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 80062ac: 693b ldr r3, [r7, #16] 80062ae: 015a lsls r2, r3, #5 80062b0: 697b ldr r3, [r7, #20] 80062b2: 4413 add r3, r2 80062b4: f503 6310 add.w r3, r3, #2304 ; 0x900 80062b8: 691b ldr r3, [r3, #16] 80062ba: 693a ldr r2, [r7, #16] 80062bc: 0151 lsls r1, r2, #5 80062be: 697a ldr r2, [r7, #20] 80062c0: 440a add r2, r1 80062c2: f502 6210 add.w r2, r2, #2304 ; 0x900 80062c6: f023 53ff bic.w r3, r3, #534773760 ; 0x1fe00000 80062ca: f423 13c0 bic.w r3, r3, #1572864 ; 0x180000 80062ce: 6113 str r3, [r2, #16] if (ep->xfer_len > ep->maxpacket) 80062d0: 68bb ldr r3, [r7, #8] 80062d2: 695a ldr r2, [r3, #20] 80062d4: 68bb ldr r3, [r7, #8] 80062d6: 689b ldr r3, [r3, #8] 80062d8: 429a cmp r2, r3 80062da: d903 bls.n 80062e4 { ep->xfer_len = ep->maxpacket; 80062dc: 68bb ldr r3, [r7, #8] 80062de: 689a ldr r2, [r3, #8] 80062e0: 68bb ldr r3, [r7, #8] 80062e2: 615a str r2, [r3, #20] } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); 80062e4: 693b ldr r3, [r7, #16] 80062e6: 015a lsls r2, r3, #5 80062e8: 697b ldr r3, [r7, #20] 80062ea: 4413 add r3, r2 80062ec: f503 6310 add.w r3, r3, #2304 ; 0x900 80062f0: 691b ldr r3, [r3, #16] 80062f2: 693a ldr r2, [r7, #16] 80062f4: 0151 lsls r1, r2, #5 80062f6: 697a ldr r2, [r7, #20] 80062f8: 440a add r2, r1 80062fa: f502 6210 add.w r2, r2, #2304 ; 0x900 80062fe: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006302: 6113 str r3, [r2, #16] USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 8006304: 693b ldr r3, [r7, #16] 8006306: 015a lsls r2, r3, #5 8006308: 697b ldr r3, [r7, #20] 800630a: 4413 add r3, r2 800630c: f503 6310 add.w r3, r3, #2304 ; 0x900 8006310: 691a ldr r2, [r3, #16] 8006312: 68bb ldr r3, [r7, #8] 8006314: 695b ldr r3, [r3, #20] 8006316: f3c3 0312 ubfx r3, r3, #0, #19 800631a: 6939 ldr r1, [r7, #16] 800631c: 0148 lsls r0, r1, #5 800631e: 6979 ldr r1, [r7, #20] 8006320: 4401 add r1, r0 8006322: f501 6110 add.w r1, r1, #2304 ; 0x900 8006326: 4313 orrs r3, r2 8006328: 610b str r3, [r1, #16] } if (dma == 1U) 800632a: 79fb ldrb r3, [r7, #7] 800632c: 2b01 cmp r3, #1 800632e: d11e bne.n 800636e { if ((uint32_t)ep->dma_addr != 0U) 8006330: 68bb ldr r3, [r7, #8] 8006332: 691b ldr r3, [r3, #16] 8006334: 2b00 cmp r3, #0 8006336: d009 beq.n 800634c { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); 8006338: 693b ldr r3, [r7, #16] 800633a: 015a lsls r2, r3, #5 800633c: 697b ldr r3, [r7, #20] 800633e: 4413 add r3, r2 8006340: f503 6310 add.w r3, r3, #2304 ; 0x900 8006344: 461a mov r2, r3 8006346: 68bb ldr r3, [r7, #8] 8006348: 691b ldr r3, [r3, #16] 800634a: 6153 str r3, [r2, #20] } /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 800634c: 693b ldr r3, [r7, #16] 800634e: 015a lsls r2, r3, #5 8006350: 697b ldr r3, [r7, #20] 8006352: 4413 add r3, r2 8006354: f503 6310 add.w r3, r3, #2304 ; 0x900 8006358: 681b ldr r3, [r3, #0] 800635a: 693a ldr r2, [r7, #16] 800635c: 0151 lsls r1, r2, #5 800635e: 697a ldr r2, [r7, #20] 8006360: 440a add r2, r1 8006362: f502 6210 add.w r2, r2, #2304 ; 0x900 8006366: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 800636a: 6013 str r3, [r2, #0] 800636c: e092 b.n 8006494 } else { /* EP enable, IN data in FIFO */ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 800636e: 693b ldr r3, [r7, #16] 8006370: 015a lsls r2, r3, #5 8006372: 697b ldr r3, [r7, #20] 8006374: 4413 add r3, r2 8006376: f503 6310 add.w r3, r3, #2304 ; 0x900 800637a: 681b ldr r3, [r3, #0] 800637c: 693a ldr r2, [r7, #16] 800637e: 0151 lsls r1, r2, #5 8006380: 697a ldr r2, [r7, #20] 8006382: 440a add r2, r1 8006384: f502 6210 add.w r2, r2, #2304 ; 0x900 8006388: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 800638c: 6013 str r3, [r2, #0] /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) 800638e: 68bb ldr r3, [r7, #8] 8006390: 695b ldr r3, [r3, #20] 8006392: 2b00 cmp r3, #0 8006394: d07e beq.n 8006494 { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); 8006396: 697b ldr r3, [r7, #20] 8006398: f503 6300 add.w r3, r3, #2048 ; 0x800 800639c: 6b5a ldr r2, [r3, #52] ; 0x34 800639e: 68bb ldr r3, [r7, #8] 80063a0: 781b ldrb r3, [r3, #0] 80063a2: f003 030f and.w r3, r3, #15 80063a6: 2101 movs r1, #1 80063a8: fa01 f303 lsl.w r3, r1, r3 80063ac: 6979 ldr r1, [r7, #20] 80063ae: f501 6100 add.w r1, r1, #2048 ; 0x800 80063b2: 4313 orrs r3, r2 80063b4: 634b str r3, [r1, #52] ; 0x34 80063b6: e06d b.n 8006494 { /* Program the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 80063b8: 693b ldr r3, [r7, #16] 80063ba: 015a lsls r2, r3, #5 80063bc: 697b ldr r3, [r7, #20] 80063be: 4413 add r3, r2 80063c0: f503 6330 add.w r3, r3, #2816 ; 0xb00 80063c4: 691b ldr r3, [r3, #16] 80063c6: 693a ldr r2, [r7, #16] 80063c8: 0151 lsls r1, r2, #5 80063ca: 697a ldr r2, [r7, #20] 80063cc: 440a add r2, r1 80063ce: f502 6230 add.w r2, r2, #2816 ; 0xb00 80063d2: 0cdb lsrs r3, r3, #19 80063d4: 04db lsls r3, r3, #19 80063d6: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 80063d8: 693b ldr r3, [r7, #16] 80063da: 015a lsls r2, r3, #5 80063dc: 697b ldr r3, [r7, #20] 80063de: 4413 add r3, r2 80063e0: f503 6330 add.w r3, r3, #2816 ; 0xb00 80063e4: 691b ldr r3, [r3, #16] 80063e6: 693a ldr r2, [r7, #16] 80063e8: 0151 lsls r1, r2, #5 80063ea: 697a ldr r2, [r7, #20] 80063ec: 440a add r2, r1 80063ee: f502 6230 add.w r2, r2, #2816 ; 0xb00 80063f2: f023 53ff bic.w r3, r3, #534773760 ; 0x1fe00000 80063f6: f423 13c0 bic.w r3, r3, #1572864 ; 0x180000 80063fa: 6113 str r3, [r2, #16] if (ep->xfer_len > 0U) 80063fc: 68bb ldr r3, [r7, #8] 80063fe: 695b ldr r3, [r3, #20] 8006400: 2b00 cmp r3, #0 8006402: d003 beq.n 800640c { ep->xfer_len = ep->maxpacket; 8006404: 68bb ldr r3, [r7, #8] 8006406: 689a ldr r2, [r3, #8] 8006408: 68bb ldr r3, [r7, #8] 800640a: 615a str r2, [r3, #20] } USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 800640c: 693b ldr r3, [r7, #16] 800640e: 015a lsls r2, r3, #5 8006410: 697b ldr r3, [r7, #20] 8006412: 4413 add r3, r2 8006414: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006418: 691b ldr r3, [r3, #16] 800641a: 693a ldr r2, [r7, #16] 800641c: 0151 lsls r1, r2, #5 800641e: 697a ldr r2, [r7, #20] 8006420: 440a add r2, r1 8006422: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006426: f443 2300 orr.w r3, r3, #524288 ; 0x80000 800642a: 6113 str r3, [r2, #16] USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 800642c: 693b ldr r3, [r7, #16] 800642e: 015a lsls r2, r3, #5 8006430: 697b ldr r3, [r7, #20] 8006432: 4413 add r3, r2 8006434: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006438: 691a ldr r2, [r3, #16] 800643a: 68bb ldr r3, [r7, #8] 800643c: 689b ldr r3, [r3, #8] 800643e: f3c3 0312 ubfx r3, r3, #0, #19 8006442: 6939 ldr r1, [r7, #16] 8006444: 0148 lsls r0, r1, #5 8006446: 6979 ldr r1, [r7, #20] 8006448: 4401 add r1, r0 800644a: f501 6130 add.w r1, r1, #2816 ; 0xb00 800644e: 4313 orrs r3, r2 8006450: 610b str r3, [r1, #16] if (dma == 1U) 8006452: 79fb ldrb r3, [r7, #7] 8006454: 2b01 cmp r3, #1 8006456: d10d bne.n 8006474 { if ((uint32_t)ep->xfer_buff != 0U) 8006458: 68bb ldr r3, [r7, #8] 800645a: 68db ldr r3, [r3, #12] 800645c: 2b00 cmp r3, #0 800645e: d009 beq.n 8006474 { USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); 8006460: 68bb ldr r3, [r7, #8] 8006462: 68d9 ldr r1, [r3, #12] 8006464: 693b ldr r3, [r7, #16] 8006466: 015a lsls r2, r3, #5 8006468: 697b ldr r3, [r7, #20] 800646a: 4413 add r3, r2 800646c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006470: 460a mov r2, r1 8006472: 615a str r2, [r3, #20] } } /* EP enable */ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 8006474: 693b ldr r3, [r7, #16] 8006476: 015a lsls r2, r3, #5 8006478: 697b ldr r3, [r7, #20] 800647a: 4413 add r3, r2 800647c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006480: 681b ldr r3, [r3, #0] 8006482: 693a ldr r2, [r7, #16] 8006484: 0151 lsls r1, r2, #5 8006486: 697a ldr r2, [r7, #20] 8006488: 440a add r2, r1 800648a: f502 6230 add.w r2, r2, #2816 ; 0xb00 800648e: f043 4304 orr.w r3, r3, #2214592512 ; 0x84000000 8006492: 6013 str r3, [r2, #0] } return HAL_OK; 8006494: 2300 movs r3, #0 } 8006496: 4618 mov r0, r3 8006498: 371c adds r7, #28 800649a: 46bd mov sp, r7 800649c: f85d 7b04 ldr.w r7, [sp], #4 80064a0: 4770 bx lr 080064a2 : * 1 : DMA feature used * @retval HAL status */ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { 80064a2: b480 push {r7} 80064a4: b089 sub sp, #36 ; 0x24 80064a6: af00 add r7, sp, #0 80064a8: 60f8 str r0, [r7, #12] 80064aa: 60b9 str r1, [r7, #8] 80064ac: 4611 mov r1, r2 80064ae: 461a mov r2, r3 80064b0: 460b mov r3, r1 80064b2: 71fb strb r3, [r7, #7] 80064b4: 4613 mov r3, r2 80064b6: 80bb strh r3, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80064b8: 68fb ldr r3, [r7, #12] 80064ba: 617b str r3, [r7, #20] uint8_t *pSrc = src; 80064bc: 68bb ldr r3, [r7, #8] 80064be: 61fb str r3, [r7, #28] uint32_t count32b; uint32_t i; if (dma == 0U) 80064c0: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 80064c4: 2b00 cmp r3, #0 80064c6: d123 bne.n 8006510 { count32b = ((uint32_t)len + 3U) / 4U; 80064c8: 88bb ldrh r3, [r7, #4] 80064ca: 3303 adds r3, #3 80064cc: 089b lsrs r3, r3, #2 80064ce: 613b str r3, [r7, #16] for (i = 0U; i < count32b; i++) 80064d0: 2300 movs r3, #0 80064d2: 61bb str r3, [r7, #24] 80064d4: e018 b.n 8006508 { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); 80064d6: 79fb ldrb r3, [r7, #7] 80064d8: 031a lsls r2, r3, #12 80064da: 697b ldr r3, [r7, #20] 80064dc: 4413 add r3, r2 80064de: f503 5380 add.w r3, r3, #4096 ; 0x1000 80064e2: 461a mov r2, r3 80064e4: 69fb ldr r3, [r7, #28] 80064e6: 681b ldr r3, [r3, #0] 80064e8: 6013 str r3, [r2, #0] pSrc++; 80064ea: 69fb ldr r3, [r7, #28] 80064ec: 3301 adds r3, #1 80064ee: 61fb str r3, [r7, #28] pSrc++; 80064f0: 69fb ldr r3, [r7, #28] 80064f2: 3301 adds r3, #1 80064f4: 61fb str r3, [r7, #28] pSrc++; 80064f6: 69fb ldr r3, [r7, #28] 80064f8: 3301 adds r3, #1 80064fa: 61fb str r3, [r7, #28] pSrc++; 80064fc: 69fb ldr r3, [r7, #28] 80064fe: 3301 adds r3, #1 8006500: 61fb str r3, [r7, #28] for (i = 0U; i < count32b; i++) 8006502: 69bb ldr r3, [r7, #24] 8006504: 3301 adds r3, #1 8006506: 61bb str r3, [r7, #24] 8006508: 69ba ldr r2, [r7, #24] 800650a: 693b ldr r3, [r7, #16] 800650c: 429a cmp r2, r3 800650e: d3e2 bcc.n 80064d6 } } return HAL_OK; 8006510: 2300 movs r3, #0 } 8006512: 4618 mov r0, r3 8006514: 3724 adds r7, #36 ; 0x24 8006516: 46bd mov sp, r7 8006518: f85d 7b04 ldr.w r7, [sp], #4 800651c: 4770 bx lr 0800651e : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 800651e: b480 push {r7} 8006520: b08b sub sp, #44 ; 0x2c 8006522: af00 add r7, sp, #0 8006524: 60f8 str r0, [r7, #12] 8006526: 60b9 str r1, [r7, #8] 8006528: 4613 mov r3, r2 800652a: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 800652c: 68fb ldr r3, [r7, #12] 800652e: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8006530: 68bb ldr r3, [r7, #8] 8006532: 627b str r3, [r7, #36] ; 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8006534: 88fb ldrh r3, [r7, #6] 8006536: 089b lsrs r3, r3, #2 8006538: b29b uxth r3, r3 800653a: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 800653c: 88fb ldrh r3, [r7, #6] 800653e: f003 0303 and.w r3, r3, #3 8006542: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8006544: 2300 movs r3, #0 8006546: 623b str r3, [r7, #32] 8006548: e014 b.n 8006574 { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 800654a: 69bb ldr r3, [r7, #24] 800654c: f503 5380 add.w r3, r3, #4096 ; 0x1000 8006550: 681a ldr r2, [r3, #0] 8006552: 6a7b ldr r3, [r7, #36] ; 0x24 8006554: 601a str r2, [r3, #0] pDest++; 8006556: 6a7b ldr r3, [r7, #36] ; 0x24 8006558: 3301 adds r3, #1 800655a: 627b str r3, [r7, #36] ; 0x24 pDest++; 800655c: 6a7b ldr r3, [r7, #36] ; 0x24 800655e: 3301 adds r3, #1 8006560: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006562: 6a7b ldr r3, [r7, #36] ; 0x24 8006564: 3301 adds r3, #1 8006566: 627b str r3, [r7, #36] ; 0x24 pDest++; 8006568: 6a7b ldr r3, [r7, #36] ; 0x24 800656a: 3301 adds r3, #1 800656c: 627b str r3, [r7, #36] ; 0x24 for (i = 0U; i < count32b; i++) 800656e: 6a3b ldr r3, [r7, #32] 8006570: 3301 adds r3, #1 8006572: 623b str r3, [r7, #32] 8006574: 6a3a ldr r2, [r7, #32] 8006576: 697b ldr r3, [r7, #20] 8006578: 429a cmp r2, r3 800657a: d3e6 bcc.n 800654a } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 800657c: 8bfb ldrh r3, [r7, #30] 800657e: 2b00 cmp r3, #0 8006580: d01e beq.n 80065c0 { i = 0U; 8006582: 2300 movs r3, #0 8006584: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8006586: 69bb ldr r3, [r7, #24] 8006588: f503 5380 add.w r3, r3, #4096 ; 0x1000 800658c: 461a mov r2, r3 800658e: f107 0310 add.w r3, r7, #16 8006592: 6812 ldr r2, [r2, #0] 8006594: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8006596: 693a ldr r2, [r7, #16] 8006598: 6a3b ldr r3, [r7, #32] 800659a: b2db uxtb r3, r3 800659c: 00db lsls r3, r3, #3 800659e: fa22 f303 lsr.w r3, r2, r3 80065a2: b2da uxtb r2, r3 80065a4: 6a7b ldr r3, [r7, #36] ; 0x24 80065a6: 701a strb r2, [r3, #0] i++; 80065a8: 6a3b ldr r3, [r7, #32] 80065aa: 3301 adds r3, #1 80065ac: 623b str r3, [r7, #32] pDest++; 80065ae: 6a7b ldr r3, [r7, #36] ; 0x24 80065b0: 3301 adds r3, #1 80065b2: 627b str r3, [r7, #36] ; 0x24 remaining_bytes--; 80065b4: 8bfb ldrh r3, [r7, #30] 80065b6: 3b01 subs r3, #1 80065b8: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 80065ba: 8bfb ldrh r3, [r7, #30] 80065bc: 2b00 cmp r3, #0 80065be: d1ea bne.n 8006596 } return ((void *)pDest); 80065c0: 6a7b ldr r3, [r7, #36] ; 0x24 } 80065c2: 4618 mov r0, r3 80065c4: 372c adds r7, #44 ; 0x2c 80065c6: 46bd mov sp, r7 80065c8: f85d 7b04 ldr.w r7, [sp], #4 80065cc: 4770 bx lr 080065ce : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 80065ce: b480 push {r7} 80065d0: b085 sub sp, #20 80065d2: af00 add r7, sp, #0 80065d4: 6078 str r0, [r7, #4] 80065d6: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80065d8: 687b ldr r3, [r7, #4] 80065da: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80065dc: 683b ldr r3, [r7, #0] 80065de: 781b ldrb r3, [r3, #0] 80065e0: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80065e2: 683b ldr r3, [r7, #0] 80065e4: 785b ldrb r3, [r3, #1] 80065e6: 2b01 cmp r3, #1 80065e8: d12c bne.n 8006644 { if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) 80065ea: 68bb ldr r3, [r7, #8] 80065ec: 015a lsls r2, r3, #5 80065ee: 68fb ldr r3, [r7, #12] 80065f0: 4413 add r3, r2 80065f2: f503 6310 add.w r3, r3, #2304 ; 0x900 80065f6: 681b ldr r3, [r3, #0] 80065f8: 2b00 cmp r3, #0 80065fa: db12 blt.n 8006622 80065fc: 68bb ldr r3, [r7, #8] 80065fe: 2b00 cmp r3, #0 8006600: d00f beq.n 8006622 { USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 8006602: 68bb ldr r3, [r7, #8] 8006604: 015a lsls r2, r3, #5 8006606: 68fb ldr r3, [r7, #12] 8006608: 4413 add r3, r2 800660a: f503 6310 add.w r3, r3, #2304 ; 0x900 800660e: 681b ldr r3, [r3, #0] 8006610: 68ba ldr r2, [r7, #8] 8006612: 0151 lsls r1, r2, #5 8006614: 68fa ldr r2, [r7, #12] 8006616: 440a add r2, r1 8006618: f502 6210 add.w r2, r2, #2304 ; 0x900 800661c: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 8006620: 6013 str r3, [r2, #0] } USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 8006622: 68bb ldr r3, [r7, #8] 8006624: 015a lsls r2, r3, #5 8006626: 68fb ldr r3, [r7, #12] 8006628: 4413 add r3, r2 800662a: f503 6310 add.w r3, r3, #2304 ; 0x900 800662e: 681b ldr r3, [r3, #0] 8006630: 68ba ldr r2, [r7, #8] 8006632: 0151 lsls r1, r2, #5 8006634: 68fa ldr r2, [r7, #12] 8006636: 440a add r2, r1 8006638: f502 6210 add.w r2, r2, #2304 ; 0x900 800663c: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 8006640: 6013 str r3, [r2, #0] 8006642: e02b b.n 800669c } else { if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) 8006644: 68bb ldr r3, [r7, #8] 8006646: 015a lsls r2, r3, #5 8006648: 68fb ldr r3, [r7, #12] 800664a: 4413 add r3, r2 800664c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006650: 681b ldr r3, [r3, #0] 8006652: 2b00 cmp r3, #0 8006654: db12 blt.n 800667c 8006656: 68bb ldr r3, [r7, #8] 8006658: 2b00 cmp r3, #0 800665a: d00f beq.n 800667c { USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 800665c: 68bb ldr r3, [r7, #8] 800665e: 015a lsls r2, r3, #5 8006660: 68fb ldr r3, [r7, #12] 8006662: 4413 add r3, r2 8006664: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006668: 681b ldr r3, [r3, #0] 800666a: 68ba ldr r2, [r7, #8] 800666c: 0151 lsls r1, r2, #5 800666e: 68fa ldr r2, [r7, #12] 8006670: 440a add r2, r1 8006672: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006676: f023 4380 bic.w r3, r3, #1073741824 ; 0x40000000 800667a: 6013 str r3, [r2, #0] } USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 800667c: 68bb ldr r3, [r7, #8] 800667e: 015a lsls r2, r3, #5 8006680: 68fb ldr r3, [r7, #12] 8006682: 4413 add r3, r2 8006684: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006688: 681b ldr r3, [r3, #0] 800668a: 68ba ldr r2, [r7, #8] 800668c: 0151 lsls r1, r2, #5 800668e: 68fa ldr r2, [r7, #12] 8006690: 440a add r2, r1 8006692: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006696: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 800669a: 6013 str r3, [r2, #0] } return HAL_OK; 800669c: 2300 movs r3, #0 } 800669e: 4618 mov r0, r3 80066a0: 3714 adds r7, #20 80066a2: 46bd mov sp, r7 80066a4: f85d 7b04 ldr.w r7, [sp], #4 80066a8: 4770 bx lr 080066aa : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { 80066aa: b480 push {r7} 80066ac: b085 sub sp, #20 80066ae: af00 add r7, sp, #0 80066b0: 6078 str r0, [r7, #4] 80066b2: 6039 str r1, [r7, #0] uint32_t USBx_BASE = (uint32_t)USBx; 80066b4: 687b ldr r3, [r7, #4] 80066b6: 60fb str r3, [r7, #12] uint32_t epnum = (uint32_t)ep->num; 80066b8: 683b ldr r3, [r7, #0] 80066ba: 781b ldrb r3, [r3, #0] 80066bc: 60bb str r3, [r7, #8] if (ep->is_in == 1U) 80066be: 683b ldr r3, [r7, #0] 80066c0: 785b ldrb r3, [r3, #1] 80066c2: 2b01 cmp r3, #1 80066c4: d128 bne.n 8006718 { USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 80066c6: 68bb ldr r3, [r7, #8] 80066c8: 015a lsls r2, r3, #5 80066ca: 68fb ldr r3, [r7, #12] 80066cc: 4413 add r3, r2 80066ce: f503 6310 add.w r3, r3, #2304 ; 0x900 80066d2: 681b ldr r3, [r3, #0] 80066d4: 68ba ldr r2, [r7, #8] 80066d6: 0151 lsls r1, r2, #5 80066d8: 68fa ldr r2, [r7, #12] 80066da: 440a add r2, r1 80066dc: f502 6210 add.w r2, r2, #2304 ; 0x900 80066e0: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 80066e4: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 80066e6: 683b ldr r3, [r7, #0] 80066e8: 78db ldrb r3, [r3, #3] 80066ea: 2b03 cmp r3, #3 80066ec: d003 beq.n 80066f6 80066ee: 683b ldr r3, [r7, #0] 80066f0: 78db ldrb r3, [r3, #3] 80066f2: 2b02 cmp r3, #2 80066f4: d138 bne.n 8006768 { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 80066f6: 68bb ldr r3, [r7, #8] 80066f8: 015a lsls r2, r3, #5 80066fa: 68fb ldr r3, [r7, #12] 80066fc: 4413 add r3, r2 80066fe: f503 6310 add.w r3, r3, #2304 ; 0x900 8006702: 681b ldr r3, [r3, #0] 8006704: 68ba ldr r2, [r7, #8] 8006706: 0151 lsls r1, r2, #5 8006708: 68fa ldr r2, [r7, #12] 800670a: 440a add r2, r1 800670c: f502 6210 add.w r2, r2, #2304 ; 0x900 8006710: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8006714: 6013 str r3, [r2, #0] 8006716: e027 b.n 8006768 } } else { USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 8006718: 68bb ldr r3, [r7, #8] 800671a: 015a lsls r2, r3, #5 800671c: 68fb ldr r3, [r7, #12] 800671e: 4413 add r3, r2 8006720: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006724: 681b ldr r3, [r3, #0] 8006726: 68ba ldr r2, [r7, #8] 8006728: 0151 lsls r1, r2, #5 800672a: 68fa ldr r2, [r7, #12] 800672c: 440a add r2, r1 800672e: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006732: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 8006736: 6013 str r3, [r2, #0] if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) 8006738: 683b ldr r3, [r7, #0] 800673a: 78db ldrb r3, [r3, #3] 800673c: 2b03 cmp r3, #3 800673e: d003 beq.n 8006748 8006740: 683b ldr r3, [r7, #0] 8006742: 78db ldrb r3, [r3, #3] 8006744: 2b02 cmp r3, #2 8006746: d10f bne.n 8006768 { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 8006748: 68bb ldr r3, [r7, #8] 800674a: 015a lsls r2, r3, #5 800674c: 68fb ldr r3, [r7, #12] 800674e: 4413 add r3, r2 8006750: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006754: 681b ldr r3, [r3, #0] 8006756: 68ba ldr r2, [r7, #8] 8006758: 0151 lsls r1, r2, #5 800675a: 68fa ldr r2, [r7, #12] 800675c: 440a add r2, r1 800675e: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006762: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8006766: 6013 str r3, [r2, #0] } } return HAL_OK; 8006768: 2300 movs r3, #0 } 800676a: 4618 mov r0, r3 800676c: 3714 adds r7, #20 800676e: 46bd mov sp, r7 8006770: f85d 7b04 ldr.w r7, [sp], #4 8006774: 4770 bx lr 08006776 : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) { 8006776: b480 push {r7} 8006778: b085 sub sp, #20 800677a: af00 add r7, sp, #0 800677c: 6078 str r0, [r7, #4] 800677e: 460b mov r3, r1 8006780: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8006782: 687b ldr r3, [r7, #4] 8006784: 60fb str r3, [r7, #12] USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); 8006786: 68fb ldr r3, [r7, #12] 8006788: f503 6300 add.w r3, r3, #2048 ; 0x800 800678c: 681b ldr r3, [r3, #0] 800678e: 68fa ldr r2, [r7, #12] 8006790: f502 6200 add.w r2, r2, #2048 ; 0x800 8006794: f423 63fe bic.w r3, r3, #2032 ; 0x7f0 8006798: 6013 str r3, [r2, #0] USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; 800679a: 68fb ldr r3, [r7, #12] 800679c: f503 6300 add.w r3, r3, #2048 ; 0x800 80067a0: 681a ldr r2, [r3, #0] 80067a2: 78fb ldrb r3, [r7, #3] 80067a4: 011b lsls r3, r3, #4 80067a6: f403 63fe and.w r3, r3, #2032 ; 0x7f0 80067aa: 68f9 ldr r1, [r7, #12] 80067ac: f501 6100 add.w r1, r1, #2048 ; 0x800 80067b0: 4313 orrs r3, r2 80067b2: 600b str r3, [r1, #0] return HAL_OK; 80067b4: 2300 movs r3, #0 } 80067b6: 4618 mov r0, r3 80067b8: 3714 adds r7, #20 80067ba: 46bd mov sp, r7 80067bc: f85d 7b04 ldr.w r7, [sp], #4 80067c0: 4770 bx lr 080067c2 : * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { 80067c2: b480 push {r7} 80067c4: b085 sub sp, #20 80067c6: af00 add r7, sp, #0 80067c8: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80067ca: 687b ldr r3, [r7, #4] 80067cc: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 80067ce: 68fb ldr r3, [r7, #12] 80067d0: f503 6360 add.w r3, r3, #3584 ; 0xe00 80067d4: 681b ldr r3, [r3, #0] 80067d6: 68fa ldr r2, [r7, #12] 80067d8: f502 6260 add.w r2, r2, #3584 ; 0xe00 80067dc: f023 0303 bic.w r3, r3, #3 80067e0: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; 80067e2: 68fb ldr r3, [r7, #12] 80067e4: f503 6300 add.w r3, r3, #2048 ; 0x800 80067e8: 685b ldr r3, [r3, #4] 80067ea: 68fa ldr r2, [r7, #12] 80067ec: f502 6200 add.w r2, r2, #2048 ; 0x800 80067f0: f023 0302 bic.w r3, r3, #2 80067f4: 6053 str r3, [r2, #4] return HAL_OK; 80067f6: 2300 movs r3, #0 } 80067f8: 4618 mov r0, r3 80067fa: 3714 adds r7, #20 80067fc: 46bd mov sp, r7 80067fe: f85d 7b04 ldr.w r7, [sp], #4 8006802: 4770 bx lr 08006804 : * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { 8006804: b480 push {r7} 8006806: b085 sub sp, #20 8006808: af00 add r7, sp, #0 800680a: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800680c: 687b ldr r3, [r7, #4] 800680e: 60fb str r3, [r7, #12] /* In case phy is stopped, ensure to ungate and restore the phy CLK */ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); 8006810: 68fb ldr r3, [r7, #12] 8006812: f503 6360 add.w r3, r3, #3584 ; 0xe00 8006816: 681b ldr r3, [r3, #0] 8006818: 68fa ldr r2, [r7, #12] 800681a: f502 6260 add.w r2, r2, #3584 ; 0xe00 800681e: f023 0303 bic.w r3, r3, #3 8006822: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; 8006824: 68fb ldr r3, [r7, #12] 8006826: f503 6300 add.w r3, r3, #2048 ; 0x800 800682a: 685b ldr r3, [r3, #4] 800682c: 68fa ldr r2, [r7, #12] 800682e: f502 6200 add.w r2, r2, #2048 ; 0x800 8006832: f043 0302 orr.w r3, r3, #2 8006836: 6053 str r3, [r2, #4] return HAL_OK; 8006838: 2300 movs r3, #0 } 800683a: 4618 mov r0, r3 800683c: 3714 adds r7, #20 800683e: 46bd mov sp, r7 8006840: f85d 7b04 ldr.w r7, [sp], #4 8006844: 4770 bx lr 08006846 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) { 8006846: b480 push {r7} 8006848: b085 sub sp, #20 800684a: af00 add r7, sp, #0 800684c: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 800684e: 687b ldr r3, [r7, #4] 8006850: 695b ldr r3, [r3, #20] 8006852: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8006854: 687b ldr r3, [r7, #4] 8006856: 699b ldr r3, [r3, #24] 8006858: 68fa ldr r2, [r7, #12] 800685a: 4013 ands r3, r2 800685c: 60fb str r3, [r7, #12] return tmpreg; 800685e: 68fb ldr r3, [r7, #12] } 8006860: 4618 mov r0, r3 8006862: 3714 adds r7, #20 8006864: 46bd mov sp, r7 8006866: f85d 7b04 ldr.w r7, [sp], #4 800686a: 4770 bx lr 0800686c : * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { 800686c: b480 push {r7} 800686e: b085 sub sp, #20 8006870: af00 add r7, sp, #0 8006872: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8006874: 687b ldr r3, [r7, #4] 8006876: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 8006878: 68fb ldr r3, [r7, #12] 800687a: f503 6300 add.w r3, r3, #2048 ; 0x800 800687e: 699b ldr r3, [r3, #24] 8006880: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 8006882: 68fb ldr r3, [r7, #12] 8006884: f503 6300 add.w r3, r3, #2048 ; 0x800 8006888: 69db ldr r3, [r3, #28] 800688a: 68ba ldr r2, [r7, #8] 800688c: 4013 ands r3, r2 800688e: 60bb str r3, [r7, #8] return ((tmpreg & 0xffff0000U) >> 16); 8006890: 68bb ldr r3, [r7, #8] 8006892: 0c1b lsrs r3, r3, #16 } 8006894: 4618 mov r0, r3 8006896: 3714 adds r7, #20 8006898: 46bd mov sp, r7 800689a: f85d 7b04 ldr.w r7, [sp], #4 800689e: 4770 bx lr 080068a0 : * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { 80068a0: b480 push {r7} 80068a2: b085 sub sp, #20 80068a4: af00 add r7, sp, #0 80068a6: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80068a8: 687b ldr r3, [r7, #4] 80068aa: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_DEVICE->DAINT; 80068ac: 68fb ldr r3, [r7, #12] 80068ae: f503 6300 add.w r3, r3, #2048 ; 0x800 80068b2: 699b ldr r3, [r3, #24] 80068b4: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DAINTMSK; 80068b6: 68fb ldr r3, [r7, #12] 80068b8: f503 6300 add.w r3, r3, #2048 ; 0x800 80068bc: 69db ldr r3, [r3, #28] 80068be: 68ba ldr r2, [r7, #8] 80068c0: 4013 ands r3, r2 80068c2: 60bb str r3, [r7, #8] return ((tmpreg & 0xFFFFU)); 80068c4: 68bb ldr r3, [r7, #8] 80068c6: b29b uxth r3, r3 } 80068c8: 4618 mov r0, r3 80068ca: 3714 adds r7, #20 80068cc: 46bd mov sp, r7 80068ce: f85d 7b04 ldr.w r7, [sp], #4 80068d2: 4770 bx lr 080068d4 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 80068d4: b480 push {r7} 80068d6: b085 sub sp, #20 80068d8: af00 add r7, sp, #0 80068da: 6078 str r0, [r7, #4] 80068dc: 460b mov r3, r1 80068de: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80068e0: 687b ldr r3, [r7, #4] 80068e2: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; 80068e4: 78fb ldrb r3, [r7, #3] 80068e6: 015a lsls r2, r3, #5 80068e8: 68fb ldr r3, [r7, #12] 80068ea: 4413 add r3, r2 80068ec: f503 6330 add.w r3, r3, #2816 ; 0xb00 80068f0: 689b ldr r3, [r3, #8] 80068f2: 60bb str r3, [r7, #8] tmpreg &= USBx_DEVICE->DOEPMSK; 80068f4: 68fb ldr r3, [r7, #12] 80068f6: f503 6300 add.w r3, r3, #2048 ; 0x800 80068fa: 695b ldr r3, [r3, #20] 80068fc: 68ba ldr r2, [r7, #8] 80068fe: 4013 ands r3, r2 8006900: 60bb str r3, [r7, #8] return tmpreg; 8006902: 68bb ldr r3, [r7, #8] } 8006904: 4618 mov r0, r3 8006906: 3714 adds r7, #20 8006908: 46bd mov sp, r7 800690a: f85d 7b04 ldr.w r7, [sp], #4 800690e: 4770 bx lr 08006910 : * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { 8006910: b480 push {r7} 8006912: b087 sub sp, #28 8006914: af00 add r7, sp, #0 8006916: 6078 str r0, [r7, #4] 8006918: 460b mov r3, r1 800691a: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800691c: 687b ldr r3, [r7, #4] 800691e: 617b str r3, [r7, #20] uint32_t tmpreg; uint32_t msk; uint32_t emp; msk = USBx_DEVICE->DIEPMSK; 8006920: 697b ldr r3, [r7, #20] 8006922: f503 6300 add.w r3, r3, #2048 ; 0x800 8006926: 691b ldr r3, [r3, #16] 8006928: 613b str r3, [r7, #16] emp = USBx_DEVICE->DIEPEMPMSK; 800692a: 697b ldr r3, [r7, #20] 800692c: f503 6300 add.w r3, r3, #2048 ; 0x800 8006930: 6b5b ldr r3, [r3, #52] ; 0x34 8006932: 60fb str r3, [r7, #12] msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; 8006934: 78fb ldrb r3, [r7, #3] 8006936: f003 030f and.w r3, r3, #15 800693a: 68fa ldr r2, [r7, #12] 800693c: fa22 f303 lsr.w r3, r2, r3 8006940: 01db lsls r3, r3, #7 8006942: b2db uxtb r3, r3 8006944: 693a ldr r2, [r7, #16] 8006946: 4313 orrs r3, r2 8006948: 613b str r3, [r7, #16] tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; 800694a: 78fb ldrb r3, [r7, #3] 800694c: 015a lsls r2, r3, #5 800694e: 697b ldr r3, [r7, #20] 8006950: 4413 add r3, r2 8006952: f503 6310 add.w r3, r3, #2304 ; 0x900 8006956: 689b ldr r3, [r3, #8] 8006958: 693a ldr r2, [r7, #16] 800695a: 4013 ands r3, r2 800695c: 60bb str r3, [r7, #8] return tmpreg; 800695e: 68bb ldr r3, [r7, #8] } 8006960: 4618 mov r0, r3 8006962: 371c adds r7, #28 8006964: 46bd mov sp, r7 8006966: f85d 7b04 ldr.w r7, [sp], #4 800696a: 4770 bx lr 0800696c : * This parameter can be one of these values: * 0 : Host * 1 : Device */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { 800696c: b480 push {r7} 800696e: b083 sub sp, #12 8006970: af00 add r7, sp, #0 8006972: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8006974: 687b ldr r3, [r7, #4] 8006976: 695b ldr r3, [r3, #20] 8006978: f003 0301 and.w r3, r3, #1 } 800697c: 4618 mov r0, r3 800697e: 370c adds r7, #12 8006980: 46bd mov sp, r7 8006982: f85d 7b04 ldr.w r7, [sp], #4 8006986: 4770 bx lr 08006988 : * @brief Activate EP0 for Setup transactions * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { 8006988: b480 push {r7} 800698a: b085 sub sp, #20 800698c: af00 add r7, sp, #0 800698e: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 8006990: 687b ldr r3, [r7, #4] 8006992: 60fb str r3, [r7, #12] /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 8006994: 68fb ldr r3, [r7, #12] 8006996: f503 6310 add.w r3, r3, #2304 ; 0x900 800699a: 681b ldr r3, [r3, #0] 800699c: 68fa ldr r2, [r7, #12] 800699e: f502 6210 add.w r2, r2, #2304 ; 0x900 80069a2: f423 63ff bic.w r3, r3, #2040 ; 0x7f8 80069a6: f023 0307 bic.w r3, r3, #7 80069aa: 6013 str r3, [r2, #0] USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 80069ac: 68fb ldr r3, [r7, #12] 80069ae: f503 6300 add.w r3, r3, #2048 ; 0x800 80069b2: 685b ldr r3, [r3, #4] 80069b4: 68fa ldr r2, [r7, #12] 80069b6: f502 6200 add.w r2, r2, #2048 ; 0x800 80069ba: f443 7380 orr.w r3, r3, #256 ; 0x100 80069be: 6053 str r3, [r2, #4] return HAL_OK; 80069c0: 2300 movs r3, #0 } 80069c2: 4618 mov r0, r3 80069c4: 3714 adds r7, #20 80069c6: 46bd mov sp, r7 80069c8: f85d 7b04 ldr.w r7, [sp], #4 80069cc: 4770 bx lr ... 080069d0 : * 1 : DMA feature used * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) { 80069d0: b480 push {r7} 80069d2: b087 sub sp, #28 80069d4: af00 add r7, sp, #0 80069d6: 60f8 str r0, [r7, #12] 80069d8: 460b mov r3, r1 80069da: 607a str r2, [r7, #4] 80069dc: 72fb strb r3, [r7, #11] uint32_t USBx_BASE = (uint32_t)USBx; 80069de: 68fb ldr r3, [r7, #12] 80069e0: 617b str r3, [r7, #20] uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); 80069e2: 68fb ldr r3, [r7, #12] 80069e4: 333c adds r3, #60 ; 0x3c 80069e6: 3304 adds r3, #4 80069e8: 681b ldr r3, [r3, #0] 80069ea: 613b str r3, [r7, #16] if (gSNPSiD > USB_OTG_CORE_ID_300A) 80069ec: 693b ldr r3, [r7, #16] 80069ee: 4a26 ldr r2, [pc, #152] ; (8006a88 ) 80069f0: 4293 cmp r3, r2 80069f2: d90a bls.n 8006a0a { if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 80069f4: 697b ldr r3, [r7, #20] 80069f6: f503 6330 add.w r3, r3, #2816 ; 0xb00 80069fa: 681b ldr r3, [r3, #0] 80069fc: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 8006a00: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8006a04: d101 bne.n 8006a0a { return HAL_OK; 8006a06: 2300 movs r3, #0 8006a08: e037 b.n 8006a7a } } USBx_OUTEP(0U)->DOEPTSIZ = 0U; 8006a0a: 697b ldr r3, [r7, #20] 8006a0c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a10: 461a mov r2, r3 8006a12: 2300 movs r3, #0 8006a14: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); 8006a16: 697b ldr r3, [r7, #20] 8006a18: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a1c: 691b ldr r3, [r3, #16] 8006a1e: 697a ldr r2, [r7, #20] 8006a20: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006a24: f443 2300 orr.w r3, r3, #524288 ; 0x80000 8006a28: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); 8006a2a: 697b ldr r3, [r7, #20] 8006a2c: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a30: 691b ldr r3, [r3, #16] 8006a32: 697a ldr r2, [r7, #20] 8006a34: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006a38: f043 0318 orr.w r3, r3, #24 8006a3c: 6113 str r3, [r2, #16] USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 8006a3e: 697b ldr r3, [r7, #20] 8006a40: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a44: 691b ldr r3, [r3, #16] 8006a46: 697a ldr r2, [r7, #20] 8006a48: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006a4c: f043 43c0 orr.w r3, r3, #1610612736 ; 0x60000000 8006a50: 6113 str r3, [r2, #16] if (dma == 1U) 8006a52: 7afb ldrb r3, [r7, #11] 8006a54: 2b01 cmp r3, #1 8006a56: d10f bne.n 8006a78 { USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; 8006a58: 697b ldr r3, [r7, #20] 8006a5a: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a5e: 461a mov r2, r3 8006a60: 687b ldr r3, [r7, #4] 8006a62: 6153 str r3, [r2, #20] /* EP enable */ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; 8006a64: 697b ldr r3, [r7, #20] 8006a66: f503 6330 add.w r3, r3, #2816 ; 0xb00 8006a6a: 681b ldr r3, [r3, #0] 8006a6c: 697a ldr r2, [r7, #20] 8006a6e: f502 6230 add.w r2, r2, #2816 ; 0xb00 8006a72: f043 2380 orr.w r3, r3, #2147516416 ; 0x80008000 8006a76: 6013 str r3, [r2, #0] } return HAL_OK; 8006a78: 2300 movs r3, #0 } 8006a7a: 4618 mov r0, r3 8006a7c: 371c adds r7, #28 8006a7e: 46bd mov sp, r7 8006a80: f85d 7b04 ldr.w r7, [sp], #4 8006a84: 4770 bx lr 8006a86: bf00 nop 8006a88: 4f54300a .word 0x4f54300a 08006a8c : * @brief Reset the USB Core (needed after USB clock settings change) * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { 8006a8c: b480 push {r7} 8006a8e: b085 sub sp, #20 8006a90: af00 add r7, sp, #0 8006a92: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8006a94: 2300 movs r3, #0 8006a96: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { if (++count > 200000U) 8006a98: 68fb ldr r3, [r7, #12] 8006a9a: 3301 adds r3, #1 8006a9c: 60fb str r3, [r7, #12] 8006a9e: 4a13 ldr r2, [pc, #76] ; (8006aec ) 8006aa0: 4293 cmp r3, r2 8006aa2: d901 bls.n 8006aa8 { return HAL_TIMEOUT; 8006aa4: 2303 movs r3, #3 8006aa6: e01a b.n 8006ade } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8006aa8: 687b ldr r3, [r7, #4] 8006aaa: 691b ldr r3, [r3, #16] 8006aac: 2b00 cmp r3, #0 8006aae: daf3 bge.n 8006a98 /* Core Soft Reset */ count = 0U; 8006ab0: 2300 movs r3, #0 8006ab2: 60fb str r3, [r7, #12] USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 8006ab4: 687b ldr r3, [r7, #4] 8006ab6: 691b ldr r3, [r3, #16] 8006ab8: f043 0201 orr.w r2, r3, #1 8006abc: 687b ldr r3, [r7, #4] 8006abe: 611a str r2, [r3, #16] do { if (++count > 200000U) 8006ac0: 68fb ldr r3, [r7, #12] 8006ac2: 3301 adds r3, #1 8006ac4: 60fb str r3, [r7, #12] 8006ac6: 4a09 ldr r2, [pc, #36] ; (8006aec ) 8006ac8: 4293 cmp r3, r2 8006aca: d901 bls.n 8006ad0 { return HAL_TIMEOUT; 8006acc: 2303 movs r3, #3 8006ace: e006 b.n 8006ade } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 8006ad0: 687b ldr r3, [r7, #4] 8006ad2: 691b ldr r3, [r3, #16] 8006ad4: f003 0301 and.w r3, r3, #1 8006ad8: 2b01 cmp r3, #1 8006ada: d0f1 beq.n 8006ac0 return HAL_OK; 8006adc: 2300 movs r3, #0 } 8006ade: 4618 mov r0, r3 8006ae0: 3714 adds r7, #20 8006ae2: 46bd mov sp, r7 8006ae4: f85d 7b04 ldr.w r7, [sp], #4 8006ae8: 4770 bx lr 8006aea: bf00 nop 8006aec: 00030d40 .word 0x00030d40 08006af0 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8006af0: b580 push {r7, lr} 8006af2: b084 sub sp, #16 8006af4: af00 add r7, sp, #0 8006af6: 6078 str r0, [r7, #4] 8006af8: 460b mov r3, r1 8006afa: 70fb strb r3, [r7, #3] UNUSED(cfgidx); USBD_CDC_HandleTypeDef *hcdc; hcdc = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); 8006afc: f44f 7007 mov.w r0, #540 ; 0x21c 8006b00: f002 f9b2 bl 8008e68 8006b04: 60f8 str r0, [r7, #12] if (hcdc == NULL) 8006b06: 68fb ldr r3, [r7, #12] 8006b08: 2b00 cmp r3, #0 8006b0a: d105 bne.n 8006b18 { pdev->pClassData = NULL; 8006b0c: 687b ldr r3, [r7, #4] 8006b0e: 2200 movs r2, #0 8006b10: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc return (uint8_t)USBD_EMEM; 8006b14: 2302 movs r3, #2 8006b16: e066 b.n 8006be6 } pdev->pClassData = (void *)hcdc; 8006b18: 687b ldr r3, [r7, #4] 8006b1a: 68fa ldr r2, [r7, #12] 8006b1c: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc if (pdev->dev_speed == USBD_SPEED_HIGH) 8006b20: 687b ldr r3, [r7, #4] 8006b22: 7c1b ldrb r3, [r3, #16] 8006b24: 2b00 cmp r3, #0 8006b26: d119 bne.n 8006b5c { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 8006b28: f44f 7300 mov.w r3, #512 ; 0x200 8006b2c: 2202 movs r2, #2 8006b2e: 2181 movs r1, #129 ; 0x81 8006b30: 6878 ldr r0, [r7, #4] 8006b32: f002 f828 bl 8008b86 CDC_DATA_HS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 8006b36: 687b ldr r3, [r7, #4] 8006b38: 2201 movs r2, #1 8006b3a: 871a strh r2, [r3, #56] ; 0x38 /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 8006b3c: f44f 7300 mov.w r3, #512 ; 0x200 8006b40: 2202 movs r2, #2 8006b42: 2101 movs r1, #1 8006b44: 6878 ldr r0, [r7, #4] 8006b46: f002 f81e bl 8008b86 CDC_DATA_HS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 8006b4a: 687b ldr r3, [r7, #4] 8006b4c: 2201 movs r2, #1 8006b4e: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Set bInterval for CDC CMD Endpoint */ pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_HS_BINTERVAL; 8006b52: 687b ldr r3, [r7, #4] 8006b54: 2210 movs r2, #16 8006b56: f8a3 204e strh.w r2, [r3, #78] ; 0x4e 8006b5a: e016 b.n 8006b8a } else { /* Open EP IN */ (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, 8006b5c: 2340 movs r3, #64 ; 0x40 8006b5e: 2202 movs r2, #2 8006b60: 2181 movs r1, #129 ; 0x81 8006b62: 6878 ldr r0, [r7, #4] 8006b64: f002 f80f bl 8008b86 CDC_DATA_FS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; 8006b68: 687b ldr r3, [r7, #4] 8006b6a: 2201 movs r2, #1 8006b6c: 871a strh r2, [r3, #56] ; 0x38 /* Open EP OUT */ (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, 8006b6e: 2340 movs r3, #64 ; 0x40 8006b70: 2202 movs r2, #2 8006b72: 2101 movs r1, #1 8006b74: 6878 ldr r0, [r7, #4] 8006b76: f002 f806 bl 8008b86 CDC_DATA_FS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; 8006b7a: 687b ldr r3, [r7, #4] 8006b7c: 2201 movs r2, #1 8006b7e: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Set bInterval for CMD Endpoint */ pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_FS_BINTERVAL; 8006b82: 687b ldr r3, [r7, #4] 8006b84: 2210 movs r2, #16 8006b86: f8a3 204e strh.w r2, [r3, #78] ; 0x4e } /* Open Command IN EP */ (void)USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); 8006b8a: 2308 movs r3, #8 8006b8c: 2203 movs r2, #3 8006b8e: 2182 movs r1, #130 ; 0x82 8006b90: 6878 ldr r0, [r7, #4] 8006b92: f001 fff8 bl 8008b86 pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; 8006b96: 687b ldr r3, [r7, #4] 8006b98: 2201 movs r2, #1 8006b9a: f8a3 204c strh.w r2, [r3, #76] ; 0x4c /* Init physical Interface components */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); 8006b9e: 687b ldr r3, [r7, #4] 8006ba0: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006ba4: 681b ldr r3, [r3, #0] 8006ba6: 4798 blx r3 /* Init Xfer states */ hcdc->TxState = 0U; 8006ba8: 68fb ldr r3, [r7, #12] 8006baa: 2200 movs r2, #0 8006bac: f8c3 2214 str.w r2, [r3, #532] ; 0x214 hcdc->RxState = 0U; 8006bb0: 68fb ldr r3, [r7, #12] 8006bb2: 2200 movs r2, #0 8006bb4: f8c3 2218 str.w r2, [r3, #536] ; 0x218 if (pdev->dev_speed == USBD_SPEED_HIGH) 8006bb8: 687b ldr r3, [r7, #4] 8006bba: 7c1b ldrb r3, [r3, #16] 8006bbc: 2b00 cmp r3, #0 8006bbe: d109 bne.n 8006bd4 { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8006bc0: 68fb ldr r3, [r7, #12] 8006bc2: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8006bc6: f44f 7300 mov.w r3, #512 ; 0x200 8006bca: 2101 movs r1, #1 8006bcc: 6878 ldr r0, [r7, #4] 8006bce: f002 f8c9 bl 8008d64 8006bd2: e007 b.n 8006be4 CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 8006bd4: 68fb ldr r3, [r7, #12] 8006bd6: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 8006bda: 2340 movs r3, #64 ; 0x40 8006bdc: 2101 movs r1, #1 8006bde: 6878 ldr r0, [r7, #4] 8006be0: f002 f8c0 bl 8008d64 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 8006be4: 2300 movs r3, #0 } 8006be6: 4618 mov r0, r3 8006be8: 3710 adds r7, #16 8006bea: 46bd mov sp, r7 8006bec: bd80 pop {r7, pc} 08006bee : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 8006bee: b580 push {r7, lr} 8006bf0: b082 sub sp, #8 8006bf2: af00 add r7, sp, #0 8006bf4: 6078 str r0, [r7, #4] 8006bf6: 460b mov r3, r1 8006bf8: 70fb strb r3, [r7, #3] UNUSED(cfgidx); /* Close EP IN */ (void)USBD_LL_CloseEP(pdev, CDC_IN_EP); 8006bfa: 2181 movs r1, #129 ; 0x81 8006bfc: 6878 ldr r0, [r7, #4] 8006bfe: f001 ffe8 bl 8008bd2 pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; 8006c02: 687b ldr r3, [r7, #4] 8006c04: 2200 movs r2, #0 8006c06: 871a strh r2, [r3, #56] ; 0x38 /* Close EP OUT */ (void)USBD_LL_CloseEP(pdev, CDC_OUT_EP); 8006c08: 2101 movs r1, #1 8006c0a: 6878 ldr r0, [r7, #4] 8006c0c: f001 ffe1 bl 8008bd2 pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; 8006c10: 687b ldr r3, [r7, #4] 8006c12: 2200 movs r2, #0 8006c14: f8a3 2178 strh.w r2, [r3, #376] ; 0x178 /* Close Command IN EP */ (void)USBD_LL_CloseEP(pdev, CDC_CMD_EP); 8006c18: 2182 movs r1, #130 ; 0x82 8006c1a: 6878 ldr r0, [r7, #4] 8006c1c: f001 ffd9 bl 8008bd2 pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; 8006c20: 687b ldr r3, [r7, #4] 8006c22: 2200 movs r2, #0 8006c24: f8a3 204c strh.w r2, [r3, #76] ; 0x4c pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = 0U; 8006c28: 687b ldr r3, [r7, #4] 8006c2a: 2200 movs r2, #0 8006c2c: f8a3 204e strh.w r2, [r3, #78] ; 0x4e /* DeInit physical Interface components */ if (pdev->pClassData != NULL) 8006c30: 687b ldr r3, [r7, #4] 8006c32: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006c36: 2b00 cmp r3, #0 8006c38: d00e beq.n 8006c58 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); 8006c3a: 687b ldr r3, [r7, #4] 8006c3c: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006c40: 685b ldr r3, [r3, #4] 8006c42: 4798 blx r3 (void)USBD_free(pdev->pClassData); 8006c44: 687b ldr r3, [r7, #4] 8006c46: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006c4a: 4618 mov r0, r3 8006c4c: f002 f91a bl 8008e84 pdev->pClassData = NULL; 8006c50: 687b ldr r3, [r7, #4] 8006c52: 2200 movs r2, #0 8006c54: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc } return (uint8_t)USBD_OK; 8006c58: 2300 movs r3, #0 } 8006c5a: 4618 mov r0, r3 8006c5c: 3708 adds r7, #8 8006c5e: 46bd mov sp, r7 8006c60: bd80 pop {r7, pc} ... 08006c64 : * @param req: usb requests * @retval status */ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8006c64: b580 push {r7, lr} 8006c66: b086 sub sp, #24 8006c68: af00 add r7, sp, #0 8006c6a: 6078 str r0, [r7, #4] 8006c6c: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8006c6e: 687b ldr r3, [r7, #4] 8006c70: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006c74: 613b str r3, [r7, #16] uint16_t len; uint8_t ifalt = 0U; 8006c76: 2300 movs r3, #0 8006c78: 737b strb r3, [r7, #13] uint16_t status_info = 0U; 8006c7a: 2300 movs r3, #0 8006c7c: 817b strh r3, [r7, #10] USBD_StatusTypeDef ret = USBD_OK; 8006c7e: 2300 movs r3, #0 8006c80: 75fb strb r3, [r7, #23] if (hcdc == NULL) 8006c82: 693b ldr r3, [r7, #16] 8006c84: 2b00 cmp r3, #0 8006c86: d101 bne.n 8006c8c { return (uint8_t)USBD_FAIL; 8006c88: 2303 movs r3, #3 8006c8a: e0af b.n 8006dec } switch (req->bmRequest & USB_REQ_TYPE_MASK) 8006c8c: 683b ldr r3, [r7, #0] 8006c8e: 781b ldrb r3, [r3, #0] 8006c90: f003 0360 and.w r3, r3, #96 ; 0x60 8006c94: 2b00 cmp r3, #0 8006c96: d03f beq.n 8006d18 8006c98: 2b20 cmp r3, #32 8006c9a: f040 809f bne.w 8006ddc { case USB_REQ_TYPE_CLASS: if (req->wLength != 0U) 8006c9e: 683b ldr r3, [r7, #0] 8006ca0: 88db ldrh r3, [r3, #6] 8006ca2: 2b00 cmp r3, #0 8006ca4: d02e beq.n 8006d04 { if ((req->bmRequest & 0x80U) != 0U) 8006ca6: 683b ldr r3, [r7, #0] 8006ca8: 781b ldrb r3, [r3, #0] 8006caa: b25b sxtb r3, r3 8006cac: 2b00 cmp r3, #0 8006cae: da16 bge.n 8006cde { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 8006cb0: 687b ldr r3, [r7, #4] 8006cb2: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006cb6: 689b ldr r3, [r3, #8] 8006cb8: 683a ldr r2, [r7, #0] 8006cba: 7850 ldrb r0, [r2, #1] (uint8_t *)hcdc->data, 8006cbc: 6939 ldr r1, [r7, #16] ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 8006cbe: 683a ldr r2, [r7, #0] 8006cc0: 88d2 ldrh r2, [r2, #6] 8006cc2: 4798 blx r3 req->wLength); len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength); 8006cc4: 683b ldr r3, [r7, #0] 8006cc6: 88db ldrh r3, [r3, #6] 8006cc8: 2b07 cmp r3, #7 8006cca: bf28 it cs 8006ccc: 2307 movcs r3, #7 8006cce: 81fb strh r3, [r7, #14] (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len); 8006cd0: 693b ldr r3, [r7, #16] 8006cd2: 89fa ldrh r2, [r7, #14] 8006cd4: 4619 mov r1, r3 8006cd6: 6878 ldr r0, [r7, #4] 8006cd8: f001 fb13 bl 8008302 else { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, (uint8_t *)req, 0U); } break; 8006cdc: e085 b.n 8006dea hcdc->CmdOpCode = req->bRequest; 8006cde: 683b ldr r3, [r7, #0] 8006ce0: 785a ldrb r2, [r3, #1] 8006ce2: 693b ldr r3, [r7, #16] 8006ce4: f883 2200 strb.w r2, [r3, #512] ; 0x200 hcdc->CmdLength = (uint8_t)req->wLength; 8006ce8: 683b ldr r3, [r7, #0] 8006cea: 88db ldrh r3, [r3, #6] 8006cec: b2da uxtb r2, r3 8006cee: 693b ldr r3, [r7, #16] 8006cf0: f883 2201 strb.w r2, [r3, #513] ; 0x201 (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength); 8006cf4: 6939 ldr r1, [r7, #16] 8006cf6: 683b ldr r3, [r7, #0] 8006cf8: 88db ldrh r3, [r3, #6] 8006cfa: 461a mov r2, r3 8006cfc: 6878 ldr r0, [r7, #4] 8006cfe: f001 fb2c bl 800835a break; 8006d02: e072 b.n 8006dea ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, 8006d04: 687b ldr r3, [r7, #4] 8006d06: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006d0a: 689b ldr r3, [r3, #8] 8006d0c: 683a ldr r2, [r7, #0] 8006d0e: 7850 ldrb r0, [r2, #1] 8006d10: 2200 movs r2, #0 8006d12: 6839 ldr r1, [r7, #0] 8006d14: 4798 blx r3 break; 8006d16: e068 b.n 8006dea case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8006d18: 683b ldr r3, [r7, #0] 8006d1a: 785b ldrb r3, [r3, #1] 8006d1c: 2b0b cmp r3, #11 8006d1e: d852 bhi.n 8006dc6 8006d20: a201 add r2, pc, #4 ; (adr r2, 8006d28 ) 8006d22: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006d26: bf00 nop 8006d28: 08006d59 .word 0x08006d59 8006d2c: 08006dd5 .word 0x08006dd5 8006d30: 08006dc7 .word 0x08006dc7 8006d34: 08006dc7 .word 0x08006dc7 8006d38: 08006dc7 .word 0x08006dc7 8006d3c: 08006dc7 .word 0x08006dc7 8006d40: 08006dc7 .word 0x08006dc7 8006d44: 08006dc7 .word 0x08006dc7 8006d48: 08006dc7 .word 0x08006dc7 8006d4c: 08006dc7 .word 0x08006dc7 8006d50: 08006d83 .word 0x08006d83 8006d54: 08006dad .word 0x08006dad { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8006d58: 687b ldr r3, [r7, #4] 8006d5a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8006d5e: b2db uxtb r3, r3 8006d60: 2b03 cmp r3, #3 8006d62: d107 bne.n 8006d74 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); 8006d64: f107 030a add.w r3, r7, #10 8006d68: 2202 movs r2, #2 8006d6a: 4619 mov r1, r3 8006d6c: 6878 ldr r0, [r7, #4] 8006d6e: f001 fac8 bl 8008302 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8006d72: e032 b.n 8006dda USBD_CtlError(pdev, req); 8006d74: 6839 ldr r1, [r7, #0] 8006d76: 6878 ldr r0, [r7, #4] 8006d78: f001 fa52 bl 8008220 ret = USBD_FAIL; 8006d7c: 2303 movs r3, #3 8006d7e: 75fb strb r3, [r7, #23] break; 8006d80: e02b b.n 8006dda case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) 8006d82: 687b ldr r3, [r7, #4] 8006d84: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8006d88: b2db uxtb r3, r3 8006d8a: 2b03 cmp r3, #3 8006d8c: d107 bne.n 8006d9e { (void)USBD_CtlSendData(pdev, &ifalt, 1U); 8006d8e: f107 030d add.w r3, r7, #13 8006d92: 2201 movs r2, #1 8006d94: 4619 mov r1, r3 8006d96: 6878 ldr r0, [r7, #4] 8006d98: f001 fab3 bl 8008302 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; 8006d9c: e01d b.n 8006dda USBD_CtlError(pdev, req); 8006d9e: 6839 ldr r1, [r7, #0] 8006da0: 6878 ldr r0, [r7, #4] 8006da2: f001 fa3d bl 8008220 ret = USBD_FAIL; 8006da6: 2303 movs r3, #3 8006da8: 75fb strb r3, [r7, #23] break; 8006daa: e016 b.n 8006dda case USB_REQ_SET_INTERFACE: if (pdev->dev_state != USBD_STATE_CONFIGURED) 8006dac: 687b ldr r3, [r7, #4] 8006dae: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8006db2: b2db uxtb r3, r3 8006db4: 2b03 cmp r3, #3 8006db6: d00f beq.n 8006dd8 { USBD_CtlError(pdev, req); 8006db8: 6839 ldr r1, [r7, #0] 8006dba: 6878 ldr r0, [r7, #4] 8006dbc: f001 fa30 bl 8008220 ret = USBD_FAIL; 8006dc0: 2303 movs r3, #3 8006dc2: 75fb strb r3, [r7, #23] } break; 8006dc4: e008 b.n 8006dd8 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); 8006dc6: 6839 ldr r1, [r7, #0] 8006dc8: 6878 ldr r0, [r7, #4] 8006dca: f001 fa29 bl 8008220 ret = USBD_FAIL; 8006dce: 2303 movs r3, #3 8006dd0: 75fb strb r3, [r7, #23] break; 8006dd2: e002 b.n 8006dda break; 8006dd4: bf00 nop 8006dd6: e008 b.n 8006dea break; 8006dd8: bf00 nop } break; 8006dda: e006 b.n 8006dea default: USBD_CtlError(pdev, req); 8006ddc: 6839 ldr r1, [r7, #0] 8006dde: 6878 ldr r0, [r7, #4] 8006de0: f001 fa1e bl 8008220 ret = USBD_FAIL; 8006de4: 2303 movs r3, #3 8006de6: 75fb strb r3, [r7, #23] break; 8006de8: bf00 nop } return (uint8_t)ret; 8006dea: 7dfb ldrb r3, [r7, #23] } 8006dec: 4618 mov r0, r3 8006dee: 3718 adds r7, #24 8006df0: 46bd mov sp, r7 8006df2: bd80 pop {r7, pc} 08006df4 : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8006df4: b580 push {r7, lr} 8006df6: b084 sub sp, #16 8006df8: af00 add r7, sp, #0 8006dfa: 6078 str r0, [r7, #4] 8006dfc: 460b mov r3, r1 8006dfe: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc; PCD_HandleTypeDef *hpcd = pdev->pData; 8006e00: 687b ldr r3, [r7, #4] 8006e02: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8006e06: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 8006e08: 687b ldr r3, [r7, #4] 8006e0a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006e0e: 2b00 cmp r3, #0 8006e10: d101 bne.n 8006e16 { return (uint8_t)USBD_FAIL; 8006e12: 2303 movs r3, #3 8006e14: e04f b.n 8006eb6 } hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8006e16: 687b ldr r3, [r7, #4] 8006e18: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006e1c: 60bb str r3, [r7, #8] if ((pdev->ep_in[epnum].total_length > 0U) && 8006e1e: 78fa ldrb r2, [r7, #3] 8006e20: 6879 ldr r1, [r7, #4] 8006e22: 4613 mov r3, r2 8006e24: 009b lsls r3, r3, #2 8006e26: 4413 add r3, r2 8006e28: 009b lsls r3, r3, #2 8006e2a: 440b add r3, r1 8006e2c: 3318 adds r3, #24 8006e2e: 681b ldr r3, [r3, #0] 8006e30: 2b00 cmp r3, #0 8006e32: d029 beq.n 8006e88 ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) 8006e34: 78fa ldrb r2, [r7, #3] 8006e36: 6879 ldr r1, [r7, #4] 8006e38: 4613 mov r3, r2 8006e3a: 009b lsls r3, r3, #2 8006e3c: 4413 add r3, r2 8006e3e: 009b lsls r3, r3, #2 8006e40: 440b add r3, r1 8006e42: 3318 adds r3, #24 8006e44: 681a ldr r2, [r3, #0] 8006e46: 78f9 ldrb r1, [r7, #3] 8006e48: 68f8 ldr r0, [r7, #12] 8006e4a: 460b mov r3, r1 8006e4c: 00db lsls r3, r3, #3 8006e4e: 1a5b subs r3, r3, r1 8006e50: 009b lsls r3, r3, #2 8006e52: 4403 add r3, r0 8006e54: 3344 adds r3, #68 ; 0x44 8006e56: 681b ldr r3, [r3, #0] 8006e58: fbb2 f1f3 udiv r1, r2, r3 8006e5c: fb03 f301 mul.w r3, r3, r1 8006e60: 1ad3 subs r3, r2, r3 if ((pdev->ep_in[epnum].total_length > 0U) && 8006e62: 2b00 cmp r3, #0 8006e64: d110 bne.n 8006e88 { /* Update the packet total length */ pdev->ep_in[epnum].total_length = 0U; 8006e66: 78fa ldrb r2, [r7, #3] 8006e68: 6879 ldr r1, [r7, #4] 8006e6a: 4613 mov r3, r2 8006e6c: 009b lsls r3, r3, #2 8006e6e: 4413 add r3, r2 8006e70: 009b lsls r3, r3, #2 8006e72: 440b add r3, r1 8006e74: 3318 adds r3, #24 8006e76: 2200 movs r2, #0 8006e78: 601a str r2, [r3, #0] /* Send ZLP */ (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); 8006e7a: 78f9 ldrb r1, [r7, #3] 8006e7c: 2300 movs r3, #0 8006e7e: 2200 movs r2, #0 8006e80: 6878 ldr r0, [r7, #4] 8006e82: f001 ff4e bl 8008d22 8006e86: e015 b.n 8006eb4 } else { hcdc->TxState = 0U; 8006e88: 68bb ldr r3, [r7, #8] 8006e8a: 2200 movs r2, #0 8006e8c: f8c3 2214 str.w r2, [r3, #532] ; 0x214 if (((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt != NULL) 8006e90: 687b ldr r3, [r7, #4] 8006e92: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006e96: 691b ldr r3, [r3, #16] 8006e98: 2b00 cmp r3, #0 8006e9a: d00b beq.n 8006eb4 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); 8006e9c: 687b ldr r3, [r7, #4] 8006e9e: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006ea2: 691b ldr r3, [r3, #16] 8006ea4: 68ba ldr r2, [r7, #8] 8006ea6: f8d2 0208 ldr.w r0, [r2, #520] ; 0x208 8006eaa: 68ba ldr r2, [r7, #8] 8006eac: f502 7104 add.w r1, r2, #528 ; 0x210 8006eb0: 78fa ldrb r2, [r7, #3] 8006eb2: 4798 blx r3 } } return (uint8_t)USBD_OK; 8006eb4: 2300 movs r3, #0 } 8006eb6: 4618 mov r0, r3 8006eb8: 3710 adds r7, #16 8006eba: 46bd mov sp, r7 8006ebc: bd80 pop {r7, pc} 08006ebe : * @param pdev: device instance * @param epnum: endpoint number * @retval status */ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8006ebe: b580 push {r7, lr} 8006ec0: b084 sub sp, #16 8006ec2: af00 add r7, sp, #0 8006ec4: 6078 str r0, [r7, #4] 8006ec6: 460b mov r3, r1 8006ec8: 70fb strb r3, [r7, #3] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8006eca: 687b ldr r3, [r7, #4] 8006ecc: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006ed0: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 8006ed2: 687b ldr r3, [r7, #4] 8006ed4: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006ed8: 2b00 cmp r3, #0 8006eda: d101 bne.n 8006ee0 { return (uint8_t)USBD_FAIL; 8006edc: 2303 movs r3, #3 8006ede: e015 b.n 8006f0c } /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); 8006ee0: 78fb ldrb r3, [r7, #3] 8006ee2: 4619 mov r1, r3 8006ee4: 6878 ldr r0, [r7, #4] 8006ee6: f001 ff5e bl 8008da6 8006eea: 4602 mov r2, r0 8006eec: 68fb ldr r3, [r7, #12] 8006eee: f8c3 220c str.w r2, [r3, #524] ; 0x20c /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); 8006ef2: 687b ldr r3, [r7, #4] 8006ef4: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006ef8: 68db ldr r3, [r3, #12] 8006efa: 68fa ldr r2, [r7, #12] 8006efc: f8d2 0204 ldr.w r0, [r2, #516] ; 0x204 8006f00: 68fa ldr r2, [r7, #12] 8006f02: f502 7203 add.w r2, r2, #524 ; 0x20c 8006f06: 4611 mov r1, r2 8006f08: 4798 blx r3 return (uint8_t)USBD_OK; 8006f0a: 2300 movs r3, #0 } 8006f0c: 4618 mov r0, r3 8006f0e: 3710 adds r7, #16 8006f10: 46bd mov sp, r7 8006f12: bd80 pop {r7, pc} 08006f14 : * Handle EP0 Rx Ready event * @param pdev: device instance * @retval status */ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { 8006f14: b580 push {r7, lr} 8006f16: b084 sub sp, #16 8006f18: af00 add r7, sp, #0 8006f1a: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8006f1c: 687b ldr r3, [r7, #4] 8006f1e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8006f22: 60fb str r3, [r7, #12] if (hcdc == NULL) 8006f24: 68fb ldr r3, [r7, #12] 8006f26: 2b00 cmp r3, #0 8006f28: d101 bne.n 8006f2e { return (uint8_t)USBD_FAIL; 8006f2a: 2303 movs r3, #3 8006f2c: e01b b.n 8006f66 } if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) 8006f2e: 687b ldr r3, [r7, #4] 8006f30: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006f34: 2b00 cmp r3, #0 8006f36: d015 beq.n 8006f64 8006f38: 68fb ldr r3, [r7, #12] 8006f3a: f893 3200 ldrb.w r3, [r3, #512] ; 0x200 8006f3e: 2bff cmp r3, #255 ; 0xff 8006f40: d010 beq.n 8006f64 { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 8006f42: 687b ldr r3, [r7, #4] 8006f44: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 8006f48: 689b ldr r3, [r3, #8] 8006f4a: 68fa ldr r2, [r7, #12] 8006f4c: f892 0200 ldrb.w r0, [r2, #512] ; 0x200 (uint8_t *)hcdc->data, 8006f50: 68f9 ldr r1, [r7, #12] (uint16_t)hcdc->CmdLength); 8006f52: 68fa ldr r2, [r7, #12] 8006f54: f892 2201 ldrb.w r2, [r2, #513] ; 0x201 ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, 8006f58: b292 uxth r2, r2 8006f5a: 4798 blx r3 hcdc->CmdOpCode = 0xFFU; 8006f5c: 68fb ldr r3, [r7, #12] 8006f5e: 22ff movs r2, #255 ; 0xff 8006f60: f883 2200 strb.w r2, [r3, #512] ; 0x200 } return (uint8_t)USBD_OK; 8006f64: 2300 movs r3, #0 } 8006f66: 4618 mov r0, r3 8006f68: 3710 adds r7, #16 8006f6a: 46bd mov sp, r7 8006f6c: bd80 pop {r7, pc} ... 08006f70 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { 8006f70: b480 push {r7} 8006f72: b083 sub sp, #12 8006f74: af00 add r7, sp, #0 8006f76: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_CfgFSDesc); 8006f78: 687b ldr r3, [r7, #4] 8006f7a: 2243 movs r2, #67 ; 0x43 8006f7c: 801a strh r2, [r3, #0] return USBD_CDC_CfgFSDesc; 8006f7e: 4b03 ldr r3, [pc, #12] ; (8006f8c ) } 8006f80: 4618 mov r0, r3 8006f82: 370c adds r7, #12 8006f84: 46bd mov sp, r7 8006f86: f85d 7b04 ldr.w r7, [sp], #4 8006f8a: 4770 bx lr 8006f8c: 20000094 .word 0x20000094 08006f90 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { 8006f90: b480 push {r7} 8006f92: b083 sub sp, #12 8006f94: af00 add r7, sp, #0 8006f96: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_CfgHSDesc); 8006f98: 687b ldr r3, [r7, #4] 8006f9a: 2243 movs r2, #67 ; 0x43 8006f9c: 801a strh r2, [r3, #0] return USBD_CDC_CfgHSDesc; 8006f9e: 4b03 ldr r3, [pc, #12] ; (8006fac ) } 8006fa0: 4618 mov r0, r3 8006fa2: 370c adds r7, #12 8006fa4: 46bd mov sp, r7 8006fa6: f85d 7b04 ldr.w r7, [sp], #4 8006faa: 4770 bx lr 8006fac: 20000050 .word 0x20000050 08006fb0 : * @param speed : current device speed * @param length : pointer data length * @retval pointer to descriptor buffer */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { 8006fb0: b480 push {r7} 8006fb2: b083 sub sp, #12 8006fb4: af00 add r7, sp, #0 8006fb6: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_OtherSpeedCfgDesc); 8006fb8: 687b ldr r3, [r7, #4] 8006fba: 2243 movs r2, #67 ; 0x43 8006fbc: 801a strh r2, [r3, #0] return USBD_CDC_OtherSpeedCfgDesc; 8006fbe: 4b03 ldr r3, [pc, #12] ; (8006fcc ) } 8006fc0: 4618 mov r0, r3 8006fc2: 370c adds r7, #12 8006fc4: 46bd mov sp, r7 8006fc6: f85d 7b04 ldr.w r7, [sp], #4 8006fca: 4770 bx lr 8006fcc: 200000d8 .word 0x200000d8 08006fd0 : * return Device Qualifier descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { 8006fd0: b480 push {r7} 8006fd2: b083 sub sp, #12 8006fd4: af00 add r7, sp, #0 8006fd6: 6078 str r0, [r7, #4] *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); 8006fd8: 687b ldr r3, [r7, #4] 8006fda: 220a movs r2, #10 8006fdc: 801a strh r2, [r3, #0] return USBD_CDC_DeviceQualifierDesc; 8006fde: 4b03 ldr r3, [pc, #12] ; (8006fec ) } 8006fe0: 4618 mov r0, r3 8006fe2: 370c adds r7, #12 8006fe4: 46bd mov sp, r7 8006fe6: f85d 7b04 ldr.w r7, [sp], #4 8006fea: 4770 bx lr 8006fec: 2000000c .word 0x2000000c 08006ff0 : * @param fops: CD Interface callback * @retval status */ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) { 8006ff0: b480 push {r7} 8006ff2: b083 sub sp, #12 8006ff4: af00 add r7, sp, #0 8006ff6: 6078 str r0, [r7, #4] 8006ff8: 6039 str r1, [r7, #0] if (fops == NULL) 8006ffa: 683b ldr r3, [r7, #0] 8006ffc: 2b00 cmp r3, #0 8006ffe: d101 bne.n 8007004 { return (uint8_t)USBD_FAIL; 8007000: 2303 movs r3, #3 8007002: e004 b.n 800700e } pdev->pUserData = fops; 8007004: 687b ldr r3, [r7, #4] 8007006: 683a ldr r2, [r7, #0] 8007008: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0 return (uint8_t)USBD_OK; 800700c: 2300 movs r3, #0 } 800700e: 4618 mov r0, r3 8007010: 370c adds r7, #12 8007012: 46bd mov sp, r7 8007014: f85d 7b04 ldr.w r7, [sp], #4 8007018: 4770 bx lr 0800701a : * @param pbuff: Tx Buffer * @retval status */ uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint32_t length) { 800701a: b480 push {r7} 800701c: b087 sub sp, #28 800701e: af00 add r7, sp, #0 8007020: 60f8 str r0, [r7, #12] 8007022: 60b9 str r1, [r7, #8] 8007024: 607a str r2, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007026: 68fb ldr r3, [r7, #12] 8007028: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 800702c: 617b str r3, [r7, #20] if (hcdc == NULL) 800702e: 697b ldr r3, [r7, #20] 8007030: 2b00 cmp r3, #0 8007032: d101 bne.n 8007038 { return (uint8_t)USBD_FAIL; 8007034: 2303 movs r3, #3 8007036: e008 b.n 800704a } hcdc->TxBuffer = pbuff; 8007038: 697b ldr r3, [r7, #20] 800703a: 68ba ldr r2, [r7, #8] 800703c: f8c3 2208 str.w r2, [r3, #520] ; 0x208 hcdc->TxLength = length; 8007040: 697b ldr r3, [r7, #20] 8007042: 687a ldr r2, [r7, #4] 8007044: f8c3 2210 str.w r2, [r3, #528] ; 0x210 return (uint8_t)USBD_OK; 8007048: 2300 movs r3, #0 } 800704a: 4618 mov r0, r3 800704c: 371c adds r7, #28 800704e: 46bd mov sp, r7 8007050: f85d 7b04 ldr.w r7, [sp], #4 8007054: 4770 bx lr 08007056 : * @param pdev: device instance * @param pbuff: Rx Buffer * @retval status */ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { 8007056: b480 push {r7} 8007058: b085 sub sp, #20 800705a: af00 add r7, sp, #0 800705c: 6078 str r0, [r7, #4] 800705e: 6039 str r1, [r7, #0] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007060: 687b ldr r3, [r7, #4] 8007062: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007066: 60fb str r3, [r7, #12] if (hcdc == NULL) 8007068: 68fb ldr r3, [r7, #12] 800706a: 2b00 cmp r3, #0 800706c: d101 bne.n 8007072 { return (uint8_t)USBD_FAIL; 800706e: 2303 movs r3, #3 8007070: e004 b.n 800707c } hcdc->RxBuffer = pbuff; 8007072: 68fb ldr r3, [r7, #12] 8007074: 683a ldr r2, [r7, #0] 8007076: f8c3 2204 str.w r2, [r3, #516] ; 0x204 return (uint8_t)USBD_OK; 800707a: 2300 movs r3, #0 } 800707c: 4618 mov r0, r3 800707e: 3714 adds r7, #20 8007080: 46bd mov sp, r7 8007082: f85d 7b04 ldr.w r7, [sp], #4 8007086: 4770 bx lr 08007088 : * prepare OUT Endpoint for reception * @param pdev: device instance * @retval status */ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { 8007088: b580 push {r7, lr} 800708a: b084 sub sp, #16 800708c: af00 add r7, sp, #0 800708e: 6078 str r0, [r7, #4] USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; 8007090: 687b ldr r3, [r7, #4] 8007092: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 8007096: 60fb str r3, [r7, #12] if (pdev->pClassData == NULL) 8007098: 687b ldr r3, [r7, #4] 800709a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 800709e: 2b00 cmp r3, #0 80070a0: d101 bne.n 80070a6 { return (uint8_t)USBD_FAIL; 80070a2: 2303 movs r3, #3 80070a4: e016 b.n 80070d4 } if (pdev->dev_speed == USBD_SPEED_HIGH) 80070a6: 687b ldr r3, [r7, #4] 80070a8: 7c1b ldrb r3, [r3, #16] 80070aa: 2b00 cmp r3, #0 80070ac: d109 bne.n 80070c2 { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 80070ae: 68fb ldr r3, [r7, #12] 80070b0: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 80070b4: f44f 7300 mov.w r3, #512 ; 0x200 80070b8: 2101 movs r1, #1 80070ba: 6878 ldr r0, [r7, #4] 80070bc: f001 fe52 bl 8008d64 80070c0: e007 b.n 80070d2 CDC_DATA_HS_OUT_PACKET_SIZE); } else { /* Prepare Out endpoint to receive next packet */ (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, 80070c2: 68fb ldr r3, [r7, #12] 80070c4: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 80070c8: 2340 movs r3, #64 ; 0x40 80070ca: 2101 movs r1, #1 80070cc: 6878 ldr r0, [r7, #4] 80070ce: f001 fe49 bl 8008d64 CDC_DATA_FS_OUT_PACKET_SIZE); } return (uint8_t)USBD_OK; 80070d2: 2300 movs r3, #0 } 80070d4: 4618 mov r0, r3 80070d6: 3710 adds r7, #16 80070d8: 46bd mov sp, r7 80070da: bd80 pop {r7, pc} 080070dc : * @param id: Low level core index * @retval None */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { 80070dc: b580 push {r7, lr} 80070de: b086 sub sp, #24 80070e0: af00 add r7, sp, #0 80070e2: 60f8 str r0, [r7, #12] 80070e4: 60b9 str r1, [r7, #8] 80070e6: 4613 mov r3, r2 80070e8: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) 80070ea: 68fb ldr r3, [r7, #12] 80070ec: 2b00 cmp r3, #0 80070ee: d101 bne.n 80070f4 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif return USBD_FAIL; 80070f0: 2303 movs r3, #3 80070f2: e01f b.n 8007134 } /* Unlink previous class resources */ pdev->pClass = NULL; 80070f4: 68fb ldr r3, [r7, #12] 80070f6: 2200 movs r2, #0 80070f8: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 pdev->pUserData = NULL; 80070fc: 68fb ldr r3, [r7, #12] 80070fe: 2200 movs r2, #0 8007100: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0 pdev->pConfDesc = NULL; 8007104: 68fb ldr r3, [r7, #12] 8007106: 2200 movs r2, #0 8007108: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc /* Assign USBD Descriptors */ if (pdesc != NULL) 800710c: 68bb ldr r3, [r7, #8] 800710e: 2b00 cmp r3, #0 8007110: d003 beq.n 800711a { pdev->pDesc = pdesc; 8007112: 68fb ldr r3, [r7, #12] 8007114: 68ba ldr r2, [r7, #8] 8007116: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; 800711a: 68fb ldr r3, [r7, #12] 800711c: 2201 movs r2, #1 800711e: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->id = id; 8007122: 68fb ldr r3, [r7, #12] 8007124: 79fa ldrb r2, [r7, #7] 8007126: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); 8007128: 68f8 ldr r0, [r7, #12] 800712a: f001 fcc5 bl 8008ab8 800712e: 4603 mov r3, r0 8007130: 75fb strb r3, [r7, #23] return ret; 8007132: 7dfb ldrb r3, [r7, #23] } 8007134: 4618 mov r0, r3 8007136: 3718 adds r7, #24 8007138: 46bd mov sp, r7 800713a: bd80 pop {r7, pc} 0800713c : * @param pDevice : Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { 800713c: b580 push {r7, lr} 800713e: b084 sub sp, #16 8007140: af00 add r7, sp, #0 8007142: 6078 str r0, [r7, #4] 8007144: 6039 str r1, [r7, #0] uint16_t len = 0U; 8007146: 2300 movs r3, #0 8007148: 81fb strh r3, [r7, #14] if (pclass == NULL) 800714a: 683b ldr r3, [r7, #0] 800714c: 2b00 cmp r3, #0 800714e: d101 bne.n 8007154 { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif return USBD_FAIL; 8007150: 2303 movs r3, #3 8007152: e016 b.n 8007182 } /* link the class to the USB Device handle */ pdev->pClass = pclass; 8007154: 687b ldr r3, [r7, #4] 8007156: 683a ldr r2, [r7, #0] 8007158: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 if (pdev->pClass->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass->GetFSConfigDescriptor != NULL) 800715c: 687b ldr r3, [r7, #4] 800715e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007162: 6adb ldr r3, [r3, #44] ; 0x2c 8007164: 2b00 cmp r3, #0 8007166: d00b beq.n 8007180 { pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len); 8007168: 687b ldr r3, [r7, #4] 800716a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800716e: 6adb ldr r3, [r3, #44] ; 0x2c 8007170: f107 020e add.w r2, r7, #14 8007174: 4610 mov r0, r2 8007176: 4798 blx r3 8007178: 4602 mov r2, r0 800717a: 687b ldr r3, [r7, #4] 800717c: f8c3 22cc str.w r2, [r3, #716] ; 0x2cc } #endif /* USE_USB_FS */ return USBD_OK; 8007180: 2300 movs r3, #0 } 8007182: 4618 mov r0, r3 8007184: 3710 adds r7, #16 8007186: 46bd mov sp, r7 8007188: bd80 pop {r7, pc} 0800718a : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { 800718a: b580 push {r7, lr} 800718c: b082 sub sp, #8 800718e: af00 add r7, sp, #0 8007190: 6078 str r0, [r7, #4] /* Start the low level driver */ return USBD_LL_Start(pdev); 8007192: 6878 ldr r0, [r7, #4] 8007194: f001 fcdc bl 8008b50 8007198: 4603 mov r3, r0 } 800719a: 4618 mov r0, r3 800719c: 3708 adds r7, #8 800719e: 46bd mov sp, r7 80071a0: bd80 pop {r7, pc} 080071a2 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { 80071a2: b480 push {r7} 80071a4: b083 sub sp, #12 80071a6: af00 add r7, sp, #0 80071a8: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80071aa: 2300 movs r3, #0 } 80071ac: 4618 mov r0, r3 80071ae: 370c adds r7, #12 80071b0: 46bd mov sp, r7 80071b2: f85d 7b04 ldr.w r7, [sp], #4 80071b6: 4770 bx lr 080071b8 : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80071b8: b580 push {r7, lr} 80071ba: b084 sub sp, #16 80071bc: af00 add r7, sp, #0 80071be: 6078 str r0, [r7, #4] 80071c0: 460b mov r3, r1 80071c2: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_FAIL; 80071c4: 2303 movs r3, #3 80071c6: 73fb strb r3, [r7, #15] if (pdev->pClass != NULL) 80071c8: 687b ldr r3, [r7, #4] 80071ca: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80071ce: 2b00 cmp r3, #0 80071d0: d009 beq.n 80071e6 { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx); 80071d2: 687b ldr r3, [r7, #4] 80071d4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80071d8: 681b ldr r3, [r3, #0] 80071da: 78fa ldrb r2, [r7, #3] 80071dc: 4611 mov r1, r2 80071de: 6878 ldr r0, [r7, #4] 80071e0: 4798 blx r3 80071e2: 4603 mov r3, r0 80071e4: 73fb strb r3, [r7, #15] } return ret; 80071e6: 7bfb ldrb r3, [r7, #15] } 80071e8: 4618 mov r0, r3 80071ea: 3710 adds r7, #16 80071ec: 46bd mov sp, r7 80071ee: bd80 pop {r7, pc} 080071f0 : * @param pdev: device instance * @param cfgidx: configuration index * @retval status: USBD_StatusTypeDef */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { 80071f0: b580 push {r7, lr} 80071f2: b082 sub sp, #8 80071f4: af00 add r7, sp, #0 80071f6: 6078 str r0, [r7, #4] 80071f8: 460b mov r3, r1 80071fa: 70fb strb r3, [r7, #3] /* Clear configuration and De-initialize the Class process */ if (pdev->pClass != NULL) 80071fc: 687b ldr r3, [r7, #4] 80071fe: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007202: 2b00 cmp r3, #0 8007204: d007 beq.n 8007216 { pdev->pClass->DeInit(pdev, cfgidx); 8007206: 687b ldr r3, [r7, #4] 8007208: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800720c: 685b ldr r3, [r3, #4] 800720e: 78fa ldrb r2, [r7, #3] 8007210: 4611 mov r1, r2 8007212: 6878 ldr r0, [r7, #4] 8007214: 4798 blx r3 } return USBD_OK; 8007216: 2300 movs r3, #0 } 8007218: 4618 mov r0, r3 800721a: 3708 adds r7, #8 800721c: 46bd mov sp, r7 800721e: bd80 pop {r7, pc} 08007220 : * Handle the setup stage * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { 8007220: b580 push {r7, lr} 8007222: b084 sub sp, #16 8007224: af00 add r7, sp, #0 8007226: 6078 str r0, [r7, #4] 8007228: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); 800722a: 687b ldr r3, [r7, #4] 800722c: f203 23aa addw r3, r3, #682 ; 0x2aa 8007230: 6839 ldr r1, [r7, #0] 8007232: 4618 mov r0, r3 8007234: f000 ffba bl 80081ac pdev->ep0_state = USBD_EP0_SETUP; 8007238: 687b ldr r3, [r7, #4] 800723a: 2201 movs r2, #1 800723c: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep0_data_len = pdev->request.wLength; 8007240: 687b ldr r3, [r7, #4] 8007242: f8b3 32b0 ldrh.w r3, [r3, #688] ; 0x2b0 8007246: 461a mov r2, r3 8007248: 687b ldr r3, [r7, #4] 800724a: f8c3 2298 str.w r2, [r3, #664] ; 0x298 switch (pdev->request.bmRequest & 0x1FU) 800724e: 687b ldr r3, [r7, #4] 8007250: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa 8007254: f003 031f and.w r3, r3, #31 8007258: 2b02 cmp r3, #2 800725a: d01a beq.n 8007292 800725c: 2b02 cmp r3, #2 800725e: d822 bhi.n 80072a6 8007260: 2b00 cmp r3, #0 8007262: d002 beq.n 800726a 8007264: 2b01 cmp r3, #1 8007266: d00a beq.n 800727e 8007268: e01d b.n 80072a6 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); 800726a: 687b ldr r3, [r7, #4] 800726c: f203 23aa addw r3, r3, #682 ; 0x2aa 8007270: 4619 mov r1, r3 8007272: 6878 ldr r0, [r7, #4] 8007274: f000 fa62 bl 800773c 8007278: 4603 mov r3, r0 800727a: 73fb strb r3, [r7, #15] break; 800727c: e020 b.n 80072c0 case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); 800727e: 687b ldr r3, [r7, #4] 8007280: f203 23aa addw r3, r3, #682 ; 0x2aa 8007284: 4619 mov r1, r3 8007286: 6878 ldr r0, [r7, #4] 8007288: f000 fac6 bl 8007818 800728c: 4603 mov r3, r0 800728e: 73fb strb r3, [r7, #15] break; 8007290: e016 b.n 80072c0 case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); 8007292: 687b ldr r3, [r7, #4] 8007294: f203 23aa addw r3, r3, #682 ; 0x2aa 8007298: 4619 mov r1, r3 800729a: 6878 ldr r0, [r7, #4] 800729c: f000 fb05 bl 80078aa 80072a0: 4603 mov r3, r0 80072a2: 73fb strb r3, [r7, #15] break; 80072a4: e00c b.n 80072c0 default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); 80072a6: 687b ldr r3, [r7, #4] 80072a8: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa 80072ac: f023 037f bic.w r3, r3, #127 ; 0x7f 80072b0: b2db uxtb r3, r3 80072b2: 4619 mov r1, r3 80072b4: 6878 ldr r0, [r7, #4] 80072b6: f001 fcab bl 8008c10 80072ba: 4603 mov r3, r0 80072bc: 73fb strb r3, [r7, #15] break; 80072be: bf00 nop } return ret; 80072c0: 7bfb ldrb r3, [r7, #15] } 80072c2: 4618 mov r0, r3 80072c4: 3710 adds r7, #16 80072c6: 46bd mov sp, r7 80072c8: bd80 pop {r7, pc} 080072ca : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 80072ca: b580 push {r7, lr} 80072cc: b086 sub sp, #24 80072ce: af00 add r7, sp, #0 80072d0: 60f8 str r0, [r7, #12] 80072d2: 460b mov r3, r1 80072d4: 607a str r2, [r7, #4] 80072d6: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret; if (epnum == 0U) 80072d8: 7afb ldrb r3, [r7, #11] 80072da: 2b00 cmp r3, #0 80072dc: d138 bne.n 8007350 { pep = &pdev->ep_out[0]; 80072de: 68fb ldr r3, [r7, #12] 80072e0: f503 73aa add.w r3, r3, #340 ; 0x154 80072e4: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) 80072e6: 68fb ldr r3, [r7, #12] 80072e8: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 80072ec: 2b03 cmp r3, #3 80072ee: d14a bne.n 8007386 { if (pep->rem_length > pep->maxpacket) 80072f0: 693b ldr r3, [r7, #16] 80072f2: 689a ldr r2, [r3, #8] 80072f4: 693b ldr r3, [r7, #16] 80072f6: 68db ldr r3, [r3, #12] 80072f8: 429a cmp r2, r3 80072fa: d913 bls.n 8007324 { pep->rem_length -= pep->maxpacket; 80072fc: 693b ldr r3, [r7, #16] 80072fe: 689a ldr r2, [r3, #8] 8007300: 693b ldr r3, [r7, #16] 8007302: 68db ldr r3, [r3, #12] 8007304: 1ad2 subs r2, r2, r3 8007306: 693b ldr r3, [r7, #16] 8007308: 609a str r2, [r3, #8] (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket)); 800730a: 693b ldr r3, [r7, #16] 800730c: 68da ldr r2, [r3, #12] 800730e: 693b ldr r3, [r7, #16] 8007310: 689b ldr r3, [r3, #8] 8007312: 4293 cmp r3, r2 8007314: bf28 it cs 8007316: 4613 movcs r3, r2 8007318: 461a mov r2, r3 800731a: 6879 ldr r1, [r7, #4] 800731c: 68f8 ldr r0, [r7, #12] 800731e: f001 f839 bl 8008394 8007322: e030 b.n 8007386 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007324: 68fb ldr r3, [r7, #12] 8007326: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 800732a: b2db uxtb r3, r3 800732c: 2b03 cmp r3, #3 800732e: d10b bne.n 8007348 { if (pdev->pClass->EP0_RxReady != NULL) 8007330: 68fb ldr r3, [r7, #12] 8007332: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007336: 691b ldr r3, [r3, #16] 8007338: 2b00 cmp r3, #0 800733a: d005 beq.n 8007348 { pdev->pClass->EP0_RxReady(pdev); 800733c: 68fb ldr r3, [r7, #12] 800733e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007342: 691b ldr r3, [r3, #16] 8007344: 68f8 ldr r0, [r7, #12] 8007346: 4798 blx r3 } } (void)USBD_CtlSendStatus(pdev); 8007348: 68f8 ldr r0, [r7, #12] 800734a: f001 f834 bl 80083b6 800734e: e01a b.n 8007386 #endif } } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007350: 68fb ldr r3, [r7, #12] 8007352: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007356: b2db uxtb r3, r3 8007358: 2b03 cmp r3, #3 800735a: d114 bne.n 8007386 { if (pdev->pClass->DataOut != NULL) 800735c: 68fb ldr r3, [r7, #12] 800735e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007362: 699b ldr r3, [r3, #24] 8007364: 2b00 cmp r3, #0 8007366: d00e beq.n 8007386 { ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum); 8007368: 68fb ldr r3, [r7, #12] 800736a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800736e: 699b ldr r3, [r3, #24] 8007370: 7afa ldrb r2, [r7, #11] 8007372: 4611 mov r1, r2 8007374: 68f8 ldr r0, [r7, #12] 8007376: 4798 blx r3 8007378: 4603 mov r3, r0 800737a: 75fb strb r3, [r7, #23] if (ret != USBD_OK) 800737c: 7dfb ldrb r3, [r7, #23] 800737e: 2b00 cmp r3, #0 8007380: d001 beq.n 8007386 { return ret; 8007382: 7dfb ldrb r3, [r7, #23] 8007384: e000 b.n 8007388 } } } } return USBD_OK; 8007386: 2300 movs r3, #0 } 8007388: 4618 mov r0, r3 800738a: 3718 adds r7, #24 800738c: 46bd mov sp, r7 800738e: bd80 pop {r7, pc} 08007390 : * @param epnum: endpoint index * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { 8007390: b580 push {r7, lr} 8007392: b086 sub sp, #24 8007394: af00 add r7, sp, #0 8007396: 60f8 str r0, [r7, #12] 8007398: 460b mov r3, r1 800739a: 607a str r2, [r7, #4] 800739c: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret; if (epnum == 0U) 800739e: 7afb ldrb r3, [r7, #11] 80073a0: 2b00 cmp r3, #0 80073a2: d16b bne.n 800747c { pep = &pdev->ep_in[0]; 80073a4: 68fb ldr r3, [r7, #12] 80073a6: 3314 adds r3, #20 80073a8: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) 80073aa: 68fb ldr r3, [r7, #12] 80073ac: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 80073b0: 2b02 cmp r3, #2 80073b2: d156 bne.n 8007462 { if (pep->rem_length > pep->maxpacket) 80073b4: 693b ldr r3, [r7, #16] 80073b6: 689a ldr r2, [r3, #8] 80073b8: 693b ldr r3, [r7, #16] 80073ba: 68db ldr r3, [r3, #12] 80073bc: 429a cmp r2, r3 80073be: d914 bls.n 80073ea { pep->rem_length -= pep->maxpacket; 80073c0: 693b ldr r3, [r7, #16] 80073c2: 689a ldr r2, [r3, #8] 80073c4: 693b ldr r3, [r7, #16] 80073c6: 68db ldr r3, [r3, #12] 80073c8: 1ad2 subs r2, r2, r3 80073ca: 693b ldr r3, [r7, #16] 80073cc: 609a str r2, [r3, #8] (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length); 80073ce: 693b ldr r3, [r7, #16] 80073d0: 689b ldr r3, [r3, #8] 80073d2: 461a mov r2, r3 80073d4: 6879 ldr r1, [r7, #4] 80073d6: 68f8 ldr r0, [r7, #12] 80073d8: f000 ffae bl 8008338 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 80073dc: 2300 movs r3, #0 80073de: 2200 movs r2, #0 80073e0: 2100 movs r1, #0 80073e2: 68f8 ldr r0, [r7, #12] 80073e4: f001 fcbe bl 8008d64 80073e8: e03b b.n 8007462 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && 80073ea: 693b ldr r3, [r7, #16] 80073ec: 68da ldr r2, [r3, #12] 80073ee: 693b ldr r3, [r7, #16] 80073f0: 689b ldr r3, [r3, #8] 80073f2: 429a cmp r2, r3 80073f4: d11c bne.n 8007430 (pep->total_length >= pep->maxpacket) && 80073f6: 693b ldr r3, [r7, #16] 80073f8: 685a ldr r2, [r3, #4] 80073fa: 693b ldr r3, [r7, #16] 80073fc: 68db ldr r3, [r3, #12] if ((pep->maxpacket == pep->rem_length) && 80073fe: 429a cmp r2, r3 8007400: d316 bcc.n 8007430 (pep->total_length < pdev->ep0_data_len)) 8007402: 693b ldr r3, [r7, #16] 8007404: 685a ldr r2, [r3, #4] 8007406: 68fb ldr r3, [r7, #12] 8007408: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298 (pep->total_length >= pep->maxpacket) && 800740c: 429a cmp r2, r3 800740e: d20f bcs.n 8007430 { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); 8007410: 2200 movs r2, #0 8007412: 2100 movs r1, #0 8007414: 68f8 ldr r0, [r7, #12] 8007416: f000 ff8f bl 8008338 pdev->ep0_data_len = 0U; 800741a: 68fb ldr r3, [r7, #12] 800741c: 2200 movs r2, #0 800741e: f8c3 2298 str.w r2, [r3, #664] ; 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 8007422: 2300 movs r3, #0 8007424: 2200 movs r2, #0 8007426: 2100 movs r1, #0 8007428: 68f8 ldr r0, [r7, #12] 800742a: f001 fc9b bl 8008d64 800742e: e018 b.n 8007462 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007430: 68fb ldr r3, [r7, #12] 8007432: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007436: b2db uxtb r3, r3 8007438: 2b03 cmp r3, #3 800743a: d10b bne.n 8007454 { if (pdev->pClass->EP0_TxSent != NULL) 800743c: 68fb ldr r3, [r7, #12] 800743e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007442: 68db ldr r3, [r3, #12] 8007444: 2b00 cmp r3, #0 8007446: d005 beq.n 8007454 { pdev->pClass->EP0_TxSent(pdev); 8007448: 68fb ldr r3, [r7, #12] 800744a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800744e: 68db ldr r3, [r3, #12] 8007450: 68f8 ldr r0, [r7, #12] 8007452: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); 8007454: 2180 movs r1, #128 ; 0x80 8007456: 68f8 ldr r0, [r7, #12] 8007458: f001 fbda bl 8008c10 (void)USBD_CtlReceiveStatus(pdev); 800745c: 68f8 ldr r0, [r7, #12] 800745e: f000 ffbd bl 80083dc (void)USBD_LL_StallEP(pdev, 0x80U); } #endif } if (pdev->dev_test_mode == 1U) 8007462: 68fb ldr r3, [r7, #12] 8007464: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0 8007468: 2b01 cmp r3, #1 800746a: d122 bne.n 80074b2 { (void)USBD_RunTestMode(pdev); 800746c: 68f8 ldr r0, [r7, #12] 800746e: f7ff fe98 bl 80071a2 pdev->dev_test_mode = 0U; 8007472: 68fb ldr r3, [r7, #12] 8007474: 2200 movs r2, #0 8007476: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 800747a: e01a b.n 80074b2 } } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) 800747c: 68fb ldr r3, [r7, #12] 800747e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007482: b2db uxtb r3, r3 8007484: 2b03 cmp r3, #3 8007486: d114 bne.n 80074b2 { if (pdev->pClass->DataIn != NULL) 8007488: 68fb ldr r3, [r7, #12] 800748a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800748e: 695b ldr r3, [r3, #20] 8007490: 2b00 cmp r3, #0 8007492: d00e beq.n 80074b2 { ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum); 8007494: 68fb ldr r3, [r7, #12] 8007496: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800749a: 695b ldr r3, [r3, #20] 800749c: 7afa ldrb r2, [r7, #11] 800749e: 4611 mov r1, r2 80074a0: 68f8 ldr r0, [r7, #12] 80074a2: 4798 blx r3 80074a4: 4603 mov r3, r0 80074a6: 75fb strb r3, [r7, #23] if (ret != USBD_OK) 80074a8: 7dfb ldrb r3, [r7, #23] 80074aa: 2b00 cmp r3, #0 80074ac: d001 beq.n 80074b2 { return ret; 80074ae: 7dfb ldrb r3, [r7, #23] 80074b0: e000 b.n 80074b4 } } } } return USBD_OK; 80074b2: 2300 movs r3, #0 } 80074b4: 4618 mov r0, r3 80074b6: 3718 adds r7, #24 80074b8: 46bd mov sp, r7 80074ba: bd80 pop {r7, pc} 080074bc : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { 80074bc: b580 push {r7, lr} 80074be: b082 sub sp, #8 80074c0: af00 add r7, sp, #0 80074c2: 6078 str r0, [r7, #4] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; 80074c4: 687b ldr r3, [r7, #4] 80074c6: 2201 movs r2, #1 80074c8: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->ep0_state = USBD_EP0_IDLE; 80074cc: 687b ldr r3, [r7, #4] 80074ce: 2200 movs r2, #0 80074d0: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->dev_config = 0U; 80074d4: 687b ldr r3, [r7, #4] 80074d6: 2200 movs r2, #0 80074d8: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; 80074da: 687b ldr r3, [r7, #4] 80074dc: 2200 movs r2, #0 80074de: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 if (pdev->pClass == NULL) 80074e2: 687b ldr r3, [r7, #4] 80074e4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80074e8: 2b00 cmp r3, #0 80074ea: d101 bne.n 80074f0 { return USBD_FAIL; 80074ec: 2303 movs r3, #3 80074ee: e02f b.n 8007550 } if (pdev->pClassData != NULL) 80074f0: 687b ldr r3, [r7, #4] 80074f2: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc 80074f6: 2b00 cmp r3, #0 80074f8: d00f beq.n 800751a { if (pdev->pClass->DeInit != NULL) 80074fa: 687b ldr r3, [r7, #4] 80074fc: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007500: 685b ldr r3, [r3, #4] 8007502: 2b00 cmp r3, #0 8007504: d009 beq.n 800751a { (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); 8007506: 687b ldr r3, [r7, #4] 8007508: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800750c: 685b ldr r3, [r3, #4] 800750e: 687a ldr r2, [r7, #4] 8007510: 6852 ldr r2, [r2, #4] 8007512: b2d2 uxtb r2, r2 8007514: 4611 mov r1, r2 8007516: 6878 ldr r0, [r7, #4] 8007518: 4798 blx r3 } } /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 800751a: 2340 movs r3, #64 ; 0x40 800751c: 2200 movs r2, #0 800751e: 2100 movs r1, #0 8007520: 6878 ldr r0, [r7, #4] 8007522: f001 fb30 bl 8008b86 pdev->ep_out[0x00U & 0xFU].is_used = 1U; 8007526: 687b ldr r3, [r7, #4] 8007528: 2201 movs r2, #1 800752a: f8a3 2164 strh.w r2, [r3, #356] ; 0x164 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; 800752e: 687b ldr r3, [r7, #4] 8007530: 2240 movs r2, #64 ; 0x40 8007532: f8c3 2160 str.w r2, [r3, #352] ; 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); 8007536: 2340 movs r3, #64 ; 0x40 8007538: 2200 movs r2, #0 800753a: 2180 movs r1, #128 ; 0x80 800753c: 6878 ldr r0, [r7, #4] 800753e: f001 fb22 bl 8008b86 pdev->ep_in[0x80U & 0xFU].is_used = 1U; 8007542: 687b ldr r3, [r7, #4] 8007544: 2201 movs r2, #1 8007546: 849a strh r2, [r3, #36] ; 0x24 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; 8007548: 687b ldr r3, [r7, #4] 800754a: 2240 movs r2, #64 ; 0x40 800754c: 621a str r2, [r3, #32] return USBD_OK; 800754e: 2300 movs r3, #0 } 8007550: 4618 mov r0, r3 8007552: 3708 adds r7, #8 8007554: 46bd mov sp, r7 8007556: bd80 pop {r7, pc} 08007558 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { 8007558: b480 push {r7} 800755a: b083 sub sp, #12 800755c: af00 add r7, sp, #0 800755e: 6078 str r0, [r7, #4] 8007560: 460b mov r3, r1 8007562: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; 8007564: 687b ldr r3, [r7, #4] 8007566: 78fa ldrb r2, [r7, #3] 8007568: 741a strb r2, [r3, #16] return USBD_OK; 800756a: 2300 movs r3, #0 } 800756c: 4618 mov r0, r3 800756e: 370c adds r7, #12 8007570: 46bd mov sp, r7 8007572: f85d 7b04 ldr.w r7, [sp], #4 8007576: 4770 bx lr 08007578 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { 8007578: b480 push {r7} 800757a: b083 sub sp, #12 800757c: af00 add r7, sp, #0 800757e: 6078 str r0, [r7, #4] pdev->dev_old_state = pdev->dev_state; 8007580: 687b ldr r3, [r7, #4] 8007582: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007586: b2da uxtb r2, r3 8007588: 687b ldr r3, [r7, #4] 800758a: f883 229d strb.w r2, [r3, #669] ; 0x29d pdev->dev_state = USBD_STATE_SUSPENDED; 800758e: 687b ldr r3, [r7, #4] 8007590: 2204 movs r2, #4 8007592: f883 229c strb.w r2, [r3, #668] ; 0x29c return USBD_OK; 8007596: 2300 movs r3, #0 } 8007598: 4618 mov r0, r3 800759a: 370c adds r7, #12 800759c: 46bd mov sp, r7 800759e: f85d 7b04 ldr.w r7, [sp], #4 80075a2: 4770 bx lr 080075a4 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { 80075a4: b480 push {r7} 80075a6: b083 sub sp, #12 80075a8: af00 add r7, sp, #0 80075aa: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) 80075ac: 687b ldr r3, [r7, #4] 80075ae: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80075b2: b2db uxtb r3, r3 80075b4: 2b04 cmp r3, #4 80075b6: d106 bne.n 80075c6 { pdev->dev_state = pdev->dev_old_state; 80075b8: 687b ldr r3, [r7, #4] 80075ba: f893 329d ldrb.w r3, [r3, #669] ; 0x29d 80075be: b2da uxtb r2, r3 80075c0: 687b ldr r3, [r7, #4] 80075c2: f883 229c strb.w r2, [r3, #668] ; 0x29c } return USBD_OK; 80075c6: 2300 movs r3, #0 } 80075c8: 4618 mov r0, r3 80075ca: 370c adds r7, #12 80075cc: 46bd mov sp, r7 80075ce: f85d 7b04 ldr.w r7, [sp], #4 80075d2: 4770 bx lr 080075d4 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { 80075d4: b580 push {r7, lr} 80075d6: b082 sub sp, #8 80075d8: af00 add r7, sp, #0 80075da: 6078 str r0, [r7, #4] if (pdev->pClass == NULL) 80075dc: 687b ldr r3, [r7, #4] 80075de: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80075e2: 2b00 cmp r3, #0 80075e4: d101 bne.n 80075ea { return USBD_FAIL; 80075e6: 2303 movs r3, #3 80075e8: e012 b.n 8007610 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 80075ea: 687b ldr r3, [r7, #4] 80075ec: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80075f0: b2db uxtb r3, r3 80075f2: 2b03 cmp r3, #3 80075f4: d10b bne.n 800760e { if (pdev->pClass->SOF != NULL) 80075f6: 687b ldr r3, [r7, #4] 80075f8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80075fc: 69db ldr r3, [r3, #28] 80075fe: 2b00 cmp r3, #0 8007600: d005 beq.n 800760e { (void)pdev->pClass->SOF(pdev); 8007602: 687b ldr r3, [r7, #4] 8007604: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007608: 69db ldr r3, [r3, #28] 800760a: 6878 ldr r0, [r7, #4] 800760c: 4798 blx r3 } } return USBD_OK; 800760e: 2300 movs r3, #0 } 8007610: 4618 mov r0, r3 8007612: 3708 adds r7, #8 8007614: 46bd mov sp, r7 8007616: bd80 pop {r7, pc} 08007618 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8007618: b580 push {r7, lr} 800761a: b082 sub sp, #8 800761c: af00 add r7, sp, #0 800761e: 6078 str r0, [r7, #4] 8007620: 460b mov r3, r1 8007622: 70fb strb r3, [r7, #3] if (pdev->pClass == NULL) 8007624: 687b ldr r3, [r7, #4] 8007626: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800762a: 2b00 cmp r3, #0 800762c: d101 bne.n 8007632 { return USBD_FAIL; 800762e: 2303 movs r3, #3 8007630: e014 b.n 800765c } if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007632: 687b ldr r3, [r7, #4] 8007634: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007638: b2db uxtb r3, r3 800763a: 2b03 cmp r3, #3 800763c: d10d bne.n 800765a { if (pdev->pClass->IsoINIncomplete != NULL) 800763e: 687b ldr r3, [r7, #4] 8007640: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007644: 6a1b ldr r3, [r3, #32] 8007646: 2b00 cmp r3, #0 8007648: d007 beq.n 800765a { (void)pdev->pClass->IsoINIncomplete(pdev, epnum); 800764a: 687b ldr r3, [r7, #4] 800764c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007650: 6a1b ldr r3, [r3, #32] 8007652: 78fa ldrb r2, [r7, #3] 8007654: 4611 mov r1, r2 8007656: 6878 ldr r0, [r7, #4] 8007658: 4798 blx r3 } } return USBD_OK; 800765a: 2300 movs r3, #0 } 800765c: 4618 mov r0, r3 800765e: 3708 adds r7, #8 8007660: 46bd mov sp, r7 8007662: bd80 pop {r7, pc} 08007664 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { 8007664: b580 push {r7, lr} 8007666: b082 sub sp, #8 8007668: af00 add r7, sp, #0 800766a: 6078 str r0, [r7, #4] 800766c: 460b mov r3, r1 800766e: 70fb strb r3, [r7, #3] if (pdev->pClass == NULL) 8007670: 687b ldr r3, [r7, #4] 8007672: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007676: 2b00 cmp r3, #0 8007678: d101 bne.n 800767e { return USBD_FAIL; 800767a: 2303 movs r3, #3 800767c: e014 b.n 80076a8 } if (pdev->dev_state == USBD_STATE_CONFIGURED) 800767e: 687b ldr r3, [r7, #4] 8007680: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007684: b2db uxtb r3, r3 8007686: 2b03 cmp r3, #3 8007688: d10d bne.n 80076a6 { if (pdev->pClass->IsoOUTIncomplete != NULL) 800768a: 687b ldr r3, [r7, #4] 800768c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007690: 6a5b ldr r3, [r3, #36] ; 0x24 8007692: 2b00 cmp r3, #0 8007694: d007 beq.n 80076a6 { (void)pdev->pClass->IsoOUTIncomplete(pdev, epnum); 8007696: 687b ldr r3, [r7, #4] 8007698: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800769c: 6a5b ldr r3, [r3, #36] ; 0x24 800769e: 78fa ldrb r2, [r7, #3] 80076a0: 4611 mov r1, r2 80076a2: 6878 ldr r0, [r7, #4] 80076a4: 4798 blx r3 } } return USBD_OK; 80076a6: 2300 movs r3, #0 } 80076a8: 4618 mov r0, r3 80076aa: 3708 adds r7, #8 80076ac: 46bd mov sp, r7 80076ae: bd80 pop {r7, pc} 080076b0 : * Handle device connection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) { 80076b0: b480 push {r7} 80076b2: b083 sub sp, #12 80076b4: af00 add r7, sp, #0 80076b6: 6078 str r0, [r7, #4] /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; 80076b8: 2300 movs r3, #0 } 80076ba: 4618 mov r0, r3 80076bc: 370c adds r7, #12 80076be: 46bd mov sp, r7 80076c0: f85d 7b04 ldr.w r7, [sp], #4 80076c4: 4770 bx lr 080076c6 : * Handle device disconnection event * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { 80076c6: b580 push {r7, lr} 80076c8: b082 sub sp, #8 80076ca: af00 add r7, sp, #0 80076cc: 6078 str r0, [r7, #4] /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; 80076ce: 687b ldr r3, [r7, #4] 80076d0: 2201 movs r2, #1 80076d2: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->pClass != NULL) 80076d6: 687b ldr r3, [r7, #4] 80076d8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80076dc: 2b00 cmp r3, #0 80076de: d009 beq.n 80076f4 { (void)pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); 80076e0: 687b ldr r3, [r7, #4] 80076e2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80076e6: 685b ldr r3, [r3, #4] 80076e8: 687a ldr r2, [r7, #4] 80076ea: 6852 ldr r2, [r2, #4] 80076ec: b2d2 uxtb r2, r2 80076ee: 4611 mov r1, r2 80076f0: 6878 ldr r0, [r7, #4] 80076f2: 4798 blx r3 } return USBD_OK; 80076f4: 2300 movs r3, #0 } 80076f6: 4618 mov r0, r3 80076f8: 3708 adds r7, #8 80076fa: 46bd mov sp, r7 80076fc: bd80 pop {r7, pc} 080076fe : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { 80076fe: b480 push {r7} 8007700: b087 sub sp, #28 8007702: af00 add r7, sp, #0 8007704: 6078 str r0, [r7, #4] uint16_t _SwapVal, _Byte1, _Byte2; uint8_t *_pbuff = addr; 8007706: 687b ldr r3, [r7, #4] 8007708: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; 800770a: 697b ldr r3, [r7, #20] 800770c: 781b ldrb r3, [r3, #0] 800770e: 827b strh r3, [r7, #18] _pbuff++; 8007710: 697b ldr r3, [r7, #20] 8007712: 3301 adds r3, #1 8007714: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; 8007716: 697b ldr r3, [r7, #20] 8007718: 781b ldrb r3, [r3, #0] 800771a: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; 800771c: 8a3b ldrh r3, [r7, #16] 800771e: 021b lsls r3, r3, #8 8007720: b21a sxth r2, r3 8007722: f9b7 3012 ldrsh.w r3, [r7, #18] 8007726: 4313 orrs r3, r2 8007728: b21b sxth r3, r3 800772a: 81fb strh r3, [r7, #14] return _SwapVal; 800772c: 89fb ldrh r3, [r7, #14] } 800772e: 4618 mov r0, r3 8007730: 371c adds r7, #28 8007732: 46bd mov sp, r7 8007734: f85d 7b04 ldr.w r7, [sp], #4 8007738: 4770 bx lr ... 0800773c : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800773c: b580 push {r7, lr} 800773e: b084 sub sp, #16 8007740: af00 add r7, sp, #0 8007742: 6078 str r0, [r7, #4] 8007744: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8007746: 2300 movs r3, #0 8007748: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 800774a: 683b ldr r3, [r7, #0] 800774c: 781b ldrb r3, [r3, #0] 800774e: f003 0360 and.w r3, r3, #96 ; 0x60 8007752: 2b40 cmp r3, #64 ; 0x40 8007754: d005 beq.n 8007762 8007756: 2b40 cmp r3, #64 ; 0x40 8007758: d853 bhi.n 8007802 800775a: 2b00 cmp r3, #0 800775c: d00b beq.n 8007776 800775e: 2b20 cmp r3, #32 8007760: d14f bne.n 8007802 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 8007762: 687b ldr r3, [r7, #4] 8007764: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007768: 689b ldr r3, [r3, #8] 800776a: 6839 ldr r1, [r7, #0] 800776c: 6878 ldr r0, [r7, #4] 800776e: 4798 blx r3 8007770: 4603 mov r3, r0 8007772: 73fb strb r3, [r7, #15] break; 8007774: e04a b.n 800780c case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 8007776: 683b ldr r3, [r7, #0] 8007778: 785b ldrb r3, [r3, #1] 800777a: 2b09 cmp r3, #9 800777c: d83b bhi.n 80077f6 800777e: a201 add r2, pc, #4 ; (adr r2, 8007784 ) 8007780: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007784: 080077d9 .word 0x080077d9 8007788: 080077ed .word 0x080077ed 800778c: 080077f7 .word 0x080077f7 8007790: 080077e3 .word 0x080077e3 8007794: 080077f7 .word 0x080077f7 8007798: 080077b7 .word 0x080077b7 800779c: 080077ad .word 0x080077ad 80077a0: 080077f7 .word 0x080077f7 80077a4: 080077cf .word 0x080077cf 80077a8: 080077c1 .word 0x080077c1 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); 80077ac: 6839 ldr r1, [r7, #0] 80077ae: 6878 ldr r0, [r7, #4] 80077b0: f000 f9de bl 8007b70 break; 80077b4: e024 b.n 8007800 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); 80077b6: 6839 ldr r1, [r7, #0] 80077b8: 6878 ldr r0, [r7, #4] 80077ba: f000 fb6d bl 8007e98 break; 80077be: e01f b.n 8007800 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); 80077c0: 6839 ldr r1, [r7, #0] 80077c2: 6878 ldr r0, [r7, #4] 80077c4: f000 fbac bl 8007f20 80077c8: 4603 mov r3, r0 80077ca: 73fb strb r3, [r7, #15] break; 80077cc: e018 b.n 8007800 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); 80077ce: 6839 ldr r1, [r7, #0] 80077d0: 6878 ldr r0, [r7, #4] 80077d2: f000 fc4b bl 800806c break; 80077d6: e013 b.n 8007800 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); 80077d8: 6839 ldr r1, [r7, #0] 80077da: 6878 ldr r0, [r7, #4] 80077dc: f000 fc7c bl 80080d8 break; 80077e0: e00e b.n 8007800 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); 80077e2: 6839 ldr r1, [r7, #0] 80077e4: 6878 ldr r0, [r7, #4] 80077e6: f000 fcab bl 8008140 break; 80077ea: e009 b.n 8007800 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); 80077ec: 6839 ldr r1, [r7, #0] 80077ee: 6878 ldr r0, [r7, #4] 80077f0: f000 fcba bl 8008168 break; 80077f4: e004 b.n 8007800 default: USBD_CtlError(pdev, req); 80077f6: 6839 ldr r1, [r7, #0] 80077f8: 6878 ldr r0, [r7, #4] 80077fa: f000 fd11 bl 8008220 break; 80077fe: bf00 nop } break; 8007800: e004 b.n 800780c default: USBD_CtlError(pdev, req); 8007802: 6839 ldr r1, [r7, #0] 8007804: 6878 ldr r0, [r7, #4] 8007806: f000 fd0b bl 8008220 break; 800780a: bf00 nop } return ret; 800780c: 7bfb ldrb r3, [r7, #15] } 800780e: 4618 mov r0, r3 8007810: 3710 adds r7, #16 8007812: 46bd mov sp, r7 8007814: bd80 pop {r7, pc} 8007816: bf00 nop 08007818 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8007818: b580 push {r7, lr} 800781a: b084 sub sp, #16 800781c: af00 add r7, sp, #0 800781e: 6078 str r0, [r7, #4] 8007820: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8007822: 2300 movs r3, #0 8007824: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) 8007826: 683b ldr r3, [r7, #0] 8007828: 781b ldrb r3, [r3, #0] 800782a: f003 0360 and.w r3, r3, #96 ; 0x60 800782e: 2b40 cmp r3, #64 ; 0x40 8007830: d005 beq.n 800783e 8007832: 2b40 cmp r3, #64 ; 0x40 8007834: d82f bhi.n 8007896 8007836: 2b00 cmp r3, #0 8007838: d001 beq.n 800783e 800783a: 2b20 cmp r3, #32 800783c: d12b bne.n 8007896 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) 800783e: 687b ldr r3, [r7, #4] 8007840: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007844: b2db uxtb r3, r3 8007846: 3b01 subs r3, #1 8007848: 2b02 cmp r3, #2 800784a: d81d bhi.n 8007888 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 800784c: 683b ldr r3, [r7, #0] 800784e: 889b ldrh r3, [r3, #4] 8007850: b2db uxtb r3, r3 8007852: 2b01 cmp r3, #1 8007854: d813 bhi.n 800787e { ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 8007856: 687b ldr r3, [r7, #4] 8007858: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 800785c: 689b ldr r3, [r3, #8] 800785e: 6839 ldr r1, [r7, #0] 8007860: 6878 ldr r0, [r7, #4] 8007862: 4798 blx r3 8007864: 4603 mov r3, r0 8007866: 73fb strb r3, [r7, #15] if ((req->wLength == 0U) && (ret == USBD_OK)) 8007868: 683b ldr r3, [r7, #0] 800786a: 88db ldrh r3, [r3, #6] 800786c: 2b00 cmp r3, #0 800786e: d110 bne.n 8007892 8007870: 7bfb ldrb r3, [r7, #15] 8007872: 2b00 cmp r3, #0 8007874: d10d bne.n 8007892 { (void)USBD_CtlSendStatus(pdev); 8007876: 6878 ldr r0, [r7, #4] 8007878: f000 fd9d bl 80083b6 } else { USBD_CtlError(pdev, req); } break; 800787c: e009 b.n 8007892 USBD_CtlError(pdev, req); 800787e: 6839 ldr r1, [r7, #0] 8007880: 6878 ldr r0, [r7, #4] 8007882: f000 fccd bl 8008220 break; 8007886: e004 b.n 8007892 default: USBD_CtlError(pdev, req); 8007888: 6839 ldr r1, [r7, #0] 800788a: 6878 ldr r0, [r7, #4] 800788c: f000 fcc8 bl 8008220 break; 8007890: e000 b.n 8007894 break; 8007892: bf00 nop } break; 8007894: e004 b.n 80078a0 default: USBD_CtlError(pdev, req); 8007896: 6839 ldr r1, [r7, #0] 8007898: 6878 ldr r0, [r7, #4] 800789a: f000 fcc1 bl 8008220 break; 800789e: bf00 nop } return ret; 80078a0: 7bfb ldrb r3, [r7, #15] } 80078a2: 4618 mov r0, r3 80078a4: 3710 adds r7, #16 80078a6: 46bd mov sp, r7 80078a8: bd80 pop {r7, pc} 080078aa : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80078aa: b580 push {r7, lr} 80078ac: b084 sub sp, #16 80078ae: af00 add r7, sp, #0 80078b0: 6078 str r0, [r7, #4] 80078b2: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; USBD_StatusTypeDef ret = USBD_OK; 80078b4: 2300 movs r3, #0 80078b6: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); 80078b8: 683b ldr r3, [r7, #0] 80078ba: 889b ldrh r3, [r3, #4] 80078bc: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) 80078be: 683b ldr r3, [r7, #0] 80078c0: 781b ldrb r3, [r3, #0] 80078c2: f003 0360 and.w r3, r3, #96 ; 0x60 80078c6: 2b40 cmp r3, #64 ; 0x40 80078c8: d007 beq.n 80078da 80078ca: 2b40 cmp r3, #64 ; 0x40 80078cc: f200 8145 bhi.w 8007b5a 80078d0: 2b00 cmp r3, #0 80078d2: d00c beq.n 80078ee 80078d4: 2b20 cmp r3, #32 80078d6: f040 8140 bne.w 8007b5a { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 80078da: 687b ldr r3, [r7, #4] 80078dc: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80078e0: 689b ldr r3, [r3, #8] 80078e2: 6839 ldr r1, [r7, #0] 80078e4: 6878 ldr r0, [r7, #4] 80078e6: 4798 blx r3 80078e8: 4603 mov r3, r0 80078ea: 73fb strb r3, [r7, #15] break; 80078ec: e13a b.n 8007b64 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) 80078ee: 683b ldr r3, [r7, #0] 80078f0: 785b ldrb r3, [r3, #1] 80078f2: 2b03 cmp r3, #3 80078f4: d007 beq.n 8007906 80078f6: 2b03 cmp r3, #3 80078f8: f300 8129 bgt.w 8007b4e 80078fc: 2b00 cmp r3, #0 80078fe: d07f beq.n 8007a00 8007900: 2b01 cmp r3, #1 8007902: d03c beq.n 800797e 8007904: e123 b.n 8007b4e { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) 8007906: 687b ldr r3, [r7, #4] 8007908: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 800790c: b2db uxtb r3, r3 800790e: 2b02 cmp r3, #2 8007910: d002 beq.n 8007918 8007912: 2b03 cmp r3, #3 8007914: d016 beq.n 8007944 8007916: e02c b.n 8007972 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8007918: 7bbb ldrb r3, [r7, #14] 800791a: 2b00 cmp r3, #0 800791c: d00d beq.n 800793a 800791e: 7bbb ldrb r3, [r7, #14] 8007920: 2b80 cmp r3, #128 ; 0x80 8007922: d00a beq.n 800793a { (void)USBD_LL_StallEP(pdev, ep_addr); 8007924: 7bbb ldrb r3, [r7, #14] 8007926: 4619 mov r1, r3 8007928: 6878 ldr r0, [r7, #4] 800792a: f001 f971 bl 8008c10 (void)USBD_LL_StallEP(pdev, 0x80U); 800792e: 2180 movs r1, #128 ; 0x80 8007930: 6878 ldr r0, [r7, #4] 8007932: f001 f96d bl 8008c10 8007936: bf00 nop } else { USBD_CtlError(pdev, req); } break; 8007938: e020 b.n 800797c USBD_CtlError(pdev, req); 800793a: 6839 ldr r1, [r7, #0] 800793c: 6878 ldr r0, [r7, #4] 800793e: f000 fc6f bl 8008220 break; 8007942: e01b b.n 800797c case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 8007944: 683b ldr r3, [r7, #0] 8007946: 885b ldrh r3, [r3, #2] 8007948: 2b00 cmp r3, #0 800794a: d10e bne.n 800796a { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) 800794c: 7bbb ldrb r3, [r7, #14] 800794e: 2b00 cmp r3, #0 8007950: d00b beq.n 800796a 8007952: 7bbb ldrb r3, [r7, #14] 8007954: 2b80 cmp r3, #128 ; 0x80 8007956: d008 beq.n 800796a 8007958: 683b ldr r3, [r7, #0] 800795a: 88db ldrh r3, [r3, #6] 800795c: 2b00 cmp r3, #0 800795e: d104 bne.n 800796a { (void)USBD_LL_StallEP(pdev, ep_addr); 8007960: 7bbb ldrb r3, [r7, #14] 8007962: 4619 mov r1, r3 8007964: 6878 ldr r0, [r7, #4] 8007966: f001 f953 bl 8008c10 } } (void)USBD_CtlSendStatus(pdev); 800796a: 6878 ldr r0, [r7, #4] 800796c: f000 fd23 bl 80083b6 break; 8007970: e004 b.n 800797c default: USBD_CtlError(pdev, req); 8007972: 6839 ldr r1, [r7, #0] 8007974: 6878 ldr r0, [r7, #4] 8007976: f000 fc53 bl 8008220 break; 800797a: bf00 nop } break; 800797c: e0ec b.n 8007b58 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) 800797e: 687b ldr r3, [r7, #4] 8007980: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007984: b2db uxtb r3, r3 8007986: 2b02 cmp r3, #2 8007988: d002 beq.n 8007990 800798a: 2b03 cmp r3, #3 800798c: d016 beq.n 80079bc 800798e: e030 b.n 80079f2 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8007990: 7bbb ldrb r3, [r7, #14] 8007992: 2b00 cmp r3, #0 8007994: d00d beq.n 80079b2 8007996: 7bbb ldrb r3, [r7, #14] 8007998: 2b80 cmp r3, #128 ; 0x80 800799a: d00a beq.n 80079b2 { (void)USBD_LL_StallEP(pdev, ep_addr); 800799c: 7bbb ldrb r3, [r7, #14] 800799e: 4619 mov r1, r3 80079a0: 6878 ldr r0, [r7, #4] 80079a2: f001 f935 bl 8008c10 (void)USBD_LL_StallEP(pdev, 0x80U); 80079a6: 2180 movs r1, #128 ; 0x80 80079a8: 6878 ldr r0, [r7, #4] 80079aa: f001 f931 bl 8008c10 80079ae: bf00 nop } else { USBD_CtlError(pdev, req); } break; 80079b0: e025 b.n 80079fe USBD_CtlError(pdev, req); 80079b2: 6839 ldr r1, [r7, #0] 80079b4: 6878 ldr r0, [r7, #4] 80079b6: f000 fc33 bl 8008220 break; 80079ba: e020 b.n 80079fe case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) 80079bc: 683b ldr r3, [r7, #0] 80079be: 885b ldrh r3, [r3, #2] 80079c0: 2b00 cmp r3, #0 80079c2: d11b bne.n 80079fc { if ((ep_addr & 0x7FU) != 0x00U) 80079c4: 7bbb ldrb r3, [r7, #14] 80079c6: f003 037f and.w r3, r3, #127 ; 0x7f 80079ca: 2b00 cmp r3, #0 80079cc: d004 beq.n 80079d8 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); 80079ce: 7bbb ldrb r3, [r7, #14] 80079d0: 4619 mov r1, r3 80079d2: 6878 ldr r0, [r7, #4] 80079d4: f001 f93b bl 8008c4e } (void)USBD_CtlSendStatus(pdev); 80079d8: 6878 ldr r0, [r7, #4] 80079da: f000 fcec bl 80083b6 ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); 80079de: 687b ldr r3, [r7, #4] 80079e0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 80079e4: 689b ldr r3, [r3, #8] 80079e6: 6839 ldr r1, [r7, #0] 80079e8: 6878 ldr r0, [r7, #4] 80079ea: 4798 blx r3 80079ec: 4603 mov r3, r0 80079ee: 73fb strb r3, [r7, #15] } break; 80079f0: e004 b.n 80079fc default: USBD_CtlError(pdev, req); 80079f2: 6839 ldr r1, [r7, #0] 80079f4: 6878 ldr r0, [r7, #4] 80079f6: f000 fc13 bl 8008220 break; 80079fa: e000 b.n 80079fe break; 80079fc: bf00 nop } break; 80079fe: e0ab b.n 8007b58 case USB_REQ_GET_STATUS: switch (pdev->dev_state) 8007a00: 687b ldr r3, [r7, #4] 8007a02: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007a06: b2db uxtb r3, r3 8007a08: 2b02 cmp r3, #2 8007a0a: d002 beq.n 8007a12 8007a0c: 2b03 cmp r3, #3 8007a0e: d032 beq.n 8007a76 8007a10: e097 b.n 8007b42 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) 8007a12: 7bbb ldrb r3, [r7, #14] 8007a14: 2b00 cmp r3, #0 8007a16: d007 beq.n 8007a28 8007a18: 7bbb ldrb r3, [r7, #14] 8007a1a: 2b80 cmp r3, #128 ; 0x80 8007a1c: d004 beq.n 8007a28 { USBD_CtlError(pdev, req); 8007a1e: 6839 ldr r1, [r7, #0] 8007a20: 6878 ldr r0, [r7, #4] 8007a22: f000 fbfd bl 8008220 break; 8007a26: e091 b.n 8007b4c } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8007a28: f997 300e ldrsb.w r3, [r7, #14] 8007a2c: 2b00 cmp r3, #0 8007a2e: da0b bge.n 8007a48 8007a30: 7bbb ldrb r3, [r7, #14] 8007a32: f003 027f and.w r2, r3, #127 ; 0x7f 8007a36: 4613 mov r3, r2 8007a38: 009b lsls r3, r3, #2 8007a3a: 4413 add r3, r2 8007a3c: 009b lsls r3, r3, #2 8007a3e: 3310 adds r3, #16 8007a40: 687a ldr r2, [r7, #4] 8007a42: 4413 add r3, r2 8007a44: 3304 adds r3, #4 8007a46: e00b b.n 8007a60 &pdev->ep_out[ep_addr & 0x7FU]; 8007a48: 7bbb ldrb r3, [r7, #14] 8007a4a: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8007a4e: 4613 mov r3, r2 8007a50: 009b lsls r3, r3, #2 8007a52: 4413 add r3, r2 8007a54: 009b lsls r3, r3, #2 8007a56: f503 73a8 add.w r3, r3, #336 ; 0x150 8007a5a: 687a ldr r2, [r7, #4] 8007a5c: 4413 add r3, r2 8007a5e: 3304 adds r3, #4 8007a60: 60bb str r3, [r7, #8] pep->status = 0x0000U; 8007a62: 68bb ldr r3, [r7, #8] 8007a64: 2200 movs r2, #0 8007a66: 601a str r2, [r3, #0] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8007a68: 68bb ldr r3, [r7, #8] 8007a6a: 2202 movs r2, #2 8007a6c: 4619 mov r1, r3 8007a6e: 6878 ldr r0, [r7, #4] 8007a70: f000 fc47 bl 8008302 break; 8007a74: e06a b.n 8007b4c case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) 8007a76: f997 300e ldrsb.w r3, [r7, #14] 8007a7a: 2b00 cmp r3, #0 8007a7c: da11 bge.n 8007aa2 { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) 8007a7e: 7bbb ldrb r3, [r7, #14] 8007a80: f003 020f and.w r2, r3, #15 8007a84: 6879 ldr r1, [r7, #4] 8007a86: 4613 mov r3, r2 8007a88: 009b lsls r3, r3, #2 8007a8a: 4413 add r3, r2 8007a8c: 009b lsls r3, r3, #2 8007a8e: 440b add r3, r1 8007a90: 3324 adds r3, #36 ; 0x24 8007a92: 881b ldrh r3, [r3, #0] 8007a94: 2b00 cmp r3, #0 8007a96: d117 bne.n 8007ac8 { USBD_CtlError(pdev, req); 8007a98: 6839 ldr r1, [r7, #0] 8007a9a: 6878 ldr r0, [r7, #4] 8007a9c: f000 fbc0 bl 8008220 break; 8007aa0: e054 b.n 8007b4c } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) 8007aa2: 7bbb ldrb r3, [r7, #14] 8007aa4: f003 020f and.w r2, r3, #15 8007aa8: 6879 ldr r1, [r7, #4] 8007aaa: 4613 mov r3, r2 8007aac: 009b lsls r3, r3, #2 8007aae: 4413 add r3, r2 8007ab0: 009b lsls r3, r3, #2 8007ab2: 440b add r3, r1 8007ab4: f503 73b2 add.w r3, r3, #356 ; 0x164 8007ab8: 881b ldrh r3, [r3, #0] 8007aba: 2b00 cmp r3, #0 8007abc: d104 bne.n 8007ac8 { USBD_CtlError(pdev, req); 8007abe: 6839 ldr r1, [r7, #0] 8007ac0: 6878 ldr r0, [r7, #4] 8007ac2: f000 fbad bl 8008220 break; 8007ac6: e041 b.n 8007b4c } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8007ac8: f997 300e ldrsb.w r3, [r7, #14] 8007acc: 2b00 cmp r3, #0 8007ace: da0b bge.n 8007ae8 8007ad0: 7bbb ldrb r3, [r7, #14] 8007ad2: f003 027f and.w r2, r3, #127 ; 0x7f 8007ad6: 4613 mov r3, r2 8007ad8: 009b lsls r3, r3, #2 8007ada: 4413 add r3, r2 8007adc: 009b lsls r3, r3, #2 8007ade: 3310 adds r3, #16 8007ae0: 687a ldr r2, [r7, #4] 8007ae2: 4413 add r3, r2 8007ae4: 3304 adds r3, #4 8007ae6: e00b b.n 8007b00 &pdev->ep_out[ep_addr & 0x7FU]; 8007ae8: 7bbb ldrb r3, [r7, #14] 8007aea: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ 8007aee: 4613 mov r3, r2 8007af0: 009b lsls r3, r3, #2 8007af2: 4413 add r3, r2 8007af4: 009b lsls r3, r3, #2 8007af6: f503 73a8 add.w r3, r3, #336 ; 0x150 8007afa: 687a ldr r2, [r7, #4] 8007afc: 4413 add r3, r2 8007afe: 3304 adds r3, #4 8007b00: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) 8007b02: 7bbb ldrb r3, [r7, #14] 8007b04: 2b00 cmp r3, #0 8007b06: d002 beq.n 8007b0e 8007b08: 7bbb ldrb r3, [r7, #14] 8007b0a: 2b80 cmp r3, #128 ; 0x80 8007b0c: d103 bne.n 8007b16 { pep->status = 0x0000U; 8007b0e: 68bb ldr r3, [r7, #8] 8007b10: 2200 movs r2, #0 8007b12: 601a str r2, [r3, #0] 8007b14: e00e b.n 8007b34 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) 8007b16: 7bbb ldrb r3, [r7, #14] 8007b18: 4619 mov r1, r3 8007b1a: 6878 ldr r0, [r7, #4] 8007b1c: f001 f8b6 bl 8008c8c 8007b20: 4603 mov r3, r0 8007b22: 2b00 cmp r3, #0 8007b24: d003 beq.n 8007b2e { pep->status = 0x0001U; 8007b26: 68bb ldr r3, [r7, #8] 8007b28: 2201 movs r2, #1 8007b2a: 601a str r2, [r3, #0] 8007b2c: e002 b.n 8007b34 } else { pep->status = 0x0000U; 8007b2e: 68bb ldr r3, [r7, #8] 8007b30: 2200 movs r2, #0 8007b32: 601a str r2, [r3, #0] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); 8007b34: 68bb ldr r3, [r7, #8] 8007b36: 2202 movs r2, #2 8007b38: 4619 mov r1, r3 8007b3a: 6878 ldr r0, [r7, #4] 8007b3c: f000 fbe1 bl 8008302 break; 8007b40: e004 b.n 8007b4c default: USBD_CtlError(pdev, req); 8007b42: 6839 ldr r1, [r7, #0] 8007b44: 6878 ldr r0, [r7, #4] 8007b46: f000 fb6b bl 8008220 break; 8007b4a: bf00 nop } break; 8007b4c: e004 b.n 8007b58 default: USBD_CtlError(pdev, req); 8007b4e: 6839 ldr r1, [r7, #0] 8007b50: 6878 ldr r0, [r7, #4] 8007b52: f000 fb65 bl 8008220 break; 8007b56: bf00 nop } break; 8007b58: e004 b.n 8007b64 default: USBD_CtlError(pdev, req); 8007b5a: 6839 ldr r1, [r7, #0] 8007b5c: 6878 ldr r0, [r7, #4] 8007b5e: f000 fb5f bl 8008220 break; 8007b62: bf00 nop } return ret; 8007b64: 7bfb ldrb r3, [r7, #15] } 8007b66: 4618 mov r0, r3 8007b68: 3710 adds r7, #16 8007b6a: 46bd mov sp, r7 8007b6c: bd80 pop {r7, pc} ... 08007b70 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8007b70: b580 push {r7, lr} 8007b72: b084 sub sp, #16 8007b74: af00 add r7, sp, #0 8007b76: 6078 str r0, [r7, #4] 8007b78: 6039 str r1, [r7, #0] uint16_t len = 0U; 8007b7a: 2300 movs r3, #0 8007b7c: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; 8007b7e: 2300 movs r3, #0 8007b80: 60fb str r3, [r7, #12] uint8_t err = 0U; 8007b82: 2300 movs r3, #0 8007b84: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) 8007b86: 683b ldr r3, [r7, #0] 8007b88: 885b ldrh r3, [r3, #2] 8007b8a: 0a1b lsrs r3, r3, #8 8007b8c: b29b uxth r3, r3 8007b8e: 3b01 subs r3, #1 8007b90: 2b0e cmp r3, #14 8007b92: f200 8152 bhi.w 8007e3a 8007b96: a201 add r2, pc, #4 ; (adr r2, 8007b9c ) 8007b98: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007b9c: 08007c0d .word 0x08007c0d 8007ba0: 08007c25 .word 0x08007c25 8007ba4: 08007c65 .word 0x08007c65 8007ba8: 08007e3b .word 0x08007e3b 8007bac: 08007e3b .word 0x08007e3b 8007bb0: 08007ddb .word 0x08007ddb 8007bb4: 08007e07 .word 0x08007e07 8007bb8: 08007e3b .word 0x08007e3b 8007bbc: 08007e3b .word 0x08007e3b 8007bc0: 08007e3b .word 0x08007e3b 8007bc4: 08007e3b .word 0x08007e3b 8007bc8: 08007e3b .word 0x08007e3b 8007bcc: 08007e3b .word 0x08007e3b 8007bd0: 08007e3b .word 0x08007e3b 8007bd4: 08007bd9 .word 0x08007bd9 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) 8007bd8: 687b ldr r3, [r7, #4] 8007bda: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007bde: 69db ldr r3, [r3, #28] 8007be0: 2b00 cmp r3, #0 8007be2: d00b beq.n 8007bfc { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); 8007be4: 687b ldr r3, [r7, #4] 8007be6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007bea: 69db ldr r3, [r3, #28] 8007bec: 687a ldr r2, [r7, #4] 8007bee: 7c12 ldrb r2, [r2, #16] 8007bf0: f107 0108 add.w r1, r7, #8 8007bf4: 4610 mov r0, r2 8007bf6: 4798 blx r3 8007bf8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007bfa: e126 b.n 8007e4a USBD_CtlError(pdev, req); 8007bfc: 6839 ldr r1, [r7, #0] 8007bfe: 6878 ldr r0, [r7, #4] 8007c00: f000 fb0e bl 8008220 err++; 8007c04: 7afb ldrb r3, [r7, #11] 8007c06: 3301 adds r3, #1 8007c08: 72fb strb r3, [r7, #11] break; 8007c0a: e11e b.n 8007e4a #endif case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); 8007c0c: 687b ldr r3, [r7, #4] 8007c0e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007c12: 681b ldr r3, [r3, #0] 8007c14: 687a ldr r2, [r7, #4] 8007c16: 7c12 ldrb r2, [r2, #16] 8007c18: f107 0108 add.w r1, r7, #8 8007c1c: 4610 mov r0, r2 8007c1e: 4798 blx r3 8007c20: 60f8 str r0, [r7, #12] break; 8007c22: e112 b.n 8007e4a case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8007c24: 687b ldr r3, [r7, #4] 8007c26: 7c1b ldrb r3, [r3, #16] 8007c28: 2b00 cmp r3, #0 8007c2a: d10d bne.n 8007c48 { pbuf = pdev->pClass->GetHSConfigDescriptor(&len); 8007c2c: 687b ldr r3, [r7, #4] 8007c2e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007c32: 6a9b ldr r3, [r3, #40] ; 0x28 8007c34: f107 0208 add.w r2, r7, #8 8007c38: 4610 mov r0, r2 8007c3a: 4798 blx r3 8007c3c: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8007c3e: 68fb ldr r3, [r7, #12] 8007c40: 3301 adds r3, #1 8007c42: 2202 movs r2, #2 8007c44: 701a strb r2, [r3, #0] else { pbuf = pdev->pClass->GetFSConfigDescriptor(&len); pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; 8007c46: e100 b.n 8007e4a pbuf = pdev->pClass->GetFSConfigDescriptor(&len); 8007c48: 687b ldr r3, [r7, #4] 8007c4a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007c4e: 6adb ldr r3, [r3, #44] ; 0x2c 8007c50: f107 0208 add.w r2, r7, #8 8007c54: 4610 mov r0, r2 8007c56: 4798 blx r3 8007c58: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; 8007c5a: 68fb ldr r3, [r7, #12] 8007c5c: 3301 adds r3, #1 8007c5e: 2202 movs r2, #2 8007c60: 701a strb r2, [r3, #0] break; 8007c62: e0f2 b.n 8007e4a case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) 8007c64: 683b ldr r3, [r7, #0] 8007c66: 885b ldrh r3, [r3, #2] 8007c68: b2db uxtb r3, r3 8007c6a: 2b05 cmp r3, #5 8007c6c: f200 80ac bhi.w 8007dc8 8007c70: a201 add r2, pc, #4 ; (adr r2, 8007c78 ) 8007c72: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007c76: bf00 nop 8007c78: 08007c91 .word 0x08007c91 8007c7c: 08007cc5 .word 0x08007cc5 8007c80: 08007cf9 .word 0x08007cf9 8007c84: 08007d2d .word 0x08007d2d 8007c88: 08007d61 .word 0x08007d61 8007c8c: 08007d95 .word 0x08007d95 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) 8007c90: 687b ldr r3, [r7, #4] 8007c92: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007c96: 685b ldr r3, [r3, #4] 8007c98: 2b00 cmp r3, #0 8007c9a: d00b beq.n 8007cb4 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); 8007c9c: 687b ldr r3, [r7, #4] 8007c9e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007ca2: 685b ldr r3, [r3, #4] 8007ca4: 687a ldr r2, [r7, #4] 8007ca6: 7c12 ldrb r2, [r2, #16] 8007ca8: f107 0108 add.w r1, r7, #8 8007cac: 4610 mov r0, r2 8007cae: 4798 blx r3 8007cb0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007cb2: e091 b.n 8007dd8 USBD_CtlError(pdev, req); 8007cb4: 6839 ldr r1, [r7, #0] 8007cb6: 6878 ldr r0, [r7, #4] 8007cb8: f000 fab2 bl 8008220 err++; 8007cbc: 7afb ldrb r3, [r7, #11] 8007cbe: 3301 adds r3, #1 8007cc0: 72fb strb r3, [r7, #11] break; 8007cc2: e089 b.n 8007dd8 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) 8007cc4: 687b ldr r3, [r7, #4] 8007cc6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007cca: 689b ldr r3, [r3, #8] 8007ccc: 2b00 cmp r3, #0 8007cce: d00b beq.n 8007ce8 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); 8007cd0: 687b ldr r3, [r7, #4] 8007cd2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007cd6: 689b ldr r3, [r3, #8] 8007cd8: 687a ldr r2, [r7, #4] 8007cda: 7c12 ldrb r2, [r2, #16] 8007cdc: f107 0108 add.w r1, r7, #8 8007ce0: 4610 mov r0, r2 8007ce2: 4798 blx r3 8007ce4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007ce6: e077 b.n 8007dd8 USBD_CtlError(pdev, req); 8007ce8: 6839 ldr r1, [r7, #0] 8007cea: 6878 ldr r0, [r7, #4] 8007cec: f000 fa98 bl 8008220 err++; 8007cf0: 7afb ldrb r3, [r7, #11] 8007cf2: 3301 adds r3, #1 8007cf4: 72fb strb r3, [r7, #11] break; 8007cf6: e06f b.n 8007dd8 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) 8007cf8: 687b ldr r3, [r7, #4] 8007cfa: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007cfe: 68db ldr r3, [r3, #12] 8007d00: 2b00 cmp r3, #0 8007d02: d00b beq.n 8007d1c { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); 8007d04: 687b ldr r3, [r7, #4] 8007d06: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007d0a: 68db ldr r3, [r3, #12] 8007d0c: 687a ldr r2, [r7, #4] 8007d0e: 7c12 ldrb r2, [r2, #16] 8007d10: f107 0108 add.w r1, r7, #8 8007d14: 4610 mov r0, r2 8007d16: 4798 blx r3 8007d18: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007d1a: e05d b.n 8007dd8 USBD_CtlError(pdev, req); 8007d1c: 6839 ldr r1, [r7, #0] 8007d1e: 6878 ldr r0, [r7, #4] 8007d20: f000 fa7e bl 8008220 err++; 8007d24: 7afb ldrb r3, [r7, #11] 8007d26: 3301 adds r3, #1 8007d28: 72fb strb r3, [r7, #11] break; 8007d2a: e055 b.n 8007dd8 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) 8007d2c: 687b ldr r3, [r7, #4] 8007d2e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007d32: 691b ldr r3, [r3, #16] 8007d34: 2b00 cmp r3, #0 8007d36: d00b beq.n 8007d50 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); 8007d38: 687b ldr r3, [r7, #4] 8007d3a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007d3e: 691b ldr r3, [r3, #16] 8007d40: 687a ldr r2, [r7, #4] 8007d42: 7c12 ldrb r2, [r2, #16] 8007d44: f107 0108 add.w r1, r7, #8 8007d48: 4610 mov r0, r2 8007d4a: 4798 blx r3 8007d4c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007d4e: e043 b.n 8007dd8 USBD_CtlError(pdev, req); 8007d50: 6839 ldr r1, [r7, #0] 8007d52: 6878 ldr r0, [r7, #4] 8007d54: f000 fa64 bl 8008220 err++; 8007d58: 7afb ldrb r3, [r7, #11] 8007d5a: 3301 adds r3, #1 8007d5c: 72fb strb r3, [r7, #11] break; 8007d5e: e03b b.n 8007dd8 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) 8007d60: 687b ldr r3, [r7, #4] 8007d62: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007d66: 695b ldr r3, [r3, #20] 8007d68: 2b00 cmp r3, #0 8007d6a: d00b beq.n 8007d84 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); 8007d6c: 687b ldr r3, [r7, #4] 8007d6e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007d72: 695b ldr r3, [r3, #20] 8007d74: 687a ldr r2, [r7, #4] 8007d76: 7c12 ldrb r2, [r2, #16] 8007d78: f107 0108 add.w r1, r7, #8 8007d7c: 4610 mov r0, r2 8007d7e: 4798 blx r3 8007d80: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007d82: e029 b.n 8007dd8 USBD_CtlError(pdev, req); 8007d84: 6839 ldr r1, [r7, #0] 8007d86: 6878 ldr r0, [r7, #4] 8007d88: f000 fa4a bl 8008220 err++; 8007d8c: 7afb ldrb r3, [r7, #11] 8007d8e: 3301 adds r3, #1 8007d90: 72fb strb r3, [r7, #11] break; 8007d92: e021 b.n 8007dd8 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) 8007d94: 687b ldr r3, [r7, #4] 8007d96: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007d9a: 699b ldr r3, [r3, #24] 8007d9c: 2b00 cmp r3, #0 8007d9e: d00b beq.n 8007db8 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); 8007da0: 687b ldr r3, [r7, #4] 8007da2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 8007da6: 699b ldr r3, [r3, #24] 8007da8: 687a ldr r2, [r7, #4] 8007daa: 7c12 ldrb r2, [r2, #16] 8007dac: f107 0108 add.w r1, r7, #8 8007db0: 4610 mov r0, r2 8007db2: 4798 blx r3 8007db4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007db6: e00f b.n 8007dd8 USBD_CtlError(pdev, req); 8007db8: 6839 ldr r1, [r7, #0] 8007dba: 6878 ldr r0, [r7, #4] 8007dbc: f000 fa30 bl 8008220 err++; 8007dc0: 7afb ldrb r3, [r7, #11] 8007dc2: 3301 adds r3, #1 8007dc4: 72fb strb r3, [r7, #11] break; 8007dc6: e007 b.n 8007dd8 err++; } #endif #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); 8007dc8: 6839 ldr r1, [r7, #0] 8007dca: 6878 ldr r0, [r7, #4] 8007dcc: f000 fa28 bl 8008220 err++; 8007dd0: 7afb ldrb r3, [r7, #11] 8007dd2: 3301 adds r3, #1 8007dd4: 72fb strb r3, [r7, #11] #endif break; 8007dd6: bf00 nop } break; 8007dd8: e037 b.n 8007e4a case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) 8007dda: 687b ldr r3, [r7, #4] 8007ddc: 7c1b ldrb r3, [r3, #16] 8007dde: 2b00 cmp r3, #0 8007de0: d109 bne.n 8007df6 { pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); 8007de2: 687b ldr r3, [r7, #4] 8007de4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007de8: 6b5b ldr r3, [r3, #52] ; 0x34 8007dea: f107 0208 add.w r2, r7, #8 8007dee: 4610 mov r0, r2 8007df0: 4798 blx r3 8007df2: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; 8007df4: e029 b.n 8007e4a USBD_CtlError(pdev, req); 8007df6: 6839 ldr r1, [r7, #0] 8007df8: 6878 ldr r0, [r7, #4] 8007dfa: f000 fa11 bl 8008220 err++; 8007dfe: 7afb ldrb r3, [r7, #11] 8007e00: 3301 adds r3, #1 8007e02: 72fb strb r3, [r7, #11] break; 8007e04: e021 b.n 8007e4a case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) 8007e06: 687b ldr r3, [r7, #4] 8007e08: 7c1b ldrb r3, [r3, #16] 8007e0a: 2b00 cmp r3, #0 8007e0c: d10d bne.n 8007e2a { pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); 8007e0e: 687b ldr r3, [r7, #4] 8007e10: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 8007e14: 6b1b ldr r3, [r3, #48] ; 0x30 8007e16: f107 0208 add.w r2, r7, #8 8007e1a: 4610 mov r0, r2 8007e1c: 4798 blx r3 8007e1e: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; 8007e20: 68fb ldr r3, [r7, #12] 8007e22: 3301 adds r3, #1 8007e24: 2207 movs r2, #7 8007e26: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; 8007e28: e00f b.n 8007e4a USBD_CtlError(pdev, req); 8007e2a: 6839 ldr r1, [r7, #0] 8007e2c: 6878 ldr r0, [r7, #4] 8007e2e: f000 f9f7 bl 8008220 err++; 8007e32: 7afb ldrb r3, [r7, #11] 8007e34: 3301 adds r3, #1 8007e36: 72fb strb r3, [r7, #11] break; 8007e38: e007 b.n 8007e4a default: USBD_CtlError(pdev, req); 8007e3a: 6839 ldr r1, [r7, #0] 8007e3c: 6878 ldr r0, [r7, #4] 8007e3e: f000 f9ef bl 8008220 err++; 8007e42: 7afb ldrb r3, [r7, #11] 8007e44: 3301 adds r3, #1 8007e46: 72fb strb r3, [r7, #11] break; 8007e48: bf00 nop } if (err != 0U) 8007e4a: 7afb ldrb r3, [r7, #11] 8007e4c: 2b00 cmp r3, #0 8007e4e: d11e bne.n 8007e8e { return; } if (req->wLength != 0U) 8007e50: 683b ldr r3, [r7, #0] 8007e52: 88db ldrh r3, [r3, #6] 8007e54: 2b00 cmp r3, #0 8007e56: d016 beq.n 8007e86 { if (len != 0U) 8007e58: 893b ldrh r3, [r7, #8] 8007e5a: 2b00 cmp r3, #0 8007e5c: d00e beq.n 8007e7c { len = MIN(len, req->wLength); 8007e5e: 683b ldr r3, [r7, #0] 8007e60: 88da ldrh r2, [r3, #6] 8007e62: 893b ldrh r3, [r7, #8] 8007e64: 4293 cmp r3, r2 8007e66: bf28 it cs 8007e68: 4613 movcs r3, r2 8007e6a: b29b uxth r3, r3 8007e6c: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); 8007e6e: 893b ldrh r3, [r7, #8] 8007e70: 461a mov r2, r3 8007e72: 68f9 ldr r1, [r7, #12] 8007e74: 6878 ldr r0, [r7, #4] 8007e76: f000 fa44 bl 8008302 8007e7a: e009 b.n 8007e90 } else { USBD_CtlError(pdev, req); 8007e7c: 6839 ldr r1, [r7, #0] 8007e7e: 6878 ldr r0, [r7, #4] 8007e80: f000 f9ce bl 8008220 8007e84: e004 b.n 8007e90 } } else { (void)USBD_CtlSendStatus(pdev); 8007e86: 6878 ldr r0, [r7, #4] 8007e88: f000 fa95 bl 80083b6 8007e8c: e000 b.n 8007e90 return; 8007e8e: bf00 nop } } 8007e90: 3710 adds r7, #16 8007e92: 46bd mov sp, r7 8007e94: bd80 pop {r7, pc} 8007e96: bf00 nop 08007e98 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8007e98: b580 push {r7, lr} 8007e9a: b084 sub sp, #16 8007e9c: af00 add r7, sp, #0 8007e9e: 6078 str r0, [r7, #4] 8007ea0: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) 8007ea2: 683b ldr r3, [r7, #0] 8007ea4: 889b ldrh r3, [r3, #4] 8007ea6: 2b00 cmp r3, #0 8007ea8: d131 bne.n 8007f0e 8007eaa: 683b ldr r3, [r7, #0] 8007eac: 88db ldrh r3, [r3, #6] 8007eae: 2b00 cmp r3, #0 8007eb0: d12d bne.n 8007f0e 8007eb2: 683b ldr r3, [r7, #0] 8007eb4: 885b ldrh r3, [r3, #2] 8007eb6: 2b7f cmp r3, #127 ; 0x7f 8007eb8: d829 bhi.n 8007f0e { dev_addr = (uint8_t)(req->wValue) & 0x7FU; 8007eba: 683b ldr r3, [r7, #0] 8007ebc: 885b ldrh r3, [r3, #2] 8007ebe: b2db uxtb r3, r3 8007ec0: f003 037f and.w r3, r3, #127 ; 0x7f 8007ec4: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007ec6: 687b ldr r3, [r7, #4] 8007ec8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007ecc: b2db uxtb r3, r3 8007ece: 2b03 cmp r3, #3 8007ed0: d104 bne.n 8007edc { USBD_CtlError(pdev, req); 8007ed2: 6839 ldr r1, [r7, #0] 8007ed4: 6878 ldr r0, [r7, #4] 8007ed6: f000 f9a3 bl 8008220 if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007eda: e01d b.n 8007f18 } else { pdev->dev_address = dev_addr; 8007edc: 687b ldr r3, [r7, #4] 8007ede: 7bfa ldrb r2, [r7, #15] 8007ee0: f883 229e strb.w r2, [r3, #670] ; 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); 8007ee4: 7bfb ldrb r3, [r7, #15] 8007ee6: 4619 mov r1, r3 8007ee8: 6878 ldr r0, [r7, #4] 8007eea: f000 fefb bl 8008ce4 (void)USBD_CtlSendStatus(pdev); 8007eee: 6878 ldr r0, [r7, #4] 8007ef0: f000 fa61 bl 80083b6 if (dev_addr != 0U) 8007ef4: 7bfb ldrb r3, [r7, #15] 8007ef6: 2b00 cmp r3, #0 8007ef8: d004 beq.n 8007f04 { pdev->dev_state = USBD_STATE_ADDRESSED; 8007efa: 687b ldr r3, [r7, #4] 8007efc: 2202 movs r2, #2 8007efe: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007f02: e009 b.n 8007f18 } else { pdev->dev_state = USBD_STATE_DEFAULT; 8007f04: 687b ldr r3, [r7, #4] 8007f06: 2201 movs r2, #1 8007f08: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) 8007f0c: e004 b.n 8007f18 } } } else { USBD_CtlError(pdev, req); 8007f0e: 6839 ldr r1, [r7, #0] 8007f10: 6878 ldr r0, [r7, #4] 8007f12: f000 f985 bl 8008220 } } 8007f16: bf00 nop 8007f18: bf00 nop 8007f1a: 3710 adds r7, #16 8007f1c: 46bd mov sp, r7 8007f1e: bd80 pop {r7, pc} 08007f20 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8007f20: b580 push {r7, lr} 8007f22: b084 sub sp, #16 8007f24: af00 add r7, sp, #0 8007f26: 6078 str r0, [r7, #4] 8007f28: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; 8007f2a: 2300 movs r3, #0 8007f2c: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); 8007f2e: 683b ldr r3, [r7, #0] 8007f30: 885b ldrh r3, [r3, #2] 8007f32: b2da uxtb r2, r3 8007f34: 4b4c ldr r3, [pc, #304] ; (8008068 ) 8007f36: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) 8007f38: 4b4b ldr r3, [pc, #300] ; (8008068 ) 8007f3a: 781b ldrb r3, [r3, #0] 8007f3c: 2b01 cmp r3, #1 8007f3e: d905 bls.n 8007f4c { USBD_CtlError(pdev, req); 8007f40: 6839 ldr r1, [r7, #0] 8007f42: 6878 ldr r0, [r7, #4] 8007f44: f000 f96c bl 8008220 return USBD_FAIL; 8007f48: 2303 movs r3, #3 8007f4a: e088 b.n 800805e } switch (pdev->dev_state) 8007f4c: 687b ldr r3, [r7, #4] 8007f4e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8007f52: b2db uxtb r3, r3 8007f54: 2b02 cmp r3, #2 8007f56: d002 beq.n 8007f5e 8007f58: 2b03 cmp r3, #3 8007f5a: d025 beq.n 8007fa8 8007f5c: e071 b.n 8008042 { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) 8007f5e: 4b42 ldr r3, [pc, #264] ; (8008068 ) 8007f60: 781b ldrb r3, [r3, #0] 8007f62: 2b00 cmp r3, #0 8007f64: d01c beq.n 8007fa0 { pdev->dev_config = cfgidx; 8007f66: 4b40 ldr r3, [pc, #256] ; (8008068 ) 8007f68: 781b ldrb r3, [r3, #0] 8007f6a: 461a mov r2, r3 8007f6c: 687b ldr r3, [r7, #4] 8007f6e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8007f70: 4b3d ldr r3, [pc, #244] ; (8008068 ) 8007f72: 781b ldrb r3, [r3, #0] 8007f74: 4619 mov r1, r3 8007f76: 6878 ldr r0, [r7, #4] 8007f78: f7ff f91e bl 80071b8 8007f7c: 4603 mov r3, r0 8007f7e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 8007f80: 7bfb ldrb r3, [r7, #15] 8007f82: 2b00 cmp r3, #0 8007f84: d004 beq.n 8007f90 { USBD_CtlError(pdev, req); 8007f86: 6839 ldr r1, [r7, #0] 8007f88: 6878 ldr r0, [r7, #4] 8007f8a: f000 f949 bl 8008220 } else { (void)USBD_CtlSendStatus(pdev); } break; 8007f8e: e065 b.n 800805c (void)USBD_CtlSendStatus(pdev); 8007f90: 6878 ldr r0, [r7, #4] 8007f92: f000 fa10 bl 80083b6 pdev->dev_state = USBD_STATE_CONFIGURED; 8007f96: 687b ldr r3, [r7, #4] 8007f98: 2203 movs r2, #3 8007f9a: f883 229c strb.w r2, [r3, #668] ; 0x29c break; 8007f9e: e05d b.n 800805c (void)USBD_CtlSendStatus(pdev); 8007fa0: 6878 ldr r0, [r7, #4] 8007fa2: f000 fa08 bl 80083b6 break; 8007fa6: e059 b.n 800805c case USBD_STATE_CONFIGURED: if (cfgidx == 0U) 8007fa8: 4b2f ldr r3, [pc, #188] ; (8008068 ) 8007faa: 781b ldrb r3, [r3, #0] 8007fac: 2b00 cmp r3, #0 8007fae: d112 bne.n 8007fd6 { pdev->dev_state = USBD_STATE_ADDRESSED; 8007fb0: 687b ldr r3, [r7, #4] 8007fb2: 2202 movs r2, #2 8007fb4: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->dev_config = cfgidx; 8007fb8: 4b2b ldr r3, [pc, #172] ; (8008068 ) 8007fba: 781b ldrb r3, [r3, #0] 8007fbc: 461a mov r2, r3 8007fbe: 687b ldr r3, [r7, #4] 8007fc0: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); 8007fc2: 4b29 ldr r3, [pc, #164] ; (8008068 ) 8007fc4: 781b ldrb r3, [r3, #0] 8007fc6: 4619 mov r1, r3 8007fc8: 6878 ldr r0, [r7, #4] 8007fca: f7ff f911 bl 80071f0 (void)USBD_CtlSendStatus(pdev); 8007fce: 6878 ldr r0, [r7, #4] 8007fd0: f000 f9f1 bl 80083b6 } else { (void)USBD_CtlSendStatus(pdev); } break; 8007fd4: e042 b.n 800805c else if (cfgidx != pdev->dev_config) 8007fd6: 4b24 ldr r3, [pc, #144] ; (8008068 ) 8007fd8: 781b ldrb r3, [r3, #0] 8007fda: 461a mov r2, r3 8007fdc: 687b ldr r3, [r7, #4] 8007fde: 685b ldr r3, [r3, #4] 8007fe0: 429a cmp r2, r3 8007fe2: d02a beq.n 800803a (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 8007fe4: 687b ldr r3, [r7, #4] 8007fe6: 685b ldr r3, [r3, #4] 8007fe8: b2db uxtb r3, r3 8007fea: 4619 mov r1, r3 8007fec: 6878 ldr r0, [r7, #4] 8007fee: f7ff f8ff bl 80071f0 pdev->dev_config = cfgidx; 8007ff2: 4b1d ldr r3, [pc, #116] ; (8008068 ) 8007ff4: 781b ldrb r3, [r3, #0] 8007ff6: 461a mov r2, r3 8007ff8: 687b ldr r3, [r7, #4] 8007ffa: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); 8007ffc: 4b1a ldr r3, [pc, #104] ; (8008068 ) 8007ffe: 781b ldrb r3, [r3, #0] 8008000: 4619 mov r1, r3 8008002: 6878 ldr r0, [r7, #4] 8008004: f7ff f8d8 bl 80071b8 8008008: 4603 mov r3, r0 800800a: 73fb strb r3, [r7, #15] if (ret != USBD_OK) 800800c: 7bfb ldrb r3, [r7, #15] 800800e: 2b00 cmp r3, #0 8008010: d00f beq.n 8008032 USBD_CtlError(pdev, req); 8008012: 6839 ldr r1, [r7, #0] 8008014: 6878 ldr r0, [r7, #4] 8008016: f000 f903 bl 8008220 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); 800801a: 687b ldr r3, [r7, #4] 800801c: 685b ldr r3, [r3, #4] 800801e: b2db uxtb r3, r3 8008020: 4619 mov r1, r3 8008022: 6878 ldr r0, [r7, #4] 8008024: f7ff f8e4 bl 80071f0 pdev->dev_state = USBD_STATE_ADDRESSED; 8008028: 687b ldr r3, [r7, #4] 800802a: 2202 movs r2, #2 800802c: f883 229c strb.w r2, [r3, #668] ; 0x29c break; 8008030: e014 b.n 800805c (void)USBD_CtlSendStatus(pdev); 8008032: 6878 ldr r0, [r7, #4] 8008034: f000 f9bf bl 80083b6 break; 8008038: e010 b.n 800805c (void)USBD_CtlSendStatus(pdev); 800803a: 6878 ldr r0, [r7, #4] 800803c: f000 f9bb bl 80083b6 break; 8008040: e00c b.n 800805c default: USBD_CtlError(pdev, req); 8008042: 6839 ldr r1, [r7, #0] 8008044: 6878 ldr r0, [r7, #4] 8008046: f000 f8eb bl 8008220 (void)USBD_ClrClassConfig(pdev, cfgidx); 800804a: 4b07 ldr r3, [pc, #28] ; (8008068 ) 800804c: 781b ldrb r3, [r3, #0] 800804e: 4619 mov r1, r3 8008050: 6878 ldr r0, [r7, #4] 8008052: f7ff f8cd bl 80071f0 ret = USBD_FAIL; 8008056: 2303 movs r3, #3 8008058: 73fb strb r3, [r7, #15] break; 800805a: bf00 nop } return ret; 800805c: 7bfb ldrb r3, [r7, #15] } 800805e: 4618 mov r0, r3 8008060: 3710 adds r7, #16 8008062: 46bd mov sp, r7 8008064: bd80 pop {r7, pc} 8008066: bf00 nop 8008068: 200001ac .word 0x200001ac 0800806c : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 800806c: b580 push {r7, lr} 800806e: b082 sub sp, #8 8008070: af00 add r7, sp, #0 8008072: 6078 str r0, [r7, #4] 8008074: 6039 str r1, [r7, #0] if (req->wLength != 1U) 8008076: 683b ldr r3, [r7, #0] 8008078: 88db ldrh r3, [r3, #6] 800807a: 2b01 cmp r3, #1 800807c: d004 beq.n 8008088 { USBD_CtlError(pdev, req); 800807e: 6839 ldr r1, [r7, #0] 8008080: 6878 ldr r0, [r7, #4] 8008082: f000 f8cd bl 8008220 default: USBD_CtlError(pdev, req); break; } } } 8008086: e023 b.n 80080d0 switch (pdev->dev_state) 8008088: 687b ldr r3, [r7, #4] 800808a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 800808e: b2db uxtb r3, r3 8008090: 2b02 cmp r3, #2 8008092: dc02 bgt.n 800809a 8008094: 2b00 cmp r3, #0 8008096: dc03 bgt.n 80080a0 8008098: e015 b.n 80080c6 800809a: 2b03 cmp r3, #3 800809c: d00b beq.n 80080b6 800809e: e012 b.n 80080c6 pdev->dev_default_config = 0U; 80080a0: 687b ldr r3, [r7, #4] 80080a2: 2200 movs r2, #0 80080a4: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); 80080a6: 687b ldr r3, [r7, #4] 80080a8: 3308 adds r3, #8 80080aa: 2201 movs r2, #1 80080ac: 4619 mov r1, r3 80080ae: 6878 ldr r0, [r7, #4] 80080b0: f000 f927 bl 8008302 break; 80080b4: e00c b.n 80080d0 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); 80080b6: 687b ldr r3, [r7, #4] 80080b8: 3304 adds r3, #4 80080ba: 2201 movs r2, #1 80080bc: 4619 mov r1, r3 80080be: 6878 ldr r0, [r7, #4] 80080c0: f000 f91f bl 8008302 break; 80080c4: e004 b.n 80080d0 USBD_CtlError(pdev, req); 80080c6: 6839 ldr r1, [r7, #0] 80080c8: 6878 ldr r0, [r7, #4] 80080ca: f000 f8a9 bl 8008220 break; 80080ce: bf00 nop } 80080d0: bf00 nop 80080d2: 3708 adds r7, #8 80080d4: 46bd mov sp, r7 80080d6: bd80 pop {r7, pc} 080080d8 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 80080d8: b580 push {r7, lr} 80080da: b082 sub sp, #8 80080dc: af00 add r7, sp, #0 80080de: 6078 str r0, [r7, #4] 80080e0: 6039 str r1, [r7, #0] switch (pdev->dev_state) 80080e2: 687b ldr r3, [r7, #4] 80080e4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 80080e8: b2db uxtb r3, r3 80080ea: 3b01 subs r3, #1 80080ec: 2b02 cmp r3, #2 80080ee: d81e bhi.n 800812e { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) 80080f0: 683b ldr r3, [r7, #0] 80080f2: 88db ldrh r3, [r3, #6] 80080f4: 2b02 cmp r3, #2 80080f6: d004 beq.n 8008102 { USBD_CtlError(pdev, req); 80080f8: 6839 ldr r1, [r7, #0] 80080fa: 6878 ldr r0, [r7, #4] 80080fc: f000 f890 bl 8008220 break; 8008100: e01a b.n 8008138 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; 8008102: 687b ldr r3, [r7, #4] 8008104: 2201 movs r2, #1 8008106: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif if (pdev->dev_remote_wakeup != 0U) 8008108: 687b ldr r3, [r7, #4] 800810a: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4 800810e: 2b00 cmp r3, #0 8008110: d005 beq.n 800811e { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; 8008112: 687b ldr r3, [r7, #4] 8008114: 68db ldr r3, [r3, #12] 8008116: f043 0202 orr.w r2, r3, #2 800811a: 687b ldr r3, [r7, #4] 800811c: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); 800811e: 687b ldr r3, [r7, #4] 8008120: 330c adds r3, #12 8008122: 2202 movs r2, #2 8008124: 4619 mov r1, r3 8008126: 6878 ldr r0, [r7, #4] 8008128: f000 f8eb bl 8008302 break; 800812c: e004 b.n 8008138 default: USBD_CtlError(pdev, req); 800812e: 6839 ldr r1, [r7, #0] 8008130: 6878 ldr r0, [r7, #4] 8008132: f000 f875 bl 8008220 break; 8008136: bf00 nop } } 8008138: bf00 nop 800813a: 3708 adds r7, #8 800813c: 46bd mov sp, r7 800813e: bd80 pop {r7, pc} 08008140 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008140: b580 push {r7, lr} 8008142: b082 sub sp, #8 8008144: af00 add r7, sp, #0 8008146: 6078 str r0, [r7, #4] 8008148: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 800814a: 683b ldr r3, [r7, #0] 800814c: 885b ldrh r3, [r3, #2] 800814e: 2b01 cmp r3, #1 8008150: d106 bne.n 8008160 { pdev->dev_remote_wakeup = 1U; 8008152: 687b ldr r3, [r7, #4] 8008154: 2201 movs r2, #1 8008156: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); 800815a: 6878 ldr r0, [r7, #4] 800815c: f000 f92b bl 80083b6 } } 8008160: bf00 nop 8008162: 3708 adds r7, #8 8008164: 46bd mov sp, r7 8008166: bd80 pop {r7, pc} 08008168 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008168: b580 push {r7, lr} 800816a: b082 sub sp, #8 800816c: af00 add r7, sp, #0 800816e: 6078 str r0, [r7, #4] 8008170: 6039 str r1, [r7, #0] switch (pdev->dev_state) 8008172: 687b ldr r3, [r7, #4] 8008174: f893 329c ldrb.w r3, [r3, #668] ; 0x29c 8008178: b2db uxtb r3, r3 800817a: 3b01 subs r3, #1 800817c: 2b02 cmp r3, #2 800817e: d80b bhi.n 8008198 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 8008180: 683b ldr r3, [r7, #0] 8008182: 885b ldrh r3, [r3, #2] 8008184: 2b01 cmp r3, #1 8008186: d10c bne.n 80081a2 { pdev->dev_remote_wakeup = 0U; 8008188: 687b ldr r3, [r7, #4] 800818a: 2200 movs r2, #0 800818c: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); 8008190: 6878 ldr r0, [r7, #4] 8008192: f000 f910 bl 80083b6 } break; 8008196: e004 b.n 80081a2 default: USBD_CtlError(pdev, req); 8008198: 6839 ldr r1, [r7, #0] 800819a: 6878 ldr r0, [r7, #4] 800819c: f000 f840 bl 8008220 break; 80081a0: e000 b.n 80081a4 break; 80081a2: bf00 nop } } 80081a4: bf00 nop 80081a6: 3708 adds r7, #8 80081a8: 46bd mov sp, r7 80081aa: bd80 pop {r7, pc} 080081ac : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { 80081ac: b580 push {r7, lr} 80081ae: b084 sub sp, #16 80081b0: af00 add r7, sp, #0 80081b2: 6078 str r0, [r7, #4] 80081b4: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; 80081b6: 683b ldr r3, [r7, #0] 80081b8: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); 80081ba: 68fb ldr r3, [r7, #12] 80081bc: 781a ldrb r2, [r3, #0] 80081be: 687b ldr r3, [r7, #4] 80081c0: 701a strb r2, [r3, #0] pbuff++; 80081c2: 68fb ldr r3, [r7, #12] 80081c4: 3301 adds r3, #1 80081c6: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); 80081c8: 68fb ldr r3, [r7, #12] 80081ca: 781a ldrb r2, [r3, #0] 80081cc: 687b ldr r3, [r7, #4] 80081ce: 705a strb r2, [r3, #1] pbuff++; 80081d0: 68fb ldr r3, [r7, #12] 80081d2: 3301 adds r3, #1 80081d4: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); 80081d6: 68f8 ldr r0, [r7, #12] 80081d8: f7ff fa91 bl 80076fe 80081dc: 4603 mov r3, r0 80081de: 461a mov r2, r3 80081e0: 687b ldr r3, [r7, #4] 80081e2: 805a strh r2, [r3, #2] pbuff++; 80081e4: 68fb ldr r3, [r7, #12] 80081e6: 3301 adds r3, #1 80081e8: 60fb str r3, [r7, #12] pbuff++; 80081ea: 68fb ldr r3, [r7, #12] 80081ec: 3301 adds r3, #1 80081ee: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); 80081f0: 68f8 ldr r0, [r7, #12] 80081f2: f7ff fa84 bl 80076fe 80081f6: 4603 mov r3, r0 80081f8: 461a mov r2, r3 80081fa: 687b ldr r3, [r7, #4] 80081fc: 809a strh r2, [r3, #4] pbuff++; 80081fe: 68fb ldr r3, [r7, #12] 8008200: 3301 adds r3, #1 8008202: 60fb str r3, [r7, #12] pbuff++; 8008204: 68fb ldr r3, [r7, #12] 8008206: 3301 adds r3, #1 8008208: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); 800820a: 68f8 ldr r0, [r7, #12] 800820c: f7ff fa77 bl 80076fe 8008210: 4603 mov r3, r0 8008212: 461a mov r2, r3 8008214: 687b ldr r3, [r7, #4] 8008216: 80da strh r2, [r3, #6] } 8008218: bf00 nop 800821a: 3710 adds r7, #16 800821c: 46bd mov sp, r7 800821e: bd80 pop {r7, pc} 08008220 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { 8008220: b580 push {r7, lr} 8008222: b082 sub sp, #8 8008224: af00 add r7, sp, #0 8008226: 6078 str r0, [r7, #4] 8008228: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); 800822a: 2180 movs r1, #128 ; 0x80 800822c: 6878 ldr r0, [r7, #4] 800822e: f000 fcef bl 8008c10 (void)USBD_LL_StallEP(pdev, 0U); 8008232: 2100 movs r1, #0 8008234: 6878 ldr r0, [r7, #4] 8008236: f000 fceb bl 8008c10 } 800823a: bf00 nop 800823c: 3708 adds r7, #8 800823e: 46bd mov sp, r7 8008240: bd80 pop {r7, pc} 08008242 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { 8008242: b580 push {r7, lr} 8008244: b086 sub sp, #24 8008246: af00 add r7, sp, #0 8008248: 60f8 str r0, [r7, #12] 800824a: 60b9 str r1, [r7, #8] 800824c: 607a str r2, [r7, #4] uint8_t idx = 0U; 800824e: 2300 movs r3, #0 8008250: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) 8008252: 68fb ldr r3, [r7, #12] 8008254: 2b00 cmp r3, #0 8008256: d036 beq.n 80082c6 { return; } pdesc = desc; 8008258: 68fb ldr r3, [r7, #12] 800825a: 613b str r3, [r7, #16] *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; 800825c: 6938 ldr r0, [r7, #16] 800825e: f000 f836 bl 80082ce 8008262: 4603 mov r3, r0 8008264: 3301 adds r3, #1 8008266: b29b uxth r3, r3 8008268: 005b lsls r3, r3, #1 800826a: b29a uxth r2, r3 800826c: 687b ldr r3, [r7, #4] 800826e: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; 8008270: 7dfb ldrb r3, [r7, #23] 8008272: 68ba ldr r2, [r7, #8] 8008274: 4413 add r3, r2 8008276: 687a ldr r2, [r7, #4] 8008278: 7812 ldrb r2, [r2, #0] 800827a: 701a strb r2, [r3, #0] idx++; 800827c: 7dfb ldrb r3, [r7, #23] 800827e: 3301 adds r3, #1 8008280: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; 8008282: 7dfb ldrb r3, [r7, #23] 8008284: 68ba ldr r2, [r7, #8] 8008286: 4413 add r3, r2 8008288: 2203 movs r2, #3 800828a: 701a strb r2, [r3, #0] idx++; 800828c: 7dfb ldrb r3, [r7, #23] 800828e: 3301 adds r3, #1 8008290: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 8008292: e013 b.n 80082bc { unicode[idx] = *pdesc; 8008294: 7dfb ldrb r3, [r7, #23] 8008296: 68ba ldr r2, [r7, #8] 8008298: 4413 add r3, r2 800829a: 693a ldr r2, [r7, #16] 800829c: 7812 ldrb r2, [r2, #0] 800829e: 701a strb r2, [r3, #0] pdesc++; 80082a0: 693b ldr r3, [r7, #16] 80082a2: 3301 adds r3, #1 80082a4: 613b str r3, [r7, #16] idx++; 80082a6: 7dfb ldrb r3, [r7, #23] 80082a8: 3301 adds r3, #1 80082aa: 75fb strb r3, [r7, #23] unicode[idx] = 0U; 80082ac: 7dfb ldrb r3, [r7, #23] 80082ae: 68ba ldr r2, [r7, #8] 80082b0: 4413 add r3, r2 80082b2: 2200 movs r2, #0 80082b4: 701a strb r2, [r3, #0] idx++; 80082b6: 7dfb ldrb r3, [r7, #23] 80082b8: 3301 adds r3, #1 80082ba: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') 80082bc: 693b ldr r3, [r7, #16] 80082be: 781b ldrb r3, [r3, #0] 80082c0: 2b00 cmp r3, #0 80082c2: d1e7 bne.n 8008294 80082c4: e000 b.n 80082c8 return; 80082c6: bf00 nop } } 80082c8: 3718 adds r7, #24 80082ca: 46bd mov sp, r7 80082cc: bd80 pop {r7, pc} 080082ce : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { 80082ce: b480 push {r7} 80082d0: b085 sub sp, #20 80082d2: af00 add r7, sp, #0 80082d4: 6078 str r0, [r7, #4] uint8_t len = 0U; 80082d6: 2300 movs r3, #0 80082d8: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; 80082da: 687b ldr r3, [r7, #4] 80082dc: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 80082de: e005 b.n 80082ec { len++; 80082e0: 7bfb ldrb r3, [r7, #15] 80082e2: 3301 adds r3, #1 80082e4: 73fb strb r3, [r7, #15] pbuff++; 80082e6: 68bb ldr r3, [r7, #8] 80082e8: 3301 adds r3, #1 80082ea: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') 80082ec: 68bb ldr r3, [r7, #8] 80082ee: 781b ldrb r3, [r3, #0] 80082f0: 2b00 cmp r3, #0 80082f2: d1f5 bne.n 80082e0 } return len; 80082f4: 7bfb ldrb r3, [r7, #15] } 80082f6: 4618 mov r0, r3 80082f8: 3714 adds r7, #20 80082fa: 46bd mov sp, r7 80082fc: f85d 7b04 ldr.w r7, [sp], #4 8008300: 4770 bx lr 08008302 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008302: b580 push {r7, lr} 8008304: b084 sub sp, #16 8008306: af00 add r7, sp, #0 8008308: 60f8 str r0, [r7, #12] 800830a: 60b9 str r1, [r7, #8] 800830c: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; 800830e: 68fb ldr r3, [r7, #12] 8008310: 2202 movs r2, #2 8008312: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep_in[0].total_length = len; 8008316: 68fb ldr r3, [r7, #12] 8008318: 687a ldr r2, [r7, #4] 800831a: 619a str r2, [r3, #24] #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; 800831c: 68fb ldr r3, [r7, #12] 800831e: 687a ldr r2, [r7, #4] 8008320: 61da str r2, [r3, #28] #endif /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8008322: 687b ldr r3, [r7, #4] 8008324: 68ba ldr r2, [r7, #8] 8008326: 2100 movs r1, #0 8008328: 68f8 ldr r0, [r7, #12] 800832a: f000 fcfa bl 8008d22 return USBD_OK; 800832e: 2300 movs r3, #0 } 8008330: 4618 mov r0, r3 8008332: 3710 adds r7, #16 8008334: 46bd mov sp, r7 8008336: bd80 pop {r7, pc} 08008338 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008338: b580 push {r7, lr} 800833a: b084 sub sp, #16 800833c: af00 add r7, sp, #0 800833e: 60f8 str r0, [r7, #12] 8008340: 60b9 str r1, [r7, #8] 8008342: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); 8008344: 687b ldr r3, [r7, #4] 8008346: 68ba ldr r2, [r7, #8] 8008348: 2100 movs r1, #0 800834a: 68f8 ldr r0, [r7, #12] 800834c: f000 fce9 bl 8008d22 return USBD_OK; 8008350: 2300 movs r3, #0 } 8008352: 4618 mov r0, r3 8008354: 3710 adds r7, #16 8008356: 46bd mov sp, r7 8008358: bd80 pop {r7, pc} 0800835a : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 800835a: b580 push {r7, lr} 800835c: b084 sub sp, #16 800835e: af00 add r7, sp, #0 8008360: 60f8 str r0, [r7, #12] 8008362: 60b9 str r1, [r7, #8] 8008364: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; 8008366: 68fb ldr r3, [r7, #12] 8008368: 2203 movs r2, #3 800836a: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep_out[0].total_length = len; 800836e: 68fb ldr r3, [r7, #12] 8008370: 687a ldr r2, [r7, #4] 8008372: f8c3 2158 str.w r2, [r3, #344] ; 0x158 #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_out[0].rem_length = 0U; #else pdev->ep_out[0].rem_length = len; 8008376: 68fb ldr r3, [r7, #12] 8008378: 687a ldr r2, [r7, #4] 800837a: f8c3 215c str.w r2, [r3, #348] ; 0x15c #endif /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 800837e: 687b ldr r3, [r7, #4] 8008380: 68ba ldr r2, [r7, #8] 8008382: 2100 movs r1, #0 8008384: 68f8 ldr r0, [r7, #12] 8008386: f000 fced bl 8008d64 return USBD_OK; 800838a: 2300 movs r3, #0 } 800838c: 4618 mov r0, r3 800838e: 3710 adds r7, #16 8008390: 46bd mov sp, r7 8008392: bd80 pop {r7, pc} 08008394 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { 8008394: b580 push {r7, lr} 8008396: b084 sub sp, #16 8008398: af00 add r7, sp, #0 800839a: 60f8 str r0, [r7, #12] 800839c: 60b9 str r1, [r7, #8] 800839e: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); 80083a0: 687b ldr r3, [r7, #4] 80083a2: 68ba ldr r2, [r7, #8] 80083a4: 2100 movs r1, #0 80083a6: 68f8 ldr r0, [r7, #12] 80083a8: f000 fcdc bl 8008d64 return USBD_OK; 80083ac: 2300 movs r3, #0 } 80083ae: 4618 mov r0, r3 80083b0: 3710 adds r7, #16 80083b2: 46bd mov sp, r7 80083b4: bd80 pop {r7, pc} 080083b6 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { 80083b6: b580 push {r7, lr} 80083b8: b082 sub sp, #8 80083ba: af00 add r7, sp, #0 80083bc: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; 80083be: 687b ldr r3, [r7, #4] 80083c0: 2204 movs r2, #4 80083c2: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); 80083c6: 2300 movs r3, #0 80083c8: 2200 movs r2, #0 80083ca: 2100 movs r1, #0 80083cc: 6878 ldr r0, [r7, #4] 80083ce: f000 fca8 bl 8008d22 return USBD_OK; 80083d2: 2300 movs r3, #0 } 80083d4: 4618 mov r0, r3 80083d6: 3708 adds r7, #8 80083d8: 46bd mov sp, r7 80083da: bd80 pop {r7, pc} 080083dc : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { 80083dc: b580 push {r7, lr} 80083de: b082 sub sp, #8 80083e0: af00 add r7, sp, #0 80083e2: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; 80083e4: 687b ldr r3, [r7, #4] 80083e6: 2205 movs r2, #5 80083e8: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); 80083ec: 2300 movs r3, #0 80083ee: 2200 movs r2, #0 80083f0: 2100 movs r1, #0 80083f2: 6878 ldr r0, [r7, #4] 80083f4: f000 fcb6 bl 8008d64 return USBD_OK; 80083f8: 2300 movs r3, #0 } 80083fa: 4618 mov r0, r3 80083fc: 3708 adds r7, #8 80083fe: 46bd mov sp, r7 8008400: bd80 pop {r7, pc} ... 08008404 : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { 8008404: b580 push {r7, lr} 8008406: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) 8008408: 2200 movs r2, #0 800840a: 4912 ldr r1, [pc, #72] ; (8008454 ) 800840c: 4812 ldr r0, [pc, #72] ; (8008458 ) 800840e: f7fe fe65 bl 80070dc 8008412: 4603 mov r3, r0 8008414: 2b00 cmp r3, #0 8008416: d001 beq.n 800841c { Error_Handler(); 8008418: f7f8 fc22 bl 8000c60 } if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) 800841c: 490f ldr r1, [pc, #60] ; (800845c ) 800841e: 480e ldr r0, [pc, #56] ; (8008458 ) 8008420: f7fe fe8c bl 800713c 8008424: 4603 mov r3, r0 8008426: 2b00 cmp r3, #0 8008428: d001 beq.n 800842e { Error_Handler(); 800842a: f7f8 fc19 bl 8000c60 } if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) 800842e: 490c ldr r1, [pc, #48] ; (8008460 ) 8008430: 4809 ldr r0, [pc, #36] ; (8008458 ) 8008432: f7fe fddd bl 8006ff0 8008436: 4603 mov r3, r0 8008438: 2b00 cmp r3, #0 800843a: d001 beq.n 8008440 { Error_Handler(); 800843c: f7f8 fc10 bl 8000c60 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) 8008440: 4805 ldr r0, [pc, #20] ; (8008458 ) 8008442: f7fe fea2 bl 800718a 8008446: 4603 mov r3, r0 8008448: 2b00 cmp r3, #0 800844a: d001 beq.n 8008450 { Error_Handler(); 800844c: f7f8 fc08 bl 8000c60 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } 8008450: bf00 nop 8008452: bd80 pop {r7, pc} 8008454: 20000130 .word 0x20000130 8008458: 20000624 .word 0x20000624 800845c: 20000018 .word 0x20000018 8008460: 2000011c .word 0x2000011c 08008464 : /** * @brief Initializes the CDC media low layer over the FS USB IP * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Init_FS(void) { 8008464: b580 push {r7, lr} 8008466: af00 add r7, sp, #0 /* USER CODE BEGIN 3 */ /* Set Application Buffers */ USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); 8008468: 2200 movs r2, #0 800846a: 4905 ldr r1, [pc, #20] ; (8008480 ) 800846c: 4805 ldr r0, [pc, #20] ; (8008484 ) 800846e: f7fe fdd4 bl 800701a USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); 8008472: 4905 ldr r1, [pc, #20] ; (8008488 ) 8008474: 4803 ldr r0, [pc, #12] ; (8008484 ) 8008476: f7fe fdee bl 8007056 return (USBD_OK); 800847a: 2300 movs r3, #0 /* USER CODE END 3 */ } 800847c: 4618 mov r0, r3 800847e: bd80 pop {r7, pc} 8008480: 200010f4 .word 0x200010f4 8008484: 20000624 .word 0x20000624 8008488: 200008f4 .word 0x200008f4 0800848c : /** * @brief DeInitializes the CDC media low layer * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_DeInit_FS(void) { 800848c: b480 push {r7} 800848e: af00 add r7, sp, #0 /* USER CODE BEGIN 4 */ return (USBD_OK); 8008490: 2300 movs r3, #0 /* USER CODE END 4 */ } 8008492: 4618 mov r0, r3 8008494: 46bd mov sp, r7 8008496: f85d 7b04 ldr.w r7, [sp], #4 800849a: 4770 bx lr 0800849c : * @param pbuf: Buffer containing command data (request parameters) * @param length: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) { 800849c: b480 push {r7} 800849e: b083 sub sp, #12 80084a0: af00 add r7, sp, #0 80084a2: 4603 mov r3, r0 80084a4: 6039 str r1, [r7, #0] 80084a6: 71fb strb r3, [r7, #7] 80084a8: 4613 mov r3, r2 80084aa: 80bb strh r3, [r7, #4] /* USER CODE BEGIN 5 */ switch(cmd) 80084ac: 79fb ldrb r3, [r7, #7] 80084ae: 2b23 cmp r3, #35 ; 0x23 80084b0: d84a bhi.n 8008548 80084b2: a201 add r2, pc, #4 ; (adr r2, 80084b8 ) 80084b4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80084b8: 08008549 .word 0x08008549 80084bc: 08008549 .word 0x08008549 80084c0: 08008549 .word 0x08008549 80084c4: 08008549 .word 0x08008549 80084c8: 08008549 .word 0x08008549 80084cc: 08008549 .word 0x08008549 80084d0: 08008549 .word 0x08008549 80084d4: 08008549 .word 0x08008549 80084d8: 08008549 .word 0x08008549 80084dc: 08008549 .word 0x08008549 80084e0: 08008549 .word 0x08008549 80084e4: 08008549 .word 0x08008549 80084e8: 08008549 .word 0x08008549 80084ec: 08008549 .word 0x08008549 80084f0: 08008549 .word 0x08008549 80084f4: 08008549 .word 0x08008549 80084f8: 08008549 .word 0x08008549 80084fc: 08008549 .word 0x08008549 8008500: 08008549 .word 0x08008549 8008504: 08008549 .word 0x08008549 8008508: 08008549 .word 0x08008549 800850c: 08008549 .word 0x08008549 8008510: 08008549 .word 0x08008549 8008514: 08008549 .word 0x08008549 8008518: 08008549 .word 0x08008549 800851c: 08008549 .word 0x08008549 8008520: 08008549 .word 0x08008549 8008524: 08008549 .word 0x08008549 8008528: 08008549 .word 0x08008549 800852c: 08008549 .word 0x08008549 8008530: 08008549 .word 0x08008549 8008534: 08008549 .word 0x08008549 8008538: 08008549 .word 0x08008549 800853c: 08008549 .word 0x08008549 8008540: 08008549 .word 0x08008549 8008544: 08008549 .word 0x08008549 case CDC_SEND_BREAK: break; default: break; 8008548: bf00 nop } return (USBD_OK); 800854a: 2300 movs r3, #0 /* USER CODE END 5 */ } 800854c: 4618 mov r0, r3 800854e: 370c adds r7, #12 8008550: 46bd mov sp, r7 8008552: f85d 7b04 ldr.w r7, [sp], #4 8008556: 4770 bx lr 08008558 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { 8008558: b580 push {r7, lr} 800855a: b082 sub sp, #8 800855c: af00 add r7, sp, #0 800855e: 6078 str r0, [r7, #4] 8008560: 6039 str r1, [r7, #0] /* USER CODE BEGIN 6 */ USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); 8008562: 6879 ldr r1, [r7, #4] 8008564: 4805 ldr r0, [pc, #20] ; (800857c ) 8008566: f7fe fd76 bl 8007056 USBD_CDC_ReceivePacket(&hUsbDeviceFS); 800856a: 4804 ldr r0, [pc, #16] ; (800857c ) 800856c: f7fe fd8c bl 8007088 return (USBD_OK); 8008570: 2300 movs r3, #0 /* USER CODE END 6 */ } 8008572: 4618 mov r0, r3 8008574: 3708 adds r7, #8 8008576: 46bd mov sp, r7 8008578: bd80 pop {r7, pc} 800857a: bf00 nop 800857c: 20000624 .word 0x20000624 08008580 : * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum) { 8008580: b480 push {r7} 8008582: b087 sub sp, #28 8008584: af00 add r7, sp, #0 8008586: 60f8 str r0, [r7, #12] 8008588: 60b9 str r1, [r7, #8] 800858a: 4613 mov r3, r2 800858c: 71fb strb r3, [r7, #7] uint8_t result = USBD_OK; 800858e: 2300 movs r3, #0 8008590: 75fb strb r3, [r7, #23] /* USER CODE BEGIN 13 */ UNUSED(Buf); UNUSED(Len); UNUSED(epnum); /* USER CODE END 13 */ return result; 8008592: f997 3017 ldrsb.w r3, [r7, #23] } 8008596: 4618 mov r0, r3 8008598: 371c adds r7, #28 800859a: 46bd mov sp, r7 800859c: f85d 7b04 ldr.w r7, [sp], #4 80085a0: 4770 bx lr ... 080085a4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80085a4: b480 push {r7} 80085a6: b083 sub sp, #12 80085a8: af00 add r7, sp, #0 80085aa: 4603 mov r3, r0 80085ac: 6039 str r1, [r7, #0] 80085ae: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); 80085b0: 683b ldr r3, [r7, #0] 80085b2: 2212 movs r2, #18 80085b4: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; 80085b6: 4b03 ldr r3, [pc, #12] ; (80085c4 ) } 80085b8: 4618 mov r0, r3 80085ba: 370c adds r7, #12 80085bc: 46bd mov sp, r7 80085be: f85d 7b04 ldr.w r7, [sp], #4 80085c2: 4770 bx lr 80085c4: 20000150 .word 0x20000150 080085c8 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80085c8: b480 push {r7} 80085ca: b083 sub sp, #12 80085cc: af00 add r7, sp, #0 80085ce: 4603 mov r3, r0 80085d0: 6039 str r1, [r7, #0] 80085d2: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); 80085d4: 683b ldr r3, [r7, #0] 80085d6: 2204 movs r2, #4 80085d8: 801a strh r2, [r3, #0] return USBD_LangIDDesc; 80085da: 4b03 ldr r3, [pc, #12] ; (80085e8 ) } 80085dc: 4618 mov r0, r3 80085de: 370c adds r7, #12 80085e0: 46bd mov sp, r7 80085e2: f85d 7b04 ldr.w r7, [sp], #4 80085e6: 4770 bx lr 80085e8: 20000170 .word 0x20000170 080085ec : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80085ec: b580 push {r7, lr} 80085ee: b082 sub sp, #8 80085f0: af00 add r7, sp, #0 80085f2: 4603 mov r3, r0 80085f4: 6039 str r1, [r7, #0] 80085f6: 71fb strb r3, [r7, #7] if(speed == 0) 80085f8: 79fb ldrb r3, [r7, #7] 80085fa: 2b00 cmp r3, #0 80085fc: d105 bne.n 800860a { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 80085fe: 683a ldr r2, [r7, #0] 8008600: 4907 ldr r1, [pc, #28] ; (8008620 ) 8008602: 4808 ldr r0, [pc, #32] ; (8008624 ) 8008604: f7ff fe1d bl 8008242 8008608: e004 b.n 8008614 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); 800860a: 683a ldr r2, [r7, #0] 800860c: 4904 ldr r1, [pc, #16] ; (8008620 ) 800860e: 4805 ldr r0, [pc, #20] ; (8008624 ) 8008610: f7ff fe17 bl 8008242 } return USBD_StrDesc; 8008614: 4b02 ldr r3, [pc, #8] ; (8008620 ) } 8008616: 4618 mov r0, r3 8008618: 3708 adds r7, #8 800861a: 46bd mov sp, r7 800861c: bd80 pop {r7, pc} 800861e: bf00 nop 8008620: 200018f4 .word 0x200018f4 8008624: 08008f60 .word 0x08008f60 08008628 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8008628: b580 push {r7, lr} 800862a: b082 sub sp, #8 800862c: af00 add r7, sp, #0 800862e: 4603 mov r3, r0 8008630: 6039 str r1, [r7, #0] 8008632: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); 8008634: 683a ldr r2, [r7, #0] 8008636: 4904 ldr r1, [pc, #16] ; (8008648 ) 8008638: 4804 ldr r0, [pc, #16] ; (800864c ) 800863a: f7ff fe02 bl 8008242 return USBD_StrDesc; 800863e: 4b02 ldr r3, [pc, #8] ; (8008648 ) } 8008640: 4618 mov r0, r3 8008642: 3708 adds r7, #8 8008644: 46bd mov sp, r7 8008646: bd80 pop {r7, pc} 8008648: 200018f4 .word 0x200018f4 800864c: 08008f78 .word 0x08008f78 08008650 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8008650: b580 push {r7, lr} 8008652: b082 sub sp, #8 8008654: af00 add r7, sp, #0 8008656: 4603 mov r3, r0 8008658: 6039 str r1, [r7, #0] 800865a: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; 800865c: 683b ldr r3, [r7, #0] 800865e: 221a movs r2, #26 8008660: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); 8008662: f000 f855 bl 8008710 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; 8008666: 4b02 ldr r3, [pc, #8] ; (8008670 ) } 8008668: 4618 mov r0, r3 800866a: 3708 adds r7, #8 800866c: 46bd mov sp, r7 800866e: bd80 pop {r7, pc} 8008670: 20000174 .word 0x20000174 08008674 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 8008674: b580 push {r7, lr} 8008676: b082 sub sp, #8 8008678: af00 add r7, sp, #0 800867a: 4603 mov r3, r0 800867c: 6039 str r1, [r7, #0] 800867e: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) 8008680: 79fb ldrb r3, [r7, #7] 8008682: 2b00 cmp r3, #0 8008684: d105 bne.n 8008692 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 8008686: 683a ldr r2, [r7, #0] 8008688: 4907 ldr r1, [pc, #28] ; (80086a8 ) 800868a: 4808 ldr r0, [pc, #32] ; (80086ac ) 800868c: f7ff fdd9 bl 8008242 8008690: e004 b.n 800869c } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); 8008692: 683a ldr r2, [r7, #0] 8008694: 4904 ldr r1, [pc, #16] ; (80086a8 ) 8008696: 4805 ldr r0, [pc, #20] ; (80086ac ) 8008698: f7ff fdd3 bl 8008242 } return USBD_StrDesc; 800869c: 4b02 ldr r3, [pc, #8] ; (80086a8 ) } 800869e: 4618 mov r0, r3 80086a0: 3708 adds r7, #8 80086a2: 46bd mov sp, r7 80086a4: bd80 pop {r7, pc} 80086a6: bf00 nop 80086a8: 200018f4 .word 0x200018f4 80086ac: 08008f8c .word 0x08008f8c 080086b0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80086b0: b580 push {r7, lr} 80086b2: b082 sub sp, #8 80086b4: af00 add r7, sp, #0 80086b6: 4603 mov r3, r0 80086b8: 6039 str r1, [r7, #0] 80086ba: 71fb strb r3, [r7, #7] if(speed == 0) 80086bc: 79fb ldrb r3, [r7, #7] 80086be: 2b00 cmp r3, #0 80086c0: d105 bne.n 80086ce { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 80086c2: 683a ldr r2, [r7, #0] 80086c4: 4907 ldr r1, [pc, #28] ; (80086e4 ) 80086c6: 4808 ldr r0, [pc, #32] ; (80086e8 ) 80086c8: f7ff fdbb bl 8008242 80086cc: e004 b.n 80086d8 } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); 80086ce: 683a ldr r2, [r7, #0] 80086d0: 4904 ldr r1, [pc, #16] ; (80086e4 ) 80086d2: 4805 ldr r0, [pc, #20] ; (80086e8 ) 80086d4: f7ff fdb5 bl 8008242 } return USBD_StrDesc; 80086d8: 4b02 ldr r3, [pc, #8] ; (80086e4 ) } 80086da: 4618 mov r0, r3 80086dc: 3708 adds r7, #8 80086de: 46bd mov sp, r7 80086e0: bd80 pop {r7, pc} 80086e2: bf00 nop 80086e4: 200018f4 .word 0x200018f4 80086e8: 08008f98 .word 0x08008f98 080086ec : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { 80086ec: b480 push {r7} 80086ee: b083 sub sp, #12 80086f0: af00 add r7, sp, #0 80086f2: 4603 mov r3, r0 80086f4: 6039 str r1, [r7, #0] 80086f6: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); 80086f8: 683b ldr r3, [r7, #0] 80086fa: 220c movs r2, #12 80086fc: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; 80086fe: 4b03 ldr r3, [pc, #12] ; (800870c ) } 8008700: 4618 mov r0, r3 8008702: 370c adds r7, #12 8008704: 46bd mov sp, r7 8008706: f85d 7b04 ldr.w r7, [sp], #4 800870a: 4770 bx lr 800870c: 20000164 .word 0x20000164 08008710 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { 8008710: b580 push {r7, lr} 8008712: b084 sub sp, #16 8008714: af00 add r7, sp, #0 uint32_t deviceserial0, deviceserial1, deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; 8008716: 4b0f ldr r3, [pc, #60] ; (8008754 ) 8008718: 681b ldr r3, [r3, #0] 800871a: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; 800871c: 4b0e ldr r3, [pc, #56] ; (8008758 ) 800871e: 681b ldr r3, [r3, #0] 8008720: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; 8008722: 4b0e ldr r3, [pc, #56] ; (800875c ) 8008724: 681b ldr r3, [r3, #0] 8008726: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; 8008728: 68fa ldr r2, [r7, #12] 800872a: 687b ldr r3, [r7, #4] 800872c: 4413 add r3, r2 800872e: 60fb str r3, [r7, #12] if (deviceserial0 != 0) 8008730: 68fb ldr r3, [r7, #12] 8008732: 2b00 cmp r3, #0 8008734: d009 beq.n 800874a { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); 8008736: 2208 movs r2, #8 8008738: 4909 ldr r1, [pc, #36] ; (8008760 ) 800873a: 68f8 ldr r0, [r7, #12] 800873c: f000 f814 bl 8008768 IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); 8008740: 2204 movs r2, #4 8008742: 4908 ldr r1, [pc, #32] ; (8008764 ) 8008744: 68b8 ldr r0, [r7, #8] 8008746: f000 f80f bl 8008768 } } 800874a: bf00 nop 800874c: 3710 adds r7, #16 800874e: 46bd mov sp, r7 8008750: bd80 pop {r7, pc} 8008752: bf00 nop 8008754: 1fff7a10 .word 0x1fff7a10 8008758: 1fff7a14 .word 0x1fff7a14 800875c: 1fff7a18 .word 0x1fff7a18 8008760: 20000176 .word 0x20000176 8008764: 20000186 .word 0x20000186 08008768 : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { 8008768: b480 push {r7} 800876a: b087 sub sp, #28 800876c: af00 add r7, sp, #0 800876e: 60f8 str r0, [r7, #12] 8008770: 60b9 str r1, [r7, #8] 8008772: 4613 mov r3, r2 8008774: 71fb strb r3, [r7, #7] uint8_t idx = 0; 8008776: 2300 movs r3, #0 8008778: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) 800877a: 2300 movs r3, #0 800877c: 75fb strb r3, [r7, #23] 800877e: e027 b.n 80087d0 { if (((value >> 28)) < 0xA) 8008780: 68fb ldr r3, [r7, #12] 8008782: 0f1b lsrs r3, r3, #28 8008784: 2b09 cmp r3, #9 8008786: d80b bhi.n 80087a0 { pbuf[2 * idx] = (value >> 28) + '0'; 8008788: 68fb ldr r3, [r7, #12] 800878a: 0f1b lsrs r3, r3, #28 800878c: b2da uxtb r2, r3 800878e: 7dfb ldrb r3, [r7, #23] 8008790: 005b lsls r3, r3, #1 8008792: 4619 mov r1, r3 8008794: 68bb ldr r3, [r7, #8] 8008796: 440b add r3, r1 8008798: 3230 adds r2, #48 ; 0x30 800879a: b2d2 uxtb r2, r2 800879c: 701a strb r2, [r3, #0] 800879e: e00a b.n 80087b6 } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; 80087a0: 68fb ldr r3, [r7, #12] 80087a2: 0f1b lsrs r3, r3, #28 80087a4: b2da uxtb r2, r3 80087a6: 7dfb ldrb r3, [r7, #23] 80087a8: 005b lsls r3, r3, #1 80087aa: 4619 mov r1, r3 80087ac: 68bb ldr r3, [r7, #8] 80087ae: 440b add r3, r1 80087b0: 3237 adds r2, #55 ; 0x37 80087b2: b2d2 uxtb r2, r2 80087b4: 701a strb r2, [r3, #0] } value = value << 4; 80087b6: 68fb ldr r3, [r7, #12] 80087b8: 011b lsls r3, r3, #4 80087ba: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; 80087bc: 7dfb ldrb r3, [r7, #23] 80087be: 005b lsls r3, r3, #1 80087c0: 3301 adds r3, #1 80087c2: 68ba ldr r2, [r7, #8] 80087c4: 4413 add r3, r2 80087c6: 2200 movs r2, #0 80087c8: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) 80087ca: 7dfb ldrb r3, [r7, #23] 80087cc: 3301 adds r3, #1 80087ce: 75fb strb r3, [r7, #23] 80087d0: 7dfa ldrb r2, [r7, #23] 80087d2: 79fb ldrb r3, [r7, #7] 80087d4: 429a cmp r2, r3 80087d6: d3d3 bcc.n 8008780 } } 80087d8: bf00 nop 80087da: bf00 nop 80087dc: 371c adds r7, #28 80087de: 46bd mov sp, r7 80087e0: f85d 7b04 ldr.w r7, [sp], #4 80087e4: 4770 bx lr ... 080087e8 : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { 80087e8: b580 push {r7, lr} 80087ea: b0a0 sub sp, #128 ; 0x80 80087ec: af00 add r7, sp, #0 80087ee: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80087f0: f107 036c add.w r3, r7, #108 ; 0x6c 80087f4: 2200 movs r2, #0 80087f6: 601a str r2, [r3, #0] 80087f8: 605a str r2, [r3, #4] 80087fa: 609a str r2, [r3, #8] 80087fc: 60da str r2, [r3, #12] 80087fe: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8008800: f107 0310 add.w r3, r7, #16 8008804: 225c movs r2, #92 ; 0x5c 8008806: 2100 movs r1, #0 8008808: 4618 mov r0, r3 800880a: f000 fb95 bl 8008f38 if(pcdHandle->Instance==USB_OTG_FS) 800880e: 687b ldr r3, [r7, #4] 8008810: 681b ldr r3, [r3, #0] 8008812: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8008816: d154 bne.n 80088c2 /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; 8008818: f44f 7380 mov.w r3, #256 ; 0x100 800881c: 613b str r3, [r7, #16] PeriphClkInitStruct.PLLSAI.PLLSAIM = 8; 800881e: 2308 movs r3, #8 8008820: 62bb str r3, [r7, #40] ; 0x28 PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; 8008822: 23c0 movs r3, #192 ; 0xc0 8008824: 62fb str r3, [r7, #44] ; 0x2c PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; 8008826: 2302 movs r3, #2 8008828: 637b str r3, [r7, #52] ; 0x34 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4; 800882a: 2304 movs r3, #4 800882c: 633b str r3, [r7, #48] ; 0x30 PeriphClkInitStruct.PLLSAIDivQ = 1; 800882e: 2301 movs r3, #1 8008830: 63fb str r3, [r7, #60] ; 0x3c PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP; 8008832: f04f 6300 mov.w r3, #134217728 ; 0x8000000 8008836: 667b str r3, [r7, #100] ; 0x64 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8008838: f107 0310 add.w r3, r7, #16 800883c: 4618 mov r0, r3 800883e: f7fa fde7 bl 8003410 8008842: 4603 mov r3, r0 8008844: 2b00 cmp r3, #0 8008846: d001 beq.n 800884c { Error_Handler(); 8008848: f7f8 fa0a bl 8000c60 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800884c: 2300 movs r3, #0 800884e: 60fb str r3, [r7, #12] 8008850: 4b1e ldr r3, [pc, #120] ; (80088cc ) 8008852: 6b1b ldr r3, [r3, #48] ; 0x30 8008854: 4a1d ldr r2, [pc, #116] ; (80088cc ) 8008856: f043 0301 orr.w r3, r3, #1 800885a: 6313 str r3, [r2, #48] ; 0x30 800885c: 4b1b ldr r3, [pc, #108] ; (80088cc ) 800885e: 6b1b ldr r3, [r3, #48] ; 0x30 8008860: f003 0301 and.w r3, r3, #1 8008864: 60fb str r3, [r7, #12] 8008866: 68fb ldr r3, [r7, #12] /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; 8008868: f44f 53c0 mov.w r3, #6144 ; 0x1800 800886c: 66fb str r3, [r7, #108] ; 0x6c GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800886e: 2302 movs r3, #2 8008870: 673b str r3, [r7, #112] ; 0x70 GPIO_InitStruct.Pull = GPIO_NOPULL; 8008872: 2300 movs r3, #0 8008874: 677b str r3, [r7, #116] ; 0x74 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8008876: 2303 movs r3, #3 8008878: 67bb str r3, [r7, #120] ; 0x78 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; 800887a: 230a movs r3, #10 800887c: 67fb str r3, [r7, #124] ; 0x7c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800887e: f107 036c add.w r3, r7, #108 ; 0x6c 8008882: 4619 mov r1, r3 8008884: 4812 ldr r0, [pc, #72] ; (80088d0 ) 8008886: f7f9 f92d bl 8001ae4 /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); 800888a: 4b10 ldr r3, [pc, #64] ; (80088cc ) 800888c: 6b5b ldr r3, [r3, #52] ; 0x34 800888e: 4a0f ldr r2, [pc, #60] ; (80088cc ) 8008890: f043 0380 orr.w r3, r3, #128 ; 0x80 8008894: 6353 str r3, [r2, #52] ; 0x34 8008896: 2300 movs r3, #0 8008898: 60bb str r3, [r7, #8] 800889a: 4b0c ldr r3, [pc, #48] ; (80088cc ) 800889c: 6c5b ldr r3, [r3, #68] ; 0x44 800889e: 4a0b ldr r2, [pc, #44] ; (80088cc ) 80088a0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80088a4: 6453 str r3, [r2, #68] ; 0x44 80088a6: 4b09 ldr r3, [pc, #36] ; (80088cc ) 80088a8: 6c5b ldr r3, [r3, #68] ; 0x44 80088aa: f403 4380 and.w r3, r3, #16384 ; 0x4000 80088ae: 60bb str r3, [r7, #8] 80088b0: 68bb ldr r3, [r7, #8] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); 80088b2: 2200 movs r2, #0 80088b4: 2100 movs r1, #0 80088b6: 2043 movs r0, #67 ; 0x43 80088b8: f7f9 f86d bl 8001996 HAL_NVIC_EnableIRQ(OTG_FS_IRQn); 80088bc: 2043 movs r0, #67 ; 0x43 80088be: f7f9 f886 bl 80019ce /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ } } 80088c2: bf00 nop 80088c4: 3780 adds r7, #128 ; 0x80 80088c6: 46bd mov sp, r7 80088c8: bd80 pop {r7, pc} 80088ca: bf00 nop 80088cc: 40023800 .word 0x40023800 80088d0: 40020000 .word 0x40020000 080088d4 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80088d4: b580 push {r7, lr} 80088d6: b082 sub sp, #8 80088d8: af00 add r7, sp, #0 80088da: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); 80088dc: 687b ldr r3, [r7, #4] 80088de: f8d3 2404 ldr.w r2, [r3, #1028] ; 0x404 80088e2: 687b ldr r3, [r7, #4] 80088e4: f503 7371 add.w r3, r3, #964 ; 0x3c4 80088e8: 4619 mov r1, r3 80088ea: 4610 mov r0, r2 80088ec: f7fe fc98 bl 8007220 } 80088f0: bf00 nop 80088f2: 3708 adds r7, #8 80088f4: 46bd mov sp, r7 80088f6: bd80 pop {r7, pc} 080088f8 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80088f8: b580 push {r7, lr} 80088fa: b082 sub sp, #8 80088fc: af00 add r7, sp, #0 80088fe: 6078 str r0, [r7, #4] 8008900: 460b mov r3, r1 8008902: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); 8008904: 687b ldr r3, [r7, #4] 8008906: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404 800890a: 78fa ldrb r2, [r7, #3] 800890c: 6879 ldr r1, [r7, #4] 800890e: 4613 mov r3, r2 8008910: 00db lsls r3, r3, #3 8008912: 1a9b subs r3, r3, r2 8008914: 009b lsls r3, r3, #2 8008916: 440b add r3, r1 8008918: f503 7302 add.w r3, r3, #520 ; 0x208 800891c: 681a ldr r2, [r3, #0] 800891e: 78fb ldrb r3, [r7, #3] 8008920: 4619 mov r1, r3 8008922: f7fe fcd2 bl 80072ca } 8008926: bf00 nop 8008928: 3708 adds r7, #8 800892a: 46bd mov sp, r7 800892c: bd80 pop {r7, pc} 0800892e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800892e: b580 push {r7, lr} 8008930: b082 sub sp, #8 8008932: af00 add r7, sp, #0 8008934: 6078 str r0, [r7, #4] 8008936: 460b mov r3, r1 8008938: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); 800893a: 687b ldr r3, [r7, #4] 800893c: f8d3 0404 ldr.w r0, [r3, #1028] ; 0x404 8008940: 78fa ldrb r2, [r7, #3] 8008942: 6879 ldr r1, [r7, #4] 8008944: 4613 mov r3, r2 8008946: 00db lsls r3, r3, #3 8008948: 1a9b subs r3, r3, r2 800894a: 009b lsls r3, r3, #2 800894c: 440b add r3, r1 800894e: 3348 adds r3, #72 ; 0x48 8008950: 681a ldr r2, [r3, #0] 8008952: 78fb ldrb r3, [r7, #3] 8008954: 4619 mov r1, r3 8008956: f7fe fd1b bl 8007390 } 800895a: bf00 nop 800895c: 3708 adds r7, #8 800895e: 46bd mov sp, r7 8008960: bd80 pop {r7, pc} 08008962 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8008962: b580 push {r7, lr} 8008964: b082 sub sp, #8 8008966: af00 add r7, sp, #0 8008968: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); 800896a: 687b ldr r3, [r7, #4] 800896c: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008970: 4618 mov r0, r3 8008972: f7fe fe2f bl 80075d4 } 8008976: bf00 nop 8008978: 3708 adds r7, #8 800897a: 46bd mov sp, r7 800897c: bd80 pop {r7, pc} 0800897e : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 800897e: b580 push {r7, lr} 8008980: b084 sub sp, #16 8008982: af00 add r7, sp, #0 8008984: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; 8008986: 2301 movs r3, #1 8008988: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed == PCD_SPEED_HIGH) 800898a: 687b ldr r3, [r7, #4] 800898c: 68db ldr r3, [r3, #12] 800898e: 2b00 cmp r3, #0 8008990: d102 bne.n 8008998 { speed = USBD_SPEED_HIGH; 8008992: 2300 movs r3, #0 8008994: 73fb strb r3, [r7, #15] 8008996: e008 b.n 80089aa } else if ( hpcd->Init.speed == PCD_SPEED_FULL) 8008998: 687b ldr r3, [r7, #4] 800899a: 68db ldr r3, [r3, #12] 800899c: 2b02 cmp r3, #2 800899e: d102 bne.n 80089a6 { speed = USBD_SPEED_FULL; 80089a0: 2301 movs r3, #1 80089a2: 73fb strb r3, [r7, #15] 80089a4: e001 b.n 80089aa } else { Error_Handler(); 80089a6: f7f8 f95b bl 8000c60 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); 80089aa: 687b ldr r3, [r7, #4] 80089ac: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 80089b0: 7bfa ldrb r2, [r7, #15] 80089b2: 4611 mov r1, r2 80089b4: 4618 mov r0, r3 80089b6: f7fe fdcf bl 8007558 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); 80089ba: 687b ldr r3, [r7, #4] 80089bc: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 80089c0: 4618 mov r0, r3 80089c2: f7fe fd7b bl 80074bc } 80089c6: bf00 nop 80089c8: 3710 adds r7, #16 80089ca: 46bd mov sp, r7 80089cc: bd80 pop {r7, pc} ... 080089d0 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 80089d0: b580 push {r7, lr} 80089d2: b082 sub sp, #8 80089d4: af00 add r7, sp, #0 80089d6: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); 80089d8: 687b ldr r3, [r7, #4] 80089da: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 80089de: 4618 mov r0, r3 80089e0: f7fe fdca bl 8007578 __HAL_PCD_GATE_PHYCLOCK(hpcd); 80089e4: 687b ldr r3, [r7, #4] 80089e6: 681b ldr r3, [r3, #0] 80089e8: f503 6360 add.w r3, r3, #3584 ; 0xe00 80089ec: 681b ldr r3, [r3, #0] 80089ee: 687a ldr r2, [r7, #4] 80089f0: 6812 ldr r2, [r2, #0] 80089f2: f502 6260 add.w r2, r2, #3584 ; 0xe00 80089f6: f043 0301 orr.w r3, r3, #1 80089fa: 6013 str r3, [r2, #0] /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) 80089fc: 687b ldr r3, [r7, #4] 80089fe: 6a1b ldr r3, [r3, #32] 8008a00: 2b00 cmp r3, #0 8008a02: d005 beq.n 8008a10 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8008a04: 4b04 ldr r3, [pc, #16] ; (8008a18 ) 8008a06: 691b ldr r3, [r3, #16] 8008a08: 4a03 ldr r2, [pc, #12] ; (8008a18 ) 8008a0a: f043 0306 orr.w r3, r3, #6 8008a0e: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } 8008a10: bf00 nop 8008a12: 3708 adds r7, #8 8008a14: 46bd mov sp, r7 8008a16: bd80 pop {r7, pc} 8008a18: e000ed00 .word 0xe000ed00 08008a1c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8008a1c: b580 push {r7, lr} 8008a1e: b082 sub sp, #8 8008a20: af00 add r7, sp, #0 8008a22: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); 8008a24: 687b ldr r3, [r7, #4] 8008a26: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008a2a: 4618 mov r0, r3 8008a2c: f7fe fdba bl 80075a4 } 8008a30: bf00 nop 8008a32: 3708 adds r7, #8 8008a34: 46bd mov sp, r7 8008a36: bd80 pop {r7, pc} 08008a38 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8008a38: b580 push {r7, lr} 8008a3a: b082 sub sp, #8 8008a3c: af00 add r7, sp, #0 8008a3e: 6078 str r0, [r7, #4] 8008a40: 460b mov r3, r1 8008a42: 70fb strb r3, [r7, #3] USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 8008a44: 687b ldr r3, [r7, #4] 8008a46: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008a4a: 78fa ldrb r2, [r7, #3] 8008a4c: 4611 mov r1, r2 8008a4e: 4618 mov r0, r3 8008a50: f7fe fe08 bl 8007664 } 8008a54: bf00 nop 8008a56: 3708 adds r7, #8 8008a58: 46bd mov sp, r7 8008a5a: bd80 pop {r7, pc} 08008a5c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8008a5c: b580 push {r7, lr} 8008a5e: b082 sub sp, #8 8008a60: af00 add r7, sp, #0 8008a62: 6078 str r0, [r7, #4] 8008a64: 460b mov r3, r1 8008a66: 70fb strb r3, [r7, #3] USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); 8008a68: 687b ldr r3, [r7, #4] 8008a6a: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008a6e: 78fa ldrb r2, [r7, #3] 8008a70: 4611 mov r1, r2 8008a72: 4618 mov r0, r3 8008a74: f7fe fdd0 bl 8007618 } 8008a78: bf00 nop 8008a7a: 3708 adds r7, #8 8008a7c: 46bd mov sp, r7 8008a7e: bd80 pop {r7, pc} 08008a80 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8008a80: b580 push {r7, lr} 8008a82: b082 sub sp, #8 8008a84: af00 add r7, sp, #0 8008a86: 6078 str r0, [r7, #4] USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); 8008a88: 687b ldr r3, [r7, #4] 8008a8a: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008a8e: 4618 mov r0, r3 8008a90: f7fe fe0e bl 80076b0 } 8008a94: bf00 nop 8008a96: 3708 adds r7, #8 8008a98: 46bd mov sp, r7 8008a9a: bd80 pop {r7, pc} 08008a9c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { 8008a9c: b580 push {r7, lr} 8008a9e: b082 sub sp, #8 8008aa0: af00 add r7, sp, #0 8008aa2: 6078 str r0, [r7, #4] USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); 8008aa4: 687b ldr r3, [r7, #4] 8008aa6: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008aaa: 4618 mov r0, r3 8008aac: f7fe fe0b bl 80076c6 } 8008ab0: bf00 nop 8008ab2: 3708 adds r7, #8 8008ab4: 46bd mov sp, r7 8008ab6: bd80 pop {r7, pc} 08008ab8 : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { 8008ab8: b580 push {r7, lr} 8008aba: b082 sub sp, #8 8008abc: af00 add r7, sp, #0 8008abe: 6078 str r0, [r7, #4] /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { 8008ac0: 687b ldr r3, [r7, #4] 8008ac2: 781b ldrb r3, [r3, #0] 8008ac4: 2b00 cmp r3, #0 8008ac6: d13c bne.n 8008b42 /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; 8008ac8: 4a20 ldr r2, [pc, #128] ; (8008b4c ) 8008aca: 687b ldr r3, [r7, #4] 8008acc: f8c2 3404 str.w r3, [r2, #1028] ; 0x404 pdev->pData = &hpcd_USB_OTG_FS; 8008ad0: 687b ldr r3, [r7, #4] 8008ad2: 4a1e ldr r2, [pc, #120] ; (8008b4c ) 8008ad4: f8c3 22c4 str.w r2, [r3, #708] ; 0x2c4 hpcd_USB_OTG_FS.Instance = USB_OTG_FS; 8008ad8: 4b1c ldr r3, [pc, #112] ; (8008b4c ) 8008ada: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000 8008ade: 601a str r2, [r3, #0] hpcd_USB_OTG_FS.Init.dev_endpoints = 6; 8008ae0: 4b1a ldr r3, [pc, #104] ; (8008b4c ) 8008ae2: 2206 movs r2, #6 8008ae4: 605a str r2, [r3, #4] hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; 8008ae6: 4b19 ldr r3, [pc, #100] ; (8008b4c ) 8008ae8: 2202 movs r2, #2 8008aea: 60da str r2, [r3, #12] hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; 8008aec: 4b17 ldr r3, [pc, #92] ; (8008b4c ) 8008aee: 2200 movs r2, #0 8008af0: 611a str r2, [r3, #16] hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; 8008af2: 4b16 ldr r3, [pc, #88] ; (8008b4c ) 8008af4: 2202 movs r2, #2 8008af6: 619a str r2, [r3, #24] hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; 8008af8: 4b14 ldr r3, [pc, #80] ; (8008b4c ) 8008afa: 2200 movs r2, #0 8008afc: 61da str r2, [r3, #28] hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; 8008afe: 4b13 ldr r3, [pc, #76] ; (8008b4c ) 8008b00: 2200 movs r2, #0 8008b02: 621a str r2, [r3, #32] hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; 8008b04: 4b11 ldr r3, [pc, #68] ; (8008b4c ) 8008b06: 2200 movs r2, #0 8008b08: 625a str r2, [r3, #36] ; 0x24 hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; 8008b0a: 4b10 ldr r3, [pc, #64] ; (8008b4c ) 8008b0c: 2200 movs r2, #0 8008b0e: 62da str r2, [r3, #44] ; 0x2c hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; 8008b10: 4b0e ldr r3, [pc, #56] ; (8008b4c ) 8008b12: 2200 movs r2, #0 8008b14: 631a str r2, [r3, #48] ; 0x30 if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) 8008b16: 480d ldr r0, [pc, #52] ; (8008b4c ) 8008b18: f7f9 f991 bl 8001e3e 8008b1c: 4603 mov r3, r0 8008b1e: 2b00 cmp r3, #0 8008b20: d001 beq.n 8008b26 { Error_Handler( ); 8008b22: f7f8 f89d bl 8000c60 HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); 8008b26: 2180 movs r1, #128 ; 0x80 8008b28: 4808 ldr r0, [pc, #32] ; (8008b4c ) 8008b2a: f7fa fb22 bl 8003172 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); 8008b2e: 2240 movs r2, #64 ; 0x40 8008b30: 2100 movs r1, #0 8008b32: 4806 ldr r0, [pc, #24] ; (8008b4c ) 8008b34: f7fa fad6 bl 80030e4 HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); 8008b38: 2280 movs r2, #128 ; 0x80 8008b3a: 2101 movs r1, #1 8008b3c: 4803 ldr r0, [pc, #12] ; (8008b4c ) 8008b3e: f7fa fad1 bl 80030e4 } return USBD_OK; 8008b42: 2300 movs r3, #0 } 8008b44: 4618 mov r0, r3 8008b46: 3708 adds r7, #8 8008b48: 46bd mov sp, r7 8008b4a: bd80 pop {r7, pc} 8008b4c: 20001af4 .word 0x20001af4 08008b50 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { 8008b50: b580 push {r7, lr} 8008b52: b084 sub sp, #16 8008b54: af00 add r7, sp, #0 8008b56: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 8008b58: 2300 movs r3, #0 8008b5a: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8008b5c: 2300 movs r3, #0 8008b5e: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_Start(pdev->pData); 8008b60: 687b ldr r3, [r7, #4] 8008b62: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8008b66: 4618 mov r0, r3 8008b68: f7f9 fa8d bl 8002086 8008b6c: 4603 mov r3, r0 8008b6e: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8008b70: 7bfb ldrb r3, [r7, #15] 8008b72: 4618 mov r0, r3 8008b74: f000 f990 bl 8008e98 8008b78: 4603 mov r3, r0 8008b7a: 73bb strb r3, [r7, #14] return usb_status; 8008b7c: 7bbb ldrb r3, [r7, #14] } 8008b7e: 4618 mov r0, r3 8008b80: 3710 adds r7, #16 8008b82: 46bd mov sp, r7 8008b84: bd80 pop {r7, pc} 08008b86 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { 8008b86: b580 push {r7, lr} 8008b88: b084 sub sp, #16 8008b8a: af00 add r7, sp, #0 8008b8c: 6078 str r0, [r7, #4] 8008b8e: 4608 mov r0, r1 8008b90: 4611 mov r1, r2 8008b92: 461a mov r2, r3 8008b94: 4603 mov r3, r0 8008b96: 70fb strb r3, [r7, #3] 8008b98: 460b mov r3, r1 8008b9a: 70bb strb r3, [r7, #2] 8008b9c: 4613 mov r3, r2 8008b9e: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; 8008ba0: 2300 movs r3, #0 8008ba2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8008ba4: 2300 movs r3, #0 8008ba6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); 8008ba8: 687b ldr r3, [r7, #4] 8008baa: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 8008bae: 78bb ldrb r3, [r7, #2] 8008bb0: 883a ldrh r2, [r7, #0] 8008bb2: 78f9 ldrb r1, [r7, #3] 8008bb4: f7f9 fe9e bl 80028f4 8008bb8: 4603 mov r3, r0 8008bba: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8008bbc: 7bfb ldrb r3, [r7, #15] 8008bbe: 4618 mov r0, r3 8008bc0: f000 f96a bl 8008e98 8008bc4: 4603 mov r3, r0 8008bc6: 73bb strb r3, [r7, #14] return usb_status; 8008bc8: 7bbb ldrb r3, [r7, #14] } 8008bca: 4618 mov r0, r3 8008bcc: 3710 adds r7, #16 8008bce: 46bd mov sp, r7 8008bd0: bd80 pop {r7, pc} 08008bd2 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8008bd2: b580 push {r7, lr} 8008bd4: b084 sub sp, #16 8008bd6: af00 add r7, sp, #0 8008bd8: 6078 str r0, [r7, #4] 8008bda: 460b mov r3, r1 8008bdc: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 8008bde: 2300 movs r3, #0 8008be0: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8008be2: 2300 movs r3, #0 8008be4: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); 8008be6: 687b ldr r3, [r7, #4] 8008be8: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8008bec: 78fa ldrb r2, [r7, #3] 8008bee: 4611 mov r1, r2 8008bf0: 4618 mov r0, r3 8008bf2: f7f9 fee7 bl 80029c4 8008bf6: 4603 mov r3, r0 8008bf8: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8008bfa: 7bfb ldrb r3, [r7, #15] 8008bfc: 4618 mov r0, r3 8008bfe: f000 f94b bl 8008e98 8008c02: 4603 mov r3, r0 8008c04: 73bb strb r3, [r7, #14] return usb_status; 8008c06: 7bbb ldrb r3, [r7, #14] } 8008c08: 4618 mov r0, r3 8008c0a: 3710 adds r7, #16 8008c0c: 46bd mov sp, r7 8008c0e: bd80 pop {r7, pc} 08008c10 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8008c10: b580 push {r7, lr} 8008c12: b084 sub sp, #16 8008c14: af00 add r7, sp, #0 8008c16: 6078 str r0, [r7, #4] 8008c18: 460b mov r3, r1 8008c1a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 8008c1c: 2300 movs r3, #0 8008c1e: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8008c20: 2300 movs r3, #0 8008c22: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); 8008c24: 687b ldr r3, [r7, #4] 8008c26: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8008c2a: 78fa ldrb r2, [r7, #3] 8008c2c: 4611 mov r1, r2 8008c2e: 4618 mov r0, r3 8008c30: f7f9 ffbf bl 8002bb2 8008c34: 4603 mov r3, r0 8008c36: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8008c38: 7bfb ldrb r3, [r7, #15] 8008c3a: 4618 mov r0, r3 8008c3c: f000 f92c bl 8008e98 8008c40: 4603 mov r3, r0 8008c42: 73bb strb r3, [r7, #14] return usb_status; 8008c44: 7bbb ldrb r3, [r7, #14] } 8008c46: 4618 mov r0, r3 8008c48: 3710 adds r7, #16 8008c4a: 46bd mov sp, r7 8008c4c: bd80 pop {r7, pc} 08008c4e : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8008c4e: b580 push {r7, lr} 8008c50: b084 sub sp, #16 8008c52: af00 add r7, sp, #0 8008c54: 6078 str r0, [r7, #4] 8008c56: 460b mov r3, r1 8008c58: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 8008c5a: 2300 movs r3, #0 8008c5c: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8008c5e: 2300 movs r3, #0 8008c60: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); 8008c62: 687b ldr r3, [r7, #4] 8008c64: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8008c68: 78fa ldrb r2, [r7, #3] 8008c6a: 4611 mov r1, r2 8008c6c: 4618 mov r0, r3 8008c6e: f7fa f804 bl 8002c7a 8008c72: 4603 mov r3, r0 8008c74: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8008c76: 7bfb ldrb r3, [r7, #15] 8008c78: 4618 mov r0, r3 8008c7a: f000 f90d bl 8008e98 8008c7e: 4603 mov r3, r0 8008c80: 73bb strb r3, [r7, #14] return usb_status; 8008c82: 7bbb ldrb r3, [r7, #14] } 8008c84: 4618 mov r0, r3 8008c86: 3710 adds r7, #16 8008c88: 46bd mov sp, r7 8008c8a: bd80 pop {r7, pc} 08008c8c : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8008c8c: b480 push {r7} 8008c8e: b085 sub sp, #20 8008c90: af00 add r7, sp, #0 8008c92: 6078 str r0, [r7, #4] 8008c94: 460b mov r3, r1 8008c96: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; 8008c98: 687b ldr r3, [r7, #4] 8008c9a: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8008c9e: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) 8008ca0: f997 3003 ldrsb.w r3, [r7, #3] 8008ca4: 2b00 cmp r3, #0 8008ca6: da0b bge.n 8008cc0 { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 8008ca8: 78fb ldrb r3, [r7, #3] 8008caa: f003 027f and.w r2, r3, #127 ; 0x7f 8008cae: 68f9 ldr r1, [r7, #12] 8008cb0: 4613 mov r3, r2 8008cb2: 00db lsls r3, r3, #3 8008cb4: 1a9b subs r3, r3, r2 8008cb6: 009b lsls r3, r3, #2 8008cb8: 440b add r3, r1 8008cba: 333e adds r3, #62 ; 0x3e 8008cbc: 781b ldrb r3, [r3, #0] 8008cbe: e00b b.n 8008cd8 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 8008cc0: 78fb ldrb r3, [r7, #3] 8008cc2: f003 027f and.w r2, r3, #127 ; 0x7f 8008cc6: 68f9 ldr r1, [r7, #12] 8008cc8: 4613 mov r3, r2 8008cca: 00db lsls r3, r3, #3 8008ccc: 1a9b subs r3, r3, r2 8008cce: 009b lsls r3, r3, #2 8008cd0: 440b add r3, r1 8008cd2: f503 73ff add.w r3, r3, #510 ; 0x1fe 8008cd6: 781b ldrb r3, [r3, #0] } } 8008cd8: 4618 mov r0, r3 8008cda: 3714 adds r7, #20 8008cdc: 46bd mov sp, r7 8008cde: f85d 7b04 ldr.w r7, [sp], #4 8008ce2: 4770 bx lr 08008ce4 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { 8008ce4: b580 push {r7, lr} 8008ce6: b084 sub sp, #16 8008ce8: af00 add r7, sp, #0 8008cea: 6078 str r0, [r7, #4] 8008cec: 460b mov r3, r1 8008cee: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; 8008cf0: 2300 movs r3, #0 8008cf2: 73fb strb r3, [r7, #15] USBD_StatusTypeDef usb_status = USBD_OK; 8008cf4: 2300 movs r3, #0 8008cf6: 73bb strb r3, [r7, #14] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); 8008cf8: 687b ldr r3, [r7, #4] 8008cfa: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8008cfe: 78fa ldrb r2, [r7, #3] 8008d00: 4611 mov r1, r2 8008d02: 4618 mov r0, r3 8008d04: f7f9 fdd1 bl 80028aa 8008d08: 4603 mov r3, r0 8008d0a: 73fb strb r3, [r7, #15] usb_status = USBD_Get_USB_Status(hal_status); 8008d0c: 7bfb ldrb r3, [r7, #15] 8008d0e: 4618 mov r0, r3 8008d10: f000 f8c2 bl 8008e98 8008d14: 4603 mov r3, r0 8008d16: 73bb strb r3, [r7, #14] return usb_status; 8008d18: 7bbb ldrb r3, [r7, #14] } 8008d1a: 4618 mov r0, r3 8008d1c: 3710 adds r7, #16 8008d1e: 46bd mov sp, r7 8008d20: bd80 pop {r7, pc} 08008d22 : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 8008d22: b580 push {r7, lr} 8008d24: b086 sub sp, #24 8008d26: af00 add r7, sp, #0 8008d28: 60f8 str r0, [r7, #12] 8008d2a: 607a str r2, [r7, #4] 8008d2c: 603b str r3, [r7, #0] 8008d2e: 460b mov r3, r1 8008d30: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 8008d32: 2300 movs r3, #0 8008d34: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 8008d36: 2300 movs r3, #0 8008d38: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); 8008d3a: 68fb ldr r3, [r7, #12] 8008d3c: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 8008d40: 7af9 ldrb r1, [r7, #11] 8008d42: 683b ldr r3, [r7, #0] 8008d44: 687a ldr r2, [r7, #4] 8008d46: f7f9 feea bl 8002b1e 8008d4a: 4603 mov r3, r0 8008d4c: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 8008d4e: 7dfb ldrb r3, [r7, #23] 8008d50: 4618 mov r0, r3 8008d52: f000 f8a1 bl 8008e98 8008d56: 4603 mov r3, r0 8008d58: 75bb strb r3, [r7, #22] return usb_status; 8008d5a: 7dbb ldrb r3, [r7, #22] } 8008d5c: 4618 mov r0, r3 8008d5e: 3718 adds r7, #24 8008d60: 46bd mov sp, r7 8008d62: bd80 pop {r7, pc} 08008d64 : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { 8008d64: b580 push {r7, lr} 8008d66: b086 sub sp, #24 8008d68: af00 add r7, sp, #0 8008d6a: 60f8 str r0, [r7, #12] 8008d6c: 607a str r2, [r7, #4] 8008d6e: 603b str r3, [r7, #0] 8008d70: 460b mov r3, r1 8008d72: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; 8008d74: 2300 movs r3, #0 8008d76: 75fb strb r3, [r7, #23] USBD_StatusTypeDef usb_status = USBD_OK; 8008d78: 2300 movs r3, #0 8008d7a: 75bb strb r3, [r7, #22] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); 8008d7c: 68fb ldr r3, [r7, #12] 8008d7e: f8d3 02c4 ldr.w r0, [r3, #708] ; 0x2c4 8008d82: 7af9 ldrb r1, [r7, #11] 8008d84: 683b ldr r3, [r7, #0] 8008d86: 687a ldr r2, [r7, #4] 8008d88: f7f9 fe66 bl 8002a58 8008d8c: 4603 mov r3, r0 8008d8e: 75fb strb r3, [r7, #23] usb_status = USBD_Get_USB_Status(hal_status); 8008d90: 7dfb ldrb r3, [r7, #23] 8008d92: 4618 mov r0, r3 8008d94: f000 f880 bl 8008e98 8008d98: 4603 mov r3, r0 8008d9a: 75bb strb r3, [r7, #22] return usb_status; 8008d9c: 7dbb ldrb r3, [r7, #22] } 8008d9e: 4618 mov r0, r3 8008da0: 3718 adds r7, #24 8008da2: 46bd mov sp, r7 8008da4: bd80 pop {r7, pc} 08008da6 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Received Data Size */ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { 8008da6: b580 push {r7, lr} 8008da8: b082 sub sp, #8 8008daa: af00 add r7, sp, #0 8008dac: 6078 str r0, [r7, #4] 8008dae: 460b mov r3, r1 8008db0: 70fb strb r3, [r7, #3] return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); 8008db2: 687b ldr r3, [r7, #4] 8008db4: f8d3 32c4 ldr.w r3, [r3, #708] ; 0x2c4 8008db8: 78fa ldrb r2, [r7, #3] 8008dba: 4611 mov r1, r2 8008dbc: 4618 mov r0, r3 8008dbe: f7f9 fe96 bl 8002aee 8008dc2: 4603 mov r3, r0 } 8008dc4: 4618 mov r0, r3 8008dc6: 3708 adds r7, #8 8008dc8: 46bd mov sp, r7 8008dca: bd80 pop {r7, pc} 08008dcc : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { 8008dcc: b580 push {r7, lr} 8008dce: b082 sub sp, #8 8008dd0: af00 add r7, sp, #0 8008dd2: 6078 str r0, [r7, #4] 8008dd4: 460b mov r3, r1 8008dd6: 70fb strb r3, [r7, #3] switch (msg) 8008dd8: 78fb ldrb r3, [r7, #3] 8008dda: 2b00 cmp r3, #0 8008ddc: d002 beq.n 8008de4 8008dde: 2b01 cmp r3, #1 8008de0: d01f beq.n 8008e22 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } 8008de2: e03b b.n 8008e5c if (hpcd->Init.low_power_enable) 8008de4: 687b ldr r3, [r7, #4] 8008de6: 6a1b ldr r3, [r3, #32] 8008de8: 2b00 cmp r3, #0 8008dea: d007 beq.n 8008dfc SystemClock_Config(); 8008dec: f7f7 fba4 bl 8000538 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8008df0: 4b1c ldr r3, [pc, #112] ; (8008e64 ) 8008df2: 691b ldr r3, [r3, #16] 8008df4: 4a1b ldr r2, [pc, #108] ; (8008e64 ) 8008df6: f023 0306 bic.w r3, r3, #6 8008dfa: 6113 str r3, [r2, #16] __HAL_PCD_UNGATE_PHYCLOCK(hpcd); 8008dfc: 687b ldr r3, [r7, #4] 8008dfe: 681b ldr r3, [r3, #0] 8008e00: f503 6360 add.w r3, r3, #3584 ; 0xe00 8008e04: 681b ldr r3, [r3, #0] 8008e06: 687a ldr r2, [r7, #4] 8008e08: 6812 ldr r2, [r2, #0] 8008e0a: f502 6260 add.w r2, r2, #3584 ; 0xe00 8008e0e: f023 0301 bic.w r3, r3, #1 8008e12: 6013 str r3, [r2, #0] USBD_LL_Resume(hpcd->pData); 8008e14: 687b ldr r3, [r7, #4] 8008e16: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008e1a: 4618 mov r0, r3 8008e1c: f7fe fbc2 bl 80075a4 break; 8008e20: e01c b.n 8008e5c __HAL_PCD_GATE_PHYCLOCK(hpcd); 8008e22: 687b ldr r3, [r7, #4] 8008e24: 681b ldr r3, [r3, #0] 8008e26: f503 6360 add.w r3, r3, #3584 ; 0xe00 8008e2a: 681b ldr r3, [r3, #0] 8008e2c: 687a ldr r2, [r7, #4] 8008e2e: 6812 ldr r2, [r2, #0] 8008e30: f502 6260 add.w r2, r2, #3584 ; 0xe00 8008e34: f043 0301 orr.w r3, r3, #1 8008e38: 6013 str r3, [r2, #0] USBD_LL_Suspend(hpcd->pData); 8008e3a: 687b ldr r3, [r7, #4] 8008e3c: f8d3 3404 ldr.w r3, [r3, #1028] ; 0x404 8008e40: 4618 mov r0, r3 8008e42: f7fe fb99 bl 8007578 if (hpcd->Init.low_power_enable) 8008e46: 687b ldr r3, [r7, #4] 8008e48: 6a1b ldr r3, [r3, #32] 8008e4a: 2b00 cmp r3, #0 8008e4c: d005 beq.n 8008e5a SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); 8008e4e: 4b05 ldr r3, [pc, #20] ; (8008e64 ) 8008e50: 691b ldr r3, [r3, #16] 8008e52: 4a04 ldr r2, [pc, #16] ; (8008e64 ) 8008e54: f043 0306 orr.w r3, r3, #6 8008e58: 6113 str r3, [r2, #16] break; 8008e5a: bf00 nop } 8008e5c: bf00 nop 8008e5e: 3708 adds r7, #8 8008e60: 46bd mov sp, r7 8008e62: bd80 pop {r7, pc} 8008e64: e000ed00 .word 0xe000ed00 08008e68 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { 8008e68: b480 push {r7} 8008e6a: b083 sub sp, #12 8008e6c: af00 add r7, sp, #0 8008e6e: 6078 str r0, [r7, #4] static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; 8008e70: 4b03 ldr r3, [pc, #12] ; (8008e80 ) } 8008e72: 4618 mov r0, r3 8008e74: 370c adds r7, #12 8008e76: 46bd mov sp, r7 8008e78: f85d 7b04 ldr.w r7, [sp], #4 8008e7c: 4770 bx lr 8008e7e: bf00 nop 8008e80: 200001b0 .word 0x200001b0 08008e84 : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { 8008e84: b480 push {r7} 8008e86: b083 sub sp, #12 8008e88: af00 add r7, sp, #0 8008e8a: 6078 str r0, [r7, #4] } 8008e8c: bf00 nop 8008e8e: 370c adds r7, #12 8008e90: 46bd mov sp, r7 8008e92: f85d 7b04 ldr.w r7, [sp], #4 8008e96: 4770 bx lr 08008e98 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) { 8008e98: b480 push {r7} 8008e9a: b085 sub sp, #20 8008e9c: af00 add r7, sp, #0 8008e9e: 4603 mov r3, r0 8008ea0: 71fb strb r3, [r7, #7] USBD_StatusTypeDef usb_status = USBD_OK; 8008ea2: 2300 movs r3, #0 8008ea4: 73fb strb r3, [r7, #15] switch (hal_status) 8008ea6: 79fb ldrb r3, [r7, #7] 8008ea8: 2b03 cmp r3, #3 8008eaa: d817 bhi.n 8008edc 8008eac: a201 add r2, pc, #4 ; (adr r2, 8008eb4 ) 8008eae: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8008eb2: bf00 nop 8008eb4: 08008ec5 .word 0x08008ec5 8008eb8: 08008ecb .word 0x08008ecb 8008ebc: 08008ed1 .word 0x08008ed1 8008ec0: 08008ed7 .word 0x08008ed7 { case HAL_OK : usb_status = USBD_OK; 8008ec4: 2300 movs r3, #0 8008ec6: 73fb strb r3, [r7, #15] break; 8008ec8: e00b b.n 8008ee2 case HAL_ERROR : usb_status = USBD_FAIL; 8008eca: 2303 movs r3, #3 8008ecc: 73fb strb r3, [r7, #15] break; 8008ece: e008 b.n 8008ee2 case HAL_BUSY : usb_status = USBD_BUSY; 8008ed0: 2301 movs r3, #1 8008ed2: 73fb strb r3, [r7, #15] break; 8008ed4: e005 b.n 8008ee2 case HAL_TIMEOUT : usb_status = USBD_FAIL; 8008ed6: 2303 movs r3, #3 8008ed8: 73fb strb r3, [r7, #15] break; 8008eda: e002 b.n 8008ee2 default : usb_status = USBD_FAIL; 8008edc: 2303 movs r3, #3 8008ede: 73fb strb r3, [r7, #15] break; 8008ee0: bf00 nop } return usb_status; 8008ee2: 7bfb ldrb r3, [r7, #15] } 8008ee4: 4618 mov r0, r3 8008ee6: 3714 adds r7, #20 8008ee8: 46bd mov sp, r7 8008eea: f85d 7b04 ldr.w r7, [sp], #4 8008eee: 4770 bx lr 08008ef0 <__libc_init_array>: 8008ef0: b570 push {r4, r5, r6, lr} 8008ef2: 4d0d ldr r5, [pc, #52] ; (8008f28 <__libc_init_array+0x38>) 8008ef4: 4c0d ldr r4, [pc, #52] ; (8008f2c <__libc_init_array+0x3c>) 8008ef6: 1b64 subs r4, r4, r5 8008ef8: 10a4 asrs r4, r4, #2 8008efa: 2600 movs r6, #0 8008efc: 42a6 cmp r6, r4 8008efe: d109 bne.n 8008f14 <__libc_init_array+0x24> 8008f00: 4d0b ldr r5, [pc, #44] ; (8008f30 <__libc_init_array+0x40>) 8008f02: 4c0c ldr r4, [pc, #48] ; (8008f34 <__libc_init_array+0x44>) 8008f04: f000 f820 bl 8008f48 <_init> 8008f08: 1b64 subs r4, r4, r5 8008f0a: 10a4 asrs r4, r4, #2 8008f0c: 2600 movs r6, #0 8008f0e: 42a6 cmp r6, r4 8008f10: d105 bne.n 8008f1e <__libc_init_array+0x2e> 8008f12: bd70 pop {r4, r5, r6, pc} 8008f14: f855 3b04 ldr.w r3, [r5], #4 8008f18: 4798 blx r3 8008f1a: 3601 adds r6, #1 8008f1c: e7ee b.n 8008efc <__libc_init_array+0xc> 8008f1e: f855 3b04 ldr.w r3, [r5], #4 8008f22: 4798 blx r3 8008f24: 3601 adds r6, #1 8008f26: e7f2 b.n 8008f0e <__libc_init_array+0x1e> 8008f28: 08008fc8 .word 0x08008fc8 8008f2c: 08008fc8 .word 0x08008fc8 8008f30: 08008fc8 .word 0x08008fc8 8008f34: 08008fcc .word 0x08008fcc 08008f38 : 8008f38: 4402 add r2, r0 8008f3a: 4603 mov r3, r0 8008f3c: 4293 cmp r3, r2 8008f3e: d100 bne.n 8008f42 8008f40: 4770 bx lr 8008f42: f803 1b01 strb.w r1, [r3], #1 8008f46: e7f9 b.n 8008f3c 08008f48 <_init>: 8008f48: b5f8 push {r3, r4, r5, r6, r7, lr} 8008f4a: bf00 nop 8008f4c: bcf8 pop {r3, r4, r5, r6, r7} 8008f4e: bc08 pop {r3} 8008f50: 469e mov lr, r3 8008f52: 4770 bx lr 08008f54 <_fini>: 8008f54: b5f8 push {r3, r4, r5, r6, r7, lr} 8008f56: bf00 nop 8008f58: bcf8 pop {r3, r4, r5, r6, r7} 8008f5a: bc08 pop {r3} 8008f5c: 469e mov lr, r3 8008f5e: 4770 bx lr